MAX9611AUB+T [MAXIM]
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| 型号： | MAX9611AUB+T |
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MAXIM INTEGRATED PRODUCTS |
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19-5543; Rev 2; 1/11
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
General Description
Features
0V to +60V Input Common-Mode Voltage Range
The MAX9611/MAX9612 are high-side current-sense
amplifiers with an integrated 12-bit ADC and a gain
block that can be configured either as an op amp or
comparator, making these devices ideal for a number of
industrial and automotive applications.
S
S
2.7V to 5.5V Power-Supply Range, Compatible
with 1.8V and 3.3V Logic
5µA Software Shutdown Current
Integrated 12-Bit ADC
S
S
S
S
The high-side, current-sense amplifiers operate over a
wide 0V to 60V input common-mode voltage range. The
programmable full-scale voltage (440mV, 110mV, and
55mV) of these amplifiers offers wide dynamic range,
accurate current measurement, and application flexibility
in choosing sense resistor values. A choice of either an
internal op amp or a comparator is provided to the user.
The internal amplifier can be used to limit the inrush cur-
rent or to create a current source in a closed-loop sys-
tem. The comparator can be used to monitor fault events
for fast response.
13µV Current-Sense ADC Resolution
500µV (max) Current-Sense ADC Input Offset
Voltage
0.5% (max) Current-Sense ADC Gain Error
I2C Bus with 16 Addresses
S
S
S
S
Small, 3mm x 5mm 10-Pin µMAX Package
-40NC to +125NC Operating Temperature Range
Ordering Information/
Selector Guide
An I2C controlled 12-bit, 500sps analog-to-digital con-
verter (ADC) can be used to read the voltage across the
sense resistor (V ), the input common-mode voltage
SENSE
PART
OUTPUT
Noninverting
Inverting
PIN-PACKAGE
10 FMAX
(V ), op-amp/comparator output (V ), op-amp/
RSCM OUT
MAX9611AUB+
MAX9612AUB+
comparator reference voltage (V ), and internal die
SET
10 FMAX
temperature. The I2C bus is compatible with 1.8V and
3.3V logic, allowing modern microcontrollers to interface
to it.
Note: All devices operate over the -40NC to +125NC tempera-
ture range.
The MAX9611 features a noninverting input-to-output
configuration while the MAX9612 features an inverting
input-to-output configuration.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Application Circuit
The MAX9611/MAX9612 operate with a 2.7V to 5.5V
supply voltage range, are fully specified over the -40NC
to +125NC automotive temperature range, and are avail-
R
SENSE
0V TO 60V
M
able in a 3mm x 5mm, 10-pin FMAX package.
Applications
Hybrid Automotive Power Supplies
Server Backplanes
RS+
RS-
LOAD
V
IN
V
A0
A1
CC
0.1µF
Base-Station PA Control
Base-Station Feeder Cable Bias-T
Telecom Cards
MAX9611
MAX9612
OUT
SET
µC
Battery-Operated Equipment
SCL
SCL
SDA
1.8V LOGIC
SDA
GND
FMAX is a registered trademark of Maxim Integrated Products, Inc.
Functional Diagrams appear at end of data sheet.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND.............................................................-0.3V to +6V
FMAX Package Junction-to-Ambient
RS+, RS-, OUT to GND.........................................-0.3V to +65V
Differential Input Voltage, RS+ - RS- ................................. Q65V
All Other Pins to GND .............................................-0.3V to +6V
OUT Short-Circuit to GND.........................................Continuous
Continuous Current into Any Pin..................................... Q20mA
Thermal Resistance (B ) (Note 1)............................113NC/W
JA
Operating Temperature Range........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Continuous Power Dissipation (T = +70NC)
A
10-Pin FMAX (derate 8.8mW/NC above +70NC)...........707mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal consideration, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 3.3V, V
= V
= +12V, V
= (V
- V ) = 0V, T = -40NC to +125NC, unless otherwise noted. Typical values are
RS+
RS-
SENSE
RS+
RS-
A
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
CURRENT-SENSE AMPLIFIER DC CHARACTERISTICS
Input Common-Mode Range
Guaranteed by CMRR
0
60
0.5
2
V
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= +25NC, gain = 8x
0.045
0.045
0.1
= -40NC to +125NC, gain = 8x
= +25NC, gain = 4x
0.5
2
Input Offset Voltage ADC Path
(Note 3)
V
mV
OS
= -40NC to +125NC, gain = 4x
= +25NC, gain = 1x
0.8
2.6
0.5
1.8
2.5
1.7
3.1
4
= -40NC to +125NC, gain = 1x
= +25NC, gain = 8x
0.1
= -40NC to + 85NC, gain = 8x
= -40NC to +125NC, gain = 8x
= +25NC, gain = 4x
Gain Error (Note 3)
GE
0.4
1
%
= -40NC to +125NC, gain = 4x
= +25NC, gain = 1x
= -40NC to +125NC, gain = 1x
4.7
Differential Input Resistance
R
R
300
12
1
kI
INDM
INCM
Common-Mode Input Resistance
MI
T
A
T
A
T
A
T
A
= +25NC
2
5
6
6
Input Bias Current
I
, I
FA
RS+ RS-
= -40NC to +125NC
= +25NC
3
Input Offset Current (Note 4)
(I
) - (I
nA
RS+
RS-)
= -40NC to +125NC
2
______________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.3V, V
= V
= +12V, V
= (V
- V ) = 0V, T = -40NC to +125NC, unless otherwise noted. Typical values are
RS+
RS-
SENSE
RS+
RS-
A
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Gain = 8x,
= 50mV
106
120
V
SENSE
V
= 0V to 60V,
= +25NC
Gain = 4x,
V = 100mV
SENSE
RS-
106
100
94
120
120
T
A
Gain = 1x,
V
=400mV
= 50mV
= 100mV
= 400mV
SENSE
Common-Mode Rejection Ratio
CMRR
dB
Gain 8x,
V
SENSE
V
= 0V to 60V,
= -40NC to +125NC
Gain 4x,
V
SENSE
RS-
94
T
A
Gain 1x,
V
84
SENSE
Gain = 8x,
= 50mV
57
72
67
57
V
SENSE
Gain = 4x,
= 100mV
Power-Supply Rejection Ratio
PSRR
V
= 2.7V to 5.5V
56
dB
CC
V
SENSE
Gain = 1x,
= 400mV
48
V
SENSE
Gain = 8x
Gain = 4x
Gain = 1x
55
110
Used in gain error
measurement
FS
mV
Full-Scale Sense Volt
age
440
Gain = 8x
Gain = 4x
Gain = 1x
13.44
26.88
107.50
LSB Step Size
LSB
FV
ANALOG PATH, CSA + AMPLIFIER/COMPARATOR
T
T
= +25NC
0.350
4
A
A
Input Offset Voltage
V
mV
10
OS
= -40NC to +125NC
SET Input Bias Current
I
B
1
50
nA
Maximum SET Input Voltage
Range
1.126
V
Signal Bandwidth
Gain Bandwidth
BW
Gain = 1x, RS- = 11.6V
4
MHz
MHz
Fs
GBW
2.5
1.5
8
Propagation Delay
Internal Hysteresis
Output Sink Current
Output Leakage Current
t
In comparator mode, 10mV overdrive
In comparator mode, nonlatching
PD
V
HYS
mV
mA
FA
V
= 4V
20
1.7
OUT
OUT
SINK
SINK
V
= 36V
3
1
I
I
= 8mA, T = -40°C to +85°C
A
Output Voltage Low
V
OL
V
= 8mA, T = -40NC to +125NC
0.5
1.5
A
_______________________________________________________________________________________
3
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.3V, V
= V
= +12V, V
= (V
- V ) = 0V, T = -40NC to +125NC, unless otherwise noted. Typical values are
RS+
RS-
SENSE
RS+
RS-
A
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
OUT VOLTAGE MEASUREMENT (V
Full-Scale Input Voltage
LSB Step Size
)
OUT
57.3
14
0.8
V
mV
LSB
GE
T
T
= +25NC
6
V
(V
=
A
A
RSCM
Gain Error
%
- V )/2
RS-
RS+
= -40NC to +125°C
7
T
T
= +25NC
14
110
mV
A
Input Offset Voltage
V
OSOUT
= -40NC to +125NC
160
A
COMMON-MODE VOLTAGE MEASUREMENT (V
)
RSCM
Full-Scale Input Voltage
57.3
14
V
LSB Step Size
LSB
GE
mV
T
T
= +25NC
0.3
6
V
(V
=
A
A
RSCM
Gain Error
%
- V )/2
RS-
RS+
= -40NC to +125°C
7
T
T
= +25NC
14
80
mV
160
A
Input Offset Voltage
V
OSOUT
= -40NC to +125NC
A
SET VOLTAGE MEASUREMENT (V
Full-Scale Input Voltage
LSB Step Size
)
SET
1.10
268
0.2
V
FV
T
T
= +25NC
5
V
(V
=
A
A
RSCM
Gain Error
GE
%
- V )/2
RS-
RS+
= -40NC to +125°C
6
T
T
= +25NC
0.3
10
mV
14
A
Input Offset Voltage
V
OSOUT
= -40NC to +125NC
A
Integral Nonlinearity
Differential Nonlinearity
TEMPERATURE MEASUREMENT
Accuracy
INL
1
LSB
LSB
DNL
0.2
0.48
0.48
NC
Typical Measurement Range
LSB Step Size
-40
+125
NC
NC
LSB
ANALOG-TO-DIGITAL CONVERTER
Resolution
12
2
Bit
Conversion Time
ms
SCL/SDA LOGIC LEVELS
Input Voltage Low
V
V
V
= 2.7V to 5.5V
= 2.7V to 5.5V
0.4
V
V
IL
CC
CC
Input Voltage High
V
IH
1.45
0.05 x
Input Hysteresis
V
V
HYS
V
CC
1
Input Leakage Current
200
nA
A1/A0 LOGIC LEVELS
Logic State 00-01 Threshold
Logic State 01-10 Threshold
Logic State 10-11 Threshold
Input Leakage Current
1/4 x V
1/2 x V
3/4 x V
1
V
V
CC
CC
CC
V
200
nA
4
______________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.3V, V
= V
= +12V, V
= (V
- V ) = 0V, T = -40NC to +125NC, unless otherwise noted. Typical values are
RS+
RS-
SENSE
RS+
RS-
A
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER-SUPPLY CHARACTERISTICS
Power-Supply Input Range
Quiescent Current
V
Guaranteed by PSRR
No activity on SCL
2.7
5.5
2.6
10
V
CC
CC
I
1.6
5
mA
FA
Shutdown Current
I
SHDN
I2C TIMING CHARACTERISTICS (COMPATIBLE WITH SMBus)
Serial-Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between a STOP
and a START Condition
Hold Time, (Repeated) START
Condition
t
1.3
Fs
BUF
t
t
0.6
Fs
DH,STA
SCL Clock Low Period
SCL Clock High Period
t
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
Fs
SU,STA
DH,DAT
Data Hold Time
t
0
900
Fs
Data Setup Time
t
100
ns
SU,DAT
SDA/SCL Receiving Rise Time
SDA/SCL Receiving Fall Time
SDA Transmitting Fall Time
STOP Condition Setup Time
Bus Capacitance
t
(Note 5)
(Note 5)
(Note 5)
20 + 0.1C
20 + 0.1C
20 + 0.1C
0.6
300
300
250
R
B
B
B
t
t
ns
F
F
t
Fs
pF
ns
SU,STO
C
400
B
Pulse Width of Spike Suppressed
t
SP
50
Note 2: All devices are 100% production tested at T = +25NC. Temperature limits are guaranteed by design.
A
Note 3: V
and gain error of current-sense amplifier extrapolated from from a two-point measurement made at V
) = 5mV to 50mV in gain of 8x, 5mV to 100mV in gain of 4x, and 10mV to 400mV in gain of 1x.
= (V
-
OS
SENSE
RS+
V
RS-
Note 4: Guaranteed by design.
Note 5: C is in pF.
B
2
I C Timing Diagram
SDA
SCL
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
LOW
t
SU,STO
t
HD,DAT
t
HIGH
t
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
_______________________________________________________________________________________
5
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Typical Operating Characteristics
(V
CC
= 3.3V, V = 12V, T = +25NC, unless otherwise noted.)
CM A
MAX9611 CSA OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGE
TOTAL OFFSET VOLTAGE
vs. COMMON-MODE VOLTAGE
CSA HISTOGRAM
30
700
600
500
400
300
200
100
0
4
3
8x ADC PATH
ANALOG PATH
GAIN = 8x
T = -40°C
A
T = +125°C
A
25
20
15
10
5
2
T = +25°C
A
T = +85°C
A
1
0
-1
-2
-3
-4
T = -40°C
A
-100
-200
-300
T = +85°C
A
T = +25°C
A
T = +125°C
A
0
0
10
20
30
(V)
40
50
60
0
10
20
30
(V)
40
50
60
V
(µV)
V
V
OFFSET_CSA
CM
CM
TOTAL OFFSET VOLTAGE
vs. SUPPLY VOLTAGE
CSA OFFSET VOLTAGE
vs. SUPPLY VOLTAGE
200
150
100
50
800
OP-AMP PATH
ADC PATH
GAIN = 8x
700
600
500
400
300
200
0
-50
-100
-150
-200
-250
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
V
CC
CC
RS- BIAS CURRENT
vs. COMMON-MODE VOLTAGE
RS+, RS- OFFSET CURRENT
vs. COMMON-MODE VOLTAGE
5
4
3
2
1
0
2.5
2.0
1.5
1.0
0.5
0
T
= +85°C
A
T
= +25°C
A
T
A
= -40°C
T
= +125°C
A
0
10
20
30
(V)
40
50
60
0
10
20
30
(V)
40
50
60
V
V
CM
CM
6
______________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, V = 12V, T = +25NC, unless otherwise noted.)
CM A
TOTAL GAIN ERROR
vs. COMMON-MODE VOLTAGE
SDA/SCL V
vs. SINKING CURRENT
MAX9611 CSA GAIN ERROR
vs. COMMON-MODE VOLTAGE
OL
0.4
0.2
0.05
0.04
0.03
0.02
0.01
0
1.00
ANALOG PATH
8x ADC PATH
0.80
-40°C
0.60
0.40
+25°C
0
0.20
-0.2
-0.4
-0.6
-0.8
-1.0
0
-0.20
-0.40
+85°C
+125°C
-0.60
-0.80
-1.00
0
10
20
30
(V)
40
50
60
0
0.5
1.0
1.5
2.0
2.5
3.0
0
10
20
30
40
50
60
V
SDA SINKING CURRENT (mA)
CM
V
(V)
CM
OUTPUT LOW VOLTAGE
vs. OUTPUT SINK CURRENT
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.7
1.4
1.1
0.8
0.5
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
0
5
10
15
20
25
V
CC
OUTPUT SINK CURRENT (mA)
CSA GAIN vs. FREQUENCY
(RS+/RS- TO OUT PATH)
OP-AMP GAIN vs. FREQUENCY
(SET TO OUT)
15
10
5
15
10
5
0
0
-5
-5
-10
-15
-10
-15
-20
-25
-30
-20
-25
-30
R
V
- R = 220mV
S+ S-
= 100mV
R
- R = V
S+ S- SENSE
+ V = 200mV + 300mV
IN
P-P
DC
P-P
1
10
100
1,000
10,000
1
10
100
FREQUENCY (kHz)
1,000
10,000
FREQUENCY (kHz)
_______________________________________________________________________________________
7
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, V = 12V, T = +25NC, unless otherwise noted.)
CM A
CMRR vs. FREQUENCY
CSA ADC PATH
CMRR vs. FREQUENCY
ANALOG OP-AMP PATH
P-P NOISE (RS+/RS- TO OUT)
MAX9611 toc17
0
-70
-75
V
CM
V
AC
= 12V
= 10V
P-P
-20
-80
-40
-60
-85
-90
-95
-80
-100
-105
-110
-115
-120
-100
-120
-140
1
10
100
1000
0.01
0.1
1
10
100
1000
TIME (10s/div)
FREQUENCY (kHz)
FREQUENCY (kHz)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(SET INPUT)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
(SET INPUT)
0.5
0.3
1.0
0.8
0.1
0.6
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL CODE
ADC NOISE HISTOGRAM ON
ADC NOISE HISTOGRAM ON
V
= 20mV (GAIN = 8x)
V
= 0.5V
SENSE
SET
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
DIGITAL CODE
DIGITAL CODE
8
______________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Typical Operating Characteristics (continued)
(V
CC
= 3.3V, V = 12V, T = +25NC, unless otherwise noted.)
CM A
HOT-SWAP OPERATION WITH
p-CHANNEL FET MODE 000
WATCHDOG LATCH RETRY MODE 111
WATCHDOG LATCH RETRY MODE 111
MAX9611 toc22
MAX9611 toc23
MAX9611 toc24
DTIM = 0, RTIM = 1
DTIM = 0, RTIM = 0
V
= 600mV
SET
V
SET
= 600mV
PULSE WIDTH > 1ms
V
PULSE WIDTH < 1ms
PULLUP
V
V
CSAIN
V
OUT
(UNREGULATED)
200mV/div
200mV/div
CSAIN
V
OUT
(REGULATED)
V
OUT
5V/div
V
OUT
5V/div
R
OUT
= 8I
TIME (100µs/div)
TIME (400µs/div)
TIME (4ms/div)
WATCHDOG LATCH MODE 111
WATCHDOG LATCH MODE 111
MAX9611 toc26
MAX9611 toc25
200mV/div
V
CSAIN
V
200mV/div
CSAIN
V
OUT
10V/div
DTIM = 1, RTIM = 1
5V/div
V
DTIM = 0, RTIM = 1
OUT
V
= 600mV
V
= 600mV
SET
SET
PULSE WIDTH > 1ms
PULSE WIDTH > 1ms
TIME (100µs/div)
TIME (1ms/div)
WATCHDOG LATCH RETRY MODE 111
WATCHDOG LATCH RETRY MODE 111
MAX9611 toc27
MAX9611 toc28
DTIM = 0, RTIM = 0
DTIM = 0, RTIM = 1
V
= 600mV
V
= 600mV
SET
SET
V
CSAIN
PULSE WIDTH > 1ms
PULSE WIDTH > 1ms
200mV/div
V
200mV/div
CSAIN
V
OUT
5V/div
V
OUT
5V/div
TIME (10ms/div)
TIME (10ms/div)
_______________________________________________________________________________________
9
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Pin Configuration
TOP VIEW
+
OUT
RS+
RS-
10
9
V
CC
1
2
3
4
5
A0
8
A1
MAX9611
MAX9612
SET
GND
7
SDA
SCL
6
µMAX
Pin Description
PIN
1
NAME
OUT
RS+
RS-
FUNCTION
Internal Amplifier/Comparator Output
2
Positive Current-Sensing Input. Power side connects to external sense resistor.
3
Negative Current-Sensing Input. Load side connects to external sense resistor.
4
SET
GND
SCL
SDA
A1
External Set-Point Voltage
Ground
I2C Interface Clock Input
I2C Interface Data Input/Output
Address Input 1
5
6
7
8
9
A0
Address Input 0
10
V
CC
Supply Voltage Input. Bypass V
to GND with a 0.1FF and a 4.7FF capacitor in parallel.
CC
10 _____________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Functional Diagrams
V
CC
RS+
RS-
CSA
MAX9611
1x, 4x,
8x
A0
A1
2.5x
DECODER
SCL
SDA
2
12-BIT
ADC
I C
MUX
OP AMP/
COMP
OUT
TEMP
REGISTERS
SET
GND
V
CC
RS+
RS-
CSA
MAX9612
1x, 4x,
8x
A0
A1
2.5x
DECODER
SCL
SDA
2
12-BIT
ADC
I C
MUX
OUT
OP AMP/
COMP
TEMP
REGISTERS
SET
GND
NOTE: ANALOG PATH IN BOLD.
______________________________________________________________________________________ 11
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
stage crossover distortion, typical in most rail-to-rail
Detailed Description
input current-sense amplifiers. Low input bias currents
and low input offset currents allow a wide selection of
input filters to be designed without degrading the accu-
racy of the current-sense amplifier.
The MAX9611/MAX9612 are high-side, current-sense
amplifiers with an integrated 12-bit ADC and an internal
selectable op amp/comparator. These devices are ideal
for a variety of industrial and automotive applications.
The current-sense amplifier inputs feature both a
-0.3V/+65V common-mode absolute maximum rating
as well as a Q65V differential absolute maximum rating,
allowing a wide variety of fault conditions to be withstood
easily by the device without damage.
The MAX9611/MAX9612’s high-side, current-sense
amplifiers operate over a wide 0V to 60V input com-
mon-mode voltage range. The programmable full-scale
voltage (440mV, 110mV, and 55mV) allows for a wide
dynamic range current measurement and application
flexibility in choosing sense resistor values.
The I2C bus is 1.8V and 3.3V logic compatible and
can interface with modern microcontrollers. An internal
12-bit, 500sps integrating analog-to-digital converter
(ADC) allows the user to read analog signals such as die
The current-sense amplifier has a gain of 2.5V/V and
connects directly to the output op-amp/comparator
inputs. The ADC path features a 1x, 4x, and 8x program-
mable gain providing for 440mV, 110mV, and 55mV full-
scale sense voltage.
Analog-to-Digital Converter (ADC)
The MAX9611/MAX9612 feature an internal dual-slope
integrating 12-bit ADC that has a 2ms conversion time
and a 1.8V and 3.3V logic-compatible I2C bus. An inter-
nal mux allows the following on chip variables to be
read: input sense voltage, input common-mode voltage,
SET voltage, OUT voltage, and die temperature.
temperature, V
, V
, V
, and V
.
OUT SET RSCM
SENSE
At power-up, the selectable op-amp/comparator block
is configured in the op-amp mode. The op amp has
an effective 60V Class A-type output stage and can be
used to limit inrush currents and create a current source
when used in a closed-loop system. When the internal
comparator is selected, the MAX9611/MAX9612 can
be configured to have a latched and retry functional-
ity, allowing a 60V open-drain transistor output, ideal to
operate high-side relay-disconnect FETs. The MAX9611
has a noninverting input-to-output configuration while the
MAX9612 has an inverting input-to-output configuration.
Temperature Measurement
Die temperature can be read by the ADC over the entire
operating range (-40NC to +125NC) with 0.5NC resolution.
Die temperature can be used for application calibration
and thermal monitoring and is available in a 9-bit, two’s
complement format. Readings outside of normal operat-
ing temperature range (-40NC to +125NC) are inaccurate
and should be considered invalid. See Table 1 for binary
and hex values.
Current-Sense Amplifier
The MAX9611/MAX9612 feature a precision current-sense
amplifier with a 0V to 60V input common-mode voltage
range. An internal negative charge pump eliminates input
Table 1. Binary and Hex Digital Output Values for Temperature Measurements
DIGITAL OUTPUT
TEMPERATURE (NC)
BINARY
HEX
7F8x
190x
008x
000x
FF8x
E70x
D98x
+122.4
+24
+0.48
0
0111 1111 1xxx xxxx
0001 1001 0xxx xxxx
0000 0000 1xxx xxxx
0000 0000 0xxx xxxx
1111 1111 1xxx xxxx
1110 0111 0xxx xxxx
1101 1001 1xxx xxxx
-0.48
-24
-40
12 _____________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
SET Voltage Measurement
The SET voltage serves as a reference voltage for the
internal op amp or comparator around which a control
loop can be designed. The low bias current for SET
allows high-impedance resistor-dividers and current-
output DACs to be used, making it easy to interface
without introducing additional errors.
Watchdog/Latch/Retry Functionality
Internal digital circuitry is used to implement a watchdog
feature that can be useful to handle normal application
transients that are not true fault conditions. This feature
applies both to the op amp and comparator modes of
part operation. A watchdog delay time is internally set to
1ms by default but can be changed to 100Fs. The retry
delay time is internally set to 50ms by default, but can be
changed to 10ms (see Tables 6 and 7).
The SET input can also serve as an auxiliary input port
to the ADC, if the op amp or comparator is not utilized
in the application. Its full-scale input range extends from
0V to 1.10V.
In normal operation mode, (Control Register 1 (0x0A)
000x xxxx), the amplifier output responds to the differ-
ence between its inputs, i.e., the CSA output voltage and
the SET voltage. In open-loop configuration, the op amp
can be used as a comparator.
OUT Voltage Measurement
The internal amplifier/comparator output voltage can be
monitored over the entire 0V to 57.3V range by the ADC.
An internal high-value resistor divider on OUT reduces
leakage current effects.
In a watchdog-latch-retry mode (Control Register 1
(0x0A) 111x xxxx), the output of the comparator waits
for a watchdog delay time (to ensure the CSA output
continues to stay above the SET voltage for this duration)
before responding, and then latches onto this state. After
a retry delay time, it resets the comparator state and the
cycle repeats.
Common-Mode Voltage Measurement
The input common-mode voltage is defined as the aver-
age of the voltage at RS+ and RS-. A high value resistor-
divider allows measurement of the input common-mode
voltage over the 0V to 57.3V range.
Similar functionality is implemented for the op-amp
mode as well (Control Register 1 (0x0A) 000x xxxx to
011x xxxx).
Sense Voltage Measurement
Three programmable gains allow for a wide range of cur-
rents to be read by the ADC. The current-sense amplifier
gain can be set to 1x, 4x, or 8x. The full-scale sense volt-
ages are then 440mV, 110mV, and 55mV, respectively.
A RESET bit is defined in Control Register 1 (0x0A) to
reset a latched state when commanded by the user.
2
I C Interface
Output Amplifier/Comparator
The MAX9611/MAX9612 feature an internally selectable
op amp and comparator where one of the inputs is con-
nected to the 2.5x current-sense amplifier, and the other
input is connected to the SET input. The op amp or the
comparator output can be selected and connected to
OUT. The output stage is an open-drain 60V nFET, that
requires a suitable pullup resistor for proper opera-
tion. The op amp then behaves like a Class-A output
stage. Select op amp or comparator function in Control
Register 1 (0x0A) bit 7 (see Tables 4 and 5).
The MAX9611/MAX9612 I2C interface consists of a
serial-data line (SDA) and serial-clock line (SCL). SDA
and SCL facilitate bidirectional communication between
the MAX9611/MAX9612 and the master at rates up to
400kHz. The MAX9611/MAX9612 are slave devices that
transfer and receive data. The master (typically a micro-
controller) initiates data transfer on the bus and gener-
ates the SCL signal to permit that transfer.
______________________________________________________________________________________ 13
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Slave Address
A bus master initiates communication with a slave
device by issuing a START (S) condition followed by a
slave address. When idle, the MAX9611/MAX9612 con-
tinuously wait for a START condition followed by their
slave address. When the MAX9611/MAX9612 recognize
a slave address, it is ready to accept or send data. The
MAX9611/MAX9612 offer 16 different slave addresses
using two address inputs, A1 and A0. See Table 2 for
different slave address options. The least significant bit
(LSB) of the address byte (R/W) determines whether
the master is writing to or reading from the MAX9611/
MAX9612 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the address,
the MAX9611/MAX9612 (slave) issue an acknowledge
by pulling SDA low for one clock cycle.
I2C Read Operation
In an I2C read operation (Figure 2), the bus master
issues a write command first by initiating a START condi-
tion followed by seven address bits, a write bit (R/W = 0)
and the 8-bit register address. The master then issues
a Repeated START (Sr) condition, followed by seven
address bits, a read bit (R/W = 1). If the address byte
is successfully received, the MAX9611/MAX9612 (slave)
issue an acknowledge (A). The master then reads from
the slave. For continuous read, the master issues an
acknowledge bit (AM) after each received byte. The
master terminates the read operation by sending a not
acknowledge (NA) bit. The MAX9611/MAX9612 then
release the data line SDA allowing the master to gener-
ate a STOP condition.
2
I C Write Operation
SINGLE WRITE
S
ACKNOWLEDGE FROM
MAX9611/MAX9612
A write operation (Figure 1) begins with the bus master
issuing a START condition followed by seven address
bits and a write bit (R/W = 0). If the address byte is
successfully received, the MAX9611/MAX9612 (slave)
issue an acknowledge (A). The master then writes to
the slave and the sequence is terminated by a STOP (P)
condition for a single write operation.
SLAVE ADDRESS
0
A
A
REGISTER ADDRESS
R/W
A
DATA
P
STOP
ACKNOWLEDGE FROM
MAX9611/MAX9612
BURST WRITE
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
For a burst write operation, more data bytes are sent after
the register address before the transaction is terminated.
R/W
A
A
DATA 1
DATA 3
A
A
DATA 2
DATA N
Table 2. MAX9611/MAX9612 Address
Description
A
P
STOP
DEVICE WRITE
ADDRESS (hex) ADDRESS (hex)
DEVICE READ
A1
A0
2
Figure 1. I C Write Operation
0
0
0
0xE0
0xE2
0xE4
0xE6
0xE8
0xEA
0xEC
0xEE
0xF0
0xF2
0xF4
0xF6
0xF8
0xFA
0xFC
0xFE
0xE1
0xE3
0xE5
0xE7
0xE9
0xEB
0xED
0xEF
0xF1
0xF3
0xF5
0xF7
0xF9
0xFB
0xFD
0xFF
1/3 x V
CC
CC
SINGLE READ ACKNOWLEDGE FROM
MAX9611/MAX9612
0
2/3 x V
0
V
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
DATA
CC
1/3 x V
1/3 x V
1/3 x V
1/3 x V
2/3 x V
2/3 x V
2/3 x V
2/3 x V
0
CC
CC
CC
CC
CC
CC
CC
CC
R/W
SLAVE ADDRESS
A
Sr
1
A
AM P
1/3 x V
2/3 x V
CC
R/W
ACKNOWLEDGE FROM
FROM MASTER
CC
BURST READ
S
ACKNOWLEDGE FROM
MAX9611/MAX9612
V
CC
SLAVE ADDRESS
0
A
REGISTER ADDRESS
DATA
A
0
R/W
1/3 x V
2/3 x V
CC
SLAVE ADDRESS
A
Sr
1
CC
REPEAT
START
AM
R/W
V
CC
DATA N
DATA
AM
NA P
V
V
V
V
0
CC
CC
CC
CC
NO READ-ACKNOWLEDGE
FROM MASTER
1/3 x V
2/3 x V
CC
CC
2
V
CC
Figure 2. I C Read Operation
14 _____________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Table 3 lists all the registers, their corresponding POR
values and their addresses.
Registers
The MAX9611/MAX9612 include five 12-bit data register
banks and two 8-bit control registers.
The two control registers are read/write registers used
to configure the ADC for different modes of operation.
Table 3. Internal Register/Addresses
REGISTERS
POR VALUES (hex)
0x000
REGISTER ADDRESS (hex)
CSA DATA BYTE 1 (MSBs)
CSA DATA BYTE 1 (LSBs)
RS+ DATA BYTE 1 (MSBs)
RS+ DATA BYTE 1 (LSBs)
OUT DATA BYTE 1 ( MSBs)
OUT DATA BYTE 1 (LSBs)
SET DATA BYTE 1 (MSBs)
SET DATA BYTE 1 (LSBs)
TEMP DATA BYTE 1 (MSBs)
TEMP DATA BYTE 1 (LSBs)
CONTROL REGISTER 1
CONTROL REGISTER 2
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x800
0x000
0x000
0x000
Data Registers
The five 12-bit data registers banks comprise two 8-bit registers for 8 MSBs and 4 LSBs. The 12-bit data is split
between the two 8-bit data bytes as seen in Figure 1. They are read-only registers that hold the converted data. Do not
issue a STOP command until both bytes are read. Instead use a Repeated START command to read the second byte.
Byte 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MSB12
MSB11
MSB10
MSB09
MSB08
MSB07
MSB06
MSB05
Byte 2
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB05
LSB03
LSB02
LSB01
0
0
0
0
Control Register 1
Control Register 1 is an 8-bit write/read register that configures the MAX9611/MAX9612 for different modes of opera-
tion. Tables 4 and 5 show the bit location and function for Control Register 1.
Table 4. Control Register 1 Bit Location
BIT NUMBER
7
MODE2
0
6
MODE1
0
5
MODE0
0
4
LR
0
3
SHDN
0
2
MUX2
0
1
MUX1
0
0
MUX0
0
BIT NAME
POR VALUE
______________________________________________________________________________________ 15
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Table 5. Control Register 1 Bit Description
BIT
BIT NAME
FUNCTION
000 Channel A: Read current-sense amplifier output from ADC, gain = 1x
001 Channel A: Read current-sense amplifier output from ADC, gain = 4x
010 Channel A: Read current-sense amplifier output from ADC, gain = 8x
011 Channel B: Read average voltage of RS+ (input common-mode voltage) from ADC
100 Channel C: Read voltage of OUT from ADC
MUX2, MUX1,
MUX0
2, 1, 0
101 Channel D: Read voltage of SET from ADC
110 Channel E: Read internal die temperature from ADC
111 Read all channels in fast-read mode, sequentially every 2ms. Uses last gain setting.
Power-on state = 0
0 = Normal operation
1 = Shutdown mode
3
4
SHDN
LR
0 = Normal operation
1 = Reset if comparator is latched due to MODE = 111. This bit is automatically reset after a
1 is written.
000 = Normal operation for op amp/comparator
111 = Comparator mode. OUT remains low until CSA output > V
for 1ms, OUT latches
SET
high for 50ms, then OUT autoretries by going low. The comparator has an internal
±10mV hysteresis voltage to help with noise immunity. For MAX9612, the polarity is
reversed.
MODE2, MODE1,
MODE0
7, 6, 5
011 = Op-amp mode. OUT regulates pFET for 1ms at V , OUT latches high for 50ms,
SET
then OUT autoretries by going low. For MAX9612, the polarity is reversed.
Control Register 2
Control Register 2 is an 8-bit write/read register that provides the different time delay options for asserting the com-
parator output when monitoring fault events. Tables 6 and 7 show the bit location and function for Control Register 2.
Table 6. Control Register 2
BIT NUMBER
7
X
0
6
X
0
5
X
0
4
X
0
3
DTIM
0
2
RTIM
0
1
X
0
0
X
0
BIT NAME
POR VALUE
Table 7. Control Register 2 Bit Descriptions
BIT
BIT NAME
FUNCTION
7, 6, 5, 4
X
Set to 0
Watchdog delay time
0 = 1ms
3
DTIM
1 = 100Fs
Watchdog retry delay time
0 = 50ms
1 = 10ms
2
RTIM
X
1, 0
Set to 0
16 _____________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Choose a suitable sense resistor and a low RDS-on pFET to
ensure the best efficiency during normal operation. Choose
a pFET with large power dissipation to ensure compliance
with safe operating area of the pFET. The MAX9611 comes
equipped with a variety of watchdog options to help with
this design (see Control Register 2, Table 7).
Power-On Reset
The MAX9611/MAX9612 include power-on reset cir-
cuitry that ensures all registers reset to a known state on
power-up. Once V
goes above 2.4V, the POR circuit
CC
releases the registers for normal operation.
Applications Information
Choose resistor values R1 and R2 to ensure that the
pFET is fully on in normal operating conditions and to
ensure that the VGS maximum rating is not exceeded.
Also, R1 and R2 help limit the current in the open-drain
Inrush Current Limiter
The MAX9611 can be used as an inrush current limiter
for a number of applications as shown in Figure 3. Note
that the sense resistor can be placed on either side of
the pFET. Since the input common-mode voltage of the
MAX9611 extends to ground, the sense resistor can be
placed at the load side as well, allowing current to be
sensed even when there is a dead-short on the load.
output stage of the internal op amp. R
and C
COMP
COMP
help roll-off high-frequency gain of the feedback control
system. R2 and C set a pole, for which 10kHz is a
COMP
good choice. R
and C
set a zero, for which
COMP
COMP
100kHz is a good choice.
With the internal gain of the current-sense amplifier
(2.5V/V), the inrush current-limit threshold can be set
using resistor-divider R3 and R4 as follows:
The inrush current limiting circuit reads and measures
the load-current during normal operation and can limit
the load current to a user-set value. In normal operation,
the load current is below the set threshold. The pFET
is fully turned on because the op-amp output is at 0V.
In the event of an overcurrent situation at the load, the
op-amp controls the pFET’s gate-voltage so it transitions
to a linear region, thus limiting the load current. In this
case, the op-amp output voltage is between 0V and
V
×R3
CC
(
= I
LIMIT
R2 + R3 2.5×R
(
)
)
SENSE
Note: The inrush current limiter can be changed to a
high-side relay-disconnect circuit by using the MAX9611
set to comparator mode (MODE 111).
V , as required for current-limiting.
BAT
INRUSH CURRENT LIMITER
R
SENSE
V
C
COMP
BAT
R2
P
RS+
RS-
2.7V TO 5.5V
R
COMP
LOAD
V
A0
A1
CC
0.1µF
R1
R4
MAX9611
OUT
SET
2
I C CLOCK
INPUT
0.1µF
1µF
SCL
SDA
2
I C DATA
R3
INPUT/OUTPUT
GND
(OUTPUT SET TO OP-AMP MODE)
Figure 3. Inrush Current Limiter
______________________________________________________________________________________ 17
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
When the OUT open-dran transistor is off, the gate volt-
age of the PA FET is:
Base-Station PA Gain Control
While the MAX9611 is designed to control high-side
pFETs, the MAX9612 can be similarly used to control
low-side nFETs. For example the MAX9612 can be used
to control the DC bias point of power amplifier LDMOS
or GaN nFETs in base-station applications. The circuit
shown in Figure 4 also allows the option to apply nega-
tive bias voltages to the PA FET, which is required for
certain types of transistors for proper operation.
V
R2 + R3
V
R1
(
)
NEG
CLAMP
V
=
+
GATE
R1+ R2 + R3
R1+ R2 + R3
R
COMP
and C
COMP
connected to the OUT pin compen-
sate the internal amplifier. Choose a corner frequency
of 100kHz.
In the circuit shown, the nFET is in a linear mode of
operation to allow it to amplify high-frequency RF sig-
nals, while the MAX9612 sets the DC operating point.
The gain of the FET can be varied by changing its drain
current. This operating point can be varied by an exter-
nal DAC voltage that feeds the SET pin.
Choose suitable R
as required for the application.
SENSE
The inductor isolates the DC measuring point of current
from the high-frequency AC signals through the PA FET,
as well as helping with the high-frequency gain.
Power-Supply Bypassing and Grounding
The MAX9611/MAX9612 share a common ground pin
for both the analog and digital on-chip circuitry. It is
therefore very important to properly bypass the V
GND, and to have a solid low-noise ground plane on the
circuit board so as to minimize ground bounce. Bypass
V
NEG
and V
together with R1, R2, and R3 set the
CLAMP
DC bias point limits for the PA transistor. V
is a
CLAMP
to
CC
suitable positive voltage and V
is a suitable nega-
NEG
tive voltage. When V
PA FET is:
= 0V, the gate voltage of the
OUT
V
CC
to GND with low ESR 0.1FF in parallel with a 4.7FF
ceramic capacitors to GND placed as close as possible
to the device.
V
×R2
NEG
= V
OUT
R1+ R2
(
)
Chip Information
PROCESS: BiCMOS
BASE-STATION PA GAIN CONTROL
2.7V TO 5.5V
RS-
RS+
RF
OUT
V
A0
A1
CC
C
IN
V
CLAMP
R3
2
MAX9612
I C CLOCK
SCL
SDA
R2
N
INPUT
OUT
2
I C DATA
INPUT/OUTPUT
R
R1
COMP
10-BIT
DAC
SET
C
COMP
V
NEG
GND
RF
IN
(OUTPUT SET TO OP-AMP MODE)
Figure 4. Base-Station PA Gain Control
18 _____________________________________________________________________________________
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0061
LAND PATTERN NO.
90-0330
10 FMAX
U10+2
α
α
______________________________________________________________________________________ 19
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
2
9/10
Initial release
—
16
11/10
1/11
Updated text in Table 5 to add “comparator” to mode 000 for bits 7, 6, 5
Relaxed room temperature limits for 4x and 8x gains from 0.3mV to 0.5mv
1, 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
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