MAX9667 [MAXIM]
6/8/10-Channel, 10-Bit, Nonvolatile Programmable Gamma and VCOM Reference Voltages;
| 型号： | MAX9667 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 6/8/10-Channel, 10-Bit, Nonvolatile Programmable Gamma and VCOM Reference Voltages |
| 文件： | 总41页 (文件大小：1304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5000; Rev 4; 7/10
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
General Description
Features
The MAX9665/MAX9666/MAX9667 provide multiple
programmable reference voltages for gamma correc-
tion in TFT LCDs and a programmable reference volt-
age for VCOM adjustment. All gamma and VCOM
reference voltages have a 10-bit digital-to-analog con-
verter (DAC) and buffer with high peak current. This
reduces the recovery time of the output voltage when
critical levels and patterns are displayed.
o 6/8/10 Channels Gamma Correction, 10-Bit
Resolution
o VCOM Driver
o Integrated Multiple-Time Programmable Memory
o DAC Reference Input
o Single-Wire and I2C Programming of VCOM
These devices include multiple-time programmable
(MTP) memory to store gamma and VCOM codes on
the chip, eliminating the need for external EEPROM.
The MTP memory supports up to 300 write operations.
Reference
o 950mA Peak Transient Current on VCOM Channel
The MAX9665/MAX9666/MAX9667 feature an I2C inter-
face to control the programmable reference voltages
and a single-wire interface to toggle the VCOM refer-
ence voltage up or down.
Functional Diagrams
AVDD
REF
Applications
TFT LCDs
10
OUT0
OUT1
OUT2
DAC
Ordering Information
GAMMA
CHANNELS
PIN-
PACKAGE
10
10
10
DAC
DAC
DAC
PART
TEMP RANGE
MAX9665ETP+
MAX9666ETP+
MAX9667ETP+
6
8
-40°C to +85°C 20 TQFN-EP*
-40°C to +85°C 20 TQFN-EP*
-40°C to +85°C 20 TQFN-EP*
10
2
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
OUT3
I C
MTP
MEMORY
REGISTERS
Pin Configurations
10
10
OUT4
OUT5
DAC
DAC
TOP VIEW
15
14
13
12
11
OUT3
N.C.
10
9
REF 16
AVDD 17
18
VCOM
FB
10
DAC
8
FB
VCOM 19
20
OUT4
N.C.
DVDD
SCL
MAX9665
2
I C
SDA
7
CE
MAX9665
CTL
6
OUT5
SINGLE-WIRE
INTERFACE
CTL
EP*
5
+
GND
1
2
3
4
Functional Diagrams continued at end of data sheet.
THIN QFN
5mm x 5mm
*EP = EXPOSED PAD. CONNECT TO DIGITAL GROUND PLANE.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Continuous Power Dissipation (T = +70°C)
A
AVDD to GND.....................................................-0.3V to +22V
DVDD to GND.......................................................-0.3V to +4V
Outputs
20-Pin TQFN (derate 25.6mW/°C above +70°C) ....2051.3mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
20-Pin TQFN...................................................................6°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
OUT0–OUT9, VCOM to GND .............-0.3V to (V
+ 0.3V)
AVDD
Inputs
20-Pin TQFN.................................................................39°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
SDA, SCL, CE to GND..........................................-0.3V to +4V
CTL, REF to GND ...............................................-0.3V to +22V
FB to GND ..........................................-0.3V to (V
Continuous Current
+ 0.3V)
AVDD
OUT0–OUT9, VCOM................................................... 400mA
All Other Pins................................................................ 50mA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
AVDD
REF
DVDD
GND A
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Guaranteed by power-supply rejection
ratio specification (Note 3)
Analog-Supply Voltage Range
V
9
20
20
V
AVDD
5/MAX967
Analog-Supply Voltage Range for
Programming MTP
V
15
V
V
AVDD_MTP
Digital-Supply Voltage Range
Analog Quiescent Current
V
I
2.7
3.6
22
DVDD
MAX9665
12
14
mA
MAX9666
24
AVDD
MAX9667
16
26
Digital Quiescent Current
DVDD Undervoltage Lockout
DAC
I
No SCL or SDA transitions
450
2.3
900
2.6
µA
V
DVDD
UVLO
Resolution
10
Bits
LSB
LSB
kΩ
Integral Nonlinearity Error
Differential Nonlinearity Error
REF Input Resistance
GAMMA OUTPUTS (Note 4)
Short-Circuit Current
Maximum Capacitive Load
Output Impedance
Load Regulation
INL
T
T
= +25°C, 16 ≤ CODE ≤ 1008
= +25°C, 16 ≤ CODE ≤ 1008
1
1
A
DNL
A
384
I
SC
Output to AVDD or GND, T = +25°C
A
100
-40
400
300
84
mA
pF
Placed directly at output
Output resistance when output is disabled
-5mA to +5mA
Z
kΩ
O
R
0.5
mV/mA
mV
EG
Total Output Error
T
= +25°C, measured at code = 512
+40
A
Slew Rate
SR
5V swing, measure 10% to 90%
22
V/µs
2
_______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
AVDD
REF
DVDD
GND A
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
Low Output Voltage
SYMBOL
CONDITIONS
Sinking 4mA, T = +25°C
MIN
TYP
MAX
UNITS
V
MIN
0.1
0.15
V
A
V
V
AVDD
AVDD
- 0.1
High Output Voltage
V
MAX
Sourcing 4mA, T = +25°C
A
V
- 0.15
To AVDD, f = 60kHz, REF and AVDD shorted
40
90
80
Power-Supply Rejection Ratio
PSRR
dB
dB
9V < V
< 20V, V
= 9V
REF
60
50
AVDD
Channel-to-Channel Isolation
GAMMA OUTPUTS (Note 5)
Short-Circuit Current
Maximum Capacitive Load
Output Impedance
C
f = 5MHz, all channels to all channels
XTLK
I
Outputs to AVDD or GND, T = +25°C
A
200
300
84
mA
pF
SC
Placed directly at output
Z
Output resistance when output is disabled
-5mA to +5mA
kΩ
O
Load Regulation
R
0.50
mV/mA
mV
EG
Total Output Error
T
= +25°C, measured at code = 512
-40
+40
0.2
A
Swing 5V
at input, 10% to 90%
P-P
Slew Rate
SR
22
V/µs
V
measurement on output
Low Output Voltage
High Output Voltage
V
MIN
Sinking 4mA
0.15
V
-
V
AVDD
- 0.15
AVDD
0.2
V
MAX
Sourcing 4mA
V
To AVDD, f = 60kHz, REF and AVDD shorted
40
90
Power-Supply Rejection Ratio
PSRR
dB
9V < V
< 20V, V
= 9V
REF
60
AVDD
Thermal Shutdown
160
15
°C
°C
dB
Thermal-Shutdown Hysteresis
Channel-to-Channel Isolation
VCOM OUTPUT
C
f = 5MHz, all channels to all channels
80
XTLK
Short-Circuit Current
Maximum Capacitive Load
Output Impedance
I
Outputs to AVDD or GND, T = +25°C
A
50
200
300
84
mA
pF
SC
Placed directly at output
Z
Output resistance when output is disabled
-5mA to +5mA
kΩ
O
Load Regulation
R
0.2
1
mV/mA
mV
EG
Total Output Error
T
= +25°C, measured at code = 512
-50
+50
0.2
A
Swing 4V at VCOM, 10% to 90%,
P-P
Slew Rate
SR
100
V/µs
V
R = 10kΩ, C = 50pF (Note 6)
L
L
Low Output Voltage
High Output Voltage
V
MIN
Sinking 4mA
0.15
V
V
AVDD
- 0.15
AVDD
- 0.2
V
MAX
Sourcing 4mA
V
To AVDD, f = 60kHz, REF and AVDD shorted
40
Power-Supply Rejection Ratio
PSRR
dB
9V < V
< 20V, V
= 9V
REF
70
AVDD
_______________________________________________________________________________________
3
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
AVDD
REF
DVDD
GND A
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-WIRE INTERFACE
0.3 x
CE Input Low Voltage
2.6V < V
< 3.6V
< 3.6V
V
DVDD
V
DVDD
0.7 x
CE Input High Voltage
CE Startup Time
2.6V < V
(Note 7)
V
DVDD
V
DVDD
1
ms
0.7 x
0.82 x
V
DVDD
CTL High Voltage
CTL Float Votlage
2.6V < V
< 3.6V
< 3.6V
V
V
DVDD
V
DVDD
0.4 x
0.62 x
V
DVDD
2.6V < V
DVDD
V
DVDD
0.2 x
0.32 x
V
DVDD
CTL Low Voltage
2.6V < V
< 3.6V
V
DVDD
V
DVDD
CTL Rejected Pulse Width
CTL Typical Pulse Width
20
µs
µs
µs
µs
50
CTL Minimum Pulse Width
CTL Minimum Time Between Pulses
200
10
CTL = GND
-10
5/MAX967
CTL Input Current
µA
CTL = DVDD
+10
LOGIC INPUTS AND OUTPUTS (SDA, SCL)
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
V
DVDD
0.3 x
V
IL
V
DVDD
Input Leakage Current
Input Capacitance
I
, I
V
= 0V or V
DVDD
-10
-10
+0.01
5
+10
µA
pF
µA
V
IH IL
SDA/SCL
(Note 7)
= 0V, V = 1.98V
SDA/SCL
Power-Down Input Current
SDA Output Low Voltage
I
V
+10
0.4
SDA/SCL
DVDD
V
I
= 6mA
OL
SINK
4
_______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
AVDD
REF
DVDD
GND A
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C TIMING CHARACTERISTICS (Figure 4)
Serial-Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
Hold Time (Repeated) START
Condition
t
t
0.6
µs
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
µs
SU,STA
Data Hold Time
Data Setup Time
t
0
900
ns
ns
HD,DAT
t
100
SU,DAT
SDA and SCL Receiving Rise
Time
20 +
t
(Note 8)
(Note 8)
(Note 8)
300
300
250
ns
ns
ns
R
0.1C
B
SDA and SCL Receiving Fall
Time
20 +
0.1C
t
F
B
20 +
SDA Transmitting Fall Time
t
F,TX
0.1C
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
µs
pF
ns
SU,STO
C
400
50
B
Pulse Width of Suppressed Spike
t
0
SP
Note 2: All devices are 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 3: For AVDD below 15.6V, internal LDO must be externally adjusted to meet LDO dropout specification.
Note 4: This section applies to OUT0, OUT2, OUT3, and OUT5 of the MAX9665; OUT0, OUT3, OUT4, and OUT7 of the MAX9666;
OUT0, OUT4, OUT5, and OUT9 of the MAX9667.
Note 5: This section applies to OUT1 and OUT4 of the MAX9665; OUT1, OUT2, OUT5, and OUT6 of the MAX9666; OUT1, OUT2,
OUT3, OUT6, OUT7, and OUT8 of the MAX9667.
Note 6: Measured with the VCOM amplifier configured as an inverting unity-gain amplifier. R = R = 10kΩ.
F
IN
Note 7: Guaranteed by design. Not production tested.
Note 8: C is in pF.
B
_______________________________________________________________________________________
5
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Typical Operating Characteristics
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
GND A
AVDD
REF
DVDD
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
OUTPUT OFFSET
VOLTAGE DISTRIBUTION
VCOM LOAD REGULATION
GAMMA LOAD REGULATION
20
15
10
5
30
25
20
15
10
5
20
15
10
5
CODE 512
OUT2
0
0
-5
-5
-10
-15
-20
-10
-15
-20
0
-20 -15 -10 -5
0
5
10 15 20
-28
-12 -4
4
12
20
28
-20
-20 -15 -10 -5
0
5
10 15 20
LOAD CURRENT (mA)
OUTPUT OFFSET (mV)
LOAD CURRENT (mA)
INTEGRAL NONLINEARITY
vs. DAC CODE
INTEGRAL NONLINEARITY
vs. DAC CODE
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
REF
= 15.7V
V
REF
= 15.7V
5/MAX967
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
OUT2
128 256 384 512 640 768 896 1024
VCOM
0
0
128 256 384 512 640 768 896 1024
DAC CODE
DAC CODE
INTEGRAL NONLINEARITY
vs. DAC CODE
INTEGRAL NONLINEARITY
vs. DAC CODE
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
= 10V
V
REF
= 10V
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
OUT2
VCOM
0
128 256 384 512 640 768 896 1024
DAC CODE
0
128 256 384 512 640 768 896 1024
DAC CODE
6
_______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Typical Operating Characteristics (continued)
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
GND A
AVDD
REF
DVDD
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
INTEGRAL NONLINEARITY
vs. DAC CODE
INTEGRAL NONLINEARITY
vs. DAC CODE
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
= 5V
V
= 5V
V
= 15.7V
REF
REF
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
OUT2
128 256 384 512 640 768 896 1024
VCOM
OUT2
0
0
128 256 384 512 640 768 896 1024
DAC CODE
0
128 256 384 512 640 768 896 1024
DAC CODE
DAC CODE
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
REF
= 10V
V
= 15.7V
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
OUT2
128 256 384 512 640 768 896 1024
VCOM
0
0
128 256 384 512 640 768 896 1024
DAC CODE
DAC CODE
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
= 10V
V
REF
= 5V
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
VCOM
128 256 384 512 640 768 896 1024
DAC CODE
OUT2
128 256 384 512 640 768 896 1024
DAC CODE
0
0
_______________________________________________________________________________________
7
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Typical Operating Characteristics (continued)
(V
= V
= 15.7V, V
= 3.3V, V
= 0V, VCOM connected to FB, CTL = DVDD/2, no load, T = -40°C to +85°C, unless
GND A
AVDD
REF
DVDD
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
DIFFERENTIAL NONLINEARITY
vs. DAC CODE
POWER-SUPPLY REJECTION RATIO
OF GAMMA OUTPUTS vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
OF VCOM vs. FREQUENCY
0.25
0.20
0.15
0.10
0.05
0
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
V
= 5V
REF
V
AVDD
= V = 15.7V 100mV
REF P-P
V
= V = 15.7V 100mV
REF P-P
AVDD
-0.05
-0.10
-0.15
-0.20
-0.25
VCOM
128 256 384 512 640 768 896 1024
0
10k
100k
1M
10M
10k
100k
1M
10M
DAC CODE
FREQUENCY (Hz)
FREQUENCY (Hz)
REF POWER-SUPPLY REJECTION RATIO
OF GAMMA OUTPUTS vs. FREQUENCY
REF POWER-SUPPLY REJECTION RATIO
OF VCOM vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
V
= 15.7V 100mV
P-P
REF
V
= 15.7V 100mV
REF P-P
5/MAX967
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
VCOM LOAD TRANSIENT (±ꢁ110Aꢀ
GAMMA LOAD TRANSIENT (±±110Aꢀ
MAX9665 toc21
MAX9665 toc20
VCOM OUTPUT
500mV/div
GAMMA OUTPUT0
500mV/div
VCOM LOAD CURRENT
200mA/div
GAMMA LOAD CURRENT
100mA/div
2µs/div
2µs/div
8
_______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Pin Description
PIN
NAME
FUNCTION
MAX9665
MAX9666
MAX9667
Single-Wire Control Interface Enable. Connect CE to DVDD to
enable the CTL input. Connect CE to GND to disable the CTL
input and reduce the supply current.
1
1
1
CE
2
3
2
3
2
3
DVDD
SCL
Digital Supply Input. Bypass to GND with 0.1µF capacitor.
2
I C Serial-Clock Input
2
4
4
4
SDA
I C Serial-Data Input/Output
5
5
5
GND
Ground
—
—
—
—
6
—
—
6
6
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
REF
Gamma Output 9
Gamma Output 8
Gamma Output 7
Gamma Output 6
Gamma Output 5
Gamma Output 4
Gamma Output 3
Gamma Output 2
Gamma Output 1
Gamma Output 0
Reference Input
7
8
7
9
8
10
11
12
13
14
15
16
8
10
11
13
14
15
16
10
11
13
15
16
Analog Supply Input. Bypass AVDD to GND with a minimum
0.1µF capacitor.
17
17
17
AVDD
18
19
18
19
18
19
FB
VCOM Amplifier Negative Input
VCOM Amplifier Output
VCOM
VCOM Adjustment and Multiple-Time Programmable Memory
Control. CTL sets the internal DAC code and programs the
MTP memory. A pulse-control method is used to adjust the
VCOM level. See the VCOM Adjustment (CTL) section. To
program the DAC setting into the MTP memory as the power-
on default, drive CTL to the MTP programming voltage using
the correct timing and voltage ramp rates. See the MTP
Programming (CTL) section.
20
20
20
CTL
7, 9, 12, 14
—
9, 12
—
—
—
N.C.
EP
No Connection. Not internally connected.
Exposed Pad. The exposed pad must be connected to GND.
_______________________________________________________________________________________
9
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Gamma Buffers
Detailed Description
There are two types of DAC output buffers: 5mA and
The MAX9665/MAX9666/MAX9667 are a family of multi-
10mA. The 5mA buffer is guaranteed to source or sink
channel, programmable reference voltages. Each
5mA of DC current within 0.2V of the supplies, and the
channel has a 10-bit DAC to create the reference volt-
10mA buffer does the same with 10mA. The 10mA
age. One channel has an operational amplifier that fol-
buffers should be attached to the ends of the resistor
lows the DAC while all other channels have a buffer
ladders that set the transfer function of the source dri-
after the DAC. The user can program the DAC codes
ver (look at the connections from OUT0, OUT4, OUT5,
into on-chip nonvolatile memory, which is called multi-
and OUT9 on the typical operating circuit of the
ple-time programmable (MTP) memory since data can
MAX9667). The 5mA buffers should be attached to the
be written into it up to 300 times.
middle tap points of the resistor ladder because those
The MAX9665/MAX9666/MAX9667 provide the gamma,
VCOM, and level shifter reference voltages in a LCD
panel. A single chip can potentially replace a discrete
digital variable resistor (DVR), VCOM amplifier, gamma
buffers, high-voltage linear regulator, and resistor
strings. The high-voltage linear regulator can be elimi-
nated because the DAC contains a lowpass filter that
reduces horizontal line frequency noise by 40dB. Power
sequencing is well-controlled since a single chip gener-
ates all the various reference voltages needed for the
LCD panel.
Each part has an I2C interface for programming both
the MTP memory and the I2C registers. For compatibili-
ty with legacy flicker adjustment production equipment,
these devices include a single-wire interface that is
compatible with the MAX1512.
places require less current than the ends (see the con-
nections from OUT1, OUT2, OUT7, and OUT8 on the
typical operating circuit of the MAX9667).
If the 10mA buffers cannot provide enough current to
drive the ends of the resistor ladders, attach an addi-
tional resistor from the nearest supply. For example, at
the very top of the resistor ladder, attach an additional
resistor to AVDD. At the very bottom of the resistor lad-
der, attach an additional resistor to GND. The
MAX9665/MAX9666/MAX9667 greatly diminish any
noise from the AVDD supply through the discrete resis-
tor because the high-frequency noise from REF has
been attenuated, and the buffers have excellent AC
PSRR. See Figure 1.
The source drivers can kick back a great deal of cur-
rent to the buffer outputs during a horizontal line
change or a polarity switch. The 5mA DAC output
buffers can source/sink 200mA of peak transient cur-
rent, and the 10mA DAC output buffers can source/sink
400mA of peak transient current to reduce the recovery
time of the output voltages when critical levels and pat-
terns are displayed.
With the MTP memory and the I2C interface, these
devices enable automatic gamma and flicker calibra-
tion on a panel-by-panel basis on the production line.
Contact your Maxim representative for more details.
5/MAX967
10-Bit Digital-to-Analog Converters
The reference input, REF, accepts a DC voltage
between ground (GND) and the analog supply voltage
(AVDD). The voltage at REF sets the full-scale output of
the DACs. Determine the output voltage using the fol-
lowing equations:
VCOM Amplifier
The operational amplifier attached to the bottom DAC
holds the VCOM voltage stable while providing the abil-
ity to source and sink 400mA into the backplane of a
TFT-LCD panel. The operational amplifier can directly
drive the capacitive load of the TFT-LCD backplane
without the need for a series resistor in most cases. The
VCOM amplifier has current limiting on its output to pro-
tect its bond wires.
V
OUT
= (V
x CODE)/2N
REF
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX9665 family, N = 10 and CODE ranges from 0 to
1023.
The output (VCOM) and negative input (FB) of the oper-
ational amplifier are typically connected together in a
unity-gain configuration. If higher output current is
required, add an npn emitter follower and a pnp emitter
follower in the feedback loop.
Note that even if REF is less than AVDD, the DAC can
never output REF because the maximum value of
CODE is always one LSB less than the reference. For
example, if REF = 16V and CODE = 1023, then the out-
put voltage is:
If a higher, closed-loop gain is desired, add feedback
resistors as shown in Figure 2.
V
OUT
= (16V x 1023)/210
= 15.98438V
10 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
AVDD
AVDD
REF
10
10
10
10
OUT0
OUT1
OUT2
OUT3
OUT4
DAC
DAC
DAC
DAC
10
10
10
10
DAC
SOURCE
DRIVER
LCD PANEL
2
OUT5
I C
MTP
MEMORY
DAC
DAC
DAC
DAC
DAC
DAC
REGISTERS
OUT6
OUT7
10
OUT8
OUT9
10
10
+
-
VCOM
FB
DVDD
SCL
2
I C
LEVEL
SHIFTER
SDA
CE
CTL
GND
MAX9667
SINGLE-WIRE
INTERFACE
Figure 1. Pullup and Pulldown Resistors Attached to Source Driver
______________________________________________________________________________________ 11
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Multiple-Time Programmable (MTP)
Memory
MTP memory, which is a form of nonvolatile memory,
VCOM
stores the DAC code values even when the chip is not
powered. When the chip is powered up, the code val-
ues are automatically transferred from MTP memory to
the I2C registers. See the Power-On Reset (POR)/
Power-Up section for more details.
FB
The user can program DAC codes into MTP memory for
MAX9665
MAX9666
MAX9667
up to 300 times. In conventional TFT-LCD applications, a
resistor string creates the gamma voltages. MTP memory
eliminates the resistor string and the need to change
manually the resistor values when searching for the opti-
Figure 2. VCOM Operational Amplifier with Feedback Resistors
mal gamma curve for a new TFT-LCD panel model.
Power-On Reset (POR)/Power-Up
Digital Interfaces
The POR circuit that monitors DVDD ensures that all I2C
registers are reset to their MTP values upon power-up
or POR. Once DVDD rises above 2.4V (typ), the POR
circuit releases the I2C registers and the values stored
in MTP are loaded. Should DVDD drop to less than 2.4V
typical, then the contents of the registers can no longer
be guaranteed and a reset is generated. When DVDD
rises back above the POR voltage, the values stored in
MTP are loaded back into the I2C registers.
The MAX9665/MAX9666/MAX9667 have two digital
interfaces: I2C and single-wire. Through the I2C inter-
face, the user can change all the registers and program
MTP memory. The I2C interface is the more general pur-
pose of the two interfaces.
The single-wire interface, which is compatible with the
MAX1512 digital interface, is included to support TFT-
LCD production lines that depend upon the single-wire
interface to adjust the VCOM voltage to minimize flick-
er. Note that the single-wire interface cannot program
the gamma registers or gamma MTP memory.
The transfer time of the MTP registers to I2C registers is
300µs typical and is less than 400µs in the worst case.
During this time, AVDD should not be powered up, and
the I2C does not acknowledge any commands (the I2C
only starts acknowledging commands after all registers
have been loaded from MTP).
5/MAX967
Interoperability Between the Single-Wire
Interface and the I2C Interface
To prevent any collision between the single-wire inter-
face and the I2C interface, operation through one inter-
face is only allowed if the other is in the idle state. For
example, if the I2C interface is in the middle of execut-
ing a command, any input through the single-wire inter-
face is ignored. Conversely, if the single-wire interface
is in the middle of executing a command, the I2C inter-
face does not acknowledge any commands.
Thermal Protection
When the die temperature reaches +165°C, all gamma
buffers except for the middle ones are disabled. See
Table 1.
When the die cools down by 15°C, all the buffers are
enabled again.
The VCOM operational amplifier does not have thermal
protection.
Table 1. Buffer Output Status During Thermal Shutdown
PART
ENABLED
DISABLED
MAX9665
MAX9666
MAX9667
OUT2 and OUT3
OUT3 and OUT4
OUT4 and OUT5
OUT0, OUT1, OUT4, OUT5
OUT0, OUT1, OUT2, OUT5, OUT6, OUT7
OUT0, OUT1, OUT2, OUT3, OUT6, OUT7, OUT8, OUT9
12 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
VCOM WINDOW
REGISTERS
VCOM WINDOW
MTP MEMORY
2
2
VCOM MTP MEMORY
LOCATION 0b0011
VCOM I C REGISTERS
GAMMA I C REGISTERS
GAMMA MTP MEMORY
LOCATION 0b0101
LOCATION
0b0000
LOCATION
0b0001 LOCATION
0b0010
LOCATION 0b0100
10-BIT BUS
BUS MASTER
2
I C INTERFACE
SINGLE-WIRE INTERFACE
Figure 3. 10-Bit Bus
Bus Architecture
VCOM MTP Programming
The internal memory, both volatile and nonvolatile, is
divided into blocks that are connected by a 10-bit bus
(Figure 3).
Through the I2C Interface
To program VCOM MTP memory, the I2C master must
first write the DAC code that is to be stored into the
VCOM I2C registers. Next, the I2C master must send a
command to move the data in the VCOM I2C registers
to the VCOM MTP memory, thereby finishing the pro-
gramming.
The I2C registers (volatile memory) are 8 bits wide. Two
I2C registers are needed to hold one 10-bit DAC code.
The I2C registers are separated into blocks that are dis-
tinguished by whether they hold VCOM DAC codes or
gamma DAC codes. MTP memory (nonvolatile memory)
is organized in the same manner. The VCOM MTP
memory has enough bits to store the single VCOM DAC
code. Likewise, the gamma MTP memory has enough
bits to store all of the gamma DAC codes. Each block
connected to the 10-bit bus has a unique location num-
ber with one exception. The block that contains the bus
master, I2C interface, and the single-wire interface does
not store any data, and hence, it does not have a loca-
tion number.
Although the external I2C interface transfers data in
units of 8 bits (1 byte), the internal bus that connects
the I2C registers, MTP memory, and digital interfaces is
10 bits wide because the DAC code size is 10 bits. The
10-bit bus can also accommodate data transfers of
fewer than 10 bits since communication to the outside
world is through either an 8-bit I2C interface or a 1-bit
single-wire interface. Writing a single byte to any
address location is ignored.
To read VCOM MTP memory, the I2C master must issue
a command to move the data in the VCOM MTP memo-
ry to the VCOM I2C registers. Then it can read the two
VCOM I2C registers.
To program gamma MTP memory, the I2C master must
first write the complete set of gamma DAC codes into
the gamma I2C registers. For example, six gamma DAC
codes must be written into the MAX9665 since it has six
gamma outputs. Next, the I2C master must send a com-
mand to move the data in the gamma I2C registers to
the gamma MTP memory.
To read gamma MTP memory, the I2C master must
issue a command to move the data in the gamma MTP
memory to the gamma I2C registers. Then it can read
the gamma I2C registers.
During MTP programming, the parts do not respond to
the I2C interface. The part generates an acknowledge
to the MTP programming command, but the I2C inter-
face does not generate further acknowledge signals
until MTP programming is complete.
The 10-bit bus connects together registers, MTP memo-
ries, and digital interfaces. The bus master resides in
the same block as the I2C interface and the single-wire
interface.
If the analog supply voltage is not greater than the mini-
mum required for MTP programming, the I2C still
acknowledges the MTP write command, but MTP pro-
gramming is disabled. The I2C continues to acknowl-
edge and process non-MTP write commands.
See the Register Description section for further expla-
nation on how to execute commands.
______________________________________________________________________________________ 13
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
SDA
t
BUF
t
t
SU,STA
SU,DAT
t
t
SP
HD,STA
t
t
SU,STO
t
HD,DAT
LOW
SCL
t
HIGH
t
HD,STA
t
R
t
F
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
START
CONDITION
2
Figure 4. I C Serial-Interface Timing Diagram
Through the Single-Wire Interface
For VCOM MTP programming through the single-wire
interface, see the Single-Wire Interface section.
acknowledges receipt of each byte of data. Each read
sequence is framed by a START or REPEATED START
condition, a not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on the SDA bus. SCL operates as only an
input. A pullup resistor, typically greater than 500Ω, is
required on SCL if there are multiple masters on the bus,
or if the master in a single-master system has an open-
drain SCL output. Series resistors in line with SDA and
SCL are optional. Series resistors protect the digital
inputs of the devices from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
VCOM Programming Range
Two registers, VCOMMIN and VCOMMAX, are provided
to set the minimum and maximum VCOM register value.
These two registers are accessed through the I2C inter-
face and can be written to and read from MTP memory.
If any adjustment, either through I2C or the single-wire
interface takes the VCOM register value less than
VCOMMIN, then the value in VCOMMIN is stored in the
VCOM register. Similarly, if any adjustment, either
5/MAX967
2
through I C or the single-wire interface takes the VCOM
register value greater than VCOMMAX, then the value
in VCOMMAX is stored in the VCOM register.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
I2C Interface
The MAX9665/MAX9666/MAX9667 feature an I2C/
SMBus™-compatible, 2-wire serial interface consisting
of a serial-data line (SDA) and a serial-clock line (SCL).
SDA and SCL facilitate communication between the
devices and the master at clock rates up to 400kHz.
Figure 4 shows the 2-wire interface timing diagram. The
master generates SCL and initiates data transfer on the
bus. A master device writes data to the devices by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9665/MAX9666/MAX9667 is
8 bits long and followed by an acknowledge clock
pulse. A master reading data from the devices transmits
the proper slave address followed by a series of nine
SCL pulses. The devices transmit data on SDA in sync
with the master-generated SCL pulses. The master
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 5). A
START condition from the master signals the beginning
of a transmission to the MAX9665/MAX9666/MAX9667.
The master terminates transmission, and frees the bus,
by issuing a STOP condition. The bus remains active if
a REPEATED START condition is generated instead of
a STOP condition.
SMBus is a trademark of Intel Corp.
14 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
CLOCK PULSE FOR
ACKNOWLEDGMENT
S
Sr
P
START
CONDITION
SCL
SDA
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 5. START, STOP, and REPEATED START Conditions
Figure 6. Acknowledge
Early STOP Conditions
The MAX9665/MAX9666/MAX9667 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. For proper operation, do not send a
STOP condition during the same SCL high pulse as the
START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9665/MAX9666/MAX9667 use to handshake
receipt of each byte of data when in write mode (see
Figure 6). The MAX9665/MAX9666/MAX9667 pull down
SDA during the entire master-generated ninth clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master may retry communication. The master
pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9665/
MAX9666/MAX9667 are in read mode. An acknowledge
is sent by the master after each read byte to allow data
transfer to continue. A not acknowledge is sent when
the master reads the final byte of data from the
MAX9665/MAX9666/MAX9667, followed by a STOP
condition.
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/W bit to 1 to configure the MAX9665/MAX9666/
MAX9667 to read mode. Set the R/W bit to 0 to config-
ure the MAX9665/MAX9666/MAX9667 to write mode.
The address is the first byte of information sent to the
MAX9665/MAX9666/MAX9667 after the START condi-
tion. The MAX9665/MAX9666/MAX9667 slave address
is 0x9E for writing and 0x9F for reading.
Table 2. Slave ID Description
WRITE ADDRESS
(hex)
READ ADDRESS
(hex)
B7
B6
B5
B4
B3
B2
B1
B0
1
0
0
1
1
1
1
R/W
0x9E
0x9F
______________________________________________________________________________________ 15
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Write Data Format
A write to the MAX9665/MAX9666/MAX9667 consists of
transmitting a START condition, the slave address with
the R/W bit set to 0, one data byte of data to configure
the internal register address pointer, one or more data
bytes, and a STOP condition. Figure 7 illustrates the
frame format for writing one byte of data to the
MAX9665/MAX9666/MAX9667.
Read Data Format
The master presets the address pointer by first sending
the MAX9665/MAX9666/MAX9667’s slave address with
the R/W bit set to 0 followed by the register address
after a START condition. The MAX9665/MAX9666/
MAX9667 acknowledge receipt of the slave address
and the register address by pulling SDA low during the
ninth SCL clock pulse. A REPEATED START condition
is then sent followed by the slave address with the R/W
bit set to 1. The MAX9665/MAX9666/MAX9667 transmit
the contents of the specified register. Transmitted data
is valid on the rising edge of the master-generated seri-
al clock (SCL). The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one
continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from the register address
location set by the previous transaction and not 0x00
and subsequent reads autoincrement the address
pointer until the next STOP condition. Attempting to
read from register addresses higher than the highest
valid address locations (0x13 for MAX9665, 0x17 for
MAX9666, 0x1B for MAX9667) in repeated reads from a
dummy register containing all one data. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figures 8
and 9 illustrate the frame format for reading data from
the MAX9665/MAX9666/MAX9667.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9665/
MAX9666/MAX9667. The MAX9665/MAX9666/MAX9667
acknowledge receipt of the address byte during the mas-
ter-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9665/MAX9666/MAX9667’s internal reg-
ister address pointer. The pointer tells the MAX9665/
MAX9666/MAX9667 where to write the next byte of
data. An acknowledge pulse is sent by the MAX9665/
MAX9666/MAX9667 upon receipt of the address
pointer data.
The third byte sent to the MAX9665/MAX9666/MAX9667
contains the data that is written to the chosen register.
An acknowledge pulse from the MAX9665/MAX9666/
MAX9667 signals receipt of the data byte. The address
pointer autoincrements to the next register address
after each received data byte. This autoincrement fea-
ture allows a master to write to sequential register
address locations within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition.
5/MAX967
16 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
ACKNOWLEDGE FROM MAX9665–MAX9667
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9665–MAX9667
ACKNOWLEDGE FROM MAX9665–MAX9667
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 7. Writing One Byte of Data to the MAX9665/MAX9666/MAX9667
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
A
P
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTO-INCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 8. Reading One Indexed Byte of Data from the MAX9665/MAX9666/MAX9667
ACKNOWLEDGE FROM MASTER
B7 B6 B5 B4 B3 B2 B1 B0
NOT ACKNOWLEDGE FROM MASTER
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
ACKNOWLEDGE FROM MAX9665/
MAX9666/MAX9667
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
A
A
DATA BYTE n
1 BYTE
DATA BYTE 1
1 BYTE
A
P
Sr
SLAVE ADDRESS
1
REPEATED START
R/W
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 9. Reading n Bytes of Indexed Data from the MAX9665/MAX9666/MAX9667
______________________________________________________________________________________ 17
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Register Map
The I2C interface was architected for 8-bit systems.
With the increase in DAC resolution from 8 bits to 10
bits, 2 bytes must be transferred to get 10 bits.
Therefore, the word size is 2 bytes (16 bits) in the regis-
ter map. Byte order is big endian. The least significant
byte (LSB) holds the bottom 8 bits of the 10-bit data,
while the most significant byte (MSB) holds the top 2
bits of the 10-bit data. The I2C stores each 10-bit DAC
code in two 8-bit registers, as shown in the register
maps of Tables 3, 4, and 5.
Table 3. Register Map for MAX9665
LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
COMMENTS
REGISTER
ADDRESS
0x01
REGISTER
ADDRESS
REGISTER NAME
REGISTER NAME
CMD_OPND
VCOMMIN_L
VCOMMAX_L
VCOM_L
0x00
CMD_OPRN
VCOMMIN_M
VCOMMAX_M
VCOM_M
Command
VCOM (minimum)
VCOM (maximum)
VCOM
0x03
0x05
0x07
0x09
0x0B
0x0D
0x0F
0x11
0x13
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
GMA0_L
GMA0_M
Gamma 0
GMA1_L
GMA1_M
Gamma 1
GMA2_L
GMA2_M
Gamma 2
GMA3_L
GMA3_M
Gamma 3
GMA4_L
GMA4_M
Gamma 4
GMA5_L
GMA5_M
Gamma 5
Table 4. Register Map for MAX9666
5/MAX967
LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
COMMENTS
REGISTER
REGISTER
ADDRESS
REGISTER NAME
ADDRESS
REGISTER NAME
0x01
0x03
0x05
0x07
0x09
0x0B
0x0D
0x0F
0x11
0x13
0x15
0x17
CMD_OPND
VCOMMIN_L
VCOMMAX_L
VCOM_L
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
CMD_OPRN
VCOMMIN_M
VCOMMAX_M
VCOM_M
GMA0_M
Command
VCOM (minimum)
VCOM (maximum)
VCOM
GMA0_L
Gamma 0
GMA1_L
GMA1_M
Gamma 1
GMA2_L
GMA2_M
Gamma 2
GMA3_L
GMA3_M
Gamma 3
GMA4_L
GMA4_M
Gamma 4
GMA5_L
GMA5_M
Gamma 5
GMA6_L
GMA6_M
Gamma 6
GMA7_L
GMA7_M
Gamma 7
18 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Table 5. Register Map for MAX9667
LEAST SIGNIFICANT BYTE
MOST SIGNIFICANT BYTE
COMMENTS
REGISTER
REGISTER
REGISTER NAME
REGISTER NAME
ADDRESS
0x01
0x03
0x05
0x07
0x09
0x0B
0x0D
0x0F
0x11
0x13
0x15
0x17
0x19
0x1B
ADDRESS
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
CMD_OPND
VCOMMIN_L
VCOMMAX_L
VCOM_L
GMA0_L
CMD_OPRN
VCOMMIN_M
VCOMMAX_M
VCOM_M
GMA0_M
Command
VCOM (minimum)
VCOM (maximum)
VCOM
Gamma 0
GMA1_L
GMA1_M
Gamma 1
GMA2_L
GMA2_M
Gamma 2
GMA3_L
GMA3_M
Gamma 3
GMA4_L
GMA4_M
Gamma 4
GMA5_L
GMA5_M
Gamma 5
GMA6_L
GMA6_M
Gamma 6
GMA7_L
GMA7_M
Gamma 7
GMA8_L
GMA8_M
Gamma 8
GMA9_L
GMA9_M
Gamma 9
Register Description
The form of the command is shown below:
The I2C registers either hold DAC codes or commands
(see Tables 6, 7, and 8). After power-up, the digital cir-
cuitry loads the values stored in MTP memory into the
VCOM and gamma registers. This process takes
approximately 350µs. During this time, the I2C does not
respond to any commands (either from the user or from
the single-wire interface). To ensure the gamma chip
does not reverse bias, the source driver, the VCOM
DAC code, and the gamma DAC codes upon power-up
are as shown in the Tables 6, 7, and 8.
The I2C master can write a command such as MOV
(move) into a pair of command registers. To execute a
valid command, the command operation (CMD_OPRN)
and command operand (CMD_OPND) registers must
be written to sequentially in the same I2C transaction
(between the same I2C start/stop).
Operation
Operands
To move data from gamma registers to gamma MTP
memory, use the following command (essentially, data
is being written into MTP memory):
MOV
MOV Gamma Registers
Gamma MTP
MOV is the operation. Gamma registers and gamma
MTP memory are operands. Both the operation and the
operands must be assembled into machine code that is
written into the command registers. The machine code
for the operation must be written into the command
operation register (CMD_OPRN). The machine code for
the operands (if there are any) must be written into
command operand register (CMD_OPND). Table 9
shows the list of operations and operands.
______________________________________________________________________________________ 19
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Table 6. MAX9665 Register Description
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Command
operation
Write
only
0x00
0x01
CMD_OPRN
CMD_OPND
d7 d6 d5 d4 d3 d2 d1 d0
d7 d6 d5 d4 d3 d2 d1 d0
0x00
0x00
Not applicable
Not applicable
Command
operand
Write
only
VCOMMIN
(most significant
byte)
Read
and
write
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
VCOMMIN_M
x
x
x
x
x
x
d9 d8
0x00
0x00
0x03
0xFF
0x02
0x00
0x03
0x80
0x03
0x00
0x02
0x00
0x00
0x03
0xFF
0x02
0x00
0x03
0x80
0x03
0x00
0x02
VCOMMIN
Read
and
write
VCOMMIN_L (least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
VCOMMAX
(most significant
byte)
Read
and
write
VCOMMAX_M
VCOMMAX_L
VCOM_M
VCOM_L
x
x
x
x
x
x
d9 d8
VCOMMAX
(least significant
byte)
Read
and
write
d7 d6 d5 d4 d3 d2 d1 d0
Read
and
write
VCOM (most
significant byte)
x
x
x
x
x
x
d9 d8
5/MAX967
Read
and
write
VCOM (least
significant byte)
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 0
(most significant
byte)
Read
and
write
GMA0_M
GMA0_L
x
x
x
x
x
x
d9 d8
Gamma 0
(least significant
byte)
Read
and
write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 1
(most significant
byte)
Read
and
write
GMA1_M
GMA1_L
x
x
x
x
x
x
d9 d8
Gamma 1
Read
and
write
(least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
Gamma 2
(most significant
byte)
Read
and
write
GMA2_M
x
x
x
x
x
x
d9 d8
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
20 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Table 6. MAX9665 Register Description (continued)
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Gamma 2
(least significant
byte)
Read
and
write
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
GMA2_L
GMA3_M
GMA3_L
GMA4_M
GMA4_L
GMA5_M
GMA5_L
d7 d6 d5 d4 d3 d2 d1 d0
0x80
0x01
0x80
0x01
0x00
0x00
0x80
0x80
0x01
0x80
0x01
0x00
0x00
0x80
Gamma 3
(most significant
byte)
Read
and
write
x
x
x
x
x
x
d9 d8
Gamma 3
Read
and
write
(least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
Gamma 4
(most significant
byte)
Read
and
write
x
x
x
x
x
x
d9 d8
Gamma 4
Read
and
write
(least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
Gamma 5
(most significant
byte)
Read
and
write
x
x
x
x
x
x
d9 d8
Gamma 5
Read
and
write
(least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
______________________________________________________________________________________ 21
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Table 7. MAX9666 Register Description
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Command
operation
Write
only
0x00
0x01
CMD_OPRN
CMD_OPND
d7 d6 d5 d4 d3 d2 d1 d0
d7 d6 d5 d4 d3 d2 d1 d0
0x00
0x00
Not applicable
Not applicable
Command
operand
Write
only
VCOMMIN
(most
significant
byte)
Read
and write
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
VCOMMIN_M
VCOMMIN_L
VCOMMAX_M
VCOMMAX_L
VCOM_M
x
x
x
x
x
x
d9 d8
0x00
0x00
0x03
0xFF
0x02
0x00
0x03
0x80
0x00
0x00
0x03
0xFF
0x02
0x00
0x03
0x80
VCOMMIN
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
VCOMMAX
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
VCOMMAX
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
5/MAX967
VCOM
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
VCOM
(least
significant
byte)
Read
and write
VCOM_L
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 0
(most
significant
byte)
Read
and write
GMA0_M
x
x
x
x
x
x
d9 d8
Gamma 0
(least
significant
byte)
Read
and write
GMA0_L
d7 d6 d5 d4 d3 d2 d1 d0
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
22 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Table 7. MAX9666 Register Description (continued)
BIT
POWER-ON MTP FACTORY
READ
AND
WRITE?
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Gamma 1
(most
significant
byte)
Read
and write
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
GMA1_M
GMA1_L
GMA2_M
GMA2_L
GMA3_M
GMA3_L
GMA4_M
GMA4_L
GMA5_M
x
x
x
x
x
x
d9 d8
0x03
0x40
0x03
0x00
0x02
0x80
0x01
0x80
0x01
0x03
0x40
0x03
0x00
0x02
0x80
0x01
0x80
0x01
Gamma 1
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 2
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
Gamma 2
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 3
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
Gamma 3
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 4
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
Gamma 4
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 5
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
______________________________________________________________________________________ 23
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Table 7. MAX9666 Register Description (continued)
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Gamma 5
(least
significant
byte)
Read
and write
0x13
0x14
0x15
0x16
0x17
GMA5_L
GMA6_M
GMA6_L
GMA7_M
GMA7_L
d7 d6 d5 d4 d3 d2 d1 d0
0x00
0x00
0xC0
0x00
0x80
0x00
0x00
0xC0
0x00
0x80
Gamma 6
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
Gamma 6
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 7
(most
significant
byte)
Read
and write
x
x
x
x
x
x
d9 d8
Gamma 7
(least
significant
byte)
Read
and write
d7 d6 d5 d4 d3 d2 d1 d0
5/MAX967
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
24 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Table 8. MAX9667 Register Description
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Command
operation
0x00
0x01
CMD_OPRN
CMD_OPND
d7 d6 d5 d4 d3 d2 d1 d0
d7 d6 d5 d4 d3 d2 d1 d0
0x00
0x00
Not applicable Write only
Not applicable Write only
Command
operand
VCOMMIN
(most
significant byte)
Read and
0x02
0x03
0x04
0x05
0x06
0x07
VCOMMIN_M
x
x
x
x
x
x
d9 d8
0x00
0x00
0x03
0xFF
0x02
0x00
0x00
write
VCOMMIN
Read and
VCOMMIN_L (least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
0x00
write
VCOMMAX
(most
significant byte)
Read and
VCOMMAX_M
x
x
x
x
x
x
d9 d8
0x03
write
VCOMMAX
Read and
VCOMMAX_L (least significant d7 d6 d5 d4 d3 d2 d1 d0
byte)
0xFF
write
VCOM (most
significant
byte)
Read and
VCOM_M
VCOM_L
x
x
x
x
x
x
d9 d8
0x02
write
VCOM (least
significant
byte)
Read and
d7 d6 d5 d4 d3 d2 d1 d0
0x00
write
Gamma 0
(most
significant
byte)
Read and
0x08
0x09
0x0A
0x0B
GMA0_M
GMA0_L
GMA1_M
GMA1_L
x
x
x
x
x
x
d9 d8
0x03
0x80
0x03
0x40
0x03
write
Gamma 0
(least
significant
byte)
Read and
d7 d6 d5 d4 d3 d2 d1 d0
0x80
write
Gamma 1
(most
significant
byte)
Read and
x
x
x
x
x
x
d9 d8
0x03
write
Gamma 1
(least
significant
byte)
Read and
d7 d6 d5 d4 d3 d2 d1 d0
0x40
write
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
______________________________________________________________________________________ 25
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Table 8. MAX9667 Register Description (continued)
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Gamma 2
(most
significant
byte)
Read and
write
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
GMA2_M
GMA2_L
GMA3_M
GMA3_L
GMA4_M
GMA4_L
GMA5_M
GMA5_L
GMA6_M
GMA6_L
x
x
x
x
x
x
d9 d8
0x03
0x00
0x02
0xC0
0x02
0x80
0x01
0x80
0x01
0x40
0x03
0x00
0x02
0xC0
0x02
0x80
0x01
0x80
0x01
0x40
Gamma 2
(least
significant
byte)
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 3
(most
significant
byte)
Read and
write
x
x
x
x
x
x
d9 d8
Gamma 3
(least
significant
byte)
Read and
write
d7 d6 d5 D4 d3 d2 d1 d0
Gamma 4
(most
significant
byte)
Read and
write
x
x
x
x
x
x
d9 d8
Gamma 4
(least
significant
byte)
5/MAX967
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 5
(most
significant
byte)
Read and
write
x
x
x
x
x
x
d9 d8
Gamma 5
(least
significant
byte)
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 6
(most
significant
byte)
Read and
write
x
x
x
x
x
x
d9 d8
Gamma 6
(least
significant
byte)
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
26 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Table 8. MAX9667 Register Description (continued)
POWER-ON MTP FACTORY
READ
AND
WRITE?
BIT
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
RESET
VALUE
INITIALIZATION
VALUE
7
6
5
4
3
2
1
0
Gamma 7
(most
significant
byte)
Read and
write
0x16
0x17
0x18
0x19
0x1A
0x1B
GMA7_M
GMA7_L
GMA8_M
GMA8_L
GMA9_M
GMA9_L
x
x
x
x
x
x
d9 d8
0x01
0x00
0x00
0xC0
0x00
0x80
0x01
0x00
0x00
0xC0
0x00
0x80
Gamma 7
(least
significant
byte)
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 8
(most
significant
byte)
Read and
write
x
x
x
x
x
x
d9 d8
Gamma 8
(least
significant
byte)
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Gamma 9
(most
significant
byte)
Read and
write
x
x
x
x
x
x
d9 d8
Gamma 9
(least
significant
byte)
Read and
write
d7 d6 d5 d4 d3 d2 d1 d0
Note: d0, d1, d2, d3, d4, d5, d6, d7, d8, d9 = valid data bits; x = don’t care.
Table 9. Command Set
MACHINE
CODE FOR
OPERATION
OPERANDS
DESCRIPTION
OPERATION*
0x00
0x01
NOP
None
No operation.
Move data in source location to destination location. Source location is
bits 4 through 7, and destination location is bits 0 through 3. Source
locations and destination locations must be of the same type. For
example, commands that move data from the VCOM registers to the
MOV
Source, destination
2
gamma registers and vice-versa are not valid, and the I C interface
issues a NACK.
*Write to I2C Register 0x00.
______________________________________________________________________________________ 27
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Table 10. Example Commands for MOV
Operation
Table 11. Source and Destination
Locations for MOV Command
I2C REGISTER ADDRESS
0x00 0x01
LOCATION CODE
DESCRIPTION
VCOM Window Registers
VCOM Window MTP Memory
VCOM Register
0b0000
Operation: Move Gamma register value to
Gamma MTP memory
0x01 0x45
0b0001
0b0010
Operation: Move VCOM MTP memory to VCOM
register
0x01 0x32
0x01 0x67
0b0011
VCOM MTP Memory
Gamma Registers
0b0100
Operation: Move all register values to MTP
memory
0b0101
Gamma MTP Memory
All Registers
0b0110
For a move (MOV) command, 0x01 should be written into
I2C register 0x00, and the source and destination written
in I2C register 0x01. See Table 10 for examples. The
upper 4 bits (7 to 4) designate the source, and the lower
4 bits (3 to 0) destination, per Table 11.
It takes 30ms (typ) and 32ms (max) to move one I2C reg-
ister to MTP memory. Thus, it needs 400ms (typ) and
450ms (max) to program all I2C registers to MTP memory
for VCOM window, VCOM, and gamma.
0b0111
All MTP Memory
VCOM Adjustment (CTL)
Pulse CTL low for more than 200µs to increment the
DAC setting, which lowers the VCOM level by 1 least-
significant bit (LSB) (Figure 10). Similarly, pulse CTL
high for more than 200µs, which raises the VCOM level
by 1 LSB.
To avoid unintentional VCOM adjustment, the parts are
guaranteed to reject CTL pulses shorter than 20µs. In
addition, to avoid the possibility of a single false pulse
caused by power-up sequencing between DVDD and
CTL, the very first pulse is ignored.
The command operand and operation registers must
be written to consecutively, otherwise the command
does not execute.
Single-Wire Interface
The MAX9665/MAX9666/MAX9667 have a single-wire
interface that is compatible with the MAX1512 interface.
5/MAX967
28 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
> 1ms
> 200µs
> 200µs
> 200µs >10µs > 200µs
< 20µs
< 20µs
CTL HIGH
DVDD/2
VCOM UP
CTL
FIRST
COUNT
IGNORED
VCOM DOWN
CTL LOW
SHORT
COUNTS
IGNORED
CTL
ENABLED
CE/DVDD
DAC SETTING
512
513
512
511
UNDEFINED
VCOM
Figure 10. VCOM Adjustment
______________________________________________________________________________________ 29
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
MTP Programming (CTL)
To program the MTP memory, apply the MTP program-
ming waveform through the CTL interface (Figure 11).
CTL VOLTAGE
Unlike the MAX1512, the control interface only delivers
DAC adjustment commands, not programming power.
AVDD must be valid for MTP programming to occur. If
AVDD is not valid for MTP programming, the single-wire
V
P-P
interface is in shutdown.
To apply the MTP programming waveform, carefully
ramp CTL from midscale (DVDD/2) to the programming
voltage, V , in 7.5ms as shown in Figure 11. If the
P-P
ramp is generated digitally, use at least 45 steps to
achieve the required 320mV ramp resolution. During
the ramp time, VCOM adjustment is disabled and the
MTP cell is biased in preparation for programming.
DVDD/2
0
After reaching V , hold CTL at V
for 1ms. During
P-P
P-P
T1
T2
T3
T4
TIME
the MTP program time, the MTP memory stores the
DAC setting. Next, drive CTL to ground in less than
1ms and hold for at least 200µs. Finally, drive CTL to
DVDD/2 to complete the write cycle. The MTP memory
is factory set to half scale. Follow the MTP program-
ming specification in Table 12 to guarantee reliable
MTP memory programming. Violating the specifications
can damage the MTP memory or affect data retention.
Figure 11. MTP Memory Programming
DVDD
Table 12 shows the timing and voltage parameters for
MTP programming. This table is used for programming
through the single-wire interface.
CE
5/MAX967
Single-Wire Interface Enable/Disable (CE)
The single-wire interface can be disabled to reduce the
DVDD supply current. Connect CE to GND to reduce the
typical supply current from 450µA to 320µA. Connect
CE to DVDD to enable the single-wire interface.
R
CE
PROGRAMMING
CIRCUIT
MAX9665
MAX9666
MAX9667
CTL
The programming circuit in Figure 12 drives CE high to
enable the CTL input when it is connected. When the
programming circuit is not connected, CE is pulled low
GND
through resistor R , which disables the CTL input. The
CE
CTL input is relatively immune to noise and brief voltage
transients. It can be safely left continuously enabled if
higher supply current is acceptable.
Figure 12. Optional Circuit to Drive CE
Table 12. MTP Memory Programming Specifications
PARAMETER
CTL Programming Voltage
CTL Programming Ramp
MTP Memory Program Time
SYMBOL
MIN
15.25
7.0
TYP
15.5
7.5
1.0
—
MAX
15.75
8.0
UNITS
V
V
P-P
T1
T2
T3
T4
ms
ms
µs
µs
0.9
1.1
V
Fall Time
10
1000
—
P-P
Done Hold Time
200
—
30 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
During this time, the MTP register values are loaded
Applications Information
into the I2C registers and the default I2C register values
Power-Up and Power-Down
Figure 13 below shows the power-up sequence. The
digital supply must be powered up first. The analog
supply should not be powered up for at least 350µs
(min) after the digital supply has been powered up.
are overwritten. Once AVDD is above approximately
8V, the output buffers have enough headroom and
power up proportionally with the AVDD.
For power-down, AVDD must be lowered first to 0V,
and then DVDD can safely be powered down.
VOLTAGE (V)
AVDD
15.6
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
8.0
OUT6
OUT7
OUT8
OUT9
DVDD
3.6
0
TIME
> 350µs
Figure 13. Power-Up Sequence
______________________________________________________________________________________ 31
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Electrostatic Discharge (CTL, CE)
Often, CTL and CE are exposed at the panel connector
and are therefore subject to electrostatic discharge
(ESD). Resistor-capacitor (RC) filters can be employed
at these inputs to improve their ESD performance
(Figure 14).
Leakage Current (CTL)
The CTL pin is internally biased to DVDD/2, but it is
sensitive to leakage currents above 0.1µA. When CTL is
not driven, avoid leakage currents around the CTL pin.
Otherwise, reinforce the DVDD/2 set point with an exter-
nal resistive voltage-divider.
If the CE panel connector is to be left unconnected
after programming, be sure to include a resistor to
Power Supplies and Bypass Capacitors
The MAX9665/MAX9666/MAX9667 operate from a single
9V to 20V analog supply and a 2.5V to 3.6V digital sup-
ply. Bypass AVDD to GND with 0.1µF and 10µF capaci-
tors in parallel. Use an extensive ground plane to ensure
optimum performance. Bypass DVDD to GND with a
0.1µF capacitor. Refer to the MAX9665/MAX9666/
MAX9667 evaluation kit for a proven PCB layout.
ground (R ) to ensure a valid logic-low on CE. The
CE
time constant for a CE filter is not critical, but the driving
resistor must have a much lower resistance than R to
CE
properly drive CE. If a filter is used at the CTL panel
connector, its RC time-constant should be short enough
to avoid interfering with CTL pulses or MTP memory
programming timing. A time constant less than 200µs
does not interfere with MTP memory programming. To
avoid interfering with CTL pulses, make the time con-
stant small compared to the CTL pulse width needed.
Layout and Grounding
The exposed pad on the TQFN package is electrically
connected to GND. Solder the exposed pad to a
ground plane to provide a low thermal resistance to
ground for heat dissipation. Do not route traces under
these packages.
DVDD DURING
PROGRAMMING
UNCONNECTED
10kΩ
5/MAX967
CE
AFTER PROGRAMMING
R
CE
100kΩ
0.1µF
MAX9665
MAX9666
MAX9667
1kΩ
UNCONNECTED
AFTER PROGRAMMING
CTL
0.1µF
GND
Figure 14. Improved EOS/Surge Performance
32 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Typical Operating Circuits
AVDD
REF
AVDD
REF
10
10
10
OUT0
OUT1
DAC
DAC
DAC
DAC
OUT2
OUT3
10
10
10
SOURCE
DRIVER
LCD PANEL
2
I C
OUT4
OUT5
MTP
MEMORY
DAC
DAC
REGISTERS
10
VCOM
FB
DAC
DVDD
SCL
2
I C
SDA
LEVEL
SHIFTER
MAX9665
CE
CTL
SINGLE-WIRE
INTERFACE
GND
______________________________________________________________________________________ 33
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Typical Operating Circuits (continued)
AVDD
REF
AVDD
REF
10
10
10
OUT0
OUT1
OUT2
OUT3
DAC
DAC
DAC
DAC
10
10
10
10
SOURCE
DRIVER
LCD PANEL
2
OUT4
I C
MTP
MEMORY
DAC
DAC
DAC
DAC
REGISTERS
OUT5
OUT6
5/MAX967
10
10
OUT7
VCOM
FB
DAC
DVDD
SCL
2
I C
SDA
LEVEL
SHIFTER
MAX9666
CE
SINGLE-WIRE
INTERFACE
CTL
GND
34 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Typical Operating Circuits (continued)
AVDD
REF
10
10
10
10
OUT0
DAC
DAC
DAC
DAC
OUT1
OUT2
OUT3
10
10
OUT4
OUT5
DAC
DAC
SOURCE
DRIVER
LCD PANEL
2
10
10
I C
OUT6
OUT7
MTP
MEMORY
DAC
DAC
REGISTERS
10
10
OUT8
OUT9
DAC
DAC
VCOM
FB
10
DAC
DVDD
SCL
LEVEL
SHIFTER
2
I C
SDA
MAX9667
CE
CTL
SINGLE-WIRE
INTERFACE
GND
______________________________________________________________________________________ 35
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Functional Diagrams (continued)
AVDD
REF
10
10
10
10
OUT0
OUT1
OUT2
OUT3
OUT4
DAC
DAC
DAC
DAC
2
I C
MTP
MEMORY
10
10
10
10
REGISTERS
DAC
OUT5
DAC
DAC
DAC
5/MAX967
OUT6
OUT7
VCOM
FB
10
DAC
DVDD
SCL
2
I C
SDA
MAX9666
CE
SINGLE-WIRE
INTERFACE
CTL
GND
36 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Functional Diagrams (continued)
AVDD
REF
10
10
10
10
OUT0
OUT1
OUT2
OUT3
OUT4
DAC
DAC
DAC
DAC
10
10
10
10
DAC
2
OUT5
I C
MTP
MEMORY
DAC
DAC
DAC
DAC
DAC
DAC
REGISTERS
OUT6
OUT7
10
OUT8
OUT9
10
10
VCOM
FB
DVDD
SCL
2
I C
SDA
MAX9667
CE
SINGLE-WIRE
INTERFACE
CTL
GND
______________________________________________________________________________________ 37
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Pin Configurations (continued)
TOP VIEW
TOP VIEW
15
14
13
12
11
15
14
13
12
11
OUT5
OUT6
10
9
REF 16
OUT4
N.C.
10
9
REF 16
AVDD 17
FB 18
AVDD 17
FB 18
8
OUT7
OUT8
OUT9
8
OUT5
OUT6
OUT7
MAX9667
MAX9666
VCOM
CTL
7
19
20
VCOM
CTL
7
19
20
6
6
EP*
5
EP*
5
+
+
1
2
3
4
1
2
3
4
THIN QFN
5mm x 5mm
THIN QFN
5mm x 5mm
*EP = EXPOSED PAD. CONNECT TO DIGITAL GROUND PLANE.
5/MAX967
38 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0140
90-0121
20 TQFN-EP
T2055+3
______________________________________________________________________________________ 39
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
5/MAX967
40 ______________________________________________________________________________________
6/8/10-Channel, 10-Bit, Nonvolatile Programmable
Gamma and VCOM Reference Voltages
5/MAX967
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
10/09
11/09
1/10
Initial release
—
Added soldering temperature (reflow) and made minor updates
Updated MTP write qualification and MOV command description
1, 2, 10, 38
1, 10, 12, 28, 30
1, 2, 3, 5–9, 15–20,
22, 25, 30,
3
4
3/10
7/10
Corrected various errors and added soldering temperature
Corrected terminology in TOCs 2 and 3 and typos
31, 33, 38
6, 16, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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