MAX96701 [MAXIM]
14-Bit GMSL Serializer with High-Immunity/Bandwidth Mode and Coax/STP Cable Drive;
| 型号： | MAX96701 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 14-Bit GMSL Serializer with High-Immunity/Bandwidth Mode and Coax/STP Cable Drive |
| 文件： | 总75页 (文件大小：1507K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
General Description
Benefits and Features
The MAX96701 is a compact serializer in a 4mm x 4mm
TQFN package especially suited for automotive camera
applications. In high-bandwidth mode, the parallel-clock
maximum is 116MHz for 12-bit linear or combined HDR
data types.
● Ideal for Safety Camera Applications
• Works with Low-Cost 50Ω Coax (100Ω STP) Cables
• Error Detection of Video/Control Data
• High-Immunity Mode for Robust Control-Channel
EMC Tolerance
• Retransmission of Control Data Upon Error
Detection
• Best-in-Class Supply Current: 88mA (max)
• Pre/Deemphasis Allows 15m Cable at Full Speed
• 24-Pin (4mm x 4mm) TQFN Package with 0.5mm
Lead Pitch
The embedded control channel operates at 9.6kbps to
1Mbps in I C mode, allowing programming of serializer,
deserializer (SerDes), and camera registers independent
of video timing.
2
For driving longer cables, the IC has programmable
pre/deemphasis. Programmable spread spectrum is
available on the serial output. The serial output meets
ISO 10605 and IEC 61000-4-2 ESD standards. The
supply range is 1.7V to 1.9V.
● High-Speed Data Serialization for Megapixel
Cameras
• Up to 1.74Gbps Serial-Bit Rate
• 12.5MHz to 116MHz x 12-Bit + H/V Data
The MAX96701 is available in a 24-pin TQFN package
with 0.5mm lead pitch, and operates over the -40°C to
+115°C temperature range.
● Multiple Modes for System Flexibility
2
• 9.6kbps to 1Mbps Control Channel in I C Mode
(with Clock Stretch)
• Crosspoint Switch Accepts Any Input Bitmap
• Modes for Encoded VSYNC and HSYNC
Applications
● Automotive Camera Applications
● Reduces EMI and Shielding Requirements
• Programmable Output Spread Spectrum
• Tracks Spread Spectrum Applied at the Parallel
Input
Simplified Block Diagram
• 1.7V to 1.9V I/O Supply
● Peripheral Features for Camera Power-Up and
Verification
VIDEO
VIDEO
• Built-In PRBS Generator for BER Testing
• Dedicated GPO for Camera Frame-Sync Trigger
and Other Uses
CAM
MAX96701
MAX96700
GPU
2
2
• Remote/Local Wake-Up from Sleep Mode
I C
I C
● Meets AEC-Q100 Automotive Specification
• -40°C to +115°C Operating Temperature
• ±8kV Contact and ±15kV Air IEC 61000-4-2 and
ISO 10605 ESD Protection
Ordering Information appears at end of data sheet.
19-100066; Rev 0; 6/17
MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
24-Pin TQFN-EP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Video/Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Single/Double Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
HS/VS Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Bus Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Forward Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Reverse Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2
I C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Remote-End Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Clock-Stretch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2
Packet-Based I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Packet Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Control-Channel Error Detection and Packet Retransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Cable Type Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Video Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Shutdown/Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Maxim Integrated
│ 2
www.maximintegrated.com
MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
(
)
TABLE OF CONTENTS CONTINUED
Serialization Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Link Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
GMSL Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
seraddr (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
desaddr (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
ss (0x02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
sdiv (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
main_control (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
prbs_len (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
cmllvl_preemp (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
config (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
rsvd_8 (0x08). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
i2c_source (0x09, 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
i2c_dest (0x0A, 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
i2c_config (0x0D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
gpio_en (0x0E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
gpio_out (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
gpio_in (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
errg (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
rsvd_12 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
pd (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
pktcc_lock (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
input_status (0x15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
max_rt_err (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
rsvd_17 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
crc (0x18 to 0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
cc_crc_errcnt (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
rsvd_1d (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
id (0x1E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
revision (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
crossbar (0x20 to 0x3E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
crossbar_hs (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
crossbar (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
crossbar_de (0x41). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
link_config (0x42). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Maxim Integrated
│ 3
www.maximintegrated.com
MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
(
)
TABLE OF CONTENTS CONTINUED
sync_gen_config (0x43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
vs_dly (0x44 to 0x46). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
vs_h (0x47 to 0x49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
vs_l (0x4A to 0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
cxtp (0x4D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
hs_dly (0x4E to 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
rsvd (0x51 to 0x53, 0x5D to 0x5F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
hs_h (0x54, 0x55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
hs_l (0x56, 0x57) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
hs_cnt (0x58, 0x59) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
de_dly (0x5A to 0x5C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
de_h (0x60, 0x61) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
de_l (0x62, 0x63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
de_cnt (0x64, 0x65). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
prbs_type (0x66) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
dbl_align_to (0x67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
cc_crc_length (0x68) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
hi_lo (0x69) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
rsvd_96 (0x96). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
rsvd_97 (0x97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
rsvd_98 (0x98). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
rsvd_99 (0x99). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
pktcc_en (0x9A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
rsvd_C8 (0xC8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
rsvd_c9 (0xC9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
rsvd_fc (0xFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
rsvd_fd (0xFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
rsvd_fe (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
rsvd_ff (0xFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Parallel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Bus Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Bus Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Crossbar-Switch Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Recommended Crossbar-Switch Program Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
(
)
TABLE OF CONTENTS CONTINUED
Timing-Generator Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Double-Mode Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
External High/Low Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Align from HS or DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2
I C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2
I C Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Software Programming of Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2
I C Address Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Configuration Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Cascaded/Parallel Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Dual μC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Equation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Power-Supply Circuits and Bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
High-Frequency Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Device Configuration and Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Internal Input Pulldowns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2
I C Pullup Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PRBS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
GPI/GPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Fast Detection of Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Entering/Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
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14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
LIST OF FIGURES
Figure 1. Serial-Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. Output Waveforms at OUT+, OUT-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
Figure 6. I C Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Input Setup and Hold Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Serializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. 24-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. 27-Bit High-Bandwidth Mode Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. 32-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Coax Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Crossbar-Switch Dataflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Sync-Signal Format For Video-Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Crossbar-Switch Default Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 21. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
LIST OF TABLES
Table 1. Reverse Control-Channel Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2. Link-Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3. Input Data-Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 4. Data-Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 5. Crossbar Output to Serial Link Map (D23:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 6. Crossbar Output to Serial Link Map (D31:24 and Special Packets) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 7. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 8. Timing-Generator Parameter Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 9. Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 10. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 11. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 12. Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 13. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Absolute Maximum Ratings
AVDD to GND* .....................................................-0.5V to +1.9V
DVDD to GND*.....................................................-0.5V to +1.9V
OUT+, OUT- to GND*...........................................-0.5V to +1.9V
All Other Pins to GND*..........................-0.5V to (DVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or Supply........Continuous
Continuous Power Dissipation, T = +70°C
A
TQFN (derate 27.8 mW/°C above +70°C) .............2222.2mW
Operating Temperature Range..........................-40°C to +115°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +150°C
Soldering Temperature (reflow).......................................+260°C
*EP externally connected to GND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
24-Pin TQFN-EP
Package Code
T2444+4
21-0139
90-0022
Outline Number
Land Pattern Number
Single-Layer Board:
Junction-to-Ambient Thermal Resistance (θ
)
)
48
3
JA
Junction-to-Case Thermal Resistance (θ
)
JC
Four-Layer Board:
Junction-to-Ambient Thermal Resistance (θ
Junction-to-Case Thermal Resistance (θ
36
3
JA
)
JC
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
DC Electrical Characteristics
(V
V
= V
= 1.7V to 1.9V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to GND, typical values are at
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
DVDD
AVDD L A
= V
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (DIN_, PCLKIN, HS, VS, HIM, MS)
0.65 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
IH
V
DVDD
0.35 x
V
V
IL
V
DVDD
+20
Input Current
I
V
= 0 to V
= -2mA
-20
μA
IN
IN
DVDD
SINGLE-ENDED OUTPUT (GPO)
High-Level Output
Voltage
V
DVDD
0.2
-
V
I
I
V
OH
OH
Low-Level Output
Voltage
V
= 2mA
= 0V
0.2
21
V
OL
OL
Output Short-Circuit Current
I
V
3
12
mA
OS
O
2
I C and GENERAL-PURPOSE I/Os (SDA, SCL, GPIO_) with OPEN-DRAIN OUTPUTS
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
V
DVDD
0.3 x
V
IL
V
DVDD
+5
V
V
= 0 to V
= 0 to V
(Note 2), SDA, SCL
(Note 2), GPIO_
-110
-80
IN
DVDD
Input Current
I
µA
IN
+5
0.4
10
IN
DVDD
Low-Level Open-Drain
Output Voltage
V
I
= 3mA
V
OL
OL
Input Capacitance
C
Each pin (Note 3)
pF
IN
Maxim Integrated
│ 9
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
DC Electrical Characteristics (continued)
(V
V
= V
= 1.7V to 1.9V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to GND, typical values are at
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
DVDD
AVDD L A
= V
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIFFERENTIAL OUTPUTS (OUT+, OUT-)
Preemphasis off, high drive (Figure 1)
3.3dB preemphasis, high drive (Figure 2)
3.3dB deemphasis, high drive (Figure 2)
300
350
240
400
500
610
425
Differential Output Voltage
V
mV
OD
Change in V
Between
OD
Complementary Output
States
ΔV
25
1.56
25
mV
V
OD
Output Offset Voltage
V
Preemphasis off
1.1
-60
1.4
OS
(V
+ V
)/2 = V
OUT+
OUT- OS
Change in V
Between
OS
Complementary Output
States
ΔV
mV
OS
V
V
or V
or V
= 0V
OUT+
OUT-
Output Short-Circuit Current
I
mA
OS
= 1.9V
25
25
OUT+
OUT-
Magnitude of Differential
Output Short-Circuit Current
I
V
= 0V
OD
mA
OSD
Output-Termination
Resistance (Internal)
R
From OUT+ or OUT- to AVDD
45
54
63
Ω
O
REVERSE CONTROL-CHANNEL RECEIVER OUTPUTS (OUT+, OUT-)
Legacy
27
40
High-Switching Threshold
Low-Switching Threshold
V
mV
mV
CHR
High immunity
Legacy
-27
-40
V
CLR
High immunity
SINGLE-ENDED SERIAL OUTPUTS (OUT+ or OUT-)
Preemphasis off, high drive (Figure 3)
375
435
300
-69
500
625
765
535
Single-Ended Output
Voltage
V
O
3.3dB preemphasis, high drive (Figure 2)
3.3dB deemphasis, high drive (Figure 2)
mV
V
or V
= 0V
OUT+
OUT+
OUT-
OUT-
Output Short-Circuit Current
I
mA
OS
V
or V
= 1.9V
32
63
Output-Termination
Resistance (Internal)
R
From OUT+ or OUT- to AVDD
45
54
Ω
O
Maxim Integrated
│ 10
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
DC Electrical Characteristics (continued)
(V
V
= V
= 1.7V to 1.9V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to GND, typical values are at
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
DVDD
AVDD L A
= V
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
f
= 116MHz, HIBW = 0, BWS = 0,
PCLKIN
default register values, AVDD + DVDD
(1.9V)
66
63
88
83
f
= 116MHz, HIBW = 1, BWS = 0,
PCLKIN
Supply Current, Worst-Case
Pattern (Figure 4)
I
default register values, AVDD + DVDD
mA
µA
WCS
(1.9V)
f
= 87MHz, BWS = 1,
PCLKIN
default register values, AVDD + DVDD
(1.9V)
62
40
83
Sleep-Mode Supply Current
I
Wake-up receiver enabled
100
CCS
ESD PROTECTION
Human Body Model, R = 1.5kΩ,
D
±8
±8
C
= 100pF
S
IEC 61000-4-2, R = 330Ω, C = 150pF,
D
S
Contact Discharge
IEC 61000-4-2, R = 330Ω, C = 150pF,
Air Discharge
D
S
OUT+, OUT- (Note 4)
V
V
±15
±8
kV
kV
ESD
ISO 10605, R = 2kΩ, C = 330pF,
D
S
Contact Discharge
ISO 10605, R = 2kΩ, C = 330pF,
D
S
±15
±4
Air Discharge
Human Body Model, R = 1.5kΩ,
D
All Other Pins (Note 5)
ESD
C
= 100pF
S
Maxim Integrated
│ 11
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
AC Electrical Characteristics
(V
V
= V
= 1.7V to 1.9V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to GND, typical values are at
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
DVDD
AVDD L A
= V
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK INPUT (PCLKIN)
BWS = 0, HIBW = 0, single input
BWS = 0, HIBW = 1, single input
BWS = 1, single input
16.66
36.66
12.5
33.32
73.33
25
58
58
43.5
116
116
87
Clock Frequency
f
MHz
PCLKIN
DC
BWS = 0, HIBW = 0, double input
BWS = 0, HIBW = 1, double input
BWS = 1, double input
Clock Duty Cycle
t
/t or t
/t (Note 3, Figure 5)
35
50
65
%
HIGH T
LOW T
Clock Transition Time
t
t
(Note 3, Figure 5)
4
ns
R, F
1.74Gbps bit rate, 300kHz sinusoidal jitter
(Note 3)
Clock Jitter
t
800
ps
J
2
I C PORT TIMING
2
I C Bit Rate
9.6
20
1000
150
kbps
ns
30% to 70%, C = 10pF to 100pF, 1kΩ
pullup to DVDD
L
Output Rise Time
Output Fall Time
t
R
70% to 30%, C = 10pF to 100pF, 1kΩ
L
t
20
150
ns
F
pullup to DVDD
2
I C TIMING (Figure 6)
Low f
I2CSLVSH = 10)
range: (I2CMSTBT = 010,
SCL
9.6
100
400
Mid f range: (I2CMSTBT 101,
SCL
SCL Clock Frequency
f
> 100
> 400
kHz
SCL
I2CSLVSH = 01)
High f range: (I2CMSTBT = 111,
I2CSLVSH = 00)
SCL
1000
f
f
f
f
f
f
f
f
f
f
f
f
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
4
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
t
0.6
0.26
4.7
1.3
0.5
4
µs
µs
µs
µs
HD:STA
t
LOW
t
0.6
0.26
4.7
0.6
0.26
HIGH
Repeated START Condition
Setup Time
t
SU:STA
Maxim Integrated
│ 12
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
AC Electrical Characteristics (continued)
(V
V
= V
= 1.7V to 1.9V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to GND, typical values are at
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
DVDD
AVDD L A
= V
AVDD A
PARAMETER
SYMBOL
CONDITIONS
range, Low
MIN
0
TYP
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Data Hold Time
Data Setup Time
t
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
0
ns
HD:DAT
0
250
100
50
t
ns
µs
µs
µs
µs
SU:DAT
SU:STO
4
Setup Time for STOP
Condition
t
0.6
0.26
4.7
1.3
0.5
Bus-Free Time
Data Valid Time
t
BUF
3.45
0.9
t
VD:DAT
VD:ACK
0.45
3.45
0.9
Data Valid-Acknowledge
Time
t
0.45
50
Pulse Width of Spikes
Suppressed
t
50
ns
SP
50
Capacitive Load of Each
Bus Line
C
(Note 3)
100
pF
B
SWITCHING CHARACTERISTICS (Note 3)
20% to 80%, V , 400mV differential R
OD
L
Differential/Single-Ended
Output Rise/Fall Time
t
t
= 100Ω, 500mV single-ended R = 50Ω,
250
ps
R, F
L
serial bit rate = 1.74Gbps
Total Serial-Output Jitter
(Differential Output)
1.74Gbps PRBS, measured at V
differential, preemphasis disabled (Figure 7)
= 0V
OD
t
0.25
0.15
0.25
0.15
UI
UI
UI
UI
ns
TSOJ1
Deterministic Serial-Output
Jitter (Differential Output)
1.74Gbps PRBS, measured at V = 0V
OD
t
DSOJ2
differential, preemphasis disabled (Figure 7)
Total Serial-Output Jitter
(Single-Ended Output)
1.74Gbps PRBS, measured at V /2,
O
preemphasis disabled (Figure 3)
t
TSOJ1
Deterministic Serial-Output
Jitter (Single-Ended Output)
1.74Gbps PRBS, measured at V /2,
O
preemphasis disabled (Figure 3)
t
DSOJ2
Parallel Data-Input Setup
Time
t
(Figure 8)
2
SET
Maxim Integrated
│ 13
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
AC Electrical Characteristics (continued)
(V
V
= V
= 1.7V to 1.9V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to GND, typical values are at
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
DVDD
AVDD L A
= V
AVDD A
PARAMETER
SYMBOL
t
CONDITIONS
(Figure 8) (Note 3)
MIN
TYP
MAX
UNITS
ns
Parallel Data Input Hold
Time
1
HOLD
GPI-to-GPO Delay
Serializer Delay
t
Deserializer GPI to serializer GPO (Figure 9)
350
µs
GPIO
Spread spectrum enabled (Figure 10)
(Notes 3, 6)
2065
t
Bits
SD
Spread spectrum disabled (Figure 10)
(Notes 3, 6)
1095
Link Start Time
Power-Up Time
t
(Figure 11)
(Figure 12)
2
7
ms
ms
LOCK
t
PU
Note 1: Limits are 100% production tested at T = +115°C. Limits over the operating temperature range are guaranteed by design
A
and characterization, unless otherwise noted.
Note 2: I min is due to voltage drop across the internal pullup resistor.
IN
Note 3: Not production tested. Guaranteed by design.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Measured in serial link bit times. Bit time = 1/(30 x f
) for BWS = 0; bit time = 1/(40 x f
) for BWS = 1.
PCLKIN
PCLKIN
Maxim Integrated
│ 14
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Typical Operating Characteristics
(V
= V
= 1.8V, T = +25°C, unless otherwise noted.)
AVDD
DVDD A
SUPPLY CURRENT
vs. PIXELCLOCK FREQUENCY
(BWS = 0, HIBW = 0)
SUPPLY CURREN
vs. PIXELCLOCK FREQUENCY
(BWS = 0, HIBW = 1)
toc01
toc02
75
70
65
60
55
50
45
40
75
PE = 0xB to 0xF
PE = 0x1 to 0x4
PE = 0xB to 0xF
PRBS ON,
COAX MODE,
SS OFF
PRBS ON,
70 COAX MODE,
SS OFF
PE = 0x1 to 0x4
65
DBL = 0
DBL = 0
60
55
50
45
40
DBL = 1
DBL = 1
PE OFF
75
PE OFF
75
15
35
55
95
115
15
15
10
35
55
95
115
PIXEL CLOCK FREQUENCY (MHz)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT
vs. PIXELCLOCK FREQUENCY
(BWS = 0, HIBW = 0)
SUPPLY CURRENT
vs. PIXELCLOCK FREQUENCY
(BWS = 1, HIBW = 0)
toc03
toc04
70
65
60
55
50
45
40
65
60
55
50
45
40
DBL = 1
PE = 0xB to 0xF
ALL SPREAD VALUES
PRBS ON,
COAX MODE,
PE OFF
PRBS ON,
COAX MODE,
SS OFF
DBL = 0
DBL = 0
PE = 0x1 to 0x4
DBL = 1
PE OFF
10
30
50
70
90
35
55
75
95
115
PIXEL CLOCK FREQUENCY (MHz)
PIXEL CLOCK FREQUENCY (MHz)
SUPPLY CURRENT
vs. PIXELCLOCK FREQUENCY
(BWS = 0, HIBW = 1)
SUPPLY CURRENT
vs. PIXELCLOCK FREQUENCY
(BWS = 1, HIBW = 0)
toc05
toc06
65
60
55
50
45
40
65
60
55
50
45
40
PRBS ON,
ALL SPREAD VALUES
PRBS ON,
ALL SPREAD VALUES
COAX
MODE,
PE OFF
COAX MODE,
PE OFF
DBL = 0
DBL = 0
DBL = 1
DBL = 1
15
35
55
75
95
115
30
50
70
90
PIXEL CLOCK FREQUENCY (MHz)
PIXEL CLOCK FREQUENCY (MHz)
Maxim Integrated
│ 15
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Typical Operating Characteristics (continued)
(V
= V
= 1.8V, T = +25°C, unless otherwise noted.)
AVDD
DVDD A
OUTPUT POWER SPECTRUM
vs. PCLK FREQUENCY
(VARIOUS SPREAD)
OUTPUT POWER SPECTRUM
vs. PCLK FREQUENCY
(VARIOUS SPREAD)
toc07
toc08
10
10
0
fPCLKIN = 20MHz
0.5% SPREAD
fPCLKIN = 50MHz
0.5% SPREAD
0
1% SPREAD
1% SPREAD
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-50
-60
-70
-80
NO SPREAD
20.0
NO SPREAD
50
2% SPREAD
19.0 19.5
2% SPREAD
48 49
4% SPREAD
21.0
4% SPREAD
52 53
18.5
20.5
21.5
47
51
PIXEL CLOCK FREQUENCY (MHz)
PIXEL CLOCK FREQUENCY (MHz)
MAXIMUM PIXELCLOCK FREQUENCY vs.
STP CABLE LENGTH
MAXIMUM PIXELCLOCK FREQUENCY vs.
COAX CABLE LENGTH (BER < 10-10
)
(BER < 10-10
)
toc10
toc09
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
NO PE, DBL = 0
AEQ
NO PE, DBL = 0
AEQ
9.7dB EQ
NO EQ
NO EQ
4.3dB EQ
4.3dB EQ
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
0
10
20
30
40
0
5
10
15
20
25
COAX CABLE LENGTH (m)
STP CABLE LENGTH (m)
SERIAL LINK SWITCHING PATTERN
WITH 3.3dB PREEMPHASIS
(1.5Gbps, 20m COAX CABLE)
SERIAL LINK SWITCHING PATTERN
WITH 4.4dB PREEMPHASIS
(1.5Gbps, 10m STP CABLE)
toc12
toc11
50mV/div
100mV/div
200ps/div
200ps/div
Maxim Integrated
│ 16
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Pin Configuration
TOP VIEW
18
17
16
15
14
13
19
20
21
22
23
24
12
11
10
9
PCLKIN
GPO/HIM
DIN13/VS
DIN12/HS
DIN0
DIN1
DVDD
DIN2
DIN3
MAX96701
DIN11/GPIO2
DIN10/GPIO1
DIN9
8
+
7
1
2
3
4
5
6
TQFN
(4mm x 4mm)
Pin Description
REF SUP-
PIN
NAME
FUNCTION
TYPE
PLY
POWER
3, 13
GND
Analog and Digital Ground
Power
Power
1.8V Analog Power Supply. Bypass AVDD to GND with 0.1μF, and
0.001μF capacitors as close as possible to the device with the
smaller value capacitor closest to AVDD.
16
22
EP
AVDD
1.8V Digital Power Supply. Bypass DVDD to GND with 0.1μF, and
0.001μF capacitors as close as possible to the device with the
smaller value capacitor closest to DVDD.
DVDD
Power
Power
Exposed Pad. EP is internally connected to device ground. Must
connect EP to the PCB ground plane through a via array for proper
thermal and electrical performance.
—
HIGH-SPEED DIGITAL
Single Function
1
2
4
5
6
7
DIN4
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
Digital
Digital
Digital
Digital
Digital
Digital
DIN5
DIN6
DIN7
DIN8
DIN9
Parallel Clock Input with Internal Pulldown to GND. Latches parallel
data inputs and provides the PLL reference clock.
19
PCLKIN
DVDD
Digital
Maxim Integrated
│ 17
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Pin Description (continued)
REF SUP-
PIN
NAME
FUNCTION
TYPE
PLY
20
DIN0
DIN1
DIN2
DIN3
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
Parallel Data Input. Internal pulldown to GND.
DVDD
DVDD
DVDD
DVDD
Digital
Digital
Digital
Digital
21
23
24
Multifunction
Parallel Data Input/GPIO. Defaults to parallel data input on power-
8
9
DIN10/GPIO1 up. Parallel data input has internal pulldown to GND. GPIO1 has an
DVDD
DVDD
Digital
Digital
open-drain input/output with internal 60kΩ pullup to DVDD.
Parallel Data Input/GPIO. Defaults to parallel data input on power-
DIN11/GPIO2 up. Parallel data input has internal pulldown to GND. GPIO2 has an
open-drain input/output with internal 60kΩ pullup to DVDD.
Parallel Data Input/Horizontal Sync with Internal Pulldown to GND.
Defaults to parallel data input on power-up. Defaults to horizontal-
sync input when HS/VS encoding is enabled, or when in high-
bandwidth mode.
10
11
DIN12/HS
DVDD
DVDD
Digital
Digital
Parallel Data Input/Vertical Sync with Internal Pulldown to GND.
Defaults to parallel data input on power-up. Defaults to vertical-
sync input when HS/VS encoding is enabled, or when in high-
DIN13/VS
bandwidth mode.
Configuration and Interface
General-Purpose Output/High-Immunity Mode Input with internal
Pulldown to GND. HIM is latched at power-up and switches to GPO
output automatically after power-up. Connect HIM to DVDD with a
30kΩ resistor to set high, or leave open to set low. HIGHIMM can
be programmed to a different value after power-up. HIGHIMM in
the deserializer must be set to the same value. GPO output follows
the state of the GPI (or INT) input on the GMSL deserializer. GPO
is low upon power-up.
12
GPO/HIM
DVDD
Digital
14
15
OUT-
Inverting Coax/Twisted-Pair Serial Output
—
—
Digital
Digital
OUT+
Noninverting Coax/Twisted-Pair Serial Output
Serial Data. Input/output with internal 30kΩ pullup to DVDD. SDA is
2
17
18
SDA
SCL
the SDA input/output of the serializer's I C master/slave. SDA has
DVDD
DVDD
Digital
Digital
an open-drain driver and requires a pullup resistor.
Serial Clock. Input/output with internal 30kΩ pullup to DVDD. SCL
is the SCL input/output of the serializer's I C master/slave. SCL has
2
an open-drain driver and requires a pullup resistor.
Maxim Integrated
│ 18
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Functional Block Diagram
PCLKIN
SSPLL
MAX96701
CLKDIV
DIN[9:0]
16 x 1
LATCH
(SINGLE)
TIMING
GENERATOR
DIN12/HS
DIN13/VS
CROSSPOINT
SWITCH
OUT+
VIDEO
OR
PARALLEL
TO SERIAL
SCRAMBLE/
HVEN/CRC/
PARITY/
ANY 32
INPUTS TO
ANY 22/24/30
OUTPUTS
CML TX
OUT-
16 x 2
LATCH
(DBL)
FIFO
ENCODE
SYNC
DIN10/GPIO1
DIN11/GPIO2
FCC
RX
HIM
CONTROL
GPIO
REVERSE CONTROL
CHANNEL
I2C
GPO/HIM
SCL
SDA
R /2
L
OUT+
V
OD
V
OS
OUT-
R /2
L
GND
((OUT+) + (OUT-))/2
OUT-
V
V
OS(+)
V
OS(-)
OS(-)
OUT+
DV = |V
- V
|
OS(+) OS(-)
OS
V
(+)
OD
V
OD
= 0V
V
OD(-)
V
OD(-)
DV = |V
- V
|
OD(+) OD(-)
OD
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
OUT+
OUT-
V
OD(P)
V
OD(D)
V
OS
SERIAL-BIT
TIME
Figure 2. Output Waveforms at OUT+, OUT-
OUT+
OR
V /2
O
V
V /2
O
V
O
O
OUT-
Figure 3. Single-Ended Output Template
PCLKIN
DIN_
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
Figure 4. Worst-Case Pattern Input
t
T
V
IH MIN
t
HIGH
PCLKIN
V
IL MAX
t
R
t
F
t
LOW
Figure 5. Parallel Clock Input Requirements
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
START
CONDITION
ꢁSꢂ
BIT ꢃ
MSB
ꢁAꢃꢂ
STOꢀ
CONDITION
ꢁꢀꢂ
BIT ꢄ
ꢁAꢄꢂ
BIT ꢅ
ꢁR/ꢆꢂ
ACꢇNOꢆLEDGE
ꢁAꢂ
ꢀROTOCOL
ꢈ
ꢈ
ꢈ
ꢎIGꢎ
SUꢉSTA
LOꢆ
ꢑ/ꢐ
SCL
ꢊ
ꢊ
ꢋ ꢅꢌꢃ
ꢋ ꢅꢌꢍ
DꢊDD
SCL
SDA
DꢊDD
ꢈ
Sꢀ
ꢈ
BUF
ꢈ
ꢈ
ꢐ
ꢏ
ꢊ
DꢊDD
ꢋ ꢅꢌꢃ
ꢋ ꢅꢌꢍ
ꢊ
DꢊDD
ꢈ
ꢈ
ꢈ
ꢈ
ꢈ
SUꢉSTO
ꢎDꢉSTA
ꢈ
ꢎDꢉDAT
ꢊDꢉDAT
ꢊDꢉACꢇ
SUꢉDAT
2
Figure 6. I C Timing Parameters
800mV
P-P
t
t
TSOJ1
2
TSOJ1
2
Figure 7. Differential Output Template
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
V
IH MIN
PCLKIN
V
IL MAX
t
t
HOLD
SET
V
V
V
V
IH MIN
IH MIN
DIN_
IL MAX
IL MAX
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. Input Setup and Hold Times
V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 9. GPI-to-GPO Delay
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
EXPANDED TIME SCALE
DIN_
N
N+2
N+3
N+4
N+1
PCLKIN
OUT+/-
N-1
N
t
SD
FIRST BIT
LAST BIT
Figure 10. Serializer Delay
PCLKIN
t
LOCK
500Fs
SERIAL LINK INACTIVE
SERIAL LINK ACTIVE
REVERSE CONTROL CHANNEL
ENABLED
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
AVAILABLE
Figure 11. Link Startup Time
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
PCLKIN
1.7V
V
DD
t
PU
POWERED UP,
SERIAL LINK INACTIVE
POWERED DOWN
POWERED UP, SERIAL LINK ACTIVE
500µs
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL CHANNEL DISABLED
Figure 12. Power-Up Delay
Operating Modes
Detailed Description
The GMSL devices are configurable to operate in many
modes depending on the application. These modes allow
for a more efficient use of serial bandwidth. Most of these
settings are set during system design, and are configured
through register bits.
The MAX96701 is a compact device with features
especially suited for automotive camera applications. The
device operates at a variety of input widths and word rates
up to a total serial-data rate up to 1.74Gbps. High- band-
width mode offers a 116MHz parallel clock rate with 12 bits
of video data and 2 bits of sync (HS/VS) data. An embed-
ded 9.6kbps to 1Mbps control channel programs the
Video/Configuration Link
In normal operation, the serializer runs in video link mode
(serializer SEREN = 1) with video data and control data
sent across the serial link. Set SEREN = 0 in the serializer
to turn off serialization. The serializer powers up in video
link mode and requires a valid PCLK for operation.
2
serializer, deserializer, and any attached I C peripherals.
To promote safety applications, the device features
CRC protection of video and control data. In addition,
control-channel retransmission and high-immunity modes
reduce the effects of bit errors corrupting communica-
tion. Preemphasis and a PRBS tester allow for in-system
evaluation and optimization of the link quality.
A configuration link is available to set up the serializer,
deserializer, and peripherals when PCLK is not available.
Set SEREN = 0 and CLINK = 1 in the serializer to enable
the configuration link (SEREN = 1 forces the serializer into
video link mode). Once PCLK has been established, turn
on the video link (SEREN = 1).
The MAX96701 operates over the -40°C to +115°C
automotive temperature range.
Serial Link Signaling and Data Format
By default, video link mode requires a valid PCLK for
operation. Set AUTO_CLINK bit = 1 and SEREN = 1 in the
serializer to have the device automatically switch between
the video link and configuration link whenever PCLK is
not present.
The serializer scrambles the input parallel data and
combines this with the forward control data. The data is
then encoded for transmission and output as a single-
serialized bitstream at several times the input word rate
(depending on bus width). The deserializer receives the
serial data and recovers the clock signal. The data is then
deserialized, decoded, and descrambled into parallel out-
put data and forward control data.
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Single/Double Mode
Bus Widths
Single-/double-mode operation configures the available
1.74Gbps bandwidth into a variety of widths and word
rates. Single-mode operation is compatible with all GMSL
devices and serializers, yielding one parallel word for
each serial word. Double mode serializes two half-width
parallel words for each serial word, resulting in a 2x
increase in the parallel word rate range (compared to
single mode). Set DBL = 0 for single-mode operation and
DBL = 1 for double-mode operation.
The serial link has multiple bus-width settings that
determine the parallel bus width and the resulting parallel
word rate. The serial link operates to a maximum serial
bit rate of 1.74Gbps. The BWS bit determines if each
serial packet is 30 or 40 bits long, which translates to a
maximum serial packet rate (and resulting maximum
parallel word rate) of 58MHz or 43.5MHz when BWS = 0
or 1 respectively. Encoding translates the 24, 27, or 32
parallel bits into 30- or 40-bit serial packets. One bit is
used for parity, while a second is reserved for the control
channel. An additional 6 bits are used during optional
6-bit CRC. In addition, double mode splits the remaining
word size in half, if used. The remaining bits can be used
for video bits (minus any sync bits if H/V encoding is not
used)
HS/VS Encoding
By default, GMSL assigns a video bit slot to HSYNC,
VSYNC, and DE (if used). With HS/VS encoding, the
device instead encodes special packets to sync signals to
free up additional video bit slots. HS/VS encoding is on by
default when the device is in high-bandwidth mode (HIBW
= 1). DE is encoded only when HIBW = 1 and DE_EN =
1. Set HVEN = 1 to turn on HS/VS encoding when HIBW
= 0 (DE, if enabled, uses up a video bit). HS/VS encoding
requires that HSYNC, VSYNC, and DE (if used) remain
high during the active video and low during the blanking
period. Use HS/VS inversion when using reverse-polarity
sync signals.
The following modes list the internal bus widths. The
number of available input and output pins may limit the
actual bus width available.
● 24-Bit Mode (Figure 13)
When BWS = 0 and HIBW = 0, the 30-bit serial packet
corresponds with three 8b/10b symbols representing 24
bits (24-bit mode). After the parity and control channel,
this leaves 16/22 bits of video data if CRC is/or is not used
(single mode), or 8/11 bits of video data if CRC is/or is not
used (double mode).
Error Detection
The serial link's 8b/10b encoding/decoding and 1-bit
parity detect bit errors that occur on the serial link. An
optional 6-bit CRC check is available at the expense of 6
video bits (when HIBW = 0). To activate 6-bit CRC mode,
set PXL_CRC = 1 in the remote-side device first, then in
the local-side device. When using 6-bit CRC mode, the
available internal bus width is reduced by 6 bits in single-
input mode (DBL = 0) and 3 bits in double-input mode
(DBL = 1). Note that the input bus width may already have
been reduced due to pin availability of the serializer or
deserializer; thus, the reduction of bandwidth from CRC
may not be visible (see Table 3).
● 27-Bit High-Bandwidth Mode (Figure 14)
When BWS = 0 and HIBW = 1 (high-bandwidth mode),
the 30-bit serial packet represents three 9b/10b symbols
representing 27 bits. After the parity and control channel,
this leaves 19/25 bits of video data if CRC is/or is not used
(single mode), or 9/12 bits of video data if CRC is/or is not
used (double mode)
● 32-Bit Mode (Figure 15)
When BWS = 1, the 40-bit serial packet corresponds with
four 8b/10b symbols representing 32 bits (32-bit mode).
After parity and control channel, this leaves 24/30 bits of
video data if CRC is/or is not used (single mode), or 12/15
bits of video data if CRC is/or is not used (double mode).
An additional 32-bit video line CRC is available by
setting LINE_CRC_EN = 1. When enabled, the serializer
calculates the 32-bit CRC of the video line and sends this
information during the blanking period. The deserializer
compares the received CRC with the video line data. The
deserializer's LINE_CRC_ERR bit latches when a CRC
error is detected. LINE_CRC_ERR clears when read.
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
24-BIT
MODE
22 BITS
2 BITS
SERIAL
DATA
D0
D1
D15
D16
D17
D18
D19
D20
D21
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET PARITY-
CHECK BIT
6
FORWARD
CONTROL-CHANNEL
BIT
22 VIDEO
BITS
16 VIDEO
BITS
PXL_CRC
BITS
D0
D1
D21
D0
D1
D15
D16
D17
D18
D19
D20
D21
SDA
SCL
I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
11 x 2
VIDEO
BITS*
8 x 2
VIDEO
BITS*
22 VIDEO
BITS*
PXL_CRC
16 VIDEO
BITS*
D11
D0
D12
D21
D10
D0
D1
D21
D8
D0
D9
D15
D1
D0
D1
D15
NO PXL_CRC, DBL = 0
58MHz (max)
D1
D7
NO PXL_CRC, DBL = 1
116MHz (max)
PXL_CRC ON, DBL = 0
58MHz (max)
PXL_CRC ON, DBL = 1
116MHz (max)
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 13. 24-Bit Mode Serial-Data Format
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
27-BIT
MODE
25 BITS
D17
2 BITS
SERIAL
DATA
D0
D1
D15
D16
D18
D19
D20
D21
D22
D23
D24
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET PARITY-
CHECK BIT
6
FORWARD
CONTROL-CHANNEL
BIT
25 VIDEO
BITS
19 VIDEO
BITS
PXL_CRC
BITS
SDA
SCL
D0
D1
D24
D0
D1
D15
D16
D17
D18
D22
D23
D24
I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
12 x 2
VIDEO
BITS*
9 x 2
VIDEO
BITS*
25 VIDEO
BITS*
PXL_CRC
19 VIDEO
BITS*
D12
D0
D13
D23
D11
D24
D0
D1
D24
D9
D0
D10
D17
D18
D1
D0
D1
D18
NO PXL_CRC, DBL = 0
58MHz (max)
D1
D8
NO PXL_CRC, DBL = 1
116MHz (max)
PXL_CRC ON, DBL = 0
58MHz (max)
PXL_CRC ON, DBL = 1
116MHz (max)
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 14. 27-Bit High-Bandwidth Mode Serial-Data Format
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
32-BIT
MODE
30 BITS
2 BITS
SERIAL
DATA
D0
D1
D23
D24
D25
D26
D27
D28
D29
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET
PARITY-
CHECK BIT
6
FORWARD
CONTROL-CHANNEL
BIT
30 VIDEO
BITS
24 VIDEO
BITS
PXL_CRC
BITS
SDA
SCL
I2C
D0
D2
D29
D0
D2
D23
D24
D25
D26
D27
D28
D29
DBL = 0
DBL = 1
DBL = 1
DBL = 0
15 x 2
VIDEO
BITS*
12 x 2
VIDEO
BITS*
30 VIDEO
BITS*
PXL_CRC
24 VIDEO
BITS*
D15
D0
D16
D29
D14
D0
D1
D29
D12
D0
D13
D23
D1
D0
D1
D23
NO PXL_CRC, DBL = 0
43.5MHz (max)
D1
D11
NO PXL_CRC, DBL = 1
87MHz (max)
PXL_CRC ON, DBL = 0
43.5MHz (max)
PXL_CRC ON, DBL = 1
87MHz (max)
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 15. 32-Bit Mode Serial-Data Format
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
to and from the other side of the link (remote side), allow-
ing a single microcontroller to configure the serializer,
Control Channel and Register Programming
The control channel sends information across the serial
link for control of the serializer, deserializer, and any
attached peripherals. The control channel is multiplexed
onto the serial link and is available with or without the
video channel.
deserializer, and peripherals. The microcontroller can be
located on the serializer side (display applications) and
the deserializer side (camera applications). Dual micro-
controller operations are supported as long as a software-
arbitration method is used. The serial link assumes that
only one microcontroller is talking at any given time.
Forward Control Channel
Control data sent from the serializer to the deserializer is
sent on the forward control channel. The data is encoded
as one of the serial bits in the forward high-speed link. After
deserialization, the forward control-channel data is extract-
ed from the serial link. The forward control-channel band-
width exceeds the maximum external control data rate, and
all data sent on the forward control channel appears on
the remote side after transmission delay of a few bit times.
Remote-End Operation
2
When an I C master initiates communication on the local
slave device (the serializer/deserializer directly connected
to the master), the remote-side device acts as a master
device that sends data forwarded from the local-side
device, and forwards any data received from peripher-
als attached to the remote-side device. This remote-
side master device operates according to the timing
Reverse Control Channel
2
settings in the I C master setting register. Set the master
Control data sent from the deserializer to the serializer is
sent on the reverse control channel. The data is encoded
as a series of 1μs pulses, with a maximum raw data rate of
1Mbps. High-immunity mode is available to increase the
robustness of the reverse control channel at a reduced
raw bit rate of 500kbps. In Table 1, setting the REV_FAST
bit = 1 increases this rate back to 1Mbps. When the input
data rate (after encoding) exceeds the reverse data rate,
the input clock is held through clock stretching to slow the
external clock to match the internal bit rate.
settings to match the timing settings used by the
external microcontroller.
Clock-Stretch Timing
2
The I C interface uses clock stretching to allow time for
data to be forwarded across the serial link. The master
microcontroller, along with any attached peripherals, must
accept clock stretching of the GMSL devices.
2
Packet-Based I C
A packet-based control channel is available for enhanced
error handling of the control channel. This control-
channel method handles simultaneous GPI/GPO and
2
I C Interface
2
The serial link connects the serializer and deserializer I C
2
I C transmission, along with error detection and retrans-
interfaces together through the control channel. When
2
mission.
an I C master sends a command to one side of the link
(local side) the control channel forwards this information
Table 1. Reverse Control-Channel Modes
2
REVERSE CONTROL-CHAN-
MAXIMUM I C BIT RATE
(kBPS)
HIM PIN SETTING
REVFAST BIT
NEL MODE
Legacy reverse control-channel
mode (compatible with all GMSL
devices)
Low
X
0
1
1000
500
High-immunity mode
Fast high-immunity mode
(requires HIBW = 0, serial-data
rate > 1.25Gbps)
High
1000
X = Don’t care.
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Packet Protocol Summary
Crossbar Switch
The packet-based control channel uses a synchronous,
symbol-based system to send data across the control
channel. Data to be sent across the control channel is split
into symbols and stored in a transmit queue and then sent
The crossbar switch routes data between the parallel
input/output and the SerDes. The anything-to-anything
routing assures the mapping between the video source
and destination. For each crossbar output (XBO_) an
input multiplexer selects from the available crossbar
inputs (XBI_) using the CROSSBAR_ register bits (Figure
17). Multiple crossbar outputs can use the same crossbar
input. By default, the sync signals share the same inputs
as the MSBs of the video data.
2
across the link. If both GPI and I C data needs to be sent
2
(e.g., when GPI transitions during an I C transmission), the
symbols from both commands are combined in the queue.
If the transmit queue is empty, idle packets are sent across
2
the link to maintain control-channel lock. Received I C
packets are output as determined by the microcontroller
SCL rate (local device) or the programmed master bit rate
(remote device). The device holds SCL low (clock stretch)
until data has been received from the remote-side device.
Video Timing Generator
The serializer includes a programmable video timing
generator to generate/retime the input sync signals. The
timing generator can be used to modify a camera's input
timing, filter out glitches in the sync signals, or to reduce
the number of required input sync signals. Each sync
signal can be individually retimed or left unmodified.
Several registers determine the length of the timing
parameters (in PCLK cycles) shown in Figure 18. Timing
parameters include high/low period length, line count, and
delay from the input VS signal.
Control-Channel Error Detection and Packet
Retransmission
When the packet-based control channel is used, all pack-
ets are checked for errors through CRC. Using 1, 5, or 8
bits, CRC detects 1, 3, or 4 random bit errors in a packet.
The transmitter retransmits packets whenever an error is
detected. The transmitter sets a flag if a number of retries
exceeds eight. The receiver filters out packets with errors.
The timing generator uses three different trigger modes,
tracking, single trigger, and autorun. Tracking mode looks
at the input VSYNC and locks once it receives three
consecutive identical VSYNC signals. The tracker then
continues to output the same identical signal, erasing any
glitches that may appear on VSYNC. The tracker attempts
to relock to a new signal if three consecutive input wave-
forms do not match the locked signal. Single trigger
generates one generated frame for each input VSYNC
edge. Autorun generates a new frame at the rate deter-
mined by the VSYNC high/low period. If a new VSYNC
signal appears before a frame is complete in either single
trigger or autorun modes, a new frame immediately starts,
cutting the previous frame short.
GPO/GPI Control
GPO on the serializer follows GPI transitions on the
deserializer. This GPO/GPI function can be used to
transmit signals such as a frame sync in a surround-view
camera system (see the Providing a Frame Sync (Camera
Applications) section). Optionally, GPO can be set directly
by register bits.
Spread Spectrum
The serializer contains a programmable spread-spectrum
output to lower emission levels by spreading the clock-
frequency peaks across a frequency spectrum. In addition,
the serializer and deserializer can track a spread input
clock, eliminating the need for multiple spread clocks.
Cable Type Configuration
The driver output is programmable for two kinds of
cable,100Ω twisted pair and 50Ω coax (contact the
factory for devices compatible with 75Ω cables). In coax
mode, connect OUT+ to IN+ of the deserializer. Leave
the unused IN_ pin unconnected, or connect it to ground
through 50Ω, and a capacitor for increased power-supply
GMSL
SERIALIZER
GMSL
DESERIALIZER
OUT+
IN+
OUT-
IN-
AVDD
rejection. Connect OUT- to V
(Figure 16).
through a 50Ω resistor
DD
OPTIONAL COMPONENTS
FOR INCREASED
50Ω
POWER-SUPPLY REJECTION
Figure 16. Coax Connection
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
DATA
LOW INPUT
DIN0
XBI0
XBI1
:
XBO0
XBO1
:
XBO29
XBO30
D0
D1
:
D29
D30
DIN1
:
:
CROSSBAR_
5
DIN9
DIN10
DIN11
DIN12/HS
DIN13/VS
XBI9
XBI10
XBI11
XBI12
XBI13
XBI14**
XBI15**
0
1
XBOHS
XBOVS
XBODE
HS
VS
DE
FORCE_MUX_
0
SYNC
PCLK
HIGH INPUT
(DBL = 1 only)
DIN0
XBI16
XBI17
:
XBI25
XBI26
XBI27
XBI28
XBI29
XBI30**
XBI31**
DIN1
:
DIN9
DIN10
DIN11
:
INVERT_MUX_
HS/DE*
HI_LO*
HS/DE
HS/DE
1
0
DIN12/HS
DIN13/VS
DIN13/VS
DIN12/HS
DIN11/GPIO2
...
XBI29
XBI28
XBI27
XBI13
XBI12
XBI11
XBI29
XBI28
XBI27
XBI13
XBI12
XBI11
...
DIN1
DIN0
XBI17
XBI16
XBI1
XBI0
XBI17
XBI16
XBI1
XBI0
XBO_
34 SWITCHES
*REGISTER SETTINGS DECIDE IF HS, DE, OR HI_LO DETERMINES THE HIGH/LOW INPUT TIMING.
**XBI14, XBI15, XBI30, XBI31 INPUT INTERNALLY CONNECTED LOW.
Figure 17. Crossbar Switch Dataflow
VS_IN
VS_DLY
VS_OUT
VS_L
VS_H
HS_DLY
HS OUT
HS_L
HS_H
HS_CNT (PULSE COUNT)
DE_CNT (PULSE COUNT)
DE_DLY
DE_L
DE OUT
DE_H
Figure 18. Sync Signal Format for Video-Timing Generation
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
CLINKEN = 0
OR SEREN = 1
CLINKEN = 0
CONFIG LINK
SLEEP = 1
FOR > 8ms
CONFIG LINK
UNLOCKED
OR SEREN = 1
POWER ON
IDLE
CONFIG
LINK
OPERATING
SLEEP = 0,
SEREN = 0
SLEEP
WAKEUP
CLINKEN = 1
CONFIG LINK
LOCKED
STARTED
PROGRAM
LINK WAKEUP SIGNAL
REGISTERS
SEREN = 1,
PCLKIN RUNNING
SEREN = 0 OR
NO PCLKIN
SLEEP = 1
POWER ON
SLEEP = 0,
SEREN = 1
SEREN = 0 OR
NO PCLKIN
PRBSEN = 0
PRBSEN = 1
POWER
DOWN
OR
VIDEO
LINK
LOCKING
POWER OFF
VIDEO LINK
LOCKED
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
POWER OFF
VIDEO LINK
UNLOCKED
Figure 19. State Diagram
serialization. In this mode, all forward communication is
shut down. The user can reenable serialization either
locally, or through the reverse channel.
Shutdown/Sleep Modes
Several sleep and shutdown modes are available when
full operation is not needed.
Sleep Mode
Configuration Link
To reduce power consumption further, the devices can
be put into sleep mode. In this mode, all registers keep
their programmed values, and all functions in the device
are powered down except for the wake-up detectors on
the local control interface, and the serial link. Any activity
seen by the wake-up detectors temporarily turns on the
control-channel interface. During this time, a microcon-
troller can command the device to exit sleep mode. See
the Shutdown/Sleep Modes section.
When the high-speed video link is not needed, or unavail-
able, a configuration link can be used in its place. In
configuration link mode, the parallel digital input/output is
disabled, the LOCK pin remains low, and the serial link
internally generates its own clock to allow full operation of
2
the control channel (I C and GPIO).
Serialization Disable
When the serial link is not needed, such as when down-
stream devices are powered off, the user can disable
Maxim Integrated
│ 32
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
video link or the configuration link is established. If the
deserializer powers up after the serializer, the control
channel becomes unavailable until 2ms after power-up.
Link Startup Procedure
Table 2 lists the startup procedure for image-sensing
applications. The control channel is available after the
Table 2. Link-Startup Procedure
NO.
μC
SERIALIZER
DESERIALIZER
—
μC Connected to Deserializer
Set Configuration Inputs
Set Configuration Inputs
Powers up and loads default
settings. Establishes video link
when valid PCLK is available.
Powers up and loads default
settings. Locks to video link
signal if available.
1
Powers up (wait t ).
PU
If no PCLK, programs CLINKEN, SEREN, and/or
AUTOCLINK bits. Wait 5ms after each command.
Locks to configuration link if
available.
1a
Establishes configuration link.
If not locked, sets any additional configuration bits
that are mismatched between the serializer and
deserializer (e.g., BWS, CX/TP). Wait 5ms for lock
after each command.
Configuration changed.
Reestablishes configuration/video
link if needed.
Configuration changed. Locks
to configuration/video link.
1b
Configuration changed.
Reestablishes configuration/video Loss-of-lock may occur.
link if needed.
Sets register 0x07 configuration bits in the serializer
(DBL, BWS, HIBW, PXL_CRC, etc.). Wait 2ms.
2
3
Sets register 0x07 configuration bits in the deserial-
izer (DBL, BWS, HIBW, PXL_CRC, etc.). Wait 5ms for
lock to reestablish.
Configuration changed. Locks
to configuration/video link.
—
4
5
Writes rest of serializer/deserializer configuration bits. Configuration changed.
Configuration changed.
Forwards commands from μC to
Forwards commands to
camera/peripherals.
Writes camera/peripheral configuration bits.
serializer.
If in configuration link, when PCLK is available, set
SEREN = 1. Wait 5ms for lock.
5a
Enables video link.
Locks to video link.
Maxim Integrated
│ 33
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Register Map
GMSL Register Map
OFFSET
NAME
MSB
LSB
CFG-
0x00
seraddr
SERADDR[6:0]
BLOCK
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
desaddr
ss
DESADDR[6:0]
RSVD
RSVD
SRNG[1:0]
SS[2:0]
AUTOFM[1:0]
PRNG[1:0]
SDIV[5:0]
RSVD[1:0]
sdiv
main_control
prbs_len
SEREN
RSVD
CLINKEN PRBSEN SLEEP
RSVD PRBS_LEN[1:0]
CMLLVL[3:0]
REVCCENFWDCCEN
RSVD RSVD
PREEMP[3:0]
RSVD
RSVD
cmllvl_preemp
config
DBL
HIBW
RSVD
BWS
RSVD
ES
RSVD
RSVD
HVEN
RSVD
RSVD PXL_CRC
rsvd_8
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
i2c_source A
i2c_dest A
i2c_source B
i2c_dest B
I2C_SRC_A[6:0]
I2C_DST_A[6:0]
I2C_SRC_B[6:0]
I2C_DST_B[6:0]
I2C_LOC_
ACK
0x0D
0x0E
0x0F
0x10
0x11
i2c_config
gpio_en
gpio_out
gpio_in
errg
I2C_SLV_SH[1:0]
I2C_MST_BT[2:0]
I2C_SLV_TO[1:0]
GPIO_
EN_2
GPIO_
RSVD
EN_1
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
EN_SET_
GPO
GPIO_
OUT_2
GPIO_
SET_GPO
OUT_1
GPIO_
IN_2
GPIO_
GPO_L
IN_1
RSVD
ERRG_
ERRG_EN
PER
ERRG_RATE[1:0]
ERRG_TYPE[1:0]
RSVD
ERRG_CNT[1:0]
0x12
0x13
rsvd_12
pd
RSVD
RSVD
RSVD
RSVD[4:0]
RSVD
SOFT_PD
RSVD
RSVD
RSVD
RSVD
RSVD[1:0]
CC_
REM_
0x14
0x15
0x16
pktcc_lock
input_status
max_rt_err
RSVD[1:0]
RSVD
RSVD
RSVD
RSVD
WBLOCK CCLOCK
OUT-
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PCLKDET
PUTEN
MAX_RT_
ERR
RSVD[5:0]
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
rsvd_17
crc 0
RSVD[7:0]
CRC_VALUE_0[7:0]
CRC_VALUE_1[7:0]
CRC_VALUE_2[7:0]
CRC_VALUE_3[7:0]
CC_CRC_ERRCNT[7:0]
RSVD[7:0]
crc 1
crc 2
crc 3
cc_crc_errcnt
rsvd_1d
Maxim Integrated
│ 34
www.maximintegrated.com
MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
GMSL Register Map (continued)
OFFSET
0x1E
NAME
MSB
LSB
id
ID[7:0]
0x1F
revision
RSVD
RSVD
RSVD
FORCE_ INVERT_
MUX_0 MUX_0
FORCE_ INVERT_
MUX_1 MUX_1
FORCE_ INVERT_
MUX_2 MUX_2
FORCE_ INVERT_
MUX_3 MUX_3
FORCE_ INVERT_
MUX_4 MUX_4
FORCE_ INVERT_
MUX_5 MUX_5
FORCE_ INVERT_
MUX_6 MUX_6
FORCE_ INVERT_
MUX_7 MUX_7
FORCE_ INVERT_
MUX_8 MUX_8
FORCE_ INVERT_
MUX_9 MUX_9
RSVD HDCPCAP
REVISION[3:0]
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
crossbar 0
crossbar 1
crossbar 2
crossbar 3
crossbar 4
crossbar 5
crossbar 6
crossbar 7
crossbar 8
crossbar 9
crossbar 10
crossbar 11
crossbar 12
crossbar 13
crossbar 14
crossbar 15
crossbar 16
crossbar 17
crossbar 18
crossbar 19
crossbar 20
CROSSBAR_0[4:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CROSSBAR_1[4:0]
CROSSBAR_2[4:0]
CROSSBAR_3[4:0]
CROSSBAR_4[4:0]
CROSSBAR_5[4:0]
CROSSBAR_6[4:0]
CROSSBAR_7[4:0]
CROSSBAR_8[4:0]
CROSSBAR_9[4:0]
CROSSBAR_10[4:0]
CROSSBAR_11[4:0]
CROSSBAR_12[4:0]
CROSSBAR_13[4:0]
CROSSBAR_14[4:0]
CROSSBAR_15[4:0]
CROSSBAR_16[4:0]
CROSSBAR_17[4:0]
CROSSBAR_18[4:0]
CROSSBAR_19[4:0]
CROSSBAR_20[4:0]
FORCE_ INVERT_
MUX_10 MUX_10
FORCE_ INVERT_
MUX_11 MUX_11
FORCE_ INVERT_
MUX_12 MUX_12
FORCE_ INVERT_
MUX_13 MUX_13
FORCE_ INVERT_
MUX_14 MUX_14
FORCE_ INVERT_
MUX_15 MUX_15
FORCE_ INVERT_
MUX_16 MUX_16
FORCE_ INVERT_
MUX_17 MUX_17
FORCE_ INVERT_
MUX_18 MUX_18
FORCE_ INVERT_
MUX_19 MUX_19
FORCE_ INVERT_
MUX_20 MUX_20
Maxim Integrated
│ 35
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
GMSL Register Map (continued)
OFFSET
NAME
MSB
LSB
FORCE_ INVERT_
MUX_21 MUX_21
0x35
crossbar 21
RSVD
CROSSBAR_21[4:0]
CROSSBAR_22[4:0]
CROSSBAR_23[4:0]
CROSSBAR_24[4:0]
CROSSBAR_25[4:0]
CROSSBAR_26[4:0]
CROSSBAR_27[4:0]
CROSSBAR_28[4:0]
CROSSBAR_29[4:0]
CROSSBAR_30[4:0]
CROSSBARHS[4:0]
CROSSBARVS[4:0]
FORCE_ INVERT_
MUX_22 MUX_22
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
crossbar 22
crossbar 23
crossbar 24
crossbar 25
crossbar 26
crossbar 27
crossbar 28
crossbar 29
crossbar 30
crossbar_hs
crossbar_vs
crossbar_de
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FORCE_ INVERT_
MUX_23 MUX_23
FORCE_ INVERT_
MUX_24 MUX_24
FORCE_ INVERT_
MUX_25 MUX_25
FORCE_ INVERT_
MUX_26 MUX_26
FORCE_ INVERT_
MUX_27 MUX_27
FORCE_ INVERT_
MUX_28 MUX_28
FORCE_ INVERT_
MUX_29 MUX_29
FORCE_ INVERT_
MUX_30 MUX_30
FORCE_ INVERT_
MUX_HS MUX_HS
FORCE_ INVERT_
MUX_VS MUX_VS
FORCE_ INVERT_
MUX_DE MUX_DE
CROSSBARDE[4:0]
GPI_
LINE_
CRC_EN RT_EN
MAX_
GPI_RT_
0x42
0x43
link_config
LINE_CRC_LOC[1:0]
RSVD
COMP_
EN
GPO_EN
EN
VS_
TRIG
sync_gen_config
RSVD
RSVD
GEN_VS GEN_HS GEN_DE
VTG_MODE[1:0]
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
vs_dly 2
vs_dly 1
vs_dly 0
vs_h 2
vs_h 1
vs_h 0
vs_l 2
VS_DLY[7:0]
VS_DLY[7:0]
VS_DLY[7:0]
VS_H[7:0]
VS_H[7:0]
VS_H[7:0]
VS_L[7:0]
vs_l 1
VS_L[7:0]
vs_l 0
VS_L[7:0]
VSYNC_ HSYNC_
INV INV
HS_DLY[7:0]
0x4D
cxtp
HIGHIMM
CXTP
RSVD
RSVD
DE_INV
RSVD
0x4E
hs_dly 2
Maxim Integrated
│ 36
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
GMSL Register Map (continued)
OFFSET
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
NAME
hs_dly 1
MSB
LSB
HS_DLY[7:0]
HS_DLY[7:0]
RSVD[7:0]
hs_dly 0
rsvd_51
rsvd_52
rsvd_53
hs_h 1
RSVD[7:0]
RSVD[7:0]
HS_H[7:0]
hs_h 0
HS_H[7:0]
hs_l 1
HS_L[7:0]
hs_l 0
HS_L[7:0]
hs_cnt 1
hs_cnt 0
de_dly 2
de_dly 1
de_dly 0
rsvd_5D
rsvd_5E
rsvd_5F
de_h 1
HS_CNT[7:0]
HS_CNT[7:0]
DE_DLY[7:0]
DE_DLY[7:0]
DE_DLY[7:0]
RSVD[7:0]
RSVD[7:0]
RSVD[7:0]
DE_H[7:0]
de_h 0
DE_H[7:0]
de_l 1
DE_L[7:0]
de_l 0
DE_L[7:0]
de_cnt 1
de_cnt 0
DE_CNT_1[7:0]
DE_CNT_0[7:0]
PRBS_
TYPE
REV_
FAST
DIS_
RWAKE
0x66
0x67
0x68
0x69
prbs_type
dbl_align_to
cc_crc_length
hi_lo
RSVD[1:0]
RSVD[1:0]
DE_EN
RSVD
RSVD
CXSEL
AUTO_
CLINK
RSVD
DBL_ALIGN_TO[2:0]
CC_CRC_
LENGTH[1:0]
RSVD
RSVD
RSVD[2:0]
RSVD[1:0]
EN_HI_ INVERT_
CROSSBAR_HI_LO[4:0]
LO
HI_LO
0x96
0x97
0x98
0x99
rsvd_96
rsvd_97
rsvd_98
rsvd_99
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD[1:0]
RSVD[2:0]
RSVD[2:0]
RSVD[1:0]
RSVD
RSVD[1:0]
RSVD[2:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
PKTCC_
EN
0x9A
pktcc_en
RSVD[1:0]
RSVD[1:0]
RSVD[1:0]
RSVD
Maxim Integrated
│ 37
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
GMSL Register Map (continued)
OFFSET
0xC8
NAME
MSB
LSB
rsvd_c8
rsvd_c9
rsvd_fc
rsvd_fd
rsvd_fe
rsvd_ff
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
0xC9
RSVD[7:0]
0xFC
0xFD
0xFE
RSVD
RSVD
RSVD
RSVD
RSVD[7:0]
RSVD[3:0]
RSVD[3:0]
0xFF
RSVD
RSVD
RSVD
RSVD[3:0]
seraddr (0x00)
BIT
7
6
5
4
3
2
1
0
Field
SERADDR[6:0]
1000000b
CFGBLOCK
0b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0000000: Write/read device address is 0x00/0x01
0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
SERADDR
7:1
0
Serializer Address: Serializer device address
Configuration Block: Set to 1 to make all
CFG-
BLOCK
0: Make all registers read/write
registers read-only. Power-on reset to clear this bit. 1: Make all registers read-only
desaddr (0x01)
BIT
7
6
5
4
3
2
1
0
RSVD
0b
Field
DESADDR[6:0]
1001000b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
DESADDR
RSVD
BITS
DESCRIPTION
DECODE
0000000: Write/read device address is 0x00/0x01
7:1
0
Deserializer Address: Deserializer device address 0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
Reserved: Do not change from default value
0: Reserved
Maxim Integrated
│ 38
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
ss (0x02)
BIT
7
6
5
4
RSVD
1b
3
2
1
0
Field
SS[2:0]
010b
PRNG[1:0]
11b
SRNG[1:0]
11b
Reset
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
000: Spread is off
001: 0.5% Spread setting
010: 1.5% Spread setting
011: 2% Spread setting
100: Spread is off
101: 1% Spread setting
110: 3% Spread setting
111: 4% Spread setting
SS
7:5
Spread Spectrum: Spread-spectrum setting
Reserved: Do not change from default value
RSVD
PRNG
4
1: Reserved
00: Select 12.5MHz to 25MHz (DBL = 0) or 25MHz
to 50MHz (DBL = 1) pixel clock range
01: Select 25MHz to 58MHz (DBL = 0) or 50MHz to
116MHz (DBL = 1) pixel clock range
Pixel Clock Range: Pixel clock-range selection
Stated ranges depend on DBL = setting
3:2
10: Automatically detect pixel clock range
11: Automatically detect pixel clock range.
00: 0.5Gbps to 1Gbps serial-data range
01: 1Gbps to 1.74Gbps serial-data range
10: Automatically detect serial-data range
11: Automatically detect serial-data range
SRNG
1:0
Serial-Data Rate Range
sdiv (0x03)
BIT
7
6
5
4
3
2
1
0
Field
AUTOFM[1:0]
SDIV[5:0]
000000b
Reset
00b
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
00: Calibration occurs once
Automatic Frequency Modulation: Modulation-
rate calibration interval
01: Calibration occurs every 2ms
10: Calibration occurs every 16ms
11: Calibration occurs every 256ms
AUTOFM
7:6
000000: Sawtooth divider automatically calibrates
the divider value
000001: Sawtooth divider set to 1
111111: Sawtooth divider set to 63
Sawtooth Divider: Sawtooth divider value
0x00 sets the sawtooth divider to autocalibrate
mode
SDIV
5:0
Maxim Integrated
│ 39
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
main_control (0x04)
BIT
Field
Reset
7
SEREN
1b
6
CLINKEN
0b
5
PRBSEN
0b
4
3
2
1
REVCCEN
1b
0
FWDCCEN
1b
SLEEP
0b
RSVD[3:2]
01b
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read
Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Serialization Enable: Requires a valid PCLK for
serialization
0: Disable serialization
1: Enable serialization
SEREN
7
Configuration Link Enable: Configuration link
enabled only when the video link is not enabled
(SEREN = 1)
0: Disable configuration link
1: Enable configuration link
CLINKEN
PRBSEN
6
5
PRBS Test Enable: See the PRBS test section for 0: Disable PRBS test
more details
1: Enable PRBS test
Sleep Mode Enable: Activates sleep mode
(see the Shutdown/Sleep Modes section for more
information)
0: Disable sleep mode
1: Enable sleep mode
SLEEP
4
3:2
1
RSVD
Reserved: Do not change from default value
01: Reserved
Reverse Control-Channel Enable: Enable
reverse control-channel receiver (data from
deserializer)
0: Disable reverse control-channel receiver
1: Enable reverse control-channel receiver
REVCCEN
Forward Control Channel Enable: Enable
forward control channel receiver
(data to deserializer)
0: Disable forward control channel transmitter
1: Enable forward control channel transmitter
FWDCCEN
0
prbs_len (0x05)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
PRBS_LEN[1:0]
00b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
0: Reserved
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
RSVD
0: Reserved
00: Continuous bit pattern (infinite length)
01: 9.8Mbit length
10: 167.1Mbit length
PRBS_LEN
5:4
PRBS Length: PRBS test pattern length
11: 1341.5Mbit length
RSVD
RSVD
RSVD
RSVD
3
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
Maxim Integrated
│ 40
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
cmllvl_preemp (0x06)
BIT
Field
7
6
5
4
3
2
1
0
CMLLVL[3:0]
10X0b
PREEMP[3:0]
Reset
0000b
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0000: Do not use
0001: Do not use
0010: 100mV output
0011: 150mV output
0100: 200mV output
0101: 250mV output
0110: 300mV output
0111: 350mV output
1000: 400mV output (STP default)
1001: 450mV output
1010: 500mV output (coax default)
1011: Do not use
CML Level: Output CML signal level = (register
value) x 50mV
Default level depends on cable type (CXTP)
CMLLVL
7:4
1100: Do not use
1101: Do not use
111X: Do not use
0000: Preemphasis off
0001: 1.2dB deemphasis
0010: 2.5dB deemphasis
0011: 4.1dB deemphasis
0100: 6.0dB deemphasis
0101: Do not use
011X: Do not use
PREEMP
3:0
Preemphasis Level: Preemphasis setting
1000: 1.1dB preemphasis
1001: 2.2dB preemphasis
1010: 3.3dB preemphasis
1011: 4.4dB preemphasis
1100: 6.0dB preemphasis
1101: 8.0dB preemphasis
1110: 10.5dB preemphasis
1111: 14.0dB preemphasis
Maxim Integrated
│ 41
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
config (0x07)
BIT
7
6
5
4
3
2
1
0
PXL_CRC
0b
Field
DBL
1b
HIBW
0b
BWS
0b
ES
0b
RSVD
0b
HVEN
1b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Single-input mode
1: Double-input mode
Double-Input Mode Enable: Set high to enable
double-input mode
DBL
7
High-Bandwidth Mode Enable: High-bandwidth
mode select (effective only when BWS = 0)
0: Use 24-bit mode when BWS = 0
1: Use high-bandwidth mode when BWS = 0
HIBW
BWS
6
5
0: 24-bit and high-bandwidth mode
1: 32-bit mode
Bus-Width Select
0: Parallel data clocked in on rising edge
1: Parallel data clocked in on falling edge
ES
4
3
2
1
0
Edge Select
RSVD
HVEN
RSVD
PXL_CRC
Reserved: Do not change from default value
HSYNC/VSYNC Encoding Enable
Reserved: Do not change from default value
Pixel CRC Type: Pixel error-detection type
0: Reserved
0: Disable HS/VS encoding
1: Enable HS/VS encoding
0: Reserved
0: Serial data uses 1-bit parity
1: Serial data uses 6-bit CRC
rsvd_8 (0x08)
BIT
7
6
5
4
3
2
1
0
Field
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
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│ 42
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
i2c_source (0x09, 0x0B)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
I2C_SRC[6:0]
0000000b
Write, Read
Reset
Access Type
Write, Read
BITFIELD
I2C_SRC
RSVD
BITS
7:1
0
DESCRIPTION
DECODE
0000000: Write/read device address is 0x00/0x01
0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
2
2
I C Source: I C address translator source
Reserved: Do not change from default value
0: Reserved
i2c_dest (0x0A, 0x0C)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
I2C_DST[6:0]
0000000b
Write, Read
Reset
Access Type
Write, Read
BITFIELD
BITS
7:1
DESCRIPTION
DECODE
0000000: Write/read device address is 0x00/0x01
2
2
I2C_DST
RSVD
I C Destination: I C address translator destination 0000001: Write/read device address is 0x02/0x03
1111111: Write/read device address is 0xFE/0xFF
0
Reserved: Do not change from default value
0: Reserved
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│ 43
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
i2c_config (0x0D)
BIT
7
6
5
4
3
2
1
0
I2C_LOC_
ACK
Field
I2C_SLV_SH[1:0]
I2C_MST_BT[2:0]
I2C_SLV_TO[1:0]
Reset
1b
01b
101b
10b
Access Type Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Do not send local autoacknowledge when
control channel is absent
1: Send local autoacknowledge when control
channel is absent
2
2
2
I C Local Acknowledge: I C-to-I C slave
generates local acknowledge when forward
channel is not available
I2C_LOC_
ACK
7
00: (352ns, 117ns) setup/hold time
01: (469ns, 234ns) setup/hold time
10: (938ns, 352ns) setup/hold time
11: (1406ns, 469ns) setup/hold time
2
2
2
I2C_SLV_
SH
I C Slave Setup/Hold Time: I C-to-I C slave
6:5
4:2
1:0
setup and hold-time setting (setup, hold) (typ)
000: (6.61, 8.47, 9.92) kbps
001: (22.1, 28.3, 33.2) kbps
010: (66.1, 84.7, 99.2) kbps
011: (82, 105, 123) kbps
100: (136, 173, 203) kbps
101: (265, 339, 397) kbps
110: (417, 533, 625) kbps
111: (654, 837, 980) kbps
2
2
2
I2C_MST_
BT
I C Master Bit Rate: I C-to-I C master bit-rate
setting (min, typ, max)
00: 64μs slave timeout
01: 256μs slave timeout
10: 1024μs slave timeout
11: Slave timeout disabled
2
2
2
I2C_SLV_
TO
I C Slave Timeout: I C-to-I C slave remote-side
timeout setting (typ)
gpio_en (0x0E)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
GPIO_EN_2 GPIO_EN_1
0b 0b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
RSVD
RSVD
0: Pin functions as a parallel input
1: Pin functions as a GPIO
GPIO_EN_2
2
GPIO Enable: Disabled by default
0: Pin functions as parallel input
1: Pin functions as GPIO
GPIO_EN_1
RSVD
1
0
GPIO Enable: Disabled by default
Reserved: Do not change from default value
0: Reserved
Maxim Integrated
│ 44
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
gpio_out (0x0F)
BIT
7
6
5
4
3
2
1
0
SET_GPO
0b
EN_SET_
GPO
GPIO_
OUT_2
GPIO_
OUT_1
Field
RSVD
RSVD
RSVD
RSVD
Reset
0b
0b
1b
1b
1b
1b
1b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Enable Set GPO: Set to 1 to enable setting of GPO
from SET_GPO
0: Disable setting of GPO through SET_GPO
1: Enable setting of GPO through SET_GPO
EN_SET_GPO
7
RSVD
RSVD
RSVD
RSVD
6
5
4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
1: Reserved
1: Reserved
1: Reserved
0: Set GPIO output level low
1: Set GPIO output level high
GPIO_OUT_2
GPIO_OUT_1
SET_GPO
2
1
0
GPIO Output Level: Pull down GPIO when 0
GPIO Output Level: Pull down GPIO when 0
0: Set GPIO output level low
1: Set GPIO output level high
Set GPO Level: Set GPO output high or low (when
EN_SET_GPO = 1)
0: Set GPO output low
1: Set GPO output high
gpio_in (0x10)
BIT
7
RSVD
0b
6
RSVD
0b
5
RSVD
0b
4
RSVD
0b
3
RSVD
0b
2
1
0
Field
GPIO_IN_2 GPIO_IN_1
GPO_L
0b
Reset
Xb
Xb
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
Reserved
Reserved
0: Reserved
RSVD
0: Reserved
X: Reserved
X: Reserved
X: Reserved
RSVD
Reserved
Reserved
Reserved
RSVD
RSVD
0: GPIO input is low
1: GPIO input is high
GPIO_IN_2
GPIO_IN_1
GPO_L
2
1
0
GPIO Input Level: Input pin level of GPIO
GPIO Input Level: Input pin level of GPIO
GPO Output Level
0: GPIO input is low
1: GPIO input is high
0: GPO output level is low
1: GPO output level is high
Maxim Integrated
│ 45
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
errg (0x11)
BIT
7
6
5
4
3
2
1
0
Field
ERRG_RATE[1:0]
0b
ERRG_TYPE[1:0]
0b
ERRG_CNT[1:0]
0b
ERRG_PER ERRG_EN
0b 0b
Reset
Access Type
Write, Read
Write, Read
Write, Read
Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
00: Generate errors every 2560 bits
01: Generate errors every 40,960 bits
10: Generate errors every 655,360 bits
11: Generate errors every 10,485,760 bits
Error-Generation Rate: Error-generation rate, on
average
ERRG_RATE
7:6
00: Single-bit errors
01: 2 8b/10b symbols
10: 3 8b/10b symbols
11: 4 8b/10b symbols
ERRG_TYPE
ERRG_CNT
5:4
3:2
Error-Generation Type: Type of generated errors
00: Generate errors continuously
01: Generate16 errors
10: Generate 128 errors
11: Generate 1024 errors
Error-Generation Count: Number of generated
errors
0: Generator creates errors randomly (based on
error rate)
1: Generator creates errors periodically (based
on error rate)
ERRG_PER
ERRG_EN
1
0
Periodic Error Generation Enable
Error Generator Enable
0: Disable error generator
1: Enable error generator
rsvd_12 (0x12)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
1b
RSVD
0b
RSVD[4:0]
00000b
Reset
Access Type Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
1: Reserved
RSVD
5
0: Reserved
RSVD
4:0
00000: Reserved
Maxim Integrated
│ 46
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
pd (0x13)
BIT
7
SOFT_PD
0b
6
5
4
3
2
1
0
Field
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[1:0]
10b
Reset
Write 1 to
Set, Read
Access Type
Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Soft Power Down: Set this bit to 1 to reset the
device; this bit is cleared after the device resets
0: Normal operation
1: Reset the device (bit clears itself)
SOFT_PD
7
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
6
5
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
4
0: Reserved
3
0: Reserved
2
0: Reserved
1:0
10: Reserved
pktcc_lock (0x14)
BIT
7
6
5
RSVD
Xb
4
RSVD
Xb
3
2
RSVD
Xb
1
0
CC_
WBLOCK
REM_
CCLOCK
Field
RSVD[1:0]
XXb
RSVD
Xb
Reset
Xb
Xb
Read Clears
All
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:6
5
Reserved
Reserved
Reserved
Reserved
Reserved
XX: Reserved
RSVD
X: Reserved
X: Reserved
X: Reserved
X: Reserved
RSVD
4
RSVD
3
RSVD
2
CC_
WBLOCK
0: Control-channel word boundary is not locked
1: Control-channel word boundary is locked
1
0
Control-Channel Word Boundary Locked
Remote-Side Control Channel Locked
REM_
CCLOCK
0: Remote side control channel is not locked
1: Remote side control channel is locked
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│ 47
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
input_status (0x15)
BIT
Field
7
RSVD
Xb
6
RSVD
Xb
5
RSVD
Xb
4
RSVD
0b
3
RSVD
0b
2
RSVD
0b
1
0
OUTPUTEN PCLKDET
Reset
Xb
Xb
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
2
Reserved
Reserved
X: Reserved
RSVD
X: Reserved
X: Reserved
0: Reserved
0: Reserved
0: Reserved
RSVD
Reserved
Reserved
Reserved
Reserved
RSVD
RSVD
RSVD
OUT-
PUTEN
0: Output disabled
1: Output enabled
1
0
Output Enabled
0: No valid PCLK detected
1: Valid PCLK detected
PCLKDET
PCLK Detected: Valid PCLK detected
max_rt_err (0x16)
BIT
7
6
5
4
3
2
1
0
MAX_RT_
ERR
Field
RSVD
0b
RSVD[5:0]
XXXXXXb
Read Only
Reset
Xb
Read Clears
All
Access Type
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
Reserved
0: Reserved
Maximum Retransmission Error: maximum
retransmission error bit
Goes high if packet control channel hits maximum
retransmission limit. Cleared when read
0: Device has not reached maximum retransmis-
sion limit.
1: Device has reached maximum retransmission
limit.
MAX_RT_ERR
RSVD
6
5:0
Reserved
XXXXXX: Reserved
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│ 48
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
rsvd_17 (0x17)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved
XXXXXXXX: Reserved
crc (0x18 to 0x1B)
BIT
Field
7
6
5
4
3
2
1
0
CRC_VALUE[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
CRC Value: CRC output for latest line
CRC_VALUE_3 to CRC_VALUE_0 represents
CRC[31:0]
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
CRC_VALUE
7:0
cc_crc_errcnt (0x1C)
BIT
Field
7
6
5
4
3
2
1
0
CC_CRC_ERRCNT[7:0]
XXXXXXXXb
Reset
Access Type
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
CC_CRC_
ERRCNT
Control-Channel CRC Error Count: Packet-
based control-channel CRC error counter
7:0
rsvd_1d (0x1D)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved
XXXXXXXX: Reserved
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│ 49
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
id (0x1E)
BIT
7
6
5
4
3
2
1
0
Field
ID[7:0]
Reset
XXXXXXXXb
Read Only
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
Device ID: 8-bit value depends on the GMSL
ID
01000101 Device is a MAX96701
device attached
revision (0x1F)
BIT
Field
7
6
RSVD
0b
5
RSVD
0b
4
3
2
1
0
RSVD
0b
HDCPCAP
Xb
REVISION[3:0]
Reset
XXXXb
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
RSVD
RSVD
7
Reserved
0: Reserved
0: Reserved
0: Reserved
6
5
Reserved
Reserved
0: Device does not have HDCP
1: Device is HDCP capable
HDCPCAP
4
HDCP Capability: 1 = HDCP capable
0000: Value is 0
0001: Value is 1
1111: Value is 15
REVISION 3:0
Device Revision
crossbar (0x20 to 0x3E)
BIT
Field
Reset
7
6
5
4
3
2
1
0
FORCE_
MUX
INVERT_
MUX
RSVD
0b
CROSSBAR[4:0]
0b
0b
XXXXXb
Access Type Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
Reserved: Do not change from default value
Force Mux Output
0: Reserved
FORCE_
MUX
0: Input mapped to mux output
1: Force mux output low
6
5
INVERT_
MUX
0: Do not invert mux output
1: Invert mux output
Invert Mux Output
Crossbar Setting
00000: Mux outputs data from input 0
00001: Mux outputs data from input 1
11111: Mux outputs data from input 31
CROSS-
BAR
Select 1 of 32 input signals. Default values connect
Mux N with input N for flow-through routing (i.e.,
DIN_ mapped to DOUT_)
4:0
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│ 50
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
crossbar_hs (0x3F)
BIT
Field
Reset
7
6
5
4
3
2
1
0
FORCE_
MUX_HS
INVERT_
MUX_HS
RSVD
CROSSBARHS[4:0]
0b
0b
0b
01100b
Access Type Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
Reserved: Do not change from default value
0: Reserved
FORCE_
MUX_HS
0: Input mapped to mux output
1: Force mux output low
6
5
Force Mux Output
INVERT_
MUX_HS
0: Do not invert mux output
1: Invert mux output
Invert Mux Output
Crossbar Setting HS: Select 1 of 16 input pins
for HS. Default values connect HS with the
corresponding named input pin. Use unconnected
inputs (DIN14, DIN15) when generating sync signals
with the timing generator.
00000: Mux sync signal from DIN0
00001: Mux sync signal from DIN1
01111: Mux sync signal from DIN15
1XXXX: Do Not Use
CROSS-
BARHS
4:0
crossbar (0x40)
BIT
7
6
5
4
3
2
1
0
FORCE_
MUX_VS
INVERT_
MUX_VS
Field
RSVD
CROSSBARVS[4:0]
Reset
0b
0b
0b
01101b
Access Type Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
Reserved: Do not change from default value
0: Reserved
FORCE_
MUX_VS
0: Input mapped to mux output
1: Force mux output low
6
5
Force Mux Output
INVERT_
MUX_VS
0: Do not invert mux output
1: Invert mux output
Invert Mux Output
Crossbar Setting VS: Select 1 of 16 input pins
for VS. Default values connect VS with the corre-
sponding named input pin. Use unconnected inputs
(DIN14, DIN15) when generating sync signals with
the timing generator.
00000: Mux sync signal from DIN0
00001: Mux sync signal from DIN1
01111: Mux sync signal from DIN15
1XXXX: Do Not Use
CROSS-
BARVS
4:0
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│ 51
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
crossbar_de (0x41)
BIT
Field
Reset
7
6
5
4
3
2
1
0
FORCE_
MUX_DE
INVERT_
MUX_DE
RSVD
CROSSBARDE[4:0]
0b
0b
0b
01011b
Access Type Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
Reserved: Do not change from default value
0: Reserved
FORCE_
MUX_DE
0: Input mapped to mux output.
1: Force mux output low.
6
5
Force Mux Output
INVERT_
MUX_DE
0: Do not invert mux output.
1: Invert mux output.
Invert Mux Output
Crossbar Setting DE: Select 1 of 16 input pins for 00000: Mux sync signal from DIN0
CROSS-
BARDE
DE. Default values connect DE with DIN11. Uncon- 00001: Mux sync signal from DIN1
4:0
nected inputs (DIN14, DIN15) when generating
sync signals with the timing generator.
01111: Mux sync signal from DIN15
1XXXX: Do Not Use
link_config (0x42)
BIT
7
6
5
4
3
2
1
GPI_RT_EN
1b
0
GPO_EN
1b
LINE_CRC_ MAX_RT_
GPI_
COMP_EN
Field
LINE_CRC_LOC[1:0]
RSVD
EN
EN
Reset
01b
0b
1b
1b
0b
Access Type
Write, Read
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
00: CRC insertion at [1...4]
LINE_CRC_
LOC
Line CRC Location: Video line CRC insertion
location
01: CRC insertion at [5...8]
10: CRC insertion at [9...12]
11: CRC insertion at [13...16]
7:6
5
LINE_CRC_
EN
0: Disable CRC
1: Enable CRC
Line CRC Enable: Video line CRC enable
0: Disable maximum retransmission limit
1: Enable maximum retransmission limit
MAX_RT_EN
4
3
2
Maximum Retransmission Limit Enable
Reserved: Do not change from default value
GPI Compensation Enable
RSVD
1: Reserved
GPI_COMP_
EN
0: Disable GPI compensation
1: Enable GPI compensation
0: Disable GPI retransmission
1: Enable GPI retransmission
GPI_RT_EN
GPO_EN
1
0
GPI Retransmission Enable
0: Disable GPO pin
1: Enable GPO pin
GPO Enable: Enable GPO pin
Maxim Integrated
│ 52
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
sync_gen_config (0x43)
BIT
Field
Reset
7
6
5
GEN_VS
0b
4
GEN_HS
0b
3
GEN_DE
0b
2
VS_TRIG
1b
1
0
RSVD
0b
RSVD
0b
VTG_MODE[1:0]
01b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
RSVD
0: Disable VS output generation (VS used from
VSYNC Generation: Enable to generate VS output input)
GEN_VS
GEN_HS
5
4
according to the timing definition
1: Enable VS output generation (VS internally
generated)
0: Disable HS output generation (HS used from
HSYNC Generation: Enable to generate HS
input)
utput according to the timing definition
1: Enable HS output generation (HS internally
generated)
0: Disable DE output generation (DE used from
DE Generation: Enable to generate DE output
according to the timing definition
input)
GEN_DE
VS_TRIG
3
2
1: Enable DE output generation (DE internally
generated)
0: VS trigger uses falling edge
1: VS trigger uses rising edge
VSYNC Trigger Edge Select
00: VS input is tracked and then locked after three
consecutive matches (three consecutive mismatch-
es unlock tracking)
01: VS edge triggers one VS frame (current frame
is extended/cut short to adjust timing to next
trigger)
VTG_
MODE
1:0
Video Timing Generator Mode
10: VS edge triggers VS generation (current frame
is extended/cut short to adjust timing to next
trigger)
11: Same as above
vs_dly (0x44 to 0x46)
BIT
Field
7
6
5
4
3
2
1
0
VS_DLY[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
VSYNC Delay: VS delay in terms of PCLK cycles;
the output VS delay by VS_DELAY cycles from the 00000001: Value is 1
input VS 11111111: Value is 255
00000000: Value is 0
VS_DLY
7:0
Maxim Integrated
│ 53
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
vs_h (0x47 to 0x49)
BIT
Field
7
6
5
4
3
2
1
0
VS_H[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
VSYNC High: VS high period in terms of PCLK
cycles
VS_H
7:0
vs_l (0x4A to 0x4C)
BIT
Field
7
6
5
4
3
2
1
0
VS_L[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
VSYNC Low: VS low period in terms of PCLK
cycles
VS_L
7:0
cxtp (0x4D)
BIT
7
6
5
4
3
2
1
DE_INV
0b
0
Field
HIGHIMM
Xb
CXTP
1b
RSVD
0b
RSVD
0b
VSYNC_INV HSYNC_INV
0b 0b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
High Immunity Mode: Default value depends on
the state of the HIM input
0: Use legacy reverse channel mode
1: Use high immunity mode
HIGHIMM
7
0: Use differential output (STP mode)
1: Use dual single ended outputs (coax)
CXTP
6
Coax/Twisted Pair Select: Default to STP mode
RSVD
RSVD
5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
VSYNC_
INV
VSYNC Inversion: Invert output VSYNC in
TIMING GEN
0: Do not invert VS in timing generator
1: Invert VS in timing generator
3
2
HSYNC_
INV
HSYNC Inversion: Invert output HSYNC in
TIMING GEN
0: Do not invert HS in timing generator
1: Invert HS in timing generator
0: Do not invert DE in timing generator
1: Invert DE in timing generator
DE_INV
RSVD
1
0
DE Inversion: Invert output DE in TIMING GEN
Reserved: Do not change from default value
0: Reserved
Maxim Integrated
│ 54
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
hs_dly (0x4E to 0x50)
BIT
Field
7
6
5
4
3
2
1
0
HS_DLY[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
VSYNC to HSYNC Delay: VS edge to the rising
edge of the first HS in terms of PCLK cycles
(bits [15:8])
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
HS_DLY
7:0
rsvd (0x51 to 0x53, 0x5D to 0x5F)
BIT
Field
7
6
5
4
3
2
1
0
RSVD[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:0
Reserved: Do not change from default value
00000000: Reserved
hs_h (0x54, 0x55)
BIT
Field
7
6
5
4
3
2
1
0
HS_H[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
HSYNC High Period: HS high period in terms of
PCLK cycles
HS_H
7:0
hs_l (0x56, 0x57)
BIT
Field
7
6
5
4
3
2
1
0
HS_L[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
HSYNC Low Period: HS low period in terms of
PCLK cycles
00000000: Value is 0
00000001: Value is 1
HS_L
7:0
11111111: Value is 255
Maxim Integrated
│ 55
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
hs_cnt (0x58, 0x59)
BIT
Field
7
6
5
4
3
2
1
0
0
0
0
HS_CNT[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
HS_CNT
7:0
HSYNC Count: Lines per panel (bits [7:0]).
de_dly (0x5A to 0x5C)
BIT
Field
7
7
7
6
5
4
3
2
1
DE_DLY[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
VSYNC to DE: VS falling edge to the rising edge of
the first DE in terms of PCLK cycles
DE_DLY
7:0
de_h (0x60, 0x61)
BIT
Field
6
5
4
3
2
1
DE_H[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
DE High Period: DE high period in terms of PCLK
DE_H
cycles
de_l (0x62, 0x63)
BIT
Field
6
5
4
3
2
1
DE_L[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
11111111: Value is 255
DE Low Period: DE low period in terms of PCLK
DE_L
cycles
Maxim Integrated
│ 56
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
de_cnt (0x64, 0x65)
BIT
Field
7
6
5
4
3
2
1
0
DE_CNT[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
DE_CNT
7:0
DE Count: Active lines per panel
11111111: Value is 255
prbs_type (0x66)
BIT
7
6
5
4
3
DE_EN
0b
2
1
0
PRBS_
TYPE
DIS_
RWAKE
Field
RSVD[1:0]
REV_FAST
0b
RSVD
0b
CXSEL
1b
Reset
01b
1b
0b
Access Type
Write, Read
Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:6
Reserved: Do not change from default value
01: Reserved
PRBS_
TYPE
0: Select legacy PRBS mode
1: Select MAX9271–MAX9273 PRBS mode
5
PRBS Type: PRBS type select
REV_
FAST
0: Disable reverse channel fast mode
1: Enable reverse channel fast mode
4
3
Reverse Channel Fast-Mode Enable
0: Disable separate processing of HS and DE
signals
1: Enable separate processing of HS and DE
signals
DE Enable: Enable processing separate HS and
DE signals
DE_EN
DIS_
RWAKE
Disable Remote Wake-Up: Disable wake-up
receiver
0: Do not disable remote wake-up receiver
1: Disable remote wake-up receiver
2
1
0
RSVD
Reserved: Do not change from default value
0: Reserved
0: Coax cable connected to inverting output
1: Coax cable connected to noninverting output
CXSEL
Coax Select
Maxim Integrated
│ 57
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
dbl_align_to (0x67)
BIT
7
6
5
4
3
2
1
0
AUTO_
CLINK
Field
RSVD[1:0]
RSVD
RSVD
DBL_ALIGN_TO[2:0]
Reset
11b
0b
0b
0b
111b
Access Type
Write, Read
Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:6
Reserved: Do not change from default value
11: Reserved
0: Enable configuration link only when
AUTO_
CLINK
Auto Configuration Link: Automatic control of
configuration link
CLINKEN = 1 and SEREN = 0
1: Automatically enable configuration link when
5
SEREN = 1 and PCLKDET = 0
RSVD
RSVD
4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
000: Align at each rising edge of HS. Turn off
alignment after HS is low (MAX9286). Use this
setting when an external high/low signal is used.
001: Do not use
010: Force align
011: Do not use
100: Align at each rising edge of HS
101: Align at each rising edge of DE
110: Force align
Double Alignment Mode: Sets the alignment
mode when DBL = 1 in the serializer and DBL =
0 in the deserializer. Set DBL_ALIGN_TO = 000
when an external high-low signal is used
(EN_HI_LO =1).
DBL_
ALIGN_TO
2:0
111: No alignment done while in DBL mode
cc_crc_length (0x68)
BIT
Field
Reset
7
6
5
4
3
2
1
0
RSVD
0b
RSVD[2:0]
001b
RSVD[1:0]
10b
CC_CRC_LENGTH[1:0]
01b
Access Type Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
6:4
3:2
001: Reserved
10: Reserved
RSVD
00: 1-bit CC CRC length
01: 5-bit CC CRC length
10: 8-bit CC CRC length
11: Do not use
CC_CRC_
LENGTH
1:0
Control-Channel CRC Length
Maxim Integrated
│ 58
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
hi_lo (0x69)
BIT
7
6
EN_HI_LO
0b
5
4
3
2
1
0
INVERT_
HI_LO
Field
RSVD
CROSSBAR_HI_LO[4:0]
Reset
0b
0b
01101
Access Type Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
Reserved: Do not change from default value
0: Reserved
0: Do not align using a Hi-Lo signal
1: Use a Hi-Lo signal to align input data
EN_HI_LO
6
5
Enable High/Low Signal Alignment
INVERT_
HI_LO
0: Do not invert Hi-Lo signal
1: Invert Hi-Lo signal
Invert High/Low Signal Alignment
00000: Mux Hi-Lo signal from DIN0
00001: Mux Hi-Lo signal from DIN1
01111: Mux Hi-Lo signal from DIN15
1XXXX: Do Not Use
CROSS-
BAR_HI_
LO
Crossbar High Low: Select 1 of 16 input pins for
the Hi-Lo signal. (effective when
DBL_ALIGN_TO = 000)
4:0
rsvd_96 (0x96)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
1b
RSVD[1:0]
10b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
1b: Reserved
10: Reserved
5
4
3
2
1:0
Maxim Integrated
│ 59
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
rsvd_97 (0x97)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
1b
RSVD
1b
RSVD[2:0]
111b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
1: Reserved
1: Reserved
111: Reserved
RSVD
RSVD
5
RSVD
4
RSVD
3
RSVD
2:0
rsvd_98 (0x98)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[1:0]
01b
RSVD[2:0]
001b
RSVD[2:0]
010b
Reset
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:6
5:3
2:0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
01: Reserved
001: Reserved
010: Reserved
RSVD
RSVD
rsvd_99 (0x99)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
1b
RSVD
1b
RSVD[1:0]
01b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
1: Reserved
1: Reserved
01: Reserved
5
4
3
2
1:0
Maxim Integrated
│ 60
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
pktcc_en (0x9A)
BIT
7
6
5
4
3
2
1
0
RSVD
0b
Field
RSVD[1:0]
00b
RSVD[1:0]
01b
PKTCC_EN
0b
RSVD[1:0]
00b
Reset
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:6
5:4
Reserved: Do not change from default value
Reserved: Do not change from default value
00: Reserved
01: Reserved
RSVD
PKTCC_
EN
0: Disable packet-based control-channel mode
1: Enable packet-based control-channel mode
3
Packet-Based Control-Channel-Mode Enable
RSVD
RSVD
2:1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
00: Reserved
0: Reserved
rsvd_C8 (0xC8)
BIT
Field
7
6
RSVD
Xb
5
RSVD
Xb
4
RSVD
Xb
3
2
1
0
RSVD
0b
RSVD[3:2]
10b
RSVD[1:0]
10b
Reset
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved
Reserved
0: Reserved
X: Reserved
X: Reserved
X: Reserved
10: Reserved
10: Reserved
RSVD
RSVD
5
Reserved
Reserved
Reserved
Reserved
RSVD
4
RSVD
3:2
1:0
RSVD
rsvd_c9 (0xC9)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
Reset
XXXXXXXXb
Read Only
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved
XXXXXXXX: Reserved
Maxim Integrated
│ 61
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
rsvd_fc (0xFC)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
rsvd_fd (0xFD)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved: Do not change from default value
00000000: Reserved
Maxim Integrated
│ 62
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
rsvd_fe (0xFE)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
0000b
RSVD[3:0]
0000b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:4
3:0
Reserved: Do not change from default value
Reserved: Do not change from default value
0000: Reserved
0000: Reserved
RSVD
rsvd_ff (0xFF)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[3:0]
Reset
XXXXb
Access Type Write, Read Write, Read Write, Read Write, Read
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved
DECODE
7
6
0: Reserved
0: Reserved
0: Reserved
0: Reserved
XXXX: Reserved
RSVD
RSVD
5
RSVD
4
RSVD
3:0
Maxim Integrated
│ 63
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
when in double mode (DBL = 1). Table 3 shows the avail-
able bit widths and default mapping for various modes.
Applications Information
Parallel Interface
Bus Data Rates
The CMOS parallel interface-data width is programmable
and depends on the application. Using a larger width
(BWS = 1) results in a lower-pixel clock rate, while a
smaller width (BWS = 0) allows a higher-pixel clock rate.
The bus data rate depends on the settings for BWS and
DBL. Table 4 lists the available PCLK rates available for
different bus-width settings. For lower PCLK rates, set
DBL = 0 (if DBL = 1 in both the serializer and deserializer).
Bus Data Width
The bus data width depends on the selected modes. The
available bus width is less when using error detection or
Table 3. Input Data-Width Selection
REGISTER BIT SETTINGS
INPUT MAPPING
HVEN
DBL
1
BWS
1
HIBW
—
—
—
—
1
PXL_CRC
1
1
0
0
1
0
1
1
0
0
1
1
0
0
-
1
0
DIN11:0, HS, VS
DIN11:0
1
1
*
1
1
1
DIN11:0 , HS, VS
1
1
0
DIN13:0*
DIN8:0, HS, VS
DIN11:0, HS, VS
DIN7:0, HS, VS
DIN7:0
1
0
—
—
1
1
0
1
1
0
0
1
0
0
0
1
0
0
1
DIN10:0, HS, VS
DIN10:0
1
0
0
0
0
1
—
—
—
—
1
1
DIN11:0*, HS, VS
DIN13:0*
0
1
0
0
1
1
DIN11:0*, HS, VS
DIN13:0*
0
1
0
0
0
—
1
DIN11:0*, HS, VS
DIN11:0*, HS, VS
DIN13:0*
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
DIN11:0*, HS, VS
DIN13:0*
0
0
0
0
*The input bit width is limited by the number of available inputs.
Table 4. Data-Rate Selection
DBL
BWS
HIBW
PCLK RANGE (MHz)
25 to 87
1
1
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
33.3 to 116
73.3 to 116
12.5 to 43.5
16.7 to 58
36.6 to 58
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2. Set the low- and high-input crossbar bits (CROSSBAR0,
CROSSBAR 16) to the desired selected mapped input
(e.g., CROSSBAR0 = 00100, CROSSBAR16 = 10100).
Crossbar Switch
By default, the crossbar switch connects the serializer
input pins DIN_ and HS/VS (when HV encoding is used)
to the corresponding deserializer output pins DOUT_ and
HS/VS. Reprogram the crossbar switch when changing
the input or output pin assignments, or when connecting
to devices that do not have a DBL = 1 mode.
3. Repeat for the other crossbar outputs, making sure
the set of high and low crossbar outputs are assigned
to the same crossbar input set. In general, XBO[i] and
XBO[i+16] should be assigned to XBI[j] and XBI[j+16].
4. For XBOHS, XBOVS, and XBODE, set crossbar to use
the low-input pins (CROSSBAR_ = 00000 to 01111). Note
that HS, VS, and DE use both the low and high input.
Crossbar-Switch Programming
Each crossbar-switch output can select any of the 14
DIN_ inputs for either high or low words (when DBL =
1) for a total of 32 possible inputs. Multiple outputs can
share the same input. HS, VS, and DE remain the same
for both word halves, and should be programmed to use
the low-word input of the corresponding pin. To invert
an input data bit, set the respective INVERT_MUX_ =
1. To force an output low, (and ignore the input) set the
FORCE_MUX_ bit = 1. To force an output high set both
INVERT_MUX_ and FORCE_MUX_ = 1.
● Both Devices' DBL Do Not Match
1. Table 5, Table 6, and Table 7 list which crossbar output
(XBO_) maps to each serial bit.
2. For each crossbar output, select which pin and high/
low clock cycle (if needed) to map (e.g., DIN4 low input).
3. Set the crossbar bits (CROSSBAR_) to select the
desired selected mapped input (e.g., CROSSBAR0 =
00100 maps DIN4 low input to XBO0).
Recommended Crossbar-Switch Program Procedure
4. Repeat for the other crossbar outputs; any unused
serial bits should have a force low mapped to the
respective crossbar output.
The procedure to program the crossbar switch depends on
the DBL settings on the serializer and deserializer. Devices
without double mode can be assumed to have DBL = 0.
5. For XBOHS, XBOVS, and XBODE, set crossbar to use
the low-input pins (CROSSBAR_ = 00000 to 01111). Note
that HS, VS, and DE use both the low and high input.
● Both Devices' DBL Set to the Same Value
1. For the crossbar-output equivalent of DIN0 (XBO0,
XBO16) select which pin to map (e.g., DIN4 → XBI4,
XBI20).
Table 5. Crossbar Output to Serial Link Map (D23:0)
BIT SETTING
SERIAL BITS
10 11 12 13 14 15 16 17 18 19 20 21 22 23
DB HV BW HB CR DE
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
9
9
9
9
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
10 11 12 13 14 15
Z
F
Z
Z
Z
Z
Z
F
Z
Z
5
F
4
Z
E
Z
Z
Z
Z
Z
E
Z
Z
6
Z
E
Z
Z
Z
Z
Z
E
Z
Z
7
Z
E
Z
F
Z
Z
Z
E
Z
Z
8
Z
E
Z
E
Z
Z
Z
E
Z
Z
9
Z
E
Z
F
E
F
E
Z
Z
F
E
Z
Z
F
E
F
P
P
P
P
Z
Z
P
P
Z
Z
P
P
P
E
Z
Z
Z
E
Z
Z
16 17 18 19 20 21 22 23 24 25 26
16 17 18 19 20 21 22 23
0
3
1
4
0
2
5
1
3
6
2
4
7
3
10
E
Z
0
1
2
E
5
E
6
E
7
E
8
16 17 18 19 20 21 22 23 24 25 26 27
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Table 5. Crossbar Output to Serial Link Map (D23:0) (continued)
BIT SETTING
SERIAL BITS
DB HV BW HB CR DE
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
1
1
X
X
1
0
1
0
1
0
X
1
0
16 17 18 19 20 21 22 23 24
0
1
2
3
4
5
6
0
7
1
4
4
5
5
F
F
1
4
4
8
2
5
5
6
6
E
E
2
5
5
Z
3
6
6
7
7
E
E
3
6
6
F
4
7
7
8
8
E
E
4
7
7
E
5
8
8
9
9
E
E
5
8
8
E
6
E
7
P
8
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
16 17 18 19 20 21 22 23 24 25 26 DH
16 17 18 19 20 21 22 23 24 25 26 27
0
0
1
1
4
4
1
1
2
2
5
5
2
2
3
3
6
6
3
9
10 DL
10 11
3
9
16 17 18 19 20 21 22 23 24 25 DH
16 17 18 19 20 21 22 23 24 25 26
0
0
3
3
4
DL
10
E
E
6
F
F
E
E
7
P
P
P
P
8
4
16 17 18 19 20 21 22 DH
16 17 18 19 20 21 22 23
0
0
1
1
2
2
DL
7
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
0
16 17 18 19 20 21 22 23 24 25 26 DH
16 17 18 19 20 21 22 23 24 25 26 27
0
0
1
1
2
2
3
9
10 DL
10 11
3
9
Table 6. Crossbar Output to Serial Link Map (D31:24 and Special Packets)
BIT SETTING
SPECIAL PACKETS
DB HV BW HB CR DE
24
—
—
Z
25
—
—
Z
26
—
—
Z
27
—
—
—
—
Z
28
—
—
—
—
Z
29
—
—
—
—
Z
30
—
—
—
—
F
31
—
—
—
—
P
C0
—
—
Z
C1
—
—
Z
C2
—
—
Z
C3
—
—
Z
HS
—
—
H
VS
—
—
V
DE
—
—
D
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
E
E
E
Z
Z
Z
Z
H
V
D
Z
Z
Z
—
—
—
—
—
—
—
—
A
—
—
—
—
—
—
—
—
Z
—
—
—
—
—
—
—
—
A
—
—
—
—
—
—
—
—
A
—
—
H
—
—
V
—
—
—
—
—
—
—
—
D
F
E
E
E
E
E
E
P
—
—
Z
—
—
Z
—
—
Z
—
—
Z
—
—
Z
—
—
Z
—
—
F
—
—
P
H
V
H
V
F
E
E
E
E
E
E
P
H
V
—
—
9
—
—
10
E
—
—
11
E
—
—
—
—
12
E
—
—
—
—
13
E
—
—
—
—
14
E
—
—
—
—
F
—
—
—
—
P
—
—
H
—
—
V
E
A
Z
A
A
H
V
D
9
10
E
11
E
—
—
—
—
—
—
—
—
—
-
—
—
—
—
—
—
—
—
—
-
—
—
—
—
—
—
—
—
—
-
—
—
—
—
—
—
—
—
—
-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-
F
E
P
0
F
E
E
E
E
E
E
P
1
—
—
—
—
9
—
—
—
—
10
E
—
—
—
—
11
E
—
—
—
—
12
E
—
—
—
—
13
E
—
—
—
—
14
E
—
—
—
—
F
—
—
—
—
P
HH/L VH/L
HH/L VH/L
HH/L VH/L
HH/L VH/L
HH/L VH/L
HH/L VH/L
HH/L VH/L
0
1
0
X
1
F
E
P
0
F
E
E
E
E
E
E
P
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Table 7. Legend
BIT SETTINGS
MAP INPUTS
DB
HV
BW
HB
CR
DE
X
Double-mode bit DBL
H
V
HSYNC ( when DBL = 0 or HIBW = 1)
VSYNC ( when DBL = 0 or HIBW = 1)
DE ( when DBL = 0 or HIBW = 1)
HSYNC (high word, DBL = 1)
VSYNC (high word, DBL = 1)
DE (high word, DBL = 1)
H/V Encoding bit HVEN
BWS bit
D
HIBW bit
HH
VH
DH
HL
VL
DL
#
PXL_CRC bit
DE = 1 when DEEN = 1 and not processed in RGB888 mode
1 or 0
HSYNC (low word, DBL = 1)
VSYNC (low word, DBL = 1)
DE (low word, DBL = 1)
SPECIAL PACKETS
C0
C1
C2
C3
CNT_0
CNT_1
CNT_2
CNT_3
XBO output from crossbar switch
Internal forward control-channel bit
Internal pixel CRC bit
F
E
BIT COLOR
Output bits from crossbar
P
Internal pixel parity bit
—
Z
Serial bit not sent
Internal bits
Zero
Other output bits
Output bits from sync
A
Internal alignment bit (used when HIBW=1)
INPUT PIN
PIXEL
N
N+1
PCLK
XBI31**
XBI30**
XBI29
XBI28
XBI27
XBI26
XBI25
XBI24
XBI23
XBI22
XBI21
XBI20
XBI19
XBI18
XBI17
XBI16
XBI15**
XBI14**
XBI13
XBI12
XBI11
XBI10
XBI9
XBI8
XBI7
XBI6
XBI5
XBI31**
XBI30**
XBI29
XBI28
XBI27
XBI26
XBI25
XBI24
XBI23
XBI22
XBI21
XBI20
XBI19
XBI18
XBI17
XBI16
XBI15**
XBI14**
XBI13
XBI12
XBI11
XBI10
XBI9
XBI8
XBI7
XBI6
XBI5
DIN13/VS
DIN12/HS
DIN11
DIN10
DIN9
DIN8
DIN7
DIN6
DIN5
DIN4
DIN3
DIN2
DIN1
XBI4
XBI3
XBI2
XBI1
XBI4
XBI3
XBI2
XBI1
DIN0
XBI0
XBI0
ALIGNMENT
HS*
HS
DE
HS
DE
DE*
HI_LO*
*REGISTER SETTINGS DECIDE IF HS, DE, OR HI_LO DETERMINES
THE HIGH/LOW INPUT TIMING.
**XBI14, XBI15, XBI30, XBI31 INPUT INTERNALLY CONNECTED LOW.
Figure 20. Crossbar-Switch Default Mapping
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Align from HS or DE
Timing-Generator Programming
To align from a sync signal, set the DBL_ALIGN_TO to
select the input signal. When using this mode, ensure
that the signal used for alignment uses the same value
for both the high and low word (e.g., for pixels [1H, 1L,
2H, 2L...], aligning on DE requires values of [DE1, DE1,
DE2, DE2...]).
Timing-generator parameters are stored in the registers
as unsigned integers as PCLK periods. To prevent out-
put glitches, program all timing-generator parameters
while the device is in configuration-link mode, or when
PCLK is not applied. By default, the timing generator
is set to single trigger, and is disabled. Figure 18 show
the timing waveforms under the default conditions with
rising-edge trigger, and noninverted signals. Do not pro-
gram the HSYNC or DE signals such that the total length
exceeds the length of a VSYNC period (Table 8). All delay
parameters are positive. To implement a negative delay,
set the delay value subtracted from the VSYNC period
(e.g., a delay value of VS_HIGH + VS_LOW - N creates
a delay of -N PCLK cycles). Do not set any delay lengths
larger than the VSYNC period.
2
I C Interface
2
The control channel forwards I C commands from the
microcontroller side to the other side of the GMSL link.
2
The remote device acts as an I C master to the other
2
peripherals connected to the remote-side device. I C-to-
2
I C mode uses clock stretching to hold the microcontroller
until the data and an acknowledge or not acknowledge
have been sent across the link.
2
I C Bit Rate
Double-Mode Alignment
2
The I C interface accepts bit rates from 9.6kbps to
1Mbps. The local I C rate is set by the microcontroller.
The remote I C rate is set by the remote device. By
default, the control channel is set up for a 400kbps I C bit
rate. Program the I2C_MSTBT and SLV_SH bits (register
0x0D) to match the desired microcontroller I C rate.
When DBL = 1 in both the serializer and deserializer, GMSL
automatically keeps the pixels in order. Use double-mode
alignment when DBL = 1 in the serializer and DBL = 0
(or is not supported) in the deserializer. Two different
methods are available for double-mode alignment.
2
2
2
2
External High/Low Signal
To use an external alignment signal, set EN_HI_LO =
1, DBL_ALIGN_TO = 000, and select which input DIN_
pin to use by setting the CROSSBAR_HI_LO bits. The
external signal designates whether the clocked word is
the high or low word (e.g., for pixels [1H, 1L, 2H, 2L...] the
high/low signal would be [1, 0, 1, 0...]).
Table 8. Timing-Generator Parameter Restrictions
MIN VALUE
(HEX)
MAXIMUM VALUE RESTRICTION
(HEX)
SIGNAL
SIZE (BITS)
VS_HIGH
VS_LOW
VS_DLY
HS_HIGH
HS_LOW
HS_CNT
HS_DLY
DE_HIGH
DE_LOW
DE_CNT
DE_DLY
24
24
24
16
16
16
24
16
16
16
24
1
1
0
1
1
1
0
1
1
1
0
VS_HIGH + VS_LOW < 0xFFFFFF
VS_HIGH + VS_LOW < 0xFFFFFF
VS_DLY < VS_HIGH + VS_LOW
(HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW
(HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW
(HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW
HS_DLY < VS_HIGH + VS_LOW
(DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW
(DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW
(DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW
DE_DLY < VS_HIGH + VS_LOW
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14-Bit GMSL Serializer with High-Immunity/
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Software Programming of Device Addresses
Dual μC Control
The serializer and deserializer have programmable device
addresses. This allows multiple GMSL devices, along with
I C peripherals, to coexist on the same control channel.
Most systems use a single microcontroller; however μCs
can reside on each side simultaneously and trade off
in running the control channel. Contention occurs if both
μCs attempt to use the control channel at the same time.
It is up to the user to prevent this contention by imple-
menting a higher level protocol. In addition, the control
2
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
write to the device whose address changes (register 0x00
of the serializer for serializer device address change, or
register 0x01 of the deserializer for deserializer device
address change). Then, write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
2
channel does not provide arbitration between I C masters
on both sides of the link. An acknowledge frame is not
generated when communication fails due to contention. If
communication across the serial link is not required, the
μCs can disable the forward and reverse control channel
using the FWDCCEN and REVCCEN bits (0x04, D[1:0])
in the serializer/deserializer. Communication across the
serial link is stopped and contention between μCs cannot
occur.
2
I C Address Translation
Device Address
2
The device supports I C address translation for up to
The serializer/deserializer both have a 7-bit-long slave
address stored in registers 0x00 and 0x01. The bit follow-
ing a 7-bit slave address is the R/W bit, which is low for a
write command and high for a read command. The default
slave address is 0x80. After startup, a microcontroller can
reprogram the slave address as needed.
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
2
Spread Spectrum
Configuration Blocking
Program the SS bits in the serializer to turn on spread
spectrum in the serializer (Table 9). If the deserializer
driven by the serializer has programmable spread
spectrum, do not enable spread for both at the same
The device can block changes to its registers. Set
CFGBLOCK to make all registers read-only. Once set, the
registers remain blocked until the supplies are removed.
Cascaded/Parallel Devices
time or their interaction cancels benefits. The deserializer
tracks the serializer’s spread and passes the spread to
the deserializer output. Some spread-spectrum ampli-
tudes can only be used at lower PCLKIN frequencies
(Table 10). When the spread spectrum is turned on or off,
the serial link stops for several microseconds and then
restarts in order for the deserializer to lose and relock
to the new serial-data stream. Changing the spread-
spectrum amplitude does not cause a loss of lock.
GMSL supports both cascaded and parallel devices
2
connected through I C. When cascading or using parallel
2
links, all I C commands are forwarded to all links. Each
link attempts to hold the control channel until it receives
an acknowledge/not acknowledge from the remote-side
device. It is important to keep the control channel active
between links to prevent timeout. If a link is unused, keep
the control channel clear by turning on the configuration
2
link, disconnecting the I C lines, or powering down the
unused device.
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Manual Programming of the Spread-Spectrum
Divider
Board Layout
Power-Supply Circuits and Bypassing
By default, autodetection of the PCLKIN operation range
guarantees a spread-spectrum modulation frequency
within 20kHz to 40kHz. Additionally, manual configura-
tion of the sawtooth divider (SDIV: 0x03,D[5:0]) allows
the user to set a modulation frequency (typically 20kHz)
according to the PCLKIN frequency.
The serializer uses an AVDD and DVDD of 1.7V to 1.9V.
All inputs and outputs, except for the serial output, derive
power from DVDD. Proper voltage-supply bypassing is
essential for high-frequency circuit stability.
High-Frequency Signals
Separate the LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout STP-PCB traces close to
each other for a 100Ω differential characteristic imped-
ance. The trace dimensions depend on the type of trace
used (microstrip or stripline).
Equation:
Relation of modulation rate to the PCLKIN frequency:
f
= f
/(MOD x SDIV)
M
PCLKIN
where:
f
f
= Modulation frequency
M
= PCLKIN frequency
PCLKIN
Note: Two 50Ω PCB traces do not have 100Ω differential
impedance when brought close together; the impedance
goes down when the traces are brought closer. Use a 50Ω
trace for the single-ended output when driving coax. Route
the PCB traces for differential CML in parallel to maintain
the differential characteristic impedance. Avoid via arrays.
Keep PCB traces that make up a differential pair equal in
length to avoid skew within the differential pair.
MOD = Modulation coefficient given in Table 11
SDIV = 6-bit SDIV setting, manually programmed by the μC
To program the SDIV setting, first look up the modulation
coefficient according to the desired bus-width and spread-
spectrum settings. Solve the above equation for SDIV using
the desired pixel clock and modulation frequencies. If the
calculated SDIV value is larger than the maximum allowed
SDIV value in Table 11, set SDIV to the maximum value.
Table 9. Output Spread
SS
000
001
010
011
100
101
110
111
SPREAD (%)
Power-up default (no spread spectrum)
±0.5% spread spectrum
±1.5% spread spectrum
±2% spread spectrum
No spread spectrum
±1% spread spectrum
±3% spread spectrum
±4% spread spectrum
Table 10. Spread Limitations
BWS = 0 MODE, PCLKIN
BWS = 1 MODE, PCLKIN
SERIAL LINK BIT RATE
(MBPS)
AVAILABLE SPREAD
RATES
FREQUENCY (MHz)
FREQUENCY (MHz)
< 33.3 (DBL = 0)
< 66.6 (DBL = 1)
< 25 (DBL = 0)
< 50 (DBL = 1)
< 1000
All rates available
33.3 to 58 (DBL = 0)
66.6 to 116 (DBL = 1)
25 to 43.5 (DBL = 0)
50 to 87 (DBL = 1)
≥ 1000
1.5%, 1%, 0.5%
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Table 11. Modulation Coefficients and
Maximum SDIV Settings
R
1.5kΩ
D
1MΩ
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(DEC)
SDIV UPPER
LIMIT (DEC)
CHARGE-CURRENT- DISCHARGE
BWS
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
S
STORAGE
CAPACITOR
1
0.5
3
104
104
152
152
204
204
80
40
63
27
54
15
30
52
63
37
63
21
42
SOURCE
1
1.5
4
Figure 21. Human Body Model ESD Test Circuit
2
1
0.5
3
80
R
D
330Ω
112
112
152
152
0
1.5
4
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
2
C
150pF
S
STORAGE
CAPACITOR
SOURCE
ESD Protection
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human Body
Model discharge components are CS = 100pF and RD =
1.5kΩ (Figure 21). The IEC 61000-4-2 discharge compo-
nents are CS = 150pF and RD = 330Ω (Figure 22). The
ISO 10605 discharge components are CS = 330pF and
RD = 2kΩ (Figure 23).
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit
R
D
2kΩ
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Compatibility with Other GMSL Devices
The device is designed to pair with the MAX96705–
MAX96711 family of devices, but interoperates with any
GMSL device. See Table 12 for operating limitations.
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit
Device Configuration and Component Selection
Internal Input Pulldowns
The control and configuration inputs include a pulldown
resistor to GND; external pulldown resistors are not
needed.
set a high level. Leave the configuration input open to set
a low level.
2
I C Pullup Resistors
2
The I C open-drain lines require a pullup resistor to
Multifunction GPO/HIM
provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise may
be required when choosing pullup resistor values. Every
device connected to the bus introduces some capaci-
Functions as the GPO output, and as a configuration
pin. On power-up, or when reverting from a power-down
state, the pins act as the HIM input. After latching the
input state, the pin becomes the GPO output. Connect a
configuration input through a 30kΩ resistor to DVDD to
2
tance even when the device is not in operation. I C speci-
fies 300ns rise times (30% to 70%) for fast mode, which
2
is defined for data rates up to 400kbps (see the I C Port
Maxim Integrated
│ 71
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Timing section in the AC Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
are required to match the transmission-line impedance
(usually 100Ω differential, 50Ω single-ended). This leaves
the capacitor selection to change the system time con-
stant. Use 0.22μF or larger high-frequency, surface-mount
ceramic capacitors with sufficient voltage rating to with-
stand a short to battery, to pass the lower speed reverse
control-channel signal. Use capacitors with a case size less
than 3.2mm x 1.6mm to have lower-parasitic effects to the
high-speed signal.
choose the pullup resistors so that rise time t = 0.85 x
R
R
x C
< 300ns. The waveforms are not rec-
PULLUP
BUS
ognized if the transition time becomes too slow. GMSL
2
supports I C rates up to 1Mbps.
AC-Coupling Capacitors
Voltage droop and the digital-sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition
time is fixed, starting the signal transition from different
voltage levels causes timing jitter. The time constant for
an AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for
an AC-coupled link consists of the CML/coax receiver
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω; contact the factory for 75Ω operation).
Table 13 lists the suggested cables and connectors used
in the GMSL link.
termination resistor (R ), the CML/coax-driver termi-
TR
nation resistor (R ), and the series AC-coupling
TD
capacitors (C). The RC time constant for four equal-value
series capacitors is (C x (R
+ R ))/4. R
and R
TD TR
TD
TR
Table 12. Feature Compatibility
SERIALIZER FEATURE
GMSL DESERIALIZER
HSYNC/VSYNC Encoding
If feature not supported in the deserializer, turn off in the serializer.
If feature not supported in the deserializer, do not use control channel.
If feature not supported in the deserializer, use legacy control channel.
If feature not supported in the deserializer, turn off in the serializer.
2
2
I C to I C
Packet Control Channel
CRC Error Detection
If feature not supported in the deserializer, data is output as a single word at half the
input frequency. Use crossbar switch and double alignment to correct input mapping.
Double Input
Coax
If feature not supported in the deserializer, connect unused serial input through 200nF
and 50Ω in series to AVDD, and set the reverse control-channel amplitude to 100mV.
2
2
I S Encoding
If supported in the deserializer, disable I S in the deserializer.
High-Bandwidth Mode
High-Immunity Mode
Low-Speed Mode
If feature not supported in the deserializer, turn off in the serializer.
If feature not supported in the deserializer, turn off in the serializer.
If supported in the deserializer, set DRS to 0 in the deserializer.
Table 13. Suggested Connectors and Cables for GMSL
VENDOR
CONNECTOR
59S2AX-400A5-Y
D4S10A-40ML5-Z
GT11L-2S
CABLE
TYPE
Coax
STP
Rosenberger
Dacar 302
Rosenberger
Nissei
Dacar 535-2
F-2WME AWG28
A-BW-Lxxxxx
STP
JAE
MX38-FF
STP
Maxim Integrated
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
mode (with 5-bit CRC). Skew between multiple GPI/
GPO channels is 115μs (max) in legacy mode and 21μs
PRBS
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To
run the PRBS test, set PRBSEN = 1 (0x04, D5) in the
deserializer, then in the serializer. To exit the PRBS
test, set PRBSEN = 0 (0x04, D5) in the serializer. The
deserializer automatically ends PRBS checking and sets
the PRBS_OK bit high. During PRBS mode, the forward
control channel is not available except to exit PRBS mode
if autoacknowledge is enabled in the deserializer; other-
wise, the remote control channel is not available at all.
(max) in packet mode. If a lower skew signal is required
in legacy mode, connect the camera’s frame-sync input
2
to one of the serializer’s GPIOs and use an I C broad-
cast-write command to change the GPIO output state.
This has a maximum skew of 1.5μs, independent from
2
the used I C bit rate. In packet-based control-channel
mode, set GPI_COMP_EN = 1 in both the serializer and
deserializer to turn on GPI/GPO compensation. This
reduces the device-to-device skew to 0.35μs.
To run the PRBS with a 3Gbps SerDes, or when HIBW
= 1, first set the PRBS_TYPE bit = 0 in the MAX967XX.
Then set PRBSEN = 1 (0x04, D5) in the serializer
and then in the deserializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the deserializer, then in the
serializer. PRBS_TYPE = 0 does not support DBL = 1.
Entering/Exiting Sleep Mode
The procedure for entering and exiting sleep mode
depends on the location of the microcontroller, and the
type of control-channel interface used. If wake up from a
remote (deserializer) side microcontroller is not needed or
desired, set the DIS_RWAKE bit = 1 to shut down remote
wake-up for further power savings.
During PRBS test, ERRB function changes to reflect
PRBS errors only. ERRB goes low when any PRBS errors
occur. ERRB goes high when the PRBS error counter is
reset when PRBS_ERR is read. Normal ERRB function
resumes when exiting the PRBS test.
Legacy Control Channel:
To enter sleep mode, set SLEEP = 1. The device sleeps
after 8ms. To wake up the device, send an arbitrary
control-channel command to the serializer (the serializer
does not send an acknowledge), wait for 5ms for the chip
to power up and then set SLEEP = 0 to make the wake-
up permanent.
GPI/GPO
GPO on the serializer follows GPI transitions on the
deserializer. By default, the GPI-to-GPO delay is 0.35ms
(max). Keep the time between GPI transitions to a
minimum 0.35ms. GPI_IN the deserializer stores the GPI
input state. GPO is low after power-up. The μC can set
GPO by writing to the SET_GPO register bit.
Packet-Based Control Channel:
● When μC is on the deserializer side, set SLEEP = 1 in
serializer. Next set REVCCEN = 0 in the deserializer to
stop reverse-control transmission to the serializer. The
device sleeps after 8ms.
Fast Detection of Loss-of-Lock
To wake up the serializer, first set REVCCEN = 1, wait
8ms for the device to wake up and then set SLEEP = 0
to exit sleep mode permanently.
A measure of link quality is the recovery time from loss-
of-synchronization. The host can be quickly notified of
loss-of-lock by connecting the deserializer’s LOCK output
to the GPI input (when PKTCC_EN = 0). If other sources
use the GPI input, such as a touch-screen controller, the
μC can implement a routine to distinguish between inter-
rupts from loss-of-sync and normal interrupts. Reverse
control-channel communication does not require an active
forward link to operate and accurately tracks the LOCK
status of the GMSL link. LOCK asserts for video link only
and not for the configuration link.
● When μC is on the serializer side, first set SLEEP =
1 in the deserializer. If the deserializer must remain
awake, switch to legacy control-channel mode. Next,
set SLEEP = 1 in the serializer. The device sleeps after
8ms.
To wake up the device, send an arbitrary control-
channel command to the serializer (the serializer does
not send an acknowledge). Wait for 5ms for the chip to
power up and then set SLEEP = 0 to make the wake-
up permanent. The deserializer wakes up and clears its
SLEEP bit when serialization is enabled and it locks to
the serializer.
Providing a Frame Sync (Camera Applications)
The GPI and GPO provide a simple solution for camera
applications that require a frame-sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame-sync signal to the GPI input and connect the GPO
output to the camera frame-sync input. GPI/GPO have a
typical delay of 275μs in legacy mode and 21μs in packet
Maxim Integrated
│ 73
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Typical Application Circuits
PCLKOUT
DOUT[11:0]
DOUT12/HS
PCLK
DIN[11:0]
PCLK
DIN[11:0]
PCLKIN
DIN[11:0]
HS
VS
DIN12/HS
DIN13/VS
HS
VS
DOUT13/VS
MAX96701
MAX96700
GPU
CAMERA
45.3kΩ
4.99kΩ
SDA
SCL
SDA
SCL
49.9Ω
LMN0
RX/SDA
TX/SCL
SDA
SCL
OUT-
I2C
OUT+
IN+
IN-
GPI
FSYNC
49.9kΩ
LOCK
LOCK
49.9Ω
ERRB
LFLTB
ERR
LFLT
ECU
I2CSEL = 1, CX/TP = 1
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
CAMERA APPLICATION
Ordering Information
PART NUMBER
MAX96701GTG/V+
MAX96701GTG/V+T
TEMP RANGE
-40°C to +115°C
-40°C to +115°C
PIN-PACKAGE
24 TQFN-EP*
24 TQFN-EP*
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Maxim Integrated
│ 74
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MAX96701
14-Bit GMSL Serializer with High-Immunity/
Bandwidth Mode and Coax/STP Cable Drive
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
6/17
Initial release
—
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 75
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