MAX96708GTJ+ [MAXIM]
Line Receiver,;型号: | MAX96708GTJ+ |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Line Receiver, 接口集成电路 |
文件: | 总68页 (文件大小:1145K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
General Description
Benefits and Features
The MAX96708 is a compact deserializer especially suited
for automotive camera applications. Features include
adaptive equalization and an output crosspoint switch. An
embedded control channel operates at 9.6kbps to 1Mbps
● Ideal for Safety Camera Applications
• Works with Low-Cost 50Ω Coax (100Ω STP) Cable
• Error Detection of Video/Control Data
• High-Immunity Mode for Robust Control-Channel
EMC Tolerance
2
2
in UART, I C, and mixed UART/I C modes, allowing
programming of serializer, deserializer (SerDes), and
camera registers, independent of video timing.
• Best-in-Class Supply Current: 185mA (max)
• Adaptive Equalization for 15m Cable at Full Speed
• 32-Pin (5mm x 5mm) TQFN Package
• Horizontal- and Vertical-Sync Encoding
and Tracking
The deserializer can track data from a spread-
spectrum serial input. The serial input meets ISO 10605
and IEC 61000-4-2 ESD standards. The core supply
range is 1.7V to 1.9V and the I/O supply range is 1.7V
to 3.6V. The device is available in a 32-pin (5mm x 5mm)
TQFN package with 0.5mm lead pitch and operates over
-40ºC to +115ºC temperature range.
● High-Speed Deserialization for Megapixel Cameras
• Up to 1.74Gbps Serial-Bit Rate
• 6.25MHz to 87MHz x 12-Bit + H/V Data
• 36.66MHz to 116MHz x 11-Bit + H/V Data
● Multiple Modes for System Flexibility
• 9.6kbps to 1Mbps Control Channel in UART,
Applications
● Automotive Camera Applications
2
2
• I C (with Clock Stretch), or UART-to-I C Modes
• 2:1 Input Mux for Camera Selection
2
• 15 Hardware-Selectable I C-Device Addresses
• Pairs with Any Maxim GMSL Serializer
• Crosspoint Switch Maps Data to any Output
Simplified Block Diagram
● Reduces EMI and Shielding Requirements
• Spread-Spectrum Serial-Input Tracking and Transfer
to the Parallel Output
VIDEO
VIDEO
• 1.7V to 1.9V Core and 1.7V to 3.6V I/O Supply
CAM
MAX96709
MAX96708
GPU
● Peripheral Features for System Verification
• Built-In PRBS Receiver for BER Testing
• Dedicated “Up/Down” GPI for Camera Frame Sync
Trigger and Other Uses
2
2
I C
I C
● Meets AEC-Q100 Automotive Specification
• -40°C to +115°C Operating Temperature Range
• ±8kV Contact and ±15kV Air IEC 61000-4-2 and
ISO 10605 ESD Protection
Ordering Information appears at end of data sheet.
19-7784; Rev 1; 3/17
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
32-Pin TQFN-EP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Video/Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Single and Double Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
HS/VS Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Bus Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Forward Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Reverse Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Remote-End Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock-Stretch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Adaptive Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Spread-Spectrum Tracking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Cable-Type Configuration and Input MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Crosspoint Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Shutdown/Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serialization Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Link-Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Maxim Integrated
│ 2
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
TABLE OF CONTENTS (CONTINUED)
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
seraddr (0x00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
desaddr (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
invpinh (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
invpinl (0x03). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
main config (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
eqtune (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
hvsrc (0x06). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
config (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
lflt_en (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
i2csrc (0x09, 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
i2cdst (0x0A, 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
i2cconfig (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
det_thr (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
filt_track (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
rsvd_10 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
rsvd_11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
underbst (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
rsvd_13 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
aeq (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
det_err (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
prbs_err (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
lf (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
rsvd_18 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
rsvd_19 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
rsvd_1a (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
i2csel (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
rsvd_1c (0x1C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
aeq_bst (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
id (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
revision (0x1F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
rsvd (0x20 to 0x23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
crossbar (0x65 to 0x6B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
rsvd_96 (0x96) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
rev_fast (0x97) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
rsvd_98 (0x98) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
rsvd_99 (0x99) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
rsvd_9a (0x9A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Maxim Integrated
│ 3
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
TABLE OF CONTENTS (CONTINUED)
rsvd_9b (0x9B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
rsvd_9c (0x9C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
rsvd_9d (0x9D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
rsvd_9f (0x9F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
rsvd_a0 (0xA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
rsvd_9e (0x9E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
rsvd_a1(0xA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
rsvd_a2 (0xA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
rsvd_a3 (0xA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
rsvd_a4 (0xA4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
rsvd_a5 (0xA5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
rsvd_a6 (0xA6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
rsvd_c9 (0xC9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
rsvd_ca (0xCA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
rsvd_cb (0xCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
rsvd_cc (0xCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
rsvd_cd (0xCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
rsvd_fd (0xFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
rsvd_fe (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
rsvd_ff (0xFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Parallel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Bus Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Bus Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Crossbar Switch Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Recommended Crossbar Switch Programming Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Control-Channel Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2
I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2
I C Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2
I C Address Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Configuration Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Cascaded/Parallel Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Dual μC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Maxim Integrated
│ 4
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
TABLE OF CONTENTS (CONTINUED)
2
UART-to-I C Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Cable Equalizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
ERRB Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Auto-Error Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Power-Supply Circuits and Bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
High-Frequency Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Device Configuration and Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Internal Input Pulldowns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Multifunction Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2
I C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PRBS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
GPI/GPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Fast Detection of Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Entering/Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
LIST OF FIGURES
Figure 1. Reverse Control-Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 2. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4. Line Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. Test Circuit for Single-Ended Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
Figure 6. I C Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Deserializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Maxim Integrated
│ 5
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
LIST OF FIGURES (CONTINUED)
Figure 10. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Active Output to High-Impedance Time, High Impedance to Active-Output Time Test Circuit . . . . . . . . . 25
Figure 13. Active Output to High-Impedance Time, High Impedance to Active-Output Time . . . . . . . . . . . . . . . . . . 25
Figure 14. 24-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. 32-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Coax Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Crosspoint-Switch Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. GMSL-UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 20. GMSL-UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21. SYNC Byte (0x79). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 22. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2
Figure 23. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0). . . . . . . . 62
2
Figure 24. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1). . . . . . . . 62
Figure 25. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 26. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 27. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LIST OF TABLES
Table 1. Reverse Control-Channel Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2. Link-Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3. Output-Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 4. Data-Rate Selection Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 5. Output Map (DBL = 0 or DBL = 1, First Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 6. Output Map (DBL = 1, Second Word) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 7. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 8. Default-Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 9. Cable-Equalizer Boost Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 10. Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 11. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Maxim Integrated
│ 6
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Absolute Maximum Ratings
AVDD to EP* ........................................................-0.5V to +1.9V
DVDD to EP*........................................................-0.5V to +1.9V
IOVDD to EP*.......................................................-0.5V to +3.9V
LMN_ to EP* (15mA current limit)........................-0.5V to +3.9V
IN_+, IN_- to EP*..................................................-0.5V to +1.9V
All Other Pins to EP*......................... -0.5V to (IOVDD + 0.5V)V
IN_+, IN_- Short Circuit to Ground or Supply ...........Continuous
Operating Temperature Range..........................-40°C to +115°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Continuous Power Dissipation T
= +70°C, 32-pin TQFN
A
(derate 34.5 mW/°C above +70°C.) ......................2758.6mW
*EP connected to IC ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
32-Pin TQFN-EP
PACKAGE CODE
T3255+8
21-0140
90-0013
Outline Number
Land Pattern Number
Thermal Resistance, Single Layer Board:
Junction-to-Ambient (θ
)
47
JA
Junction-to-Case Thermal Resistance (θ
)
1.7
JC
Thermal Resistance, Four Layer Board:
Junction-to-Ambient (θ
)
29
JA
Junction-to-Case Thermal Resistance (θ
)
1.7
JC
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 7
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (GPI, CXTP, I2CSEL, ADD_, HIM, PWDNB, MS)
0.65 x
High-Level Input Voltage
V
V
IH1
V
IOVDD
0.35 x
Low-Level Input Voltage
Input Current
V
V
IL1
V
IOVDD
20
I
V
= 0 to V
IOVDD
-20
μA
IN1
IN
SINGLE-ENDED OUTPUTS (DOUT_, VS, HS, DE, PCLKOUT)
V
V
IOVDD
- 0.3
I
I
= -2mA, DCS = 0
= -2mA, DCS = 1
OH
High-Level
Output Voltage
V
V
OH1
IOVDD
- 0.2
OH
I
I
= 2mA, DCS = 0
= 2mA, DCS = 1
0.3
0.2
Low-Level
Output Voltage
OL
V
I
V
OL1
OL
High-Impedance
Output Current
OUTENB = 1, V
= 0V or V
-20
15
3
20
39
13
63
21
50
17
97
32
μA
OZ
OUT
IOVDD
DOUT_, V = 0V, DCS = 0,
V
O
25
7
= 3.0V to 3.6V
IOVDD
DOUT_, V = 0V, DCS = 0,
V
O
= 1.7V to 1.9V
IOVDD
DOUT_, V = 0V, DCS = 1,
V
O
20
5
35
10
33
10
54
16
= 3.0V to 3.6V
IOVDD
DOUT_, V = 0V, DCS = 1,
V
O
= 1.7V to 1.9V
IOVDD
Output Short-Circuit Current
I
mA
OS
PCLKOUT_, V = 0V, DCS = 0,
V
O
15
5
= 3.0V to 3.6V
IOVDD
PCLKOUT_, V = 0V, DCS = 0,
V
O
= 1.7V to 1.9V
IOVDD
PCLKOUT_, V = 0V, DCS = 1,
V
O
30
9
= 3.0V to 3.6V
IOVDD
PCLKOUT_, V = 0V, DCS = 1,
V
O
= 1.7V to 1.9V
IOVDD
Maxim Integrated
│ 8
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
UART/I C and GENERAL-PURPOSE I/Os (RX/SDA, TX/SCL, GPIO_, ERRB, LOCK, LFLTB) with OPEN-DRAIN OUTPUTS
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH2
V
IOVDD
0.3 x
V
IL2
V
IOVDD
V
= 0 to V
(Note 2), RX/SDA,
(Note 2), GPIO_,
= 1.7V to 1.9V
IN
IOVDD
I
-110
-80
5
5
IN2
TX/SCL
Input Current
μA
V
= 0 to V
IN
IOVDD
I
IN
ERRB, LOCK
I
I
= 3mA, V
= 3mA, V
0.4
0.3
10
Low-Level Open-Drain Output
Voltage
OL
IOVDD
V
V
OL
= 3.0V to 3.6V
OL
IOVDD
Input Capacitance
C
Each pin (Note 3)
pF
IN
OUTPUTS FOR REVERSE CONTROL CHANNEL (IN0+, IN0-, IN1+, IN1-)
Forward channel disabled,
normal-immunity mode (Figure 1)
30
50
60
100
-30
-50
60
Differential High-Output Peak
Voltage (V - V
V
mV
mV
mV
mV
RODH
)
IN-
Forward channel disabled, high-immunity
mode (Figure 1)
IN+
Forward channel disabled,
normal-immunity mode (Figure 1)
-60
-100
30
Differential Low-Output Peak
Voltage (V - V
V
RODL
)
IN-
Forward channel disabled, high-immunity
mode (Figure 1)
IN+
Forward channel disabled,
normal-immunity mode (Figure 1)
Single-Ended High-Output
Peak Voltage
V
ROSH
Forward channel disabled, high-immunity
mode (Figure 1)
50
100
-30
-50
Forward channel disabled,
normal-immunity mode (Figure 1)
-60
-100
Single-Ended Low-Output
Peak Voltage
V
ROSL
Forward channel disabled, high-immunity
mode (Figure 1)
Maxim Integrated
│ 9
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIFFERENTIAL INPUTS (IN0+, IN0-, IN1+, IN1-)
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 2)
60
49
Differential High-Input
Threshold Peak Voltage
V
mV
IDH(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 2)
(V
- V
)
IN+
IN-
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 2)
-60
-49
1
Differential Low-Input
Threshold Peak Voltage
V
mV
IDL(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 2)
(V
- V
)
IN+
IN-
Input Common-Mode Voltage
(V + V )/2
V
1.3
1.6
V
CMR
IN+
IN-
Differential-Input Resistance
(Internal)
R
80
100
130
Ω
I
SINGLE-ENDED INPUTS (IN0+, IN0-, IN1+, IN1-)
Activity detector, medium threshold
43
33
(0x22 D[6:5] = 01) (Figure 3)
Single-Ended High-Input
V
mV
ISH(P)
Threshold Peak Voltage
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 3)
Activity detector, medium threshold
(0x22 D[6:5] = 01) (Figure 3)
-43
Single-Ended Low-Input
Threshold Peak Voltage
V
mV
ISL(P)
Activity detector, low threshold
(0x22 D[6:5] = 00) (Figure 3)
-33
40
Input Resistance (Internal)
R
50
65
Ω
I
LINE FAULT DETECTION INPUTS (LMN0, LMN1)
Short-to-Ground Threshold
Normal Threshold
V
V
(Figure 4)
(Figure 4)
0.3
V
V
TG
0.57
1.45
1.07
TN
V
+
IO
Open Threshold
V
(Figure 4)
V
TO
0.06
Open-Input Voltage
V
(Figure 4)
(Figure 4)
1.47
2.47
1.75
V
V
IO
Short-to-Battery Threshold
V
TE
Maxim Integrated
│ 10
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
f
= 116MHz, BWS = 0, double
PCLKOUT
95
22
115
25
output, AVDD + DVDD (1.9V)
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (1.9V) C = 5pF
L
(DCS = 0) (Note 3)
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (1.9V), C = 10pF
(DCS = 1) (Note 3)
31
44
63
95
17
24
33
35
49
70
115
19
27
36
L
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (3.6V), C = 5pF
L
(DCS = 0) (Note 3)
f
= 116MHz, BWS = 0, double
PCLKOUT
output, IOVDD (3.6V), C = 10pF
L
(DCS = 1) (Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (1.9V), AVDD + DVDD
(1.9V)
f
= 87MHz, BWS = 1, double
PCLKOUT
Worst-Case Supply Current
(Figure 5)
I
output, IOVDD (1.9V), C = 5pF (DCS = 0)
WCS
L
(Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (1.9V), C = 10pF
L
(DCS = 1) (Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (3.6V), C = 5pF (DCS = 0)
L
(Note 3)
f
= 87MHz, BWS = 1, double
PCLKOUT
output, IOVDD (3.6V), C = 10pF
(DCS = 1) (Note 3)
44
70
11
49
84
13
L
f
= 58MHz, BWS = 0, single
PCLKOUT
output, AVDD + DVDD (1.9V)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (1.9V), C = 5pF
L
(DCS = 0) (Note 3)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (3.6V), C = 10pF
15
18
L
(DCS = 1) (Note 3)
Maxim Integrated
│ 11
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
DC Electrical Characteristics (continued)
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY (continued)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (3.6V), C = 5pF
22
25
L
(DCS = 0) (Note 3)
f
= 58MHz, BWS = 0, single
PCLKOUT
output, IOVDD (3.6V), C = 10pF
(DCS = 1) (Note 3)
30
70
8
34
84
10
L
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, AVDD + DVDD (1.9V)
f
= 43.5MHz, BWS = 1, single
PCLKOUT
Worst-Case Supply Current
(Figure 5) (continued)
output, IOVDD (1.9V), C = 5pF
L
I
mA
WCS
(DCS = 0) (Note 3)
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, IOVDD (1.9V), C = 10pF
(DCS = 1) (Note 3)
12
16
22
14
18
25
L
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, IOVDD (3.6V), C = 5pF
L
(DCS = 0) (Note 3)
f
= 43.5MHz, BWS = 1, single
PCLKOUT
output, IOVDD (3.6V), C = 10pF
L
(DCS = 1) (Note 3)
Wake-up receivers enabled
Wake-up receivers disabled
PWDNB = low
54
15
15
160
100
100
Sleep-Mode Supply Current
I
μA
μA
CCS
Power-Down Supply Current
I
CCZ
ESD PROTECTION
Human Body Model, R = 1.5kΩ,
D
±8
C
= 100pF
S
IEC 61000-4-2, R = 330Ω, C = 150pF,
Contact discharge
D
S
±10
±15
±10
±30
IEC 61000-4-2, R = 330Ω, C = 150pF,
D
S
IN+, IN- (Note 4)
V
V
kV
ESD
Air discharge
ISO 10605, R = 2kΩ, C = 330pF,
D
S
Contact discharge
ISO 10605, R = 2kΩ, C = 330pF,
D
S
Air discharge
Human Body Model, R = 1.5kΩ,
D
±4
kV
V
C
= 100pF
All Other Pins (Note 5)
S
ESD
Machine Model
250
Maxim Integrated
│ 12
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
AC Electrical Characteristics
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
BWS = 1, DRS = 1, single output
BWS = 0, DRS = 1, single output
BWS = 1, DRS = 0, single output
BWS = 0, DRS = 0, single output
BWS = 1, DRS = 0, double output
BWS = 0, DRS = 0, double output
PCLKOUT and DOUT_, DCS = 1,
6.25
8.33
12.5
16.66
25
12.5
16.66
43.5
58
Clock Frequency
f
MHz
PCLKOUT
87
33.33
116
C = 10pF or DCS = 0, C = 5pF,
nonstaggered DOUT_
0.4T
0.35T
0.35T
0.3T
0.5T
0.4T
0.4T
0.35T
0.05
0.01
L
L
Data Valid Before Clock
Data Valid After Clock
Clock Jitter
t
ns
DVB
PCLKOUT and DOUT_, DCS = 1,
C = 10pF or DCS = 0, C = 5pF,
L
L
staggered DOUT_
PCLKOUT and DOUT_, DCS = 1,
C = 10pF or DCS = 0, C = 5pF,
L
L
nonstaggered DOUT_
t
ns
UI
DVA
PCLKOUT and DOUT_, DCS = 1, C =
L
10pF or DCS = 0, C = 5pF,
L
staggered DOUT_
RMS period jitter, spread off, 1.74Gbps
PRBS pattern, UI = 1/f
DBL = 1,
PCLKOUT,
double output)
t
J
Period jitter; peak-to-peak, spread off,
1.74Gbps, PRBS pattern, UI = 1/f
PCLKOUT,
DBL = 0, single output)
2
I C/UART PORT TIMING
2
I C/UART Bit Rate
9.6
20
1000
150
kbps
ns
30% to 70%, C = 10pF to 100pF,
1kΩ pullup to IOVDD
L
Output Rise Time
Output Fall Time
t
R
70% to 30%, C = 10pF to 100pF,
L
t
20
150
ns
F
1kΩ pullup to IOVDD
2
I C TIMING (Figure 6)
Low f
I2CSLVSH = 10)
range: (I2CMSTBT = 010,
SCL
9.6
100
400
Mid f range: (I2CMSTBT 101,
SCL
SCL Clock Frequency
f
>100
>400
kHz
SCL
I2CSLVSH = 01)
High f range: (I2CMSTBT = 111,
I2CSLVSH = 00)
SCL
1000
Maxim Integrated
│ 13
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
AC Electrical Characteristics (continued)
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
4
TYP
MAX
UNITS
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
range, Low
range, Mid
range, High
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
t
0.6
0.26
4.7
1.3
0.5
4
µs
HD:STA
t
µs
µs
µs
ns
ns
µs
µs
µs
µs
LOW
t
0.6
0.26
4.7
0.6
0.26
0
HIGH
Repeated START Condition
Setup Time
t
SU:STA
HD:DAT
Data Hold Time
Data Setup Time
t
0
0
250
100
50
t
SU:DAT
SU:STO
4
Setup Time for STOP
Condition
t
0.6
0.26
4.7
1.3
0.5
Bus Free Time
t
BUF
3.45
0.9
Data Valid Time
t
VD:DAT
VD:ACK
0.45
3.45
0.9
Data Valid Acknowledge Time
t
0.45
50
Pulse Width of Spikes
Suppressed
t
50
ns
SP
50
Capacitive load each bus line
C
100
pF
B
Maxim Integrated
│ 14
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
AC Electrical Characteristics (continued)
(V
= V
= 1.7 to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
DVDD
AVDD
IOVDD L A
+115°C, Typical values are at, V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)
DVDD
AVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING CHARACTERISTICS (Note 3)
20% to 80%, V
= 1.7V to 1.9V,
IOVDD
0.4
0.5
0.25
0.3
0.5
0.6
0.3
0.4
2.2
2.8
1.8
2
DCS = 1, C = 10pF
L
20% to 80%, V
= 1.7V to 1.9V,
= 3.0V to 3.6V,
= 3.0V to 3.6V,
= 1.7V to 1.9V,
= 1.7V to 1.9V,
= 3.0V to 3.6V,
= 3.0V to 3.6V,
IOVDD
DCS = 0, C = 5pF
PCLKOUT Rise-and-Fall Time
(Figure 7)
L
t
t
ns
R, F
20% to 80%, V
IOVDD
DCS = 1, C = 10pF
L
20% to 80%, V
IOVDD
DCS = 0, C = 5pF
L
20% to 80%, V
IOVDD
3.1
3.8
2.2
DCS = 1, C = 10pF
L
20% to 80%, V
IOVDD
DCS = 0, C = 5pF
Parallel Data Rise-and-Fall
Time (Figure 7)
L
t
t
ns
R, F
20% to 80%, V
IOVDD
DCS = 1, C = 10pF
L
20% to 80%, V
DCS = 0, C = 5pF
L
IOVDD
2.4
2160
400
Deserializer Delay
t
(Figure 8) (Note 6)
Bits
ns
SD
Reverse Control-Channel
Output Rise Time
t
No forward-channel data transmission
No forward-channel data transmission
180
180
R
Reverse Control-Channel
Output Fall Time
t
400
350
ns
µs
F
Deserializer GPI to serializer GPO
(Figure 9)
GPI-to-GPO Delay
t
GPIO
(Figure 10) AEQ on
(Figure 10) AEQ off
(Figure 11)
1.6
1
Lock Time (Note 3)
t
ms
LOCK
Power-Up Time
t
6.5
ms
ns
PU
Active Output to High-Imped-
ance Time
(Figure 12, Figure 13)
CC write OUTENB =1
t
t
250
OAZ
OZA
Active High-Impedance to
Output Time
(Figure 12, Figure 13)
CC write OUTENB =0
250
ns
Note 1: Limits are 100% production tested at T = +115°C. Limits over the operating temperature range are guaranteed by design
A
and characterization, unless otherwise noted.
Note 2: I min is due to voltage drop across the internal pullup resistor.
IN
Note 3: Not production tested. Guaranteed by design.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Measured in serial link bit times. Bit time = 1/(30 x f
) for BWS = GND. Bit time = 1/(40 x f
) for BWS = 1.
PCLKOUT
PCLKOUT
Maxim Integrated
│ 15
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Typical Operating Characteristics
(V
= V
= V
= 1.8V, T = +25°C, unless otherwise noted.)
AVDD
DVDD
IOVDD A
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY (BWS = 1)
SUPPLY CURRENT vs.
PIXEL CLOCK FREQUENCY (BWS = 0)
toc01
toc02
100
90
80
70
60
50
40
100
90
80
70
60
50
40
PRBS ON,
DBL = 1
EQ ON
PRBS ON,
COAX MODE
EQ ON
COAX MODE
DBL = 0
DBL = 0
DBL = 1
EQ OFF
75
EQ OFF
15
35
55
95
115
10
30
50
70
90
PIXEL CLOCK FREQUENCY (MHz)
PIXEL CLOCK FREQUENCY (MHz)
MAXIMUM PIXEL CLOCK FREQUENCY vs.
STP CABLE LENGTH (BER < 10-10
MAXIMUM PIXEL CLOCK FREQUENCY vs.
)
COAX CABLE LENGTH (BER < 10-10
)
toc03
toc04
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
NO PE, DBL = 0
AEQ
NO PE, DBL = 0
AEQ
9.7dB EQ
NO EQ
NO EQ
4.3dB EQ
4.3dB EQ
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
0
5
10
15
20
25
0
10
20
30
40
STP CABLE LENGTH (m)
COAX CABLE LENGTH (m)
Maxim Integrated
│ 16
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
DOUT4
DOUT3
DOUT11/CXTP/DE
15
14
13
12
11
10
9
DOUT12/HS
DOUT13/VS
DVDD
PWDNB
LFLTB
DOUT2
DOUT1
DOUT0
MS
MAX96708
LOCK
ERRB
TX/SCL
RX/SDA
+
1
2
3
4
5
6
7
8
TQFN
(5mm x 5mm)
Maxim Integrated
│ 17
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Description
PIN
NAME
FUNCTION
REF SUPPLY
TYPE
POWER
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1μF and
0.001μF capacitors placed as close as possible to the device, with
the smaller-value capacitor closest to AVDD.
5
AVDD
DVDD
Power
Power
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1μF and
0.001μF capacitors placed as close as possible to the device, with
the smaller-value capacitor closest to DVDD.
13
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass
IOVDD to EP with 0.1μF and 0.001μF capacitors placed as close
as possible to the device, with the smaller-value capacitor closest
to IOVDD.
22
IOVDD
Power
Power
Exposed Pad. EP is internally connected to device ground. Must
connect EP to the PCB ground plane through a via array for proper
thermal and electrical performance.
EP
—
HIGH-SPEED DIGITAL
High-Speed Digital / Multifunction
Parallel-Data/Vertical-Sync Output. Defaults to parallel-data
14
DOUT13/VS output on power-up. Vertical-sync output when HS/VS encoding is
enabled.
IOVDD
IOVDD
Digital
Digital
Parallel-Data/Horizontal-Sync Output. Defaults to parallel-data
DOUT12/HS output on power-up. Horizontal-sync output when HS/VS encoding
is enabled.
15
Parallel-Data Output/Cable-Type Input/Data-Enable Output with
internal pulldown to EP. CX/TP is latched at power-up, or when
DOUT11/
CXTP/DE
resuming from power-down mode (PWDNB = low), and switches
to parallel/data-enable output after power-up. Connect CXTP to
IOVDD with a 30kΩ resistor to set high (coax mode), or leave open
to set low (twisted-pair mode).
16
IOVDD
Digital
2
Parallel-Data Output/I C-Select Input with Internal Pulldown to EP.
I2CSEL is latched at power-up, or when resuming from power-
down mode (PWDNB = low), and switches to parallel-data output
after power-up. Connect I2CSEL to IOVDD with a 30kΩ resistor to
DOUT10/
I2CSEL
17
18
19
IOVDD
IOVDD
IOVDD
Digital
Digital
Digital
2
set high (I C interface), or leave open to set low (UART interface).
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD3 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD3 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT9/
ADD3
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD2 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD2 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT8/
ADD2
Maxim Integrated
│ 18
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Description (continued)
PIN
NAME
FUNCTION
REF SUPPLY
TYPE
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD1 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD1 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT7/
ADD1
20
IOVDD
Digital
Parallel-Data Output/Address Input with Internal Pulldown to EP.
ADD0 is latched at power-up, or when resuming from power-down
mode (PWDNB = low), and switches to parallel-data output after
power-up. Connect ADD0 to IOVDD with a 30kΩ resistor to set
high, or leave open to set low.
DOUT6/
ADD0
23
24
IOVDD
Digital
Parallel-Data Output/High-Immunity Mode Input with Internal
Pulldown to EP. HIM input latched at power-up, or when resuming
from power-down mode (PWDNB = low), and switches to parallel-
data output after power-up. Connect HIM to IOVDD with a 30kΩ
resistor to set high, or leave open to set low. HIGHIMM in the
serializer must be set to the same value.
DOUT5/HIM
IOVDD
IOVDD
Digital
Digital
High-Speed Digital / Single Function
Parallel-Clock Output. Provides timing signal to latch parallel-data
outputs to the input of another device.
21
PCLKOUT
25
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
Parallel-Data Output
Parallel-Data Output
Parallel-Data Output
Parallel-Data Output
Parallel-Data Output
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
Digital
Digital
Digital
Digital
Digital
26
29
30
31
LINE FAULT
2
8
LMN1
LMN0
Line-Fault Monitor Input 1 (see Figure 4)
Line-Fault Monitor Input 0 (see Figure 4)
Analog
Analog
Line-Fault Output. LFLTB is active low, and has a 60kΩ internal pullup
to IOVDD. LFLTB low indicates a line-fault condition at LMN0, or
LMN1. LFLTB is output high when PWDNB is low.
28
LFLTB
IOVDD
IOVDD
Digital
OTHER PINS
General-Purpose Input with Internal Pulldown to EP. Serializer
GPO (or INT) output follows the state of the GPI.
1
GPI
Digital
Noninverting CML Serial-Data Input 1. Coax input when CXTP
is high.
3
4
6
7
IN1+
IN1-
IN0+
IN0-
Inverting CML Serial-Data Input 1
Noninverting CML Serial-Data Input 0. Coax input when CXTP
is high.
Inverting CML Serial-Data Input 0
Receive/Serial Data. Input/output with internal 30kΩ pullup to
IOVDD. In UART mode, RX/SDA is the Rx input of the
2
9
RX/SDA
serializer's UART. In I C mode, RX/SDA is the SDA input/output
IOVDD
Digital
2
of the serializer's I C master/slave. RX/SDA has an open-drain
driver and requires a pullup resistor.
Maxim Integrated
│ 19
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Pin Description (continued)
PIN
NAME
FUNCTION
REF SUPPLY
TYPE
Transmit/Serial Clock. Input/output with internal 30kΩ pullup to
IOVDD. In UART mode, TX/SCL is the Tx output of the serializer's
2
10
TX/SCL
UART. In I C mode, TX/SCL is the SCL input/output of the serial-
IOVDD
Digital
2
izer's I C master/slave. TX/SCL has an open-drain driver and
requires a pullup resistor.
Error Output. Active-low, open-drain video data error output with
internal pullup to IOVDD. ERRB goes low when decoding errors
during normal operation exceed a programmed threshold, or when
at least one PRBS error is detected during a PRBS test. ERRB is
output high when PWDNB is low.
11
12
ERRB
LOCK
IOVDD
IOVDD
Digital
Digital
Lock Output. Open-drain output with internal pullup to IOVDD.
LOCK high indicates PLLs are locked with correct serial-word
boundary alignment. LOCK low indicates PLLs are not locked, or
incorrect serial-word boundary alignment. LOCK is low when the
configuration link is active. LOCK is output high when PWDNB is
low.
Active-Low, Power-Down Input with Internal Pulldown to EP.
Set PWDNB low to enter power-down mode to reduce power
consumption.
27
32
PWDNB
IOVDD
IOVDD
Digital
Digital
Mode-Select Input with Internal Pulldown to EP. Set MS low to
select base mode. Set MS high to select bypass mode.
MS
Functional Diagrams
VIDEO
VIDEO
CAM
MAX96709
MAX96708
GPU
2
2
I C
I C
Maxim Integrated
│ 20
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
R /2
L
ꢀꢁꢂL
ꢃEꢂEꢄIALIꢅEꢄ
IN+
IN-
V
OD
REVERSE
V
CMR
CONTROL-CHANNEL
TRANSMITTER
R /2
L
IN+
IN-
IN-
V
CMR
IN+
V
ROH
0.9 x V
ROH
0.1 x V
ROH
(IN+) - (IN-)
0.1 x V
ROL
ROL
t
R
0.9 x V
V
ROL
t
F
Figure 1. Reverse Control-Channel Output Parameters
Maxim Integrated
│ 21
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
R /2
L
IN+
IN-
VIS(P)
0.22µF
49.9Ω
IN_
V
ID(P)
R /2
L
_
V
IN+
+
_
C
IN
C
IN
+
-
VIN_
+
_
V
CIN
IN-
V ꢀ V - V
ID(P) = IN+ IN-
ꢀ
V
(V + V )/2
CMR = IN+
IN-
Figure 2. Test Circuit for Differential Input Measurement
Figure 3. Test Circuit for Single-Ended Input Measurement
1.8V
45.3kΩ*
4.99kΩ*
45.3kΩ*
4.99kΩ*
GMSL
DESERIALIZER
LMN0
LMN1
LMN0
GMSL
DESERIALIZER
OUTPUT
LOGIC
(IN+)
TWISTED PAIR
IN+
IN-
49.9kΩ*
49.9kΩ*
CONNECTORS
LFLTB
REFERENCE
VOLTAGE
1.8V
GENERATOR
45.3kΩ*
4.99kΩ*
LMN1
LMN0
GMSL
DESERIALIZER
OUTPUT
LOGIC
(IN-)
COAX
IN+
IN-
49.9kΩ*
49.9Ω*
CONNECTORS
*±1%
TOLERANCE
Figure 4. Line Fault
Maxim Integrated
│ 22
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
Figure 5. Worst-Case Pattern Output
START
CONDITION
BIT 7
STOP
CONDITION
(P)
BIT 6
MSB
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
(A6)
(S)
(A7)
t
t
LOW
t
SUꢀSTA
HIGH
1/ꢂ
SCL
V
V
x 0.7
x 0.3
IOVDD
IOVDD
SCL
SDA
t
SP
t
t
ꢂ
BUF
t
ꢁ
V
x 0.7
x 0.3
IOVDD
V
IOVDD
t
t
t
t
t
SUꢀSTO
HDꢀSTA
t
HDꢀDAT
VDꢀDAT
VDꢀACK
SUꢀDAT
2
Figure 6. I C Timing Parameters
C
L
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VDD
0.2 x V
I0VDD
t
t
F
R
Figure 7. Output Rise-and-Fall Times
Maxim Integrated
│ 23
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
IN+/-
FIRST BIT
LAST BIT
DOUT_
PARALLEL WORD N-1
PARALLEL WORD N
PARALLEL WORD N-2
PCLKOUT
t
SD
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. Deserializer Delay
V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 9. GPI-to-GPO Delay
IN+/-
IN+ - IN-
V
PWDN
IH1
t
LOCK
t
PU
LOCK
V
OH
LOCK
V
OH
PWDN MUST BE HIGH
Figure 10. Lock Time
Figure 11. Power-Up Delay
Maxim Integrated
│ 24
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
MAX96708
DOUT_
C
L
5kΩ
V
IOVDD
RS/SDA
UART/I2C
Figure 12. Active Output to High-Impedance Time, High Impedance to Active-Output Time Test Circuit
RX/SDA
DISABLE
PACKET
ENABLE
PACKET
0.1 x VIOVDD
0.9 x V
IOVDD
DOUT_
tOAZ
tOAZ
Figure 13. Active Output to High-Impedance Time, High Impedance to Active-Output Time
Maxim Integrated
│ 25
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Set SEREN = 0 and CLINK = 1 in the serializer to enable
the configuration link (SEREN = 1 forces the serializer into
video-link mode). Once PCLK has been established, turn
on the video link (SEREN = 1).
Detailed Description
The MAX96708 deserializer is a compact device with
features especially suited for automotive camera
applications. The device operates at a variety of output
widths and word rates up to a total serial-data rate up to
1.75Gbps. Two modes offer a 116MHz parallel clock rate
with 11 bits of video data or 87MHz parallel clock rate with
14 bits of video data. An embedded 9.6kbps to 1Mbps
control channel programs the serializer, deserializer, and
By default, video-link mode requires a valid PCLK for
operation. Set AUTO_CLINK bit = 1 (if supported), and
SEREN = 1 in the serializer to automatically switch
between the video link and configuration link whenever
PCLK is not present.
2
any attached UART or I C peripherals.
Single and Double Modes of Operation
To promote safety applications, the device features CRC
protection of video data. In addition, high-immunity mode
reduces the effects of bit errors corrupting communication.
Automatic equalization, along with a PRBS tester, allow
for in-system optimization of the link.
Single-/double-mode operation configures the available
1.74Gbps bandwidth into a variety of widths and word
rates. Single-mode operation is compatible with all GMSL
devices, and serializes one parallel word for each serial
word. Double mode serializes two half-width parallel
words for each serial word, and results in a 2x increase
in parallel word-rate range (compared to single mode).
Set DBL = 0 for single-mode operation and DBL = 1 for
double-mode operation.
This device operates over the -40°C to +115°C automotive
temperature range.
Serial Link Signaling and Data Format
The serializer scrambles the input parallel data and
combines this with the forward control data. The data is
then encoded for transmission and output as a single
bitstream at several times the input word rate (depending
on bus width). The deserializer receives the serial data
and recovers the clock signal. The data is then deserial-
ized, decoded, and descrambled into parallel output data
and forward control data.
HS/VS Encoding
By default, GMSL assigns a video bit slot to HSYNC,
VSYNC, and DE (if used). With HS/VS encoding, the
device instead encodes special packets to sync signals
to free up additional video bit slots. Set HVEN = 1 to turn
on HS/VS encoding (DE, if enabled uses up a video bit).
HS/VS encoding requires that HSYNC, VSYNC, and DE
(if used) remain high during the active video, and low
during the blanking period. Use HS/VS inversion when
using reverse-polarity sync signals.
Operating Modes
The GMSL devices are configurable to operate in many
modes, depending on the application. These modes allow
for a more efficient use of serial bandwidth. Most of these
settings are set during system design and are configured
using the external configuration pins, or through register
bits.
Error Detection
The serial link's 8b/10b encoding/decoding, and 1-bit
parity detect bit errors that occur on the serial link. An
optional 6-bit CRC check is available at the expense of 6
video bits. To activate 6-bit CRC mode, set PXL_CRC = 1
in the remote-side device first, and then in the local-side
device. When using 6-bit CRC mode, the available inter-
nal bus width is reduced by 6 bits in single-input mode
(DBL = 0) and 3 bits in double-input mode (DBL = 1). Note
that the input bus width may already have been reduced
due to pin availability of the serializer or deserializer; thus,
the reduction of bandwidth from CRC may not be visible
(see Table 3).
Video/Configuration Link
In normal operation, the serializer runs in video-link mode
(SEREN = 1) with video data and control data sent across
the serial link. Set SEREN = 0 in the serializer to turn off
serialization. The serializer powers up in video-link mode,
and requires a valid PCLK for operation.
The configuration link is available to set up the serializer,
deserializer, and peripherals when PCLK is not available.
Maxim Integrated
│ 26
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
half if used. The remaining bits can be used for video bits
minus any sync bits if HV encoding is not used.
Bus Widths
The serial link has multiple bus-width settings that
determine the parallel bus width and the resulting parallel
word rate. The serial link operates to a maximum serial
bit rate of 1.74Gbps. The BWS bit determines if each
serial packet is 30 or 40 bits long, which translates to a
maximum serial packet rate; thus, a maximum parallel
word rate of 58MHz or 43.5MHz when BWS = 0 or 1,
respectively. Decoding translates the 30- or 40-bit serial
packets into 24, or 32 parallel bits. One bit is used for
parity, while a second is reserved for the control channel.
An additional 6 bits is used during optional 6-bit CRC. In
addition, double mode splits the remaining word size in
Note: The following modes list the internal bus widths.
The number of available input and output pins may limit
the actual bus width available.
24-Bit Mode (Figure 14)
When BWS = 0, the 30-bit serial packet corresponds with
three 8b/10b symbols, representing 24 bits (24-bit mode).
After parity and control channel, this leaves 16/22 bits of
video data if CRC is/is not used (single mode), or 8/11 bits
of video data if CRC is/is not used (double mode).
24-BIT
MODE
22 BITS
2 BITS
SERIAL
DATA
D0
D1
D15
D16
D17
D18
D19
D20
D21
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET PARITY-
CHECK BIT
6
22 VIDEO
BITS
16 VIDEO
BITS
PXL_CRC
BITS
FORWARD CONTROL-
CHANNEL BIT
RX/
SDA
TX/
SCL
D0
D1
D21
D0
D1
D15
D16
D17
D18
D19
D20
D21
UART/I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
11 x 2
VIDEO
BITS*
8 x 2
VIDEO
BITS*
22 VIDEO
BITS*
PXL_CRC
16 VIDEO
BITS*
D11
D0
D12
D21
D10
D0
D1
D21
D8
D0
D9
D15
D1
D0
D1
D15
NO PXL_CRC, DBL = 0
58MHz MAX
D1
D7
NO PXL_CRC, DBL = 1
116MHz MAX
PXL_CRC ON, DBL = 0
58MHz MAX
PXL_CRC ON, DBL = 1
116MHz MAX
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 14. 24-Bit Mode Serial-Data Format
Maxim Integrated
│ 27
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
32-Bit Mode (Figure 15)
When BWS = 1 the 40-bit serial packet corresponds with four 8b/10b symbols, representing 32 bits (32-bit mode). After
parity and control channel, this leaves 24/30 bits of video data if CRC is/is not used (single mode), or 12/15 bits of video
data if CRC is/is not used (double mode).
32-BIT
MODE
30 BITS
2 BITS
SERIAL
DATA
D0
D1
D23
D24
D25
D26
D27
D28
D29
FCC
PCB
NO PXL_CRC
PXL_CRC ON
PACKET
PARITY-
CHECK BIT
6
30 VIDEO
BITS
24 VIDEO
BITS
PXL_CRC
BITS
FORWARD CONTROL-
CHANNEL BIT
RX/
SDA
TX/
SCL
D0
D2
D29
D0
D2
D23
D24
D25
D26
D27
D28
D29
UART/I2C
DBL = 0
DBL = 1
DBL = 1
DBL = 0
15 x 2
VIDEO
BITS*
12 x 2
VIDEO
BITS*
30 VIDEO
BITS*
PXL_CRC
24 VIDEO
BITS*
D15
D0
D16
D29
D14
D0
D1
D29
D12
D0
D13
D23
D1
D0
D1
D23
NO PXL_CRC, DBL = 0
43.5MHz MAX
D1
D11
NO PXL_CRC, DBL = 1
87MHz MAX
PXL_CRC ON, DBL = 0
43.5MHz MAX
PXL_CRC ON, DBL = 1
87MHz MAX
*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.
Figure 15. 32-Bit Mode Serial-Data Format
Maxim Integrated
│ 28
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
2
I C Interface
Control Channel and Register Programming
2
The serial link connects the serializer and deserializer I C
interfaces together through the control channel. When an
2
The control channel sends I C or UART information
across the serial link for control of the serializer, deserial-
izer, and any attached peripherals. The control channel
is multiplexed onto the serial link and is available with or
without the video channel.
2
I C master sends a command to one side of the link (local
side) the control channel forwards this information to and
from the other side of the link (remote side), allowing a
single microcontroller to configure the serializer,
deserializer, and peripherals. The microcontroller can be
located on the serializer side (display applications) and the
deserializer side (camera applications). Dual-μC opera-
tions are supported as long as a software-arbitration
method is used. The serial link assumes that only one
microcontroller is talking at any given time.
Forward Control Channel
Control data sent from the serializer to the deserializer is
sent on the forward control channel. The data is encoded
as one of the serial bits in the forward high-speed link.
After deserialization, the forward control-channel data is
extracted from the serial link. The forward control-channel
bandwidth exceeds the maximum external control data
rate, and all data sent on the forward control channel
appears on the remote side after transmission delay of a
few bit times.
Remote-End Operation
2
When an I C master initiates communication on the local
slave device (the serializer/deserializer directly connected
to the master), the remote-side device acts as a master
device that sends data forwarded from the local-side
device, and forwards any data received from peripher-
als attached to the remote-side device. This remote-side
master device operates according to the timing settings in
the I C Master setting register. Set the master settings to
match the timing settings used by the external microcon-
troller.
Reverse Control Channel
Control data sent from the deserializer to the serializer is
sent on the reverse control channel. The data is encoded
as a series of 1μs pulses, with a maximum raw data rate of
1Mbps. High-immunity mode is available to increase the
robustness of the reverse control channel at a reduced
raw bit rate of 500kbps (Table 1). In high-immunity mode,
set HPFTUNE = 00 in the deserializer when the serial bit
rate is larger than 1Gbps. Setting the REV_FAST bit =
2
Clock-Stretch Timing
2
The I C interface uses clock stretching to allow time for
2
1 increases this rate back to 1Mbps. In I C mode, when
data to be forwarded across the serial link. The master
microcontroller, along with any attached peripherals, must
accept clock stretching of the GMSL devices.
the input data rate (after encoding) exceeds the reverse
data rate, the input clock is held through clock stretching
to slow the external clock to match the internal bit rate.
GPO/GPI Control
UART Interface
GPO on the serializer follows GPI transitions on the
deserializer. This GPO/GPI function can be used to
transmit signals such as a frame sync in a surround-view
camera system (see the Providing a Frame Sync (Camera
Applications) section).
The UART interface, compatible with all GMSL devices,
sends commands from device to device through several
UART packets. Set I2CSEL = 0 to set the device to use
UART protocol.
Table 1. Reverse Control-Channel Modes
2
REVERSE CONTROL-
CHANNEL MODE
MAX UART/I C BIT RATE
HIM PIN SETTING
REVFAST BIT
(kbps)
1000
500
Legacy reverse control-
channel mode (compatible with
all GMSL devices)
Low
X
0
1
High-immunity mode
Fast high-immunity mode
(requires serial-data rate >
1.25Gbps)
High
1000
X = Don’t care.
Maxim Integrated
│ 29
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Adaptive Line Equalizer
Spread-Spectrum Tracking
The deserializer includes an adaptive line equalizer to
compensate for higher cable attenuation at higher frequen-
cies. The cable equalizer has 12 levels of compensation
to handle up to 30m coax and 15m STP cable lengths.
At initial lock, the adaptive equalizer selects the optimum
compensation level. The device can be programmed to
re-adapt periodically, or manually to compensate for any
significant changes in the transmission environment.
The deserializer can track a spread input clock, eliminating
the need for multiple spread clocks.
Cable-Type Configuration and Input MUX
The driver inputs are programmable for two kinds of
cable: 100Ω twisted pair and 50Ω coax (contact the
factory for devices compatible with 75Ω cables). In
coax mode, connect IN0+ to OUT+ of the serializer.
Connect IN1+ to OUT+ of the second serializer. Control-
channel data is sent to the serializer selected with the
GMSL_IN_SEL bit. Leave all unused IN_ pins uncon-
nected, or connect them to ground through 50Ω and a
capacitor for increased power-supply rejection. If OUT- is
GMSL
DESERIALIZER
ꢀꢁ
ꢂEꢃIALIꢄEꢃ
not used, connect OUT- to V
through a 50Ω resistor
DD
(Figure 16). When there are μCs at the serializer, and
at each deserializer, only one μC can communicate at a
time. Disable forward and reverse channel links according
to the communicating deserializer connection to prevent
OUT+
OUT-
IN+
IN-
2
2
AVDD
contention in I C-to-I C mode.
Crosspoint Switch
OPTIONAL COMPONENTS
FOR INCREASED
POWER-SUPPLY REJECTION
50Ω
The crosspoint switch routes data between the parallel
input/output and the SerDes (Figure 17). The anything-to-
anything routing assures the mapping between the video
source and destination.
Figure 16. Coax Connection
DATA
CROSSBAR_
4
D0
D1
:
XBI0
XBI1
:
DOUT0
DOUT1
:
:
TO OUTPUT PINS
D12
D13
XBI12
XBI13
DOUT12
DOUT13
XBI0
XBI1
:
XBI12
XBI13
0
:
DOUT_
1
14 SWITCHES
Figure 17. Crosspoint-Switch Dataflow
Maxim Integrated
│ 30
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Sleep Mode
Shutdown/Sleep Modes
To reduce power consumption further, the devices can
be put into sleep mode. In this mode, all registers keep
their programmed values, and all functions in the device
are powered down except for the wake-up detectors on
Several sleep and shutdown modes are available when
full operation is not needed.
Configuration Link
When the high-speed video link is not needed, or unavail-
able, a configuration link can be used in its place. In
configuration-link mode, the parallel-digital input/output
is disabled, the LOCK pin remains low, and the serial link
internally generates its own clock, to allow full operation
2
the local I C/UART interface, and the serial link. Any
activity seen by the wake-up detectors temporarily turns
on the control-channel interface. During this time, a micro-
controller can command the device to exit sleep mode.
See the Entering/Exiting Sleep Mode section.
2
of the control channel (UART/I C and GPIO).
Power-Down Mode
Serialization Disable
The lowest power-consumption mode is power-down
mode. In this mode, all functions are powered down, and
all register values are lost.
When the serial link is not needed, such as when down-
stream devices are powered off, the user can disable
serialization. In this mode, all forward communication is
shut down. The user can reenable serialization either
locally or through the reverse channel.
Link-Startup Procedure
Table 2 lists the startup procedure for image-sensing
applications. The control channel is available after the
video link or the configuration link is established. If the
deserializer powers up after the serializer, the control
channel becomes unavailable until 2ms after power-up.
Table 2. Link-Startup Procedure
NO.
ΜC
SERIALIZER
DESERIALIZER
—
μC connected to deserializer.
Set all configuration inputs.
Set all configuration inputs.
Powers up and loads default
settings. Establishes video link
when valid PCLK available.
Powers up and loads default
settings. Locks to video-link
signal if available.
1
Powers up. Wait t
.
PU
(If no PCLK) Programs CLINKEN, SEREN, and/or
AUTOCLINK bits. Wait 5ms after each command.
1a
Establishes configuration link.
Locks to config link if available.
(If not locked) Sets any additional configuration bits
that are mismatched between serializer and
deserializer (e.g BWS, CX/TP). Wait 5ms for lock
after each command.
Configuration changed.
Reestablishes configuration/
video link if needed.
Configuration changed. Locks
to configuration/video link.
1b
Configuration changed.
Reestablishes config/video link
if needed
Sets Register 0x07 configuration bits in the serializer
(DBL, BWS, PXL_CRC, etc.). Wait 2ms.
2
3
Loss of lock may occur.
Sets Register 0x07 configuration bits in the
deserializer (DBL, BWS, PXL_CRC, etc.). Wait 5ms
for lock to re-establish.
Configuration changed. Locks
to configuration/video link.
—
4
5
Writes rest of serializer/deserializer configuration bits. Configuration changed.
Configuration changed.
Forwards commands from μC to Forwards commands to cam-
Writes camera/peripheral configuration bits.
serializer.
era/peripherals.
If in configuration link: When PCLK is available, set
SEREN = 1. Wait 5ms for lock.
5a
Enables video link.
Locks to video link.
Maxim Integrated
│ 31
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
CONFIG LINK
CONFIG LINK
UNLOCKED
SIGNAL
DETECTED
OPERATING
WAKE UP
SIGNAL
POWER ON
IDLE
SERIAL PORT
LOCKING
SLEEP
CONFIG LINK
LOCKED
PROGRAM
REGISTERS
0 --> SLEEP
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES
AFTER µC SETS SLEEP = 1
PWDNB = HIGH,
POWER ON
GPI CHANGES FROM
LOW TO HIGH OR
PRBSEN = 0
PRBSEN = 1
POWER-
DOWN
OR
SEND GPI TO
GMSL
SERIALIZER
HIGH TO LOW
PWDNB = LOW OR
POWER OFF
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
POWER OFF
0 -- > SLEEP
Figure 18. State Diagram
Maxim Integrated
│ 32
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Register Map
OFFSET
NAME
MSB
LSB
0x00
seraddr
desaddr
SERADDR[6:0]
DESADDR[6:0]
RSVD
CFG-
BLOCK
0x01
0x02
0x03
0x04
invpinh
invpinl
INVPINH[5:0]
INVPINL[7:0]
LOCKED OUTENB PRBSEN SLEEP INTTYPE[1:0]
SRNG[1:0]
main config
REVCCENFWDCCEN
EQTUNE[3:0]
I2C-
HVTR_
MODE
0x05
eqtune
DCS
EN_EQ
METHOD
0x06
0x07
hvsrc
HIGHIMM
DBL
RSVD
DRS
RSVD
BWS
RSVD
ES
RSVD
RSVD
HV_SRC[2:0]
config
HVEN
CXTP
PXL_CRC
LFLT_EN_ LFLT_EN_
0x08
lflt_en
GPI_EN DISSTAG ERR_RST RSVD
RSVD[1:0]
POS
NEG
0x09
0x0A
0x0B
0x0C
i2csrc A
i2cdst A
i2csrc B
i2cdst B
I2C_SRC_A[6:0]
I2C_DST_A[6:0]
I2C_SRC_B[6:0]
I2C_DST_B[6:0]
RSVD
RSVD
RSVD
RSVD
I2C_LOC_
ACK
0x0D
0x0E
0x0F
i2cconfig
det_thr
I2C_SLV_SH[1:0]
I2C_MST_BT[2:0]
I2C_SLV_TO[1:0]
DET_THR[7:0]
GMSL_IN_ EN_DE_ EN_HS_ EN_VS_
PRBS_
TYPE
filt_track
DE_EN HTRACK VTRACK
SEL
FILT
FILT
FILT
0x10
0x11
rsvd_10
rsvd_11
RSVD[1:0]
RSVD
RSVD[3:0]
RSVD[1:0]
RSVD
RSVD[3:0]
RSVD[1:0]
UNDER-
BST_DET_ RSVD
EN
DIS_
RWAKE
0x12
0x13
0x14
underbst
rsvd_13
aeq
RSVD[1:0]
RSVD
RSVD RSVD
RSVD
RSVD
RSVD
RSVD[4:0]
AEQ_
PER_
AEQ_
MAN_
AEQ_EN
RSVD[4:0]
MODE TRG_REQ
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
det_err
prbs_err
lf
DET_ERR[7:0]
PRBS_ERR[7:0]
RSVD
RSVD PRBS_OK GPI_IN
LF_NEG[1:0]
LF_POS[1:0]
rsvd_18
rsvd_19
rsvd_1a
i2csel
RSVD[7:0]
RSVD[7:0]
RSVD[7:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
I2CSEL
RSVD
RSVD
RSVD
rsvd_1c
RSVD[5:0]
UNDER-
BOOST_
DET
0x1D
aeq_bst
id
RSVD
RSVD
AEQ_BST[3:0]
0x1E
ID[7:0]
Maxim Integrated
│ 33
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
OFFSET
NAME
MSB
LSB
0x1F
0x20
0x21
0x22
0x23
revision
RSVD
RSVD
RSVD HDCPCAP
REVISION[3:0]
rsvd_20
rsvd_21
rsvd_22
rsvd_23
RSVD[7:0]
RSVD[7:0]
RSVD[7:0]
RSVD[7:0]
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
crossbar 0
crossbar 2
crossbar 4
crossbar 6
crossbar 8
crossbar 10
crossbar 12
rsvd_96
CROSSBAR_N_0[3:0]
CROSSBAR_N_2[3:0]
CROSSBAR_N_4[3:0]
CROSSBAR_N_6[3:0]
CROSSBAR_N_8[3:0]
CROSSBAR_N_10[3:0]
CROSSBAR_N_12[3:0]
CROSSBAR_N+1_0[3:0]
CROSSBAR_N+1_2[3:0]
CROSSBAR_N+1_4[3:0]
CROSSBAR_N+1_6[3:0]
CROSSBAR_N+1_8[3:0]
CROSSBAR_N+1_10[3:0]
CROSSBAR_N+1_12[3:0]
RSVD[1:0]
REV_FAST RSVD
RSVD[1:0]
RSVD
RSVD[5:0]
RSVD[5:0]
RSVD RSVD
RSVD
RSVD
RSVD
rev_fast
rsvd_98
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
rsvd_99
RSVD
RSVD
RSVD
RSVD
RSVD
rsvd_9a
RSVD[1:0]
RSVD[2:0]
rsvd_9b
RSVD[1:0]
RSVD[1:0]
RSVD[2:0]
RSVD[1:0]
rsvd_9c
RSVD
RSVD[3:0]
SOFT_
PD
0x9D
rsvd_9d
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
rsvd_9e
rsvd_9f
rsvd_a0
rsvd_a1
rsvd_a2
rsvd_a3
rsvd_a4
rsvd_a5
rsvd_a6
RSVD
RSVD
RSVD
RSVD[1:0]
RSVD RSVD
RSVD[2:0]
RSVD
RSVD
RSVD
RSVD
HPFTUNE[1:0]
RSVD
RSVD[1:0]
RSVD[3:0]
RSVD[2:0]
RSVD[4:0]
RSVD[7:0]
RSVD[3:0]
RSVD[3:0]
RSVD
RSVD[1:0]
RSVD[1:0]
RSVD[2:0]
RSVD
RSVD
RSVD
RSVD[1:0]
RSVD[3:0]
RSVD[1:0]
RSVD[1:0]
RSVD
RSVD
RSVD
0xC9
0xCA
0xCB
0xCC
0xCD
rsvd_c9
rsvd_ca
rsvd_cb
rsvd_cc
rsvd_cd
RSVD[7:0]
RSVD[1:0]
RSVD RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD[6:0]
RSVD[6:0]
0xFD
0xFE
0xFF
rsvd_fd
rsvd_fe
rsvd_ff
RSVD[7:0]
RSVD[3:0]
RSVD[3:0]
RSVD[3:0]
RSVD
RSVD
RSVD
RSVD
Maxim Integrated
│ 34
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
seraddr (0x00)
BIT
7
6
5
4
3
2
1
0
RSVD
0b
Field
SERADDR[6:0]
1000000b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
SERADDR
RSVD
BITS
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
0000001: I C write/read address is 0x02, 0x03
XXXXXXX: I C write/read address is XXXXXXX0,
2
2
7:1
0
Serializer Address: Serializer device address
Reserved: Do not change from default value
XXXXXXX1
2
1111111: I C write/read address is 0xFE, 0xFF
0: Reserved
desaddr (0x01)
BIT
7
6
5
4
3
2
1
0
Field
DESADDR[6:0]
XXXXXXXb
Write, Read
CFGBLOCK
0b
Reset
Access Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
2
0000001: I C write/read address is 0x02, 0x03
Deserializer Address: Deserializer device address
(initial value depends on ADD3, ADD2, ADD1, and
ADD0 pin settings latched at power-up)
2
XXXXXXX: I C write/read address is XXXXXXX0,
XXXXXXX1
DESADDR
7:1
2
1111111: I C write/read address is 0xFE, 0xFF
0: Set all write/read registers as writable
1: Set all registers as read only
Configuration Block. When 1, make all registers
read only
CFGBLOCK
0
invpinh (0x02)
BIT
7
6
5
4
3
2
1
0
Field
INVPINH[5:0]
000000b
SRNG[1:0]
11b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
XXXXX0: Do not invert D8
XXXXX1: Invert D8
XXXX0X: Do not invert D9
XXXX1X: Invert D9
XXX0XX: Invert D10
XXX1XX: Do not invert D10
XX0XXX: Do not invert D11
XX1XXX: Invert D11
Invert Output Pins High: Invert output pins
D8–D13
INVPINH
7:2
X0XXXX: Do not invert D12
X1XXXX: Invert D12
0XXXXX: Do not invert D13
1XXXXX: Invert D13
00: 0.5 to 1Gbps
SRNG
1:0
Serial Data-Rate Range
01: 1 to 1.74Gbps
1X: Autodetect serial range
Maxim Integrated
│ 35
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
invpinl (0x03)
BIT
7
6
5
4
3
2
1
0
Field
INVPINL[7:0]
00000000b
Write, Read
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
XXXXXXX0: Do not invert D0
XXXXXXX1: Invert D0
XXXXXX0X: Do not invert D1
XXXXXX1X: Invert D1
XXXXX0XX: Do not invert D2
XXXXX1XX: Invert D2
XXXX0XXX: Do not invert D3
XXXX1XXX: Invert D3
XXX0XXXX: Do not invert D4
XXX1XXXX: Invert D4
Invert Output Pins Low: Invert output pins
D0–D7
INVPINL
7:0
XX0XXXXX: Do not invert D5
XX1XXXXX: Invert D5
X0XXXXXX: Do not invert D6
X1XXXXXX: Invert D6
0XXXXXXX: Do not invert D7
1XXXXXXX: Invert D7
main config (0x04)
BIT
Field
7
6
OUTENB
0b
5
PRBSEN
0b
4
3
2
1
REVCCEN
1b
0
FWDCCEN
1b
LOCKED
Xb
SLEEP
0b
INTTYPE[1:0]
Reset
01b
Access Type
Read Only
Write, Read Write, Read Write, Read
Write, Read
Write, Read Write, Read
DECODE
BITFIELD
BITS
DESCRIPTION
0: Video link not locked
1: Video link locked
LOCKED
7
6
5
4
LOCK Output: LOCK output pin level
Outputs Enable Bar: Disable outputs
PRBS Test Enable
0: Enable DOUT_outputs
1: Disable DOUT_ outputs
OUTENB
PRBSEN
SLEEP
0: Set device for normal operation
1: Enable PRBS test
0: Set device for normal operation
1: Put device into sleep mode
Sleep Mode: Activate sleep mode
2
00: UART-to-I C conversion
01: UART
Interface Type: Local control-channel interface
when I2CSEL = 0
INTTYPE
3:2
1X: Disable local control channel
0: Disable reverse control-channel receiver
1: Enable reverser control-channel receiver
Reverse Control-Channel Enable: Enable
reverse control channel from deserializer
REVCCEN
FWDCCEN
1
0
0: Disable forward control-channel transmitter
1: Enable forward control-channel transmitter
Forward Control-Channel Enable: Enable
forward control channel to deserializer
Maxim Integrated
│ 36
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
eqtune (0x05)
BIT
7
6
5
4
EN_EQ
1b
3
2
1
0
I2C-
METHOD
HVTR_
MODE
Field
DCS
0b
EQTUNE[3:0]
Reset
0b
1b
1001b
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
0: Send the register address during UART-to-I C
conversion
1: Do not send the register address during
2
I C Method: Skip register address when
I2CMETHOD
7
2
converting UART to I C
2
UART-to-I C conversion
0: Set device for normal operation
1: Increase CMOS driver current
Driver Current Selection: Driver current
selection for CMOS outputs
DCS
6
5
4
0: Use partial periodic HV tracking
1: Use partial and full periodic HV tracking
HV Tracking Mode: HV tracking allows
continuous HSYNC format
HVTR_MODE
EN_EQ
0: Disable equalization
1: Enable equalization
Enable Equalizer: Enable equalizer for
manual and adaptive modes
0000: 1.6dB manual EQ setting
0001: 2.1dB manual EQ setting
0010: 2.8dB manual EQ setting
0011: 3.5dB manual EQ setting
0100: 4.3dB manual EQ setting
0101: 5.2dB manual EQ setting
0110: 6.3dB manual EQ setting
0111: 7.3dB manual EQ setting
1000: 8.5dB manual EQ setting
1001: 9.7dB manual EQ setting
1010: 11dB manual EQ setting
1011: 12.2dB manual EQ setting
11XX: Do Not Use
Equalizer Tune: Equalizer boost level at
750MHz (effective when Adaptive EQ is
turned off)
EQTUNE
3:0
Maxim Integrated
│ 37
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
hvsrc (0x06)
BIT
7
HIGHIMM
Xb
6
5
4
3
2
1
0
Field
RSVD
1b
RSVD
1b
RSVD
0b
RSVD
1b
HV_SRC[2:0]
111b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
HIGHIMM
BITS
DESCRIPTION
DECODE
Hgh-Immunity Mode: Default value
depends on the state of the HIM input. 1: Use high-immunity mode
0: Use legacy reverse-channel mode
7
Reserved: Do not change from
1: Reserved
RSVD
RSVD
RSVD
RSVD
6
5
4
3
default value
Reserved: Do not change from
1: Reserved
default value
Reserved: Do not change from
0: Reserved
default value
Reserved: Do not change from
1: Reserved
default value
000: Use D18/D19 for HS/VS (use this setting when the
serializer is a 3.125Gbps device; otherwise, this setting is
for use with the MAX9273 when DBL = 0 or HVEN = 1)
001: Use D14/D15 for HS/VS (for use with the MAX9271/
MAX96705 when DBL = 0 or HVEN = 1)
010: Use D12/D13 for HS/VS (for use with the MAX96707
when DBL = 0 or HVEN = 1)
HS/VS Source Selection: HS/VS bit
selection
HV_SRC
2:0
011: Use D0/D1 for HS/VS (for use with the MAX9271/
MAX9273/MAX96705/MAX96707 when DBL = 1 and HVEN =
0)
10X: Do Not Use
110: Automatically determine the source of HSYNC/VSYNC
(for use with the MAX96707)
111: Automatically determine the source of HSYNC/VSYNC
(for use with the MAX96705)
Maxim Integrated
│ 38
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
config (0x07)
BIT
7
6
5
4
3
2
1
0
PXL_CRC
0b
Field
DBL
0b
DRS
0b
BWS
0b
ES
0b
RSVD
0b
HVEN
0b
CXTP
Xb
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
Double-Output Mode
DECODE
0: Use single-rate output
1: Use double-rate output (2x word rate at
1/2x width)
DBL
7
0: Use normal data-rate output
1: Use 1/2 rate data output (for use with low
data rates)
DRS
BWS
6
5
Data-Rate Select
0: Set bus width for 22-bit bus, 24-bit mode
1: Set bus width for 30-bit bus (32-bit mode)
Bus-Width Select
0: Set output data valid on rising edge of
PCLKOUT
1: Set output data valid on falling edge of
PCLKOUT
ES
4
Edge Select
RSVD
HVEN
3
2
Reserved: Do not change from default value
0: Reserved
0: Disable HS/VS encoding
1: Enable HS/VS encoding
HS/VS Encoding Enable
0: Use differential-output mode (for use with
twisted-pair cable)
1: Use single-ended output mode (for use with
coax cable)
CXTP
1
0
Coax/TP Select
0: Use 1-bit parity (compatible with all devices)
1: Use 6-bit CRC
PXL_CRC
Pixel CRC Enable: Pixel error-detection type
Maxim Integrated
│ 39
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
lflt_en (0x08)
BIT
7
6
5
GPI_EN
1b
4
DISSTAG
0b
3
ERR_RST
0b
2
1
0
Field
LFLT_EN_POS LFLT_EN_NEG
RSVD
0b
RSVD[1:0]
01b
Reset
1b
Xb
Access Type
Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Disable line-fault detector LMN0
1: Enable line-fault detector LMN0
Line-Fault Detector Enable Positive Line:
Enable line-fault detector LMN0
LFLT_EN_POS
7
Line-Fault Detector Enable Negative Line:
Enable line-fault detector LMN1; disabled by
default in coax mode and enabled by default in
twisted-pair mode
0: Disable line-fault detector LMN1
1: Enable line-fault detector LMN1
LFLT_EN_NEG
6
GPI-to-GPO Enable: Enable GPI-to-GPO
signal transmission to serializer
0: Disable GPI-to-GPO transmission
1: Enable GPI-to-GPO transmission
GPI_EN
5
4
Disable Staggering: Disable staggering of
outputs
0: Enable staggering of DOUT_outputs
1: Disable staggering of DOUT_outputs
DISSTAG
0: Disable automatic reset of DETERR_
Error Reset: When set to 1, automatically reset register
ERR_RST
3
DET_ERR 1μs after ERROR pin is asserted
1: Enable automatic reset of DETERR_
register
RSVD
RSVD
2
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
01: Reserved
1:0
i2csrc (0x09, 0x0B)
BIT
Field
7
6
5
4
I2C_SRC[6:0]
0b
3
2
1
0
RSVD
0b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
I2C_SRC
RSVD
BITS
7:1
0
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
0000001: I C write/read address is 0x02, 0x03
XXXXXXX: I C write/read address is
XXXXXXX0, XXXXXXX1
2
2
2
I C Address Translator Source: I C address
translator source A
2
2
1111111: I C write/read address is 0xFE, 0xFF
Reserved: Do not change from default value
0: Reserved
Maxim Integrated
│ 40
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
i2cdst (0x0A, 0x0C)
BIT
Field
7
6
5
4
I2C_DST[6:0]
0b
3
2
1
0
RSVD
0b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
0000000: I C write/read address is 0x00, 0x01
2
0000001: I C write/read address is 0x02, 0x03
2
2
I C address translator destination: I C address
translator destination A
2
I2C_DST
7:1
XXXXXXX: I C write/read address is
XXXXXXX0, XXXXXXX1
2
1111111: I C write/read address is 0xFE, 0xFF
RSVD
0
Reserved: Do not change from default value
0: Reserved
i2cconfig (0x0D)
BIT
7
6
5
4
3
I2C_MST_BT[2:0]
101b
2
1
0
Field
I2C_LOC_ACK
0b
I2C_SLV_SH[1:0]
01b
I2C_SLV_TO[1:0]
10b
Reset
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Disable local acknowledge when forward
channel is not available
1: Enable local acknowledge when forward
channel is not available
2
2
I C-to-I C Slave Local Acknowledge: When
I2C_LOC_ACK
7
forward channel is not available
00: (352, 117)ns
01: (469, 234)ns
10: (938, 352)ns
11: (1406, 469)ns
2
2
I C-to-I C Slave Setup and Hold Time Setting:
I2C_SLV_SH
I2C_MST_BT
I2C_SLV_TO
6:5
Setup, hold (typ)
000: (6.61, 8.47, 9.92)kbps bit rate
001: (22.1, 28.3, 33.2)kbps bit rate
010: (66.1, 84.7, 99.2)kbps bit rate
011: (82, 105, 123)kbps bit rate
100: (136, 173, 203)kbps bit rate
101: (265, 339, 397))kbps bit rate
110: (417, 533, 625)kbps bit rate
111: (654, 837, 980)kbps bit rate
2
2
4:2
1:0
I C-to-I C Master Bit Rate Setting: Min, typ, max.
00: 64μs timeout
01: 256μs timeout
10: 1024μs timeout
2
2
I C-to-I C Slave Remote-Side
Timeout Setting: Typ
2
11: I C timeout disabled
Maxim Integrated
│ 41
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
det_thr (0x0E)
BIT
7
6
5
4
3
2
1
0
Field
DET_THR[7:0]
Reset
00000000b
Write, Read
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1, XXXXXXXX
11111111: Value is 255
Detected Errors Threshold: Threshold for de-
tected errors
DET_THR
7:0
filt_track (0x0F)
BIT
7
6
5
4
3
DE_EN
0b
2
HTRACK
0b
1
VTRACK
0b
0
GMSL_IN_
SEL
EN_DE_
FILT
EN_HS_
FILT
EN_VS_
FILT
PRBS_
TYPE
Field
Reset
0b
0b
0b
0b
1b
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
Select GMSL Input
DECODE
0: Select IN0+, IN0-
1: Select IN1+, IN1-
GMSL_IN_SEL
7
Enable DE Glitch Filtering: Enable glitch filtering
on DOUT11
0: Disable glitch filtering on DOUT11
1: Enable glitch filtering on DOUT11
EN_DE_FILT
EN_HS_FILT
EN_VS_FILT
DE_EN
6
5
4
3
2
1
0
Enable HS Glitch Filtering: Enable glitch filtering
on DOUT12
0: Disable glitch filtering on DOUT12
1: Enable glitch filtering on DOUT12
Enable VS Glitch Filtering: Enable glitch filtering
on DOUT13
0: Disable glitch filtering on DOUT13
1: Enable glitch filtering on DOUT13
DE Processing Enable: Enable processing
separate HS and DE signals
0: Disable processing HS and DE signals
1: Enable processing HS and DE signals
0: Disable HS tracking
1: Enable HS tracking
HTRACK
HS Tracking Enable
0: Disable VS tracking
1: Enable VS tracking
VTRACK
VS Tracking Enable
0: GMSL default style PRBS test
1: MAX9272 style PRBS
PRBS_TYPE
PRBS Type Select: PRBS type select
Maxim Integrated
│ 42
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_10 (0x10)
BIT
7
6
5
RSVD
0b
4
3
2
1
0
RSVD
0b
Field
RSVD[7:6]
00b
RSVD[4:1]
0001b
Reset
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7:6
5
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
00: Reserved
0: Reserved
RSVD
RSVD
4:1
0
0001: Reserved
0: Reserved
RSVD
rsvd_11
BIT
7
6
5
4
3
2
RSVD[3:2]
00b
1
0
Field
RSVD[7:4]
1111b
RSVD[1:0]
Reset
00b
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7:4
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1111: Reserved
00: Reserved
00: Reserved
RSVD
3:2
RSVD
1:0
underbst (0x12)
BIT
7
6
5
4
3
2
1
0
UNDER-
BST_DET_
EN
DIS_
RWAKE
Field
RSVD
1b
RSVD[5:4]
RSVD
0b
RSVD
1b
RSVD
0b
Reset
0b
01b
0b
Access Type Write, Read Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0: Disable underboost detection driving
Underboost-Detection Enable: Allow under- ERROR pin
UNDERBST_DET_EN
7
boost detection driving ERRORB pin
1: Enable underboost detection driving
ERROR pin
1: Reserved
01: Reserved
0: Reserved
RSVD
RSVD
RSVD
6
5:4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Enable remote wake-up
1: Disable remote wake-up
DIS_RWAKE
2
Disable Remote Wake-up
RSVD
RSVD
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
0: Reserved
Maxim Integrated
│ 43
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_13 (0x13)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD
1b
RSVD
0b
RSVD[4:0]
01101b
Reset
Write 1 to
Set, Read
Access Type Write, Read Write, Read
Write, Read
BITFIELD
BITS
7
DESCRIPTION
DECODE
RSVD
RSVD
RSVD
RSVD
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
1: Reserved
0: Reserved
01101: Reserved
6
5
4:0
aeq (0x14)
BIT
7
AEQ_EN
1b
6
5
4
3
2
1
0
AEQ_PER_ AEQ_MAN_
MODE
Field
RSVD[4:0]
00000b
TRG_REQ
Reset
0b
0b
Write 1 to
Set, Read
Access Type Write, Read Write, Read
Write, Read
BITFIELD
AEQ_EN
BITS
DESCRIPTION
Adaptive Equalization Enable: Enable adap- 0: Disable AEQ
DECODE
7
tive equalization
1: Enable AEQ
Adaptive Equalization Periodic Mode
Select
0: Set AEQ to use nonperiodic mode
1: Set AEQ to use periodic mode
AEQ_PER_MODE
6
Adaptive Equalization Manual Fine-Tune
Request: Rising edge of this register triggers
AEQ fine tuning when not in periodic mode
0: Do not trigger AEQ fine tuning
1: Write 1 to this bit to manually trigger the
AEQ fine tuning
AEQ_MAN_TRG_REQ
5
RSVD
4:0
Reserved: Do not change from default value
00000: Reserved
det_err (0x15)
BIT
Field
7
6
5
4
3
2
1
0
DET_ERR[7:0]
Reset
XXXXXXXXb
Read Only
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
XXXXXXXX
DET_ERR
7:0
Detected Error Counter
11111111: Value is 255.
Maxim Integrated
│ 44
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
prbs_err (0x16)
BIT
7
6
5
4
3
2
1
0
Field
PRBS_ERR[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
00000000: Value is 0
00000001: Value is 1
XXXXXXXX
PRBS_ERR
7:0
PRBS Error Counter
11111111: Value is 255
lf (0x17)
BIT
7
6
5
4
3
2
1
0
Field
RSVD
Xb
RSVD
Xb
PRBS_OK
GPI_IN
Xb
LF_NEG[1:0]
LF_POS[1:0]
Reset
Xb
XXb
XXb
Read Clears
All
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved:
X: Reserved
X: Reserved
RSVD
PRBS OK: MAX9271/MAX9273-compatible PRBS
0: No MAX9271/MAX9273-compatible PRBS
test for link is terminated normally; check PRBS_ERR test completed
register for the PRBS success; for other SerDes read 1: MAX9271/MAX9273-compatible PRBS test
PRBS_OK
GPI_IN
5
4
PRBS_ERR registers
completed normally
0: GPI is input low
1: GPI is input high
GPI Pin Level
00: Short to battery detected
01: Short to ground detected
10: No faults detected
Line Fault: Line-fault status of the indicated input
LF_POS → LMN0
LF_NEG → LMN1
LF_NEG
3:2
11: Open cable detected
00: Short to battery detected
01: Short to ground detected
10: No faults detected
Line Fault: Line-fault status of the indicated input
LF_POS → LMN0
LF_NEG → LMN1
LF_POS
1:0
11: Open cable detected
Maxim Integrated
│ 45
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_18 (0x18)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
XXXXXXXX: Reserved
RSVD
Reserved: Do not change from default value
rsvd_19 (0x19)
BIT
7
7
7
6
5
4
3
3
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:0
Reserved
XXXXXXXX: Reserved
rsvd_1a (0x1A)
BIT
6
5
4
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
XXXXXXXX: Reserved
RSVD
7:0
Reserved
i2csel (0x1B)
BIT
6
5
4
2
1
0
Field
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
I2CSEL
Xb
RSVD
Xb
RSVD
Xb
RSVD
Xb
Reset
Read Clears
All
Access Type Write, Read Write, Read Write, Read Write, Read
Read Only
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
RSVD
RSVD
0: Reserved
0: Reserved
0: Reserved
0: Low-I2CSEL pin detected (UART)
1: High-I2CSEL pin detected (I2C)
I2CSEL
3
I2CSEL Pin Level: Detected I2CSEL pin level
RSVD
RSVD
RSVD
2
1
0
Reserved:
X: Reserved
X: Reserved
X: Reserved
Reserved: Do not change from default value
Reserved: Do not change from default value
Maxim Integrated
│ 46
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_1c (0x1C)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD[5:0]
XXXXXXb
Read Only
Reset
Access Type Write, Read Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved:
0: Reserved
0: Reserved
RSVD
RSVD
6
5:0
XXXXXX: Reserved
aeq_bst (0x1D)
BIT
7
6
5
4
3
2
1
0
UNDER-
BOOST_
DET
Field
RSVD
0b
RSVD
0b
RSVD
0b
AEQ_BST[3:0]
Reset
Xb
XXXXb
Access Type Write, Read Write, Read Write, Read
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
RSVD
RSVD
7
6
5
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
Underboost Detected: '1' indicates that an
underboost is detected when the AEQ is at the
maximum setting
0: Normal operation
1: Underboost (at maximum AEQ gain)
detected
UNDERBOOST_DET
4
0000: 1.6dB EQ setting
0001: 2.1dB EQ setting
0010: 2.8dB EQ setting
0011: 3.5dB EQ setting
0100: 4.3dB EQ setting
0101: 5.2dB EQ setting
0110: 6.3dB EQ setting
0111: 7.3dB EQ setting
1000: 8.5dB EQ setting
1001: 9.7dB EQ setting
1010: 11dB EQ setting
1011: 12.2dB EQ setting
11XX: Reserved
Adaptive Equalizer Boost Value: Selected
adaptive equalizer value; settings correspond to
gain at 750MHz
AEQ_BST
3:0
id (0x1E)
BIT
7
6
5
4
3
2
1
0
Field
ID[7:0]
Reset
XXXXXXXXb
Read Only
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
Device ID: 8-bit value depends on the GMSL
device attached
ID
7:0
01001100: MAX96708
Maxim Integrated
│ 47
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
revision (0x1F)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
HDCPCAP
Xb
REVISION[3:0]
Reset
XXXXb
Access Type Write, Read Write, Read Write, Read
Read Only
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
0: Device does not have HDCP
1: Device is HDCP capable
HDCPCAP
4
HDCP Capability: '1' = HDCP capable
0000: Value is 0
0001: Value is 1
1111: Value is 15
REVISION
3:0
Device Revision
rsvd (0x20 to 0x23)
BIT
Field
7
6
5
4
3
2
1
0
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:0
Reserved:
XXXXXXXX: Reserved
crossbar (0x65 to 0x6B)
BIT
Field
7
6
5
4
3
2
1
0
CROSSBAR_N[3:0]
CROSSBAR_N+1[3:0]
XXXXb
Reset
XXXXb
Access Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Crossbar Setting: CROSSBAR selects the internal
signal to connect to the output pin, DOUT_.
Register crossbar_(N) contains settings for two
outputs, with CROSSBAR_(N) at D[7:4] and
CROSSBAR_(N+1) at D[3:0]. Default settings for
CROSSBAR(N) connects internal signal D(N) to
its respective DOUT(N) pin.
0000: Connect D0 to output
0001: Connect D1 to output
:: :
1101: Connect D13 to output
1110: Force output low
1111: Force output high
CROSSBAR_N
7:4
Crossbar Setting: CROSSBAR selects the internal
signal to connect to the output pin, DOUT_.
Register crossbar_(N) contains settings for two
outputs, with CROSSBAR_(N) at D[7:4] and
CROSSBAR_(N+1) at D[3:0]. Default settings for
CROSSBAR(N) connects internal signal D(N) to its
respective DOUT(N) pin.
0000: Connect D0 to output
0001: Connect D1 to output
:: :
1101: Connect D13 to output
1110: Force output low
1111: Force output high
CROSSBAR_N+1
3:0
Maxim Integrated
│ 48
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_96 (0x96)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[1:0]
01b
RSVD[1:0]
01b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
1b
Reset
Access Type
Write, Read
Write, Read
Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
01: Reserved
7:6
5:4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
RSVD
01: Reserved
RSVD
0: Reserved
RSVD
2
0: Reserved
RSVD
1
0: Reserved
RSVD
0
1: Reserved
rev_fast (0x97)
BIT
7
6
5
4
3
2
1
0
Field
REV_FAST
0b
RSVD
0b
RSVD[5:0]
100010b
Reset
Access Type Write, Read Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
REV_
FAST
0: Disable reverse-channel fast mode
1: Enable reverse-channel fast mode
7
Reverse-Channel Fast Mode
RSVD
RSVD
6
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
5:0
100010: Reserved
rsvd_98 (0x98)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD
0b
RSVD[5:0]
011010b
Reset
Access Type Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
0: Reserved
RSVD
6
RSVD
5:0
011010: Reserved
Maxim Integrated
│ 49
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_99 (0x99)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
1b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
1: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
rsvd_9a (0x9A)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[1:0]
10b
RSVD[2:0]
010b
Reset
Access Type Write, Read Write, Read
Write, Read
Write, Read
DECODE
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
6
0: Reserved
10: Reserved
010: Reserved
0: Reserved
RSVD
5:4
3:1
0
RSVD
RSVD
Maxim Integrated
│ 50
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_9b (0x9B)
BIT
Field
7
6
5
4
3
2
1
0
0
0
RSVD
0b
RSVD[1:0]
01b
RSVD[2:0]
001b
RSVD[1:0]
10b
Reset
Access Type Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
6:5
4:2
1:0
01: Reserved
001: Reserved
10: Reserved
RSVD
RSVD
rsvd_9c (0x9C)
BIT
Field
7
6
5
4
RSVD
1b
3
2
1
RSVD
0b
RSVD[1:0]
10b
RSVD[3:0]
0100b
Reset
Access Type Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
10: Reserved
1: Reserved
RSVD
6:5
4
RSVD
RSVD
3:0
0100: Reserved
rsvd_9d (0x9D)
BIT
Field
7
6
5
4
3
SOFT_PD
0b
2
1
RSVD
0b
RSVD
0b
RSVD
1b
RSVD
01b
RSVD
0b
RSVD
0b
RSVD
0b
Reset
Write 1 to
Set, Read
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read Write, Read Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
RSVD
0: Reserved
1: Reserved
01: Reserved
RSVD
RSVD
0: Normal operation
1: Reset the device
SOFT_PD
3
Reserved: Do not change from default value
RSVD
RSVD
RSVD
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
Maxim Integrated
│ 51
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_9e (0x9E)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD[1:0]
10b
RSVD[2:0]
010b
RSVD
0b
RSVD
0b
Reset
Access Type Write, Read
Write, Read
Write, Read
Write, Read Write, Read
DECODE
BITFIELD
RSVD
BITS
7
DESCRIPTION
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
RSVD
6:5
4:2
1
10: Reserved
010: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
RSVD
0
rsvd_9f (0x9F)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
HPFTUNE[1:0]
01b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
RSVD
RSVD
00: 7.5MHz cutoff frequency
01: 3.75MHz cutoff frequency
10: 2.5MHz cutoff frequency
11: 1.87MHz cutoff frequency
HPFTUNE
2:1
Equalizer High-Pass Filter Cutoff Frequency
RSVD
0
Reserved: Do not change from default value
0: Reserved
rsvd_a0 (0xA0)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
1b
RSVD
0b
RSVD[1:0]
10b
RSVD[3:0]
1110b
Reset
Access Type Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1: Reserved
0: Reserved
10: Reserved
RSVD
6
RSVD
5:4
3:0
RSVD
1110: Reserved
Maxim Integrated
│ 52
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_a1(0xA1)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[2:0]
010b
RSVD[4:0]
00100b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:5
4:0
Reserved: Do not change from default value
Reserved: Do not change from default value
010: Reserved
RSVD
00100: Reserved
rsvd_a2 (0xA2)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
00100000b
Write, Read
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
00100000: Reserved
RSVD
Reserved: Do not change from default value
rsvd_a3 (0xA3)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
0110b
RSVD[3:0]
1011b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:4
3:0
Reserved: Do not change from default value
Reserved: Do not change from default value
0110: Reserved
1011: Reserved
RSVD
rsvd_a4 (0xA4)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[2:0]
101b
RSVD
1b
RSVD
0b
RSVD
1b
RSVD[1:0]
01b
Reset
Access Type
Write, Read
Write, Read Write, Read Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:5
4
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
101: Reserved
1: Reserved
0: Reserved
1: Reserved
01: Reserved
RSVD
RSVD
3
RSVD
2
RSVD
1:0
Maxim Integrated
│ 53
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_a5 (0xA5)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
1100b
RSVD[1:0]
11b
RSVD[1:0]
01b
Reset
Access Type
Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7:4
3:2
1:0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
1100: Reserved
11: Reserved
01: Reserved
RSVD
RSVD
rsvd_a6 (0xA6)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[1:0]
00b
RSVD[1:0]
01b
Reset
Access Type Write, Read Write, Read Write, Read Write, Read
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
00: Reserved
01: Reserved
RSVD
6
RSVD
5
RSVD
4
RSVD
3:2
1:0
RSVD
rsvd_c9 (0xC9)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
XXXXXXXXb
Read Only
Reset
Access Type
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
XXXXXXXX: Reserved
RSVD
Reserved: Do not change from default value
Maxim Integrated
│ 54
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_ca (0xCA)
BIT
Field
7
6
RSVD
Xb
5
RSVD
Xb
4
3
2
RSVD
Xb
1
RSVD
Xb
0
RSVD
Xb
RSVD
0b
RSVD[1:0]
XXb
Reset
Access Type Write, Read
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
X: Reserved
X: Reserved
XX: Reserved
X: Reserved
X: Reserved
X: Reserved
5
4:3
2
1
0
rsvd_cb (0xCB)
BIT
Field
7
6
RSVD
Xb
5
RSVD
Xb
4
RSVD
Xb
3
2
1
RSVD
Xb
0
RSVD
0b
RSVD
Xb
RSVD
Xb
RSVD
Xb
Reset
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Write, Read
BITFIELD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BITS
DESCRIPTION
DECODE
7
6
5
4
3
2
1
0
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved:
X: Reserved
X: Reserved
X: Reserved
X: Reserved
X: Reserved
X: Reserved
X: Reserved
0: Reserved
Reserved:
Reserved:
Reserved: Do not change from default value
rsvd_cc (0xCC)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD[6:0]
Reset
XXXXXXXb
Read Only
Access Type Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
XXXXXXX: Reserved
RSVD
6:0
Maxim Integrated
│ 55
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
rsvd_cd (0xCD)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD[6:0]
XXXXXXXb
Read Only
Reset
Access Type Write, Read
BITFIELD
RSVD
BITS
7
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
XXXXXXX: Reserved
RSVD
6:0
rsvd_fd (0xFD)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[7:0]
0b
Reset
Access Type
Write, Read
BITFIELD
BITS
7:0
DESCRIPTION
DECODE
RSVD
Reserved: Do not change from default value
0: Reserved
rsvd_fe (0xFE)
BIT
7
6
5
4
3
2
1
0
Field
RSVD[3:0]
0b
RSVD[3:0]
0b
Reset
Access Type
Write, Read
Write, Read
BITFIELD
RSVD
BITS
7:4
DESCRIPTION
DECODE
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
RSVD
3:0
rsvd_ff (0xFF)
BIT
Field
7
6
5
4
3
2
1
0
RSVD
0b
RSVD
0b
RSVD
0b
RSVD
0b
RSVD[3:0]
XXXXb
Reset
Access Type Write, Read Write, Read Write, Read Write, Read
Read Only
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
Reserved: Do not change from default value
0: Reserved
0: Reserved
0: Reserved
0: Reserved
RSVD
RSVD
5
RSVD
4
RSVD
3:0
XXXX: Reserved
Maxim Integrated
│ 56
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Bus Data Rates
Applications Information
The bus data rate depends on the settings BWS and
DBL. Table 4 lists the available PCLK rates available for
different bus-width settings. For lower PCLK rates, set
DBL = 0 (if DBL = 1 in both the serializer and deserializer).
Parallel Interface
The CMOS parallel-interface data width is programmable
and depends on the application. Using a larger width
(BWS = 1) results in a lower-pixel clock rate, while a
smaller width (BWS = 0) allows a higher-pixel clock rate.
Crossbar Switch
By default, the crossbar switch connects the serializer
input pins DIN_ and HS/VS (when HV encoding is used)
to the corresponding deserializer output pins DOUT_ and
HS/VS when DBL of the serializer and deserializer match.
When there is a DBL mismatch use Table 5, Table 66,
and Table 7 to map the serial bits to the crossbar inputs.
Reprogram the crossbar switch when changing the output
pin assignments.
Bus Data Width
The bus data width depends on the selected modes. The
available bus width is less when using error detection or
when in double mode (DBL = 1). Table 3 shows the avail-
able bit widths and default mapping for various modes.
Table 3. Output-Data Width Selection
Crossbar Switch Programming
REGISTER BIT SETTINGS
Each output pin can be assigned any of the 14 DOUT
signals. Multiple outputs can share the same input. To force
an output low, and ignore the input, set CROSSBAR_ bit
= 1110. To force an output high set CROSSBAR_ = 1111.
OUTPUT MAPPING
PXL_
CRC
DBL
BWS
HVEN
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DOUT11:0, HS, VS
DOUT11:0
Recommended Crossbar Switch Programming
Procedure
DOUT11:0*, HS, VS
DOUT13:0*
The following procedure programs the crossbar switch to
reassign input/output pin locations:
DOUT7:0, HS, VS
DOUT7:0
1) For the crossbar output equivalent of DOUT0 (XBO0)
DOUT10:0, HS, VS
DOUT10:0
select which pin to map (e.g., DOUT4 → XBI4).
2) Set the crossbar bits (CROSSBAR0) to the desired
selected mapped input (e.g., CROSSBAR0 = 0100).
DOUT11:0*, HS, VS
DOUT13:0*
3) Repeat for the other crossbar outputs.
DOUT11:0*, HS, VS
DOUT13:0*
Table 4. Data-Rate Selection Table
DRS
0
DBL
1
BWS
PCLK RANGE (MHZ)
25 to 87
DOUT11:0*, HS, VS
DOUT13:0*
1
0
1
0
1
0
0
1
33.3 to 116
12.5 to 43.5
16.7 to 58
DOUT11:0*, HS, VS
DOUT13:0*
0
0
0
0
*The bit width is limited by the number of available outputs.
1*
1*
0
6.25 to 12.5
8.33 to 16.7
0
*Use DRS = 1 with legacy devices only (MAX92XX).
Maxim Integrated
│ 57
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 5. Output Map (DBL = 0 or DBL = 1, First Word)
BIT SETTING
OUTPUT BITS (FIRST WORD)
A9 A10 A11 A12 A13
DB
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
HV BW CR
DE SC* A0
A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
A4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
A5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
A6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
A7
7
7
7
7
7
7
7
7
7
7
7
7
7
Z
7
7
7
7
A8
8
8
8
8
8
8
8
Z
8
8
8
8
Z
Z
8
8
8
8
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
0
0
1
1
0
0
0
0
1
1
1
1
X
X
X
X
X
X
0
1
0
1
0
0
1
1
0
0
0
1
0
1
X
1
1
0
X
X
X
X
0
1
0
1
1
1
0
X
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
9
9
9
9
9
9
9
Z
9
9
9
9
Z
Z
9
9
9
9
10
10
10
10
10
10
10
Z
11
13
11
13
11
11
Z
14
14
12
H
15
15
13
V
2
1
2
H
V
1,2
3
H
V
Z
Z
3
Z
Z
Z
3
10
10
10
Z
11
11
Z
12
Z
13
Z
3
1,2
1,2
1,2
1,2
1
HL
HL
HL
HL
HL
HL
HL
HL
VL
VL
VL
VL
VL
VL
VL
VL
10
Z
Z
Z
7
10
10
10
10
13
11
11
11
2
1,2
1,2
Maxim Integrated
│ 58
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 6. Output Map (DBL = 1, Second Word)
BIT SETTING
OUTPUT BITS (SECOND WORD)
DB
1
HV BW CR
DE SC* B0
B1
12
9
B2
13
10
17
14
13
13
10
10
17
17
17
14
B3
14
11
18
15
14
14
11
11
18
18
18
15
B4
15
12
19
16
15
15
12
12
19
19
19
16
B5
16
13
20
17
16
16
13
13
20
20
20
17
B6
17
14
21
18
17
17
14
14
21
21
21
18
B7
18
15
22
19
18
18
15
Z
B8
19
Z
B9 B10 B11 B12 B13
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
0
1
X
X
X
X
0
1
0
1
1
1
0
X
3
3
11
8
20
Z
21
Z
Z
Z
Z
1
Z
Z
Z
1
3
15
12
11
11
8
16
13
12
12
9
23
20
19
19
Z
24
21
20
20
Z
25
22
21
Z
26
23
Z
27
28
Z
1
3
Z
1
1,2
1,2
1,2
1,2
1
HH
HH
HH
HH
HH
HH
HH
HH
VH
VH
VH
VH
VH
VH
VH
VH
1
21
Z
1
Z
1
8
9
Z
Z
Z
15
28
26
26
23
1
15
15
15
12
16
16
16
13
22
22
22
19
23
23
23
20
24
24
24
21
25
25
25
22
1
2
1
1,2
1,2
1
Table 7. Legend
BIT SETTINGS
MAPPED SYNC OUTPUTS
DB
HV
BW
—
Double mode bit DBL
H
HSYNC ( when DBL = 0)
VSYNC ( when DBL = 0)
DE ( when DBL = 0)
H/V Encoding bit HVEN
BWS bit
V
D
—
HH
VH
DH
HL
VL
DL
#
HSYNC (high word, DBL = 1)
VSYNC (high word, DBL = 1)
DE (high word, DBL = 1)
HSYNC (low word, DBL = 1)
VSYNC (low word, DBL = 1)
DE (low word, DBL = 1)
Serial Bits
CR
DE
SC*
X
PXL_CRC bit
DEEN
HV_SRC (dec)
1 or 0
BIT COLOR
Sync Bits
Output on first word
Output on second word
Zero
Z
Zero
*HV_SRC is automatically set by default. MAX96705 mode automatically sets HV_SRC to 0, 1, or 3 according to the other bit set-
tings above. MAX96707 mode automatically sets HV_SRC to 0, 2, or 3 according to the other bit settings above.
Maxim Integrated
│ 59
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
2
I C Address Translation
Control-Channel Interfaces
2
I C
2
The device supports I C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
Set I2CSEL = 1 to configure the control channel for
2
2
I C-to-I C mode. In this mode, the control channel
2
I C addresses. Source addresses (address to translate
2
forwards I C commands from the microcontroller side
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
to the other side of the GMSL link. The remote device
2
acts as an I C master to the other peripherals connected
2
2
to the remote side device. I C-to-I C mode uses clock
stretching to hold the microcontroller until the data and
the acknowledge/no-acknowledge have been sent across
the link.
Configuration Blocking
The device can block changes to its registers. Set
CFGBLOCK to make all registers read only. Once set, the
registers remain blocked until the supplies are removed or
until PWDNB is low.
2
I C Bit Rate
2
The I C interface accepts bit rates from 9.6kbps to 1Mbps.
2
The local I C rate is set by the microcontroller. The remote
Cascaded/Parallel Devices
2
I C rate is set by the remote device. By default the control
GMSL supports cascaded and parallel devices connected
through I C. When cascading or using parallel links,
all I C commands are forwarded to all links. Each link
attempts to hold the control channel until it receives an
acknowledge/non-acknowledge from the remote side
device. It is important to keep the control channel active
between links in order to prevent timeout. If a link is
unused, keep the control channel clear by turning on the
2
channel is set up for a 400kbps-to-I C bit rate. Program the
2
I2C_MSTBT and SLV_SH bits (register 0x0D) to match the
2
2
desired microcontroller I C rate.
Software Programming of the Device Addresses
The serializer and deserializer have programmable device
addresses. This allows multiple GMSL devices, along with
2
I C peripherals, to coexist on the same control channel.
2
configuration link, disconnecting the I C lines, or power-
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
write to the device whose address changes (register 0x00
of the serializer for serializer device address change, or
register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
ing down the unused device.
Dual μC Control
Most systems use a single microcontroller; however, µCs
can reside on each side simultaneously and trade off
running the control channel. Contention occurs if both µCs
attempt to use the control channel at the same time. It is
up to the user to prevent this contention by implementing
a higher-level protocol. In addition, the control channel
2
does not provide arbitration between I C masters on both
sides of the link. An acknowledge frame is not generated
when communication fails due to contention. If communi-
cation across the serial link is not required, the µCs can
disable the forward and reverse control channel using
the FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the
serializer/deserializer. Communication across the serial link
is stopped and contention between µCs cannot occur.
Maxim Integrated
│ 60
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
UART
UART Timing
Set I2CSEL = 0 to configure the control channel for UART
or UART to I C. In this mode, the control channel for-
wards UART commands from the microcontroller side to
In base mode, the UART idles high (through a pullup
resistor). Each GMSL-UART byte consists of a START
bit, 8 data bits, an even-parity bit and a stop bit (Figure
19). Keep the idle time between bytes of the same UART
packet to less than 4 bit times. The GMSL-UART protocol
is listed in Figure 20. A write packet consists of a SYNC
byte (Figure 21). Device address byte, Starting register
address byte, number of bytes to write, and the data
bytes. The slave device responds with an acknowledge
byte (Figure 22) if the write was successful. A Read pack-
et consists of a SYNC byte, Device address byte, Starting
register address byte, and number of bytes to read. The
slave device responds with an acknowledge byte and the
read data bytes.
2
the other side of the GMSL link. When INTTYPE = 00, the
2
remote device acts as an I C master to the other periph-
2
erals connected to the remote side device. UART-to-I C
mode does not support devices that use clock stretching.
Base Mode
In base mode, UART packets control the serializer, dese-
rializer and attached peripherals.
1 UART FRAME
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY*
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
*BASE MODE USES EVEN PARITY
Figure 19. GMSL-UART Data Format for Base Mode
WRITE DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1
SYNC
SYNC
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 20. GMSL-UART Protocol for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
PARITY STOP
START
PARITY STOP
Figure 21. SYNC Byte (0x79)
Figure 22. ACK Byte (0xC3)
Maxim Integrated
│ 61
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
2
There are two possible methods the devices use to
UART-to-I C Conversion
2
convert UART to I C. In the first method, I2CMETHOD =
When using the UART control channel, the remote-side
2
0. The register address is sent with the I C communica-
2
device can communicate to I C peripherals through
tion (Figure 23). For devices that do not use a register
address (such as the MAX7324) set I2CMETHOD = 1
and send a dummy byte in place of the register address
(Figure 24). In this method, the remote device omits send-
ing the register address.
2
UART-to-I C conversion. Set the INTTYPE bits in the
2
remote side device to "00" to activate UART-to-I C
conversion. The converted I C bit rate is the same as
the incoming UART bit rate. I C peripherals must not use
clock stretching in order to be compatible with UART-
2
2
2
to-I C conversion.
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
Figure 23. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0)
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
11
11
11
DATA 0
11
DATA N
11
ACK FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
MASTER TO SLAVE
SLAVE TO MASTER
S: START
P: STOP A: ACKNOWLEDGE
2
Figure 24. Format Conversion Between GMSL UART and I C without Register Address (I2CMETHOD = 1)
Maxim Integrated
│ 62
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 8. Default-Device Address
D7
D6
D5
D4
D3
D2
D1
D0
1
ADD3
ADD2
1
ADD1
ADD0
0
R/W
Note: ADD[3:0] pin settings latched at power-up.
UART Bypass Mode
Table 9. Cable-Equalizer Boost Levels
In UART bypass mode, the control channel acts as a
full-duplex 9.6kbps to 1Mbps link that forwards UART
commands across the serial link without responding to
the packets themselves. Set MS high to enter bypass
mode (wait 1ms after setting bypass mode if the μC is
connected on the deserializer side). Bypass uses bit rates
from 9.6kbps to 1Mbps. Do not send a logic-low value
longer than 100μs when using the GPI/GPO functionality.
BOOST SETTING
TYPICAL BOOST GAIN AT
(MANUAL AND ADAPTIVE
750MHZ (DB)
EQ)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1.6
2.1
2.8
3.5
4.3
5.2
6.3
7.3
8.5
Device Address
The SerDes have a 7-bit-long slave address stored in
registers 0x00 and 0x01. The bit following a 7-bit slave
address is the R/W bit, which is low for a write command
and high for a read command. External inputs determine
the default slave address as shown in Table 8. After
startup, a μC can reprogram the slave address as needed.
9.7
1001
Power-up default for
Manual EQ*
Cable Equalizer
1010
1011
11.0
12.2
By default, the cable equalizer is enabled and set to
Adaptive mode. Set AEQ_EN = 0 to switch to manual EQ
mode. EQTUNE determines the boost level in manual EQ
mode (see Table 9). Set EN_EQ = 0 to disable all equal-
ization (manual or automatic).
*Automatic EQ is enabled by default.
The auto-equalization level is determined during serial-
link locking. Set AEQ_MAN_TRG_REQ = 1 to re-trigger
auto equalization. Set AEQ_PER_MODE = 1 to set up
periodic AEQ.
Additional conditions that set ERRB (disabled by default)
include:
● Insufficient boost at maximum boost setting
(set UNDERBST_DET_EN = 1). Retrigger the
equalization calibration to clear.
ERRB Output
The deserializer has an open-drain ERRB output. This
output asserts low whenever any of the following condi-
tions occur:
Auto-Error Reset
The default method to reset errors is to read the respective
error counter registers in the deserializer. Auto-error reset
clears the error counters DET_ERR ~1μs after ERR goes
low. Auto-error reset is disabled on power-up. Enable
auto-error reset through ERR_RST. Auto-error reset does
not run when the device is in PRBS test mode.
● The number of detected errors exceeds the error
thresholds during normal operation. Read DET_ERR,
set auto-error reset, or re-lock the link to clear.
Maxim Integrated
│ 63
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Board Layout
R
D
1.5kΩ
Power-Supply Circuits and Bypassing
1MΩ
The deserializer uses an AVDD and DVDD of 1.7V to
1.9V. All inputs and outputs, except for the serial input,
derive power from an IOVDD of 1.7V to 3.6V that scales
with IOVDD. Proper voltage-supply bypassing is essential
for high-frequency circuit stability.
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
S
STORAGE
CAPACITOR
SOURCE
High-Frequency Signals
Separate the LVCMOS logic signals and CML/coax
high-speed signals to prevent crosstalk. Use a four-layer
PCB with separate layers for power, ground, CML/coax,
and LVCMOS logic signals. Layout STP PCB traces
close to each other for a 100Ω differential characteristic
impedance. The trace dimensions depend on the type
of trace used (microstrip or stripline). Note that two 50Ω
PCB traces do not have 100Ω differential impedance
when brought close together—the impedance goes down
when the traces are brought closer. Use a 50Ω trace for
the single-ended output when driving coax. Route the
PCB traces for differential CML in parallel to maintain the
differential characteristic impedance. Avoid vias. Keep
PCB traces that make up a differential pair equal in length
to avoid skew within the differential pair.
Figure 25. Human Body Model ESD Test Circuit
R
D
330Ω
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
150pF
SOURCE
ESD Protection
Figure 26. IEC 61000-4-2 Contact Discharge ESD Test Circuit
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human
Body Model discharge components are CS = 100pF and
RD = 1.5kΩ (Figure 25). The IEC 61000-4-2 discharge
components are CS = 150pF and RD = 330Ω (Figure 26).
The ISO 10605 discharge components are CS = 330pF
and RD = 2kΩ (Figure 27).
R
2kΩ
D
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 27. ISO 10605 Contact Discharge ESD Test Circuit
Maxim Integrated
│ 64
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 10. Feature Compatibility
DESERIALIZER FEATURE
GMSL SERIALIZER
HSYNC/VSYNC encoding
If feature not supported in the serializer, turn off in the deserializer.
If feature not supported in the serializer, use UART-to-I2C or UART-to-UART.
If feature not supported in the serializer, turn off in the deserializer.
2
2
I C-to-I C
CRC error detection
If feature not supported in the serializer, data is output as a single word at half the input
frequency. Use Crossbar switch to correct input mapping.
Double input
Coax
If feature not supported in the serializer, connect unused serial input through 200nF
and 50Ω in series to AVDD, and set the reverse control-channel amplitude to 100mV.
2
2
I S encoding
If supported in the serializer, disable I S in the serializer
High-immunity mode
If feature not supported in the serializer, turn off in the deserializer.
300ns. The waveforms are not recognized if the transition
time becomes too slow. GMSL supports I C/UART rates
Compatibility with Other GMSL Devices
2
The MAX96708 is designed to pair with the MAX96705−
MAX96711 family of SerDes devices, but interoperates
with any GMSL device. See Table 10 for operating limita-
tions.
2
2
up to 1Mbps (UART-to-I C mode) and 400kbps (I C-to-
I C mode).
2
AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start from
different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
Device Configuration and Component Selection
Internal Input Pulldowns
The control and configuration inputs include a pulldown
resistor to GND. External pulldown resistors are not needed.
Multifunction Inputs
The device has several inputs/outputs that function both
as a parallel input/output and as a configuration pin. On
power-up, or when reverting from a power-down state,
the pins act as configuration inputs. After latching the
input state, the configuration inputs become parallel
digital input/outputs. Connect a configuration input through
a 30kΩ resistor to IOVDD to set a high level. Leave the
configuration input open to set a low level.
(R ), the CML/coax driver termination resistor (R ),
TR
TD
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(R
TD
+ R ))/4. R
and R
are required to match the
TR
TD
TR
transmission line impedance (usually 100Ω differential,
50Ω single-ended). This leaves the capacitor selection to
change the system time constant. Use 0.22μF or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower-speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
2
I C/UART Pullup Resistors
2
The I C and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compromise
may be required when choosing pullup resistor values.
Every device connected to the bus introduces some
Cables and Connectors
2
capacitance even when the device is not in operation. I C
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω (contact the factory for 75Ω operation).
Table 11 lists the suggested cables and connectors used
in the GMSL link.
specifies 300ns rise times (30% to 70%) for fast mode,
which is defined for data rates up to 400kbps. See the
2
2
I C specifications in the I C/UART Port Timing section in
the AC Electrical Characteristics table for details. To meet
the fast-mode rise-time requirement, choose the pullup
resistors so that rise time t = 0.85 x R
x C
<
R
PULLUP
BUS
Maxim Integrated
│ 65
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Table 11. Suggested Connectors and Cables for GMSL
VENDOR
CONNECTOR
59S2AX-400A5-Y
D4S10A-40ML5-Z
GT11L-2S
CABLE
TYPE
Coax
STP
Rosenberger
Dacar 302
Dacar 535-2
Rosenberger
Nissei
F-2WME AWG28
A-BW-Lxxxxx
STP
JAE
MX38-FF
STP
normal interrupts. Reverse control-channel communica-
tion does not require an active forward link to operate
and accurately tracks the LOCK status of the GMSL link.
LOCK asserts for video link only and not for the configura-
tion link.
PRBS
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To
run the PRBS test, set PRBSEN = 1 (0x04, D5) in the
deserializer, then in the serializer. To exit the PRBS
test, set PRBSEN = 0 (0x04, D5) in the serializer. The
deserializerautomaticallyendsPRBScheckingandsetsthe
PRBS_OK bit high. Note that during PRBS mode, the
remote control channel is not available except to exit
PRBS mode if I2C_LOC_ACK = 1; otherwise, the remote
control channel is not available at all.
Providing a Frame Sync (Camera Applications)
The GPI and GPO provide a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input and connect the GPO
output to the camera-frame sync input. GPI/GPO have
a typical delay of 275μs. Skew between multiple GPI/
GPO channels is 115μs (max). If a lower-skew signal is
required, connect the camera’s frame-sync input to one
To run the PRBS with a 3Gbps SerDes, first set the
PRBS_TYPE bit = 0 in the MAX967XX. Then set PRBSEN
= 1 (0x04, D5) in the serializer, then in the deserializer. To
exit the PRBS test, set PRBSEN = 0 (0x04, D5) in the
deserializer, then in the serializer.
2
of the serializer’s GPIOs and use an I C broadcast write
command to change the GPIO output state. This has a
2
maximum skew of 1.5µs, independent from the used I C
During PRBS test, ERRB function changes to reflect
PRBS errors only. ERRB goes low when any PRBS errors
occur. ERRB goes high when the PRBS error counter is
reset when PRBS_ERR is read. Normal ERRB function
resumes when exiting the PRBS test.
bit rate.
Entering/Exiting Sleep Mode
The procedure for entering and exiting sleep mode depends
on the location of the microcontroller, and the type of
control-channel interface used. If wake-up from a remote-
side (serializer-side) microcontroller is not needed or
desired, set the DIS_RWAKE bit = 1 to shut down remote
wake-up for further power savings.
GPI/GPO
GPO on the serializer follows GPI transitions on the
deserializer. By default, the GPI-to-GPO delay is 0.35ms
(max). Keep the time between GPI transitions to a
minimum 0.35ms. GPI_IN the deserializer stores the GPI
input state. GPO is low after power-up. The µC can set
GPO by writing to the SET_GPO register bit. Do not send
a logic-low value on the deserializer RX/SDA input (UART
mode) longer than 100µs in either base or bypass mode
to ensure proper GPO/GPI functionality.
When the microcontroller is on the deserializer side, first
put the serializer to sleep, or disable serialization. Next, set
SLEEP = 1 in deserializer. The device sleeps after 8ms.
To wake up the device, send an arbitrary control-channel
command to the deserializer (the device will not send an
acknowledge), wait for 5ms for the chip to power up and
then set SLEEP = 0 to make the wake-up permanent.
Fast Detection of Loss-of-Lock
When µC is on the serializer side, set SLEEP = 1 in
deserializer. Next, disable serialization. The device sleeps
after 8ms. To wake up the deserializer, reenable serializa-
tion. The deserializer wakes up and clears its SLEEP bit
when it locks to the serializer.
A measure of link quality is the recovery time from loss of
synchronization. The host can be quickly notified of loss-
of-lock by connecting the deserializer’s LOCK output to
the GPI input. If other sources use the GPI input, such as
a touch-screen controller, the μC can implement a routine
to distinguish between interrupts from loss-of-sync and
Maxim Integrated
│ 66
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Typical Application Circuit
PCLKOUT
DOUT[11:0]
DOUT12/HS
PCLK
DIN[11:0]
PCLK
DIN[11:0]
PCLKIN
DIN[11:0]
HS
VS
DIN12/HS
DIN13/VS
HS
VS
DOUT13/VS
CAMERA
MAX96709
MAX96708
GPU
45.3kΩ
4.99kΩ
SDA
SCL
SDA
SCL
49.9Ω
LMN0
RX/SDA
TX/SCL
SDA
SCL
2
OUT-
I C
OUT+
IN+
IN-
GPI
FSYNC
49.9kΩ
LOCK
LOCK
49.9Ω
ERRB
LFLTB
ERR
LFLT
ECU
I2CSEL = 1, CX/TP = 1
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
CAMERA APPLICATION
Ordering Information
PART NUMBER
TEMP RANGE
PIN-PACKAGE
MAX96708GTJ+
-40°C to +115°C 32 TQFN-EP*
-40°C to +115°C 32 TQFN-EP*
-40°C to +115°C 32 TQFN-EP*
-40°C to +115°C 32 TQFN-EP*
MAX96708GTJ+T
MAX96708GTJ/V+
MAX96708GTJ/V+T
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Maxim Integrated
│ 67
www.maximintegrated.com
MAX96708
14-Bit GMSL Deserializer
with Coax or STP Cable Input
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
3/16
Initial release
—
7, 29, 33, 38,
1
3/17
Various updates, beginning with Absolute Maximum Ratings
40, 62, 63, 65,
66
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 68
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明