MAX9742 [MAXIM]
Single-/Dual-Supply, Stereo 16W, Class D Amplifier with Differential Inputs; 单/双电源供电，立体声，16W ， D类放大器，差分输入
| 型号： | MAX9742 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-/Dual-Supply, Stereo 16W, Class D Amplifier with Differential Inputs |
| 文件： | 总36页 (文件大小：766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0731; Rev 0; 1/07
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
General Description
Features
ꢀ 2 x 16W Output Power (R = 4Ω, THD+N = 10%)
The MAX9742 stereo Class D audio power amplifier
delivers up to 2 x 16W into 4Ω loads. The MAX9742
features high-power efficiency (92% with 8Ω loads),
eliminating the need for a bulky heatsink and conserv-
ing power. The MAX9742 operates from a 20V to 40V
single supply or a 10V to 20V dual supply. ꢀeatures
include fully differential inputs, comprehensive click-
and-pop suppression, low-power shutdown mode, and
an externally adjustable gain. Short-circuit and thermal-
overload protection prevent the device from being
damaged during a fault condition.
L
ꢀ High Efficiency: Up to 92% with R = 8Ω
L
ꢀ Mute and Shutdown Modes
ꢀ Differential Inputs Suppress Common-Mode Noise
ꢀ Adjustable Gain
ꢀ Integrated Click-and-Pop Suppression
ꢀ Low 0.06% THD+N at 3.5W, R = 8Ω
L
ꢀ Output Short-Circuit and Thermal Protection
ꢀ Available in Space-Saving, 6mm x 6mm, 36-Pin
TQFN Package
The MAX9742 is available in a thermally efficient 36-pin
TQꢀN (6mm x 6mm x 0.8mm) package and is specified
over the -40°C to +85°C extended temperature range.
Ordering Information
PKG
CODE
PART
TEMP RANGE PIN-PACKAGE
Applications
MAX9742ETX+ -40°C to +85°C 36 TQꢀN-EP*
+Denotes lead-free package.
T3666-3
CRT TVs
ꢀlat-Panel Display TVs
Audio Docking Stations
Multimedia Monitors
*EP = Exposed paddle.
Pin Configuration located at end of data sheet.
Simplified Block Diagrams
R
F1
SINGLE-SUPPLY CONFIGURATION
C
FBL
20V TO 40V
FBL
V
DD
C
C
IN
R
R
IN1
INL-
INL+
LEFT NEGATIVE
AUDIO INPUT
MAX9742
C
OUT
IN
L
F
IN2
CLASS D
MODULATOR AND
HALF-BRIDGE
OUTL
LEFT POSITIVE
AUDIO INPUT
R
ZBL
C
C
R
R
FBL
F2
C
F
V
DD
MID
C
ZBL
2
F2
FBR
C
OUT
L
F
CLASS D
MODULATOR AND
HALF-BRIDGE
OUTR
C
C
IN
R
IN2
INR+
INR-
RIGHT POSITIVE
AUDIO INPUT
R
ZBL
IN
R
IN1
C
F
RIGHT NEGATIVE
AUDIO INPUT
CONTROL LOGIC/
POWER-UP
C
ZBL
SEQUENCING
FBR
SFT
V
SHDN
SS
C
FBR
C
SFT
ON
OFF
R
F1
Simplified Block Diagrams continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
ABSOLUTE MAXIMUM RATINGS
V
to V , NSENSE..............................................-0.3V to +45V
Continuous Power Dissipation (T = +70°C) (Note 1)
A
DD
SS
MID, LGND, LV , REGM, REGP, OUTR,
Single-Layer Board:
36-Pin TQꢀN (derate 26.3mW/°C above +70°C) ...........2.11W
Multilayer Board:
DD
OUTL to V .......................................................-0.3V to +45V
SS
MID, LGND, LV , REGM, REGP, OUTR,
DD
OUTL to V .......................................................-45V to +0.3V
36-Pin TQꢀN (derate 35.7mW/°C above +70°C) ...........2.86W
DD
REGLS to V .........................................................-0.3V to +12V
Junction-to-Ambient Thermal Resistance (θ
)
SS
JA
MID to REGP, REGM...............(V
- 0.3V) to (V
+ 0.3V)
Single-Layer Board:
36-Pin TQꢀN.................................................................38°C/W
Multilayer Board:
REGM
REGP
REGP to REGM.......................................................-0.3V to +12V
LV to LGND..........................................................-0.3V to +6V
DD
MAX9742
SHDN to LGND.........................................................-0.3V to +4V
SꢀT to LGND ............................................................-0.3V to +6V
ꢀB_, IN_+, IN_-, REꢀCUR to REGP,
36-Pin TQꢀN.................................................................28°C/W
Junction-to-Case Thermal Resistance (θ )...................1.4°C/W
JC
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
REGM..................................(V
- 0.3V) to (V
+ 0.3V)
REGM
REGP
BOOTR to OUTR ....................................................-0.3V to +12V
BOOTL to OUTL .....................................................-0.3V to +12V
OUTR, OUTL Shorted to LGND..................................Continuous
Note 1: Actual power capabilities are dependent on PCB layout. See the Thermal Considerations section.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single-Supply, Single-Ended Output
(V
= 24V, V = V
= LGND = 0V, V
= 3.3V, V
= 150pꢀ, C
= 12V, C
= 660µꢀ, C
= 10µꢀ, C
= 10µꢀ, R1 = R2 = R3 =
DD
SS
SUB
SHDN
ꢀB_1
MID
VDD
MID1
MID2
10kΩ, C
= 0.47µꢀ, C
= 1000µꢀ, C
= 10pꢀ, C
= 0.1µꢀ, C
= C
= 1µꢀ, R
= 30.1kΩ,
IN_
SꢀT
OUT
ꢀB_2
BOOT
REGP
REGM
R
= 121kΩ, R
= +25°C.) (Note 2)
= 562kΩ, R = 681kΩ, R
= 68kΩ, R = ∞, T = T
to T
, unless otherwise noted. Typical values are at
ꢀ1A
ꢀ1B
ꢀ2
REꢀ
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage Range
V
(Note 3)
20
40
V
DD
DD
Supply Current
I
No load, output filter removed
15
8
mA
mA
mA
kHz
Mute Mode Supply Current
Shutdown Current
No load, V
= 0V (outputs not switching)
SꢀT
No load, V
= 0V
0.8
300
1.3
SHDN
Switching ꢀrequency
f
SW
Power-Supply Rejection Ratio
(Note 4)
PSRR
V
= 24V + 500mV , f = 1kHz
68
dB
dB
DD
P-P
Crosstalk
(Notes 5 and 6)
L to R, R to L, R = 8Ω, P
= 1W, f = 1kHz
OUT
-78
9.5
L
R = 8Ω, f = 1kHz, THD+N = 10%
L
IN
Continuous Output Power
(Notes 5, 6, and 7)
R = 8Ω, f = 1kHz, THD+N = 10%,
L
IN
P
W
%
OUT
20.5
16
V
= 35V
DD
R = 4Ω, f = 1kHz, THD+N = 10%
L
IN
Efficiency
(Notes 5, 6, and 7)
R = 8Ω, P
= 9.5W, THD+N = 10%
92
L
OUT
2
_______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
ELECTRICAL CHARACTERISTICS—Single-Supply, Single-Ended Output (continued)
(V
= 24V, V = V
= LGND = 0V, V
= 3.3V, V
= 150pꢀ, C
= 12V, C
= 660µꢀ, C
= 10µꢀ, C
= 10µꢀ, R1 = R2 = R3 =
DD
SS
SUB
SHDN
ꢀB_1
MID
VDD
MID1
MID2
10kΩ, C
= 0.47µꢀ, C
= 1000µꢀ, C
= 10pꢀ, C
= 0.1µꢀ, C
= C
= 1µꢀ, R
= 30.1kΩ,
IN_
SꢀT
OUT
ꢀB_2
BOOT
REGP
REGM
R
= 121kΩ, R
= +25°C.) (Note 2)
= 562kΩ, R = 681kΩ, R
= 68kΩ, R = ∞, T = T
to T
, unless otherwise noted. Typical values are at
MAX
ꢀ1A
ꢀ1B
ꢀ2
REꢀ
L
A
MIN
T
A
PARAMETER
SYMBOL
CONDITIONS
R = 8Ω, P
MIN
TYP
MAX
UNITS
f
= 1kHz,
IN
= 3.5W
= 5W
0.06
L
OUT
OUT
Total Harmonic Distortion Plus
Noise
THD+N
BW = 22Hz to 22kHz
(Notes 5, 6, and 7)
%
R = 4Ω, P
L
0.08
88
P
= 9.5W, R = 8Ω,
L
BW = 22Hz to 22kHz
OUT
Unweighted
A-weighted
Signal-to-Noise Ratio
SNR
dB
93
(Notes 5 and 6)
Half-Bridge Switch
On-Resistance
R
0.4
50
0.7
Ω
DS(ON)
Switch Rise and ꢀall Times
IN_ Input Bias Current
No load (Note 4)
ns
µA
µA
ms
s
-1
+1
50
MID Input Bias Current
I
V
V
= 24V, no load
DD
MID
Shutdown-to-ꢀull Operation
Power-On to ꢀull Operation
t
68
SON
t
= 3.3V
1.5
PU
SHDN
Thermal-Overload Threshold
Temperature
T
Junction temperature
OUT_ shorted to V
150
oC
A
SH
SC
Short-Circuit Output Current
I
or V
2.9
4.5
-38
DD
SS
Peak voltage, 32-samples
per second, A-weighted
(Notes 4 and 8)
Into shutdown
Click-and-Pop
K
V
dBV
CP
Out of shutdown
-40
DIGITAL INPUTS (SHDN) (Note 9)
Logic-Input Low Voltage
Logic-Input High Voltage
Input Leakage Current
V
0.4
+1
V
V
IL
2.4
-1
IH
µA
ELECTRICAL CHARACTERISTICS—Dual Supplies
(V
= 15V, V = V
= -15V, V
= 3.3V, V
= LGND = 0V, C
= C
= 1000µꢀ, C
= 1µꢀ, C
= 562kΩ, R = 681kΩ, R
= 0.22µꢀ, C
ꢀB_1
ꢀ2 REꢀ
=
=
DD
SS
SUB
SHDN
= 0.1µꢀ, C
MID
= C
VDD
= 30.1kΩ, R
VSS
BYP
ꢀ1B
SꢀT
150pꢀ, C
= 10pꢀ, C
= 1µꢀ, R
= 121kΩ, R
ꢀB_2
BOOT
REGP
REGM
IN_
ꢀ1A
68kΩ, R = ∞, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage Range
V
(Note 3)
(Note 3)
10
20
V
DD
Negative Supply Voltage
Range
V
-20
-10
11
V
SS
Positive Supply Mute Mode
Current
No load, V
= 0V (outputs not switching)
= 0V (outputs not switching)
8
mA
mA
SꢀT
SꢀT
Negative Supply Mute Mode
Current
No load, V
-12
-8
_______________________________________________________________________________________
3
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V
= 15V, V = V
= -15V, V
= 3.3V, V
= LGND = 0V, C
= C
= 1000µꢀ, C
= 1µꢀ, C
= 562kΩ, R = 681kΩ, R
= 0.22µꢀ, C
ꢀB_1
ꢀ2 REꢀ
=
=
DD
SS
SUB
SHDN
= 0.1µꢀ, C
MID
= C
VDD
= 30.1kΩ, R
VSS
BYP
ꢀ1B
SꢀT
150pꢀ, C
= 10pꢀ, C
= 1µꢀ, R
= 121kΩ, R
ꢀB_2
BOOT
REGP
REGM
IN_
ꢀ1A
68kΩ, R = ∞, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
L
A
MIN
PARAMETER
Positive Supply Current
SYMBOL
CONDITIONS
No load, output filter removed
No load, output filter removed
MIN
TYP
23
MAX
UNITS
mA
I
36
DD
Negative Supply Current
I
-36
-23
mA
SS
MAX9742
Positive Supply Shutdown
Current
No load, V
= 0V
= 0V
0.001
-0.03
5
1
µA
µA
SHDN
SHDN
Negative Supply Shutdown
Current
No load, V
-1
-1
Output referred, affected by R
tolerances (Note 4)
and R
ꢀ_
IN_
Output Offset Voltage
IN_ Input Bias Current
30
+1
mV
µA
V
V
V
V
= 10V to 20V
97
100
67
DD
SS
DD
SS
= -10V to -20V
Power-Supply Rejection Ratio
(Note 4)
PSRR
dB
dB
= 15V + 500mV , f = 1kHz
P-P
= -15V + 500mV , f = 1kHz
64
P-P
Crosstalk
(Notes 5 and 6)
L to R, R to L, R = 8Ω, P
= 1W, f = 1kHz
OUT
-61
14
21
L
R = 8Ω
L
R = 8Ω, V
= 18V,
= 12V,
f
IN
= 1kHz,
L
DD
= -18V
V
THD+N = 10%
(Notes 5, 6, and 7)
Continuous Output Power
P
SS
W
OUT
R = 4Ω, V
L
DD
9.5
93
V
= -12V
SS
Efficiency
(Notes 5, 6, and 7)
R = 8Ω, P
= 15W, THD+N = 10%
%
%
L
OUT
f
= 1kHz,
IN
R = 8Ω, P
= 5W
0.06
0.08
89
L
OUT
Total Harmonic Distortion
Plus Noise
THD+N
SNR
BW = 22Hz to 22kHz
(Notes 5, 6, and 7)
R = 4Ω, P
= 10W
L
OUT
P
= 14W,
OUT
Unweighted
A-weighted
Signal-to-Noise Ratio
R = 8Ω, BW = 22Hz to
22kHz (Notes 5 and 6)
dB
L
94
Shutdown-to-ꢀull Operation
Short-Circuit Output Current
t
68
ms
A
SON
I
OUT_ shorted to V
or V
SS
2.9
4.5
SC
DD
Peak voltage, 32-samples
per second, A-weighted
(Notes 4 and 8)
Into shutdown
-36
-36
Click-and-Pop
K
CP
dBV
Out of shutdown
4
_______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
ELECTRICAL CHARACTERISTICS—Single-Supply, BTL Configuration
(V
= 24V, V = V
= LGND = 0V, V
= 3.3V, V
= 12V, C
= 660µꢀ, C
= 10µꢀ, C
= 10µꢀ, R1 = R2 = R3 =
DD
SS
SUB
SHDN
MID
VDD
MID1
MID2
10kΩ, C
= 121kΩ, R
= 0.47µꢀ, C
= 1000µꢀ, C
ꢀ2
= 150pꢀ, C
= 10pꢀ, C
= 0.1µꢀ, C
= C
= 1µꢀ, R
= 30.1kΩ, R
IN_ ꢀ1A
SꢀT
OUT
ꢀB_1
REꢀ
ꢀB_2
BOOT
to T
REGP
REGM
= 562kΩ, R = 681kΩ, R
= 68kΩ, R = ∞, T = T
, unless otherwise noted. Typical values are at T =
MAX A
ꢀ1B
L
A
MIN
+25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
7
MAX
UNITS
Output Offset Voltage
(Note 4)
mV
V
V
= 20V to 40V
88
77
DD
DD
Power-Supply Rejection Ratio
(Note 4)
PSRR
dB
W
= 24V + 500mV , f = 1kHz
P-P
R = 8Ω, f = 1kHz, THD+N = 10%,
(Notes 6, 10, and 11)
L
IN
Continuous Output Power
Efficiency
P
32
83
OUT
R = 8Ω, P = 10W, THD+N = 10%,
L
OUT
%
(Notes 5 and 6)
f = 1kHz, BW = 22Hz to 22kHz,
IN
Total Harmonic Distortion Plus
Noise (Notes 6, 10, and 11)
THD+N
SNR
0.08
%
R = 8Ω, P
= 10W
L
OUT
Unweighted
A-weighted
90
96
P
= 32W, R = 8Ω,
L
OUT
Signal-to-Noise Ratio
dB
BW = 22Hz to 22kHz
(Notes 6, 10, and 11)
Shutdown-to-ꢀull Operation
Click-and-Pop
t
68
ms
SON
Peak voltage, 32-samples
per second, A-weighted
(Notes 4, 11, and 12)
Into shutdown
-47
K
dBV
CP
Out of shutdown
-32
Note 2: All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
Note 3: Supply pumping may occur at high output powers with low audio frequencies. Use proper supply bypassing to prevent the
device from entering overvoltage protection due to supply pumping. See the Supply Pumping Effects and the Supply
Undervoltage and Overvoltage Protection sections.
Note 4: Amplifier inputs AC-coupled to ground.
Note 5: ꢀor R = 4Ω, L = 22µH and C = 0.68µꢀ. ꢀor R = 6Ω, L = 33µH and C = 0.47µꢀ. ꢀor R = 8Ω, L = 47µH and C =
L
ꢀ
ꢀ
L
ꢀ
ꢀ
L
ꢀ
ꢀ
0.33µꢀ.
Note 6: Testing performed with four-layer PCB.
Note 7: Both channels driven in phase.
Note 8: Testing performed with an 8Ω resistor connected between LC filter output and ground. Mode transitions are controlled by
SHDN. K level is calculated as 20log[(peak voltage during mode transition, no input signal) / 1V
].
RMS
CP
Note 9: Digital input specifications apply to both single-supply and dual-supply operation.
Note 10: Channels driven 180° out-of-phase. Load connected between LC filter outputs.
Note 11: L = 22µH and C = 0.68µꢀ.
ꢀ
ꢀ
Note 12: Testing performed with an 8Ω resistor connected between LC filter outputs. Mode transitions are controlled by SHDN. K
CP
level is calculated as 20log[(peak voltage during mode transition, no input signal) / 1V
].
RMS
_______________________________________________________________________________________
5
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Operating Characteristics
(24V single-supply mode, 15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, T = +25°C, unless otherwise noted. See ꢀigure 1 for test circuits, see Typical Application Circuits/ꢀunctional Diagrams for
A
test circuit component values.)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
10
100
10
100
10
SINGLE SUPPLY
SINGLE SUPPLY
SINGLE SUPPLY
V
= 24V
V
= 32V
V
= 36V
DD
DD
DD
f = 1kHz
f = 1kHz
f = 1kHz
MAX9742
R = 8Ω
L
R = 8Ω
L
R = 8Ω
L
R = 6Ω
L
R = 6Ω
L
R = 6Ω
L
1
1
1
THERMALLY
LIMITED
THERMALLY
LIMITED
R = 4Ω
L
0.1
0.01
0.1
0.01
0.1
0.01
R = 4Ω
L
R = 4Ω
L
0
5
10
15
20
0
10
20
30
40
0
10
20
30
40
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
10
100
10
100
10
SINGLE SUPPLY
BTL
CONFIGURATION
V = 24V
DD
DUAL SUPPLY
R = 8Ω
L
R = 6Ω
L
V
= 40V
DD
f = 1kHz
R = 8Ω
L
f = 1kHz
R = 8Ω
L
V
= 24V
DD
V
= 36V
DD
1
1
1
f = 1kHz
THERMALLY
LIMITED
0.1
0.01
0.1
0.01
0.1
0.01
THERMALLY
LIMITED
f = 100Hz
10
R = 4Ω
L
0
10
20
30
40
0
10
20
30
40
50
0
5
15
20
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER (W)
OUTPUT POWER PER CHANNEL (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
10
100
10
100
10
DUAL SUPPLY
SINGLE SUPPLY
SINGLE SUPPLY
THERMALLY LIMITED
R = 4Ω
V
= 24V
V
= 24V
L
DD
DD
R = 8Ω
L
R = 4Ω
L
1
1
1
f = 1kHz
f = 1kHz
f = 1kHz
0.1
0.01
0.1
0.01
0.1
0.01
f = 100Hz
f = 100Hz
f = 100Hz
0
5
10
15
20
25
30
0
5
10
15
0
5
10
15
20
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
6
_______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Typical Operating Characteristics (continued)
(24V single-supply mode, 15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, T = +25°C, unless otherwise noted. See ꢀigure 1 for test circuits, see Typical Application Circuits/ꢀunctional Diagrams for
A
test circuit component values.)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
10
100
10
100
10
BTL CONFIGURATION
SINGLE SUPPLY
SINGLE SUPPLY
V
= 24V
V
= 24V
V
= 24V
DD
DD
DD
R = 8Ω
L
R = 8Ω
R = 8Ω
L
L
T
= 40°C
T
= 40°C
A
A
1
f = 1kHz
1
1
f = 1kHz
f = 1kHz
0.1
f = 100Hz
0.1
0.01
0.1
0.01
0.01
0.001
f = 100Hz
10
f = 100Hz
0
10
20
OUTPUT POWER (W)
30
40
0
5
10
15
0
5
15
20
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
100
10
100
10
100
10
BTL CONFIGURATION
DUAL SUPPLY
R = 8Ω
DUAL SUPPLY
R = 4Ω
V
= 24V
DD
L
L
R = 8Ω
L
T
= 40°C
A
1
P
= 13W
OUT
f = 1kHz
1
1
P
= 8W
OUT
0.1
f = 100Hz
0.1
0.01
0.1
0.01
0.01
0.001
P
= 8W
10k
OUT
P
= 4W
OUT
0
10
20
OUTPUT POWER (W)
30
40
100
1k
10k
100k
100
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
100
10
100
10
100
10
SINGLE SUPPLY
SINGLE SUPPLY
BTL CONFIGURATION
V
= 24V
V
= 24V
V
= 24V
DD
DD
DD
R = 8Ω
R = 4Ω
R = 8Ω
L
L
L
P
= 9W
OUT
P
= 5W
P
= 17W
OUT
OUT
1
1
1
0.1
0.1
0.1
P
= 5W
OUT
P
= 12W
OUT
P
= 3W
10k
OUT
0.01
0.001
0.01
0.001
0.01
0.001
100
1k
100k
100
1k
10k
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
_______________________________________________________________________________________
7
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Operating Characteristics (continued)
(24V single-supply mode, 15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, T = +25°C, unless otherwise noted. See ꢀigure 1 for test circuits, see Typical Application Circuits/ꢀunctional Diagrams for
A
test circuit component values.)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE vs.
OUTPUT POWER WITH AND WITHOUT T-NETWORK
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
10
1
100
10
1
SINGLE SUPPLY
SINGLE SUPPLY
SINGLE SUPPLY
V
= 24V
V
= 24V
V
= 24V
DD
DD
DD
R = 4Ω
R = 8Ω
f = 1kHz
R = 8Ω
MAX9742
L
L
L
P
= 50mW
10
1
P
= 50mW
OUT
OUT
WITHOUT T-NETWORK
0.1
0.01
0.1
0.01
0.1
0.01
WITH T-NETWORK
100
1k
10k
100k
0.001
0.01
0.1
1
10
100
100
1k
10k
100k
FREQUENCY (Hz)
OUTPUT POWER PER CHANNEL (W)
FREQUENCY (Hz)
EFFICIENCY AND POWER
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
DISSIPATION vs. OUTPUT POWER
MAX9742 toc22
MAX9742 toc23
100
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100
90
80
70
60
50
40
30
20
10
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
90
80
70
60
50
40
30
20
10
0
EFFICIENCY
EFFICIENCY
SINGLE SUPPLY
SYSTEM POWER
DISSIPATION
SYSTEM POWER
DISSIPATION
DUAL SUPPLY
V
= 30V
DD
R = 8Ω
R = 8Ω
L
L
f
= 1kHz
f
= 1kHz
IN
IN
0
5
10
15
0
5
10
15
20
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
EFFICIENCY AND POWER
EFFICIENCY AND POWER
DISSIPATION vs. OUTPUT POWER
DISSIPATION vs. OUTPUT POWER
MAX9742 toc24
MAX9742 toc25
100
90
80
70
60
50
40
30
20
10
0
2.5
2.0
1.5
1.0
0.5
0
90
80
70
60
50
40
30
20
10
0
9
8
7
6
5
4
3
2
1
0
EFFICIENCY
EFFICIENCY
SYSTEM POWER
DISSIPATION
SYSTEM POWER
DISSIPATION
SINGLE SUPPLY
= 24V
SINGLE SUPPLY
V
V
= 24V
DD
DD
R = 8Ω
R = 4Ω
L
L
f
= 1kHz
f
= 1kHz
20
IN
IN
0
5
10
15
0
5
10
15
25
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
8
_______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Typical Operating Characteristics (continued)
(24V single-supply mode, 15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, T = +25°C, unless otherwise noted. See ꢀigure 1 for test circuits, see Typical Application Circuits/ꢀunctional Diagrams for
A
test circuit component values.)
EFFICIENCY AND POWER
OUTPUT POWER
vs. SUPPLY VOLTAGE
OUTPUT POWER
vs. SUPPLY VOLTAGE
DISSIPATION vs. OUTPUT POWER
MAX9742 toc26
100
90
80
70
60
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
1
0
30
25
20
15
10
5
25
20
15
10
5
DUAL SUPPLY
R = 8Ω
DUAL SUPPLY
R = 4Ω
L
L
10% THD+N
EFFICIENCY
SYSTEM POWER
DISSIPATION
10% THD+N
1% THD+N
1% THD+N
BTL CONFIGURATION
= 24V
V
DD
R = 8Ω
L
f
IN
= 1kHz
0
0
0
10
20
30
40
50
±10
±12
±14
±16
±18
±20
±10
±12
±14
±16
±18
±20
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
OUTPUT POWER
vs. SUPPLY VOLTAGE
OUTPUT POWER
vs. SUPPLY VOLTAGE
OUTPUT POWER
vs. SUPPLY VOLTAGE
30
25
20
15
10
5
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
SINGLE SUPPLY
R = 8Ω
SINGLE SUPPLY
R = 4Ω
L
BTL CONFIGURATION
R = 8Ω
L
L
10% THD+N
10% THD+N
10% THD+N
1% THD+N
1% THD+N
1% THD+N
0
0
0
20
25
30
35
40
20
25
30
SUPPLY VOLTAGE (V)
35
40
20
22
24
26
28
30
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
20
15
10
5
18
17
16
15
14
13
12
10
0
SINGLE SUPPLY
OUTPUT FILTER REMOVED
INPUTS GROUNDED
I
NO LOAD CONNECTED
DD
I
DD
-10
-20
-30
-40
-50
-60
DUAL SUPPLY
OUTPUT FILTER REMOVED
NO LOAD CONNECTED
I
SS
0
V
= |V |
SS
-5
DD
I
SS
DUAL SUPPLY
= |V
-10
-15
-20
V
|
SS
DD
OUTPUT FILTER REMOVED
INPUTS GROUNDED
NO LOAD CONNECTED
±10
±12
±14
±16
±18
±20
20
25
30
35
40
±10
±12
±14
±16
±18
±20
±22
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Operating Characteristics (continued)
(24V single-supply mode, 15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, T = +25°C, unless otherwise noted. See ꢀigure 1 for test circuits, see Typical Application Circuits/ꢀunctional Diagrams for
A
test circuit component values.)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
WIDEBAND OUTPUT SPECTRUM
OUTPUT SPECTRUM FFT
1.0
0.8
0.6
0.4
0.2
0
0
-20
0
-20
SINGLE SUPPLY
INPUTS AC GROUNDED
NO LOAD CONNECTED
SINGLE SUPPLY
R = 8Ω
RBW = 10kHz
MEASURED AT SINGLE-
ENDED FILTER OUTPUT
INPUTS AC GROUNDED
L
f
IN
= 1kHz
MAX9742
V
= -60dBV
OUT_
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
20
25
30
SUPPLY VOLTAGE (V)
35
40
0.1
1.0
10
100
0
5k
10k
15k
20k
FREQUENCY (MHz)
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
20
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
DUAL SUPPLY
R = 8Ω
L
BTL
SINGLE SUPPLY
V
= 24V + 500mV
DD P-P
V
= 24V + 500mV
DD
P-P
R = 8Ω
L
R = 8Ω
L
-20
-40
-60
-80
-100
-120
OUT_ PSRR
V
= -15V + 500mV
P-P
SS
MID PSRR
100
V
= 15V + 500mV
10k
DD
P-P
10
100
1k
100k
10
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
EXITING SHUTDOWN
(DUAL SUPPLY)
CROSSTALK vs. FREQUENCY
CROSSTALK vs. FREQUENCY
MAX9742 toc43
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
20
0
DUAL SUPPLY
R = 8Ω
SINGLE SUPPLY
R = 8Ω
DUAL SUPPLY
L
P
R = 8Ω
L
L
P
= 1W
= 1W
OUT
OUT
V
SHDN
-20
-40
-60
-80
-100
-120
2V/div
R INTO L
V
OUT_
20V/div
R INTO L
FILTERED
V
5V/div
OUT_
L INTO R
10k
L INTO R
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
100k
20ms/div
FREQUENCY (Hz)
10 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Typical Operating Characteristics (continued)
(24V single-supply mode, 15V dual-supply mode, both channels driven in phase, THD+N measurement bandwidth = 22Hz to
22kHz, T = +25°C, unless otherwise noted. See ꢀigure 1 for test circuits, see Typical Application Circuits/ꢀunctional Diagrams for
A
test circuit component values.)
ENTERING SHUTDOWN
(SINGLE SUPPLY)
EXITING SHUTDOWN
ENTERING SHUTDOWN
MAX9742 toc45
MAX9742 toc44
MAX9742 toc46
DUAL SUPPLY
R = 8Ω
L
SINGLE SUPPLY
R = 8Ω
L
V
SINGLE SUPPLY
R = 8Ω
SHDN
V
SHDN
2V/div
L
V
2V/div
SHDN
2V/div
V
OUT_
V
OUT_
10V/div
V
OUT_
10V/div
20V/div
FILTERED
V
OUT_
FILTERED
FILTERED
5V/div
V
OUT_
V
OUT_
5V/div
5V/div
20ms/div
10ms/div
10ms/div
CASE TEMPERATURE
vs. OUTPUT POWER
CASE TEMPERATURE
vs. OUTPUT POWER
OUTPUT WAVEFORM
MAX9742 toc49
50
40
30
20
10
0
120
100
80
60
40
20
0
SINGLE SUPPLY, V = 24V
INPUTS AC GROUNDED
DD
SINGLE SUPPLY
= 24V
V
DD
R = 4Ω
L
4-LAYER PCB
V
OUT
10V/div
V
OUTR
SINGLE SUPPLY
= 24V
10V/div
V
DD
R = 8Ω
L
4-LAYER PCB
1µs/div
0
2
4
6
8
10
12
0
5
10
15
20
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
EMI AMPLITUDE vs. FREQUENCY
EMI AMPLITUDE vs. FREQUENCY
MAX9742 toc51
MAX9742 toc50
40
35
30
25
20
15
10
5
40
EN55022B LIMIT
SINGLE SUPPLY
SINGLE SUPPLY
R = 8Ω, P = 1.25W
SPEAKER CABLE
LENTH = 1m
R = 4Ω, P
= 1.25W
L
OUT_
L
OUT
7.8dBµV/m
BELOW LIMIT
35
30
25
20
15
10
5
SPEAKER CABLE
LENTH = 1m
EN55022B LIMIT
5.8dBµV/m
BELOW LIMIT
11.3dBµV/m
BELOW LIMIT
9.4dBµV/m BELOW LIMIT
12.8dBµV/m
BELOW LIMIT
18.1dBµV/m
BELOW LIMIT
7dBµV/m
BELOW
LIMIT
3.6dBµV/m
BELOW LIMIT
30
100
1000
30
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
______________________________________________________________________________________ 11
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Pin Description
PIN
NAME
FUNCTION
1, 6, 18,
27, 28, 36
N.C.
No Connection. Not internally connected.
Left Speaker Output
2, 3
4
OUTL
SUB
Device Substrate. Connect SUB to V
.
SS
5
BOOTL
INL+
Left-Channel Bootstrap Capacitor Terminal. Connect a 0.1µꢀ capacitor between BOOTL and OUTL.
Left-Channel Positive Input
MAX9742
7
Left-Channel Negative Input. Connect an external feedback capacitor between INL- and ꢀBL. See the
8
9
INL-
ꢀBL
Feedback Capacitor (C ) section.
FB_
Left-Channel ꢀeedback Capacitor Terminal. Connect an external feedback capacitor between ꢀBL and
INL-. See the Feedback Capacitor (C ) section.
FB_
-5V Internal Regulator Output. Regulator output voltage is with respect to MID. Bypass REGM with a 1µꢀ
capacitor to signal ground plane (SGND). See the Supply Bypassing/Layout section.
10
REGM
Midsupply Bias Voltage Input. The MID input biases the internal preamplifiers to the average value of the
V
and V supply inputs. ꢀor dual-supply operation, connect to the signal ground plane (SGND). ꢀor
SS
DD
11
MID
single-supply operation, apply a voltage to MID equal to 0.5 x V through an external resistive voltage-
DD
divider and decoupling network (see the Setting V
section). See the Typical Application
MID
Circuits/Functional Diagrams and Supply Bypassing/Layout sections.
5V Internal Regulator Output. Regulator output voltage is with respect to MID. Bypass REGP with a 1µꢀ
capacitor to the signal ground plane (SGND). See the Supply Bypassing/Layout section.
12
13
14
REGP
Reference Current Resistor Terminal. Connect an external resistor from REꢀCUR to REGP to set the
switching frequency and output short-circuit current-limit value. Use resistor values greater than or equal
to 58kΩ and less than or equal to 75kΩ. See the Setting the Switching Frequency and Output Current
REꢀCUR
Limit (R
) section.
REF
Soft-Start Capacitor Terminal/Mute Input. Connect a 0.22µꢀ capacitor between SꢀT and PGND to utilize
the soft-start power-up sequence. Drive SꢀT low to mute the outputs.
SꢀT
Logic Ground. Connect LGND to signal ground (SGND) and power ground (PGND) planes. See the
Supply Bypassing/Layout section.
15
16
17
LGND
LV
Internal 5V Logic Supply. Bypass LV
to LGND with a 0.1µꢀ capacitor.
DD
DD
Active-Low Shutdown Input. Drive SHDN high for normal operation. Drive SHDN low to place the device
into shutdown mode.
SHDN
Right-Channel ꢀeedback Capacitor Terminal. Connect an external feedback capacitor between ꢀBR and
19
ꢀBR
INR-. See the Feedback Capacitor (C ) section.
FB_
Right-Channel Negative Input. Connect an external feedback capacitor between INR- and ꢀBR. See the
20
21
22
INR-
INR+
Feedback Capacitor (C ) section.
FB_
Right-Channel Positive Input
Negative Supply Sense Input. NSENSE is internally connected to V . Connect a 1µꢀ bypass capacitor
SS
between NSENSE and REGLS.
NSENSE
7V Internal Regulator Output. REGLS output voltage is with respect to V . Bypass REGLS with a 1µꢀ
SS
capacitor to NSENSE.
23
REGLS
12 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Pin Description (continued)
PIN
24
NAME
FUNCTION
Right-Channel Bootstrap Capacitor. Connect a 0.1µꢀ capacitor between BOOTR and OUTR.
Right Speaker Output
BOOTR
OUTR
25, 26
29, 30,
34, 35
Positive Power-Supply Input. Bypass V
the Supply Pumping Effects section.
to LGND with a 0.1µꢀ plus additional bulk capacitance. See
DD
V
DD
Negative Power-Supply Input. ꢀor dual-supply operation, connect to negative power-supply voltage
31, 32, 33
EP
V
and bypass V to LGND with a 0.1µꢀ plus additional bulk capacitance. ꢀor single-supply operation,
SS
connect to LGND.
SS
Exposed Paddle. EP is internally connected to device substrate. Connect EP to V through a large
SS
section of copper to maximize power dissipation.
EP
Test Circuits
Detailed Description
The MAX9742 is a two-channel, single-ended Class D
stereo amplifier capable of providing 16W of output
power on each channel into 4Ω loads in single- or dual-
supply operation. The amplifier can also provide 32W
of output power in a mono bridge-tied-load (BTL) con-
figuration. The device offers Class AB audio perfor-
mance with Class D efficiency.
SINGLE-ENDED CONFIGURATION
L
F
+
+
OUTL
OUTR
C
C
F
F
R
R
L
L
AUX-0025
FILTER
AUDIO
ANALYZER
-
MAX9742
-
The differential input architecture reduces common-
mode noise pickup. The device can also be configured
for single-ended input signals.
L
F
+
+
-
The connection of external feedback components
allows custom gain settings.
-
Class D Operation and Efficiency
Class D amplifiers are switch-mode devices capable of
significantly higher power efficiencies in comparison to
linear amplifiers. The output stage of the MAX9742 con-
sists of a half-bridge speaker driver (see ꢀigure 2). The
high efficiency of a Class D amplifier is attributed to the
region of operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current-
BTL CONFIGURATION
L
F
+
+
OUTL
OUTR
C
C
F
F
AUX-0025
FILTER
AUDIO
ANALYZER
R
L
MAX9742
L
F
steering switches by switching the output between V
DD
-
-
and V
(ground for single-supply operation). Any
SS
power loss associated with the Class D output stage is
mostly due to the I2R loss of the MOSꢀET on-resistance
and quiescent current overhead. The theoretical best
NOTE: SINGLE-ENDED CONFIGURATION IS AC-COUPLED IN SINGLE-SUPPLY MODE.
ꢀigure 1. Test Circuits for Single-Ended and BTL Configurations
______________________________________________________________________________________ 13
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
efficiency of a linear amplifier is 78%; however, that effi-
ciency is only exhibited at peak output powers. Under
normal operating levels (typical music reproduction lev-
els), efficiency falls below 30%, whereas the MAX9742
still exhibits 80% efficiency under the same conditions.
the square wave is proportional to the level of the input
signal. When the input signal is at 0V, the duty cycle of
the MAX9742 output is equal to 50%. To extract the
amplified audio signal from this PWM waveform, the
output of the MAX9742 is fed to an external LC lowpass
filter (see the Single-Ended LC Output ꢀilter Design (L
ꢀ
Since the output transistors switch the output to either
and C ) section). The LC filter works as an averaging
ꢀ
V
or V
(ground for single-supply operation), the
SS
DD
circuit for the PWM output voltage waveform. The
resulting averaged output voltage is equal to the ampli-
fied audio signal. ꢀigure 3a illustrates the resulting
PWM output waveform due to the varying input signal
level, and ꢀigure 3b shows the recovered amplified
input signal after filtering.
resulting output of a Class D amplifier is a high-fre-
quency square wave. This square wave is pulse-width-
modulated by the audio input signal. In the MAX9742,
the pulse-width modulation (PWM) is accomplished by
comparing the input audio signal to an internally gener-
ated triangle wave oscillator. The resulting duty cycle of
MAX9742
C
C
0.1µF
REGLS
1µF
BOOT
D
BOOT
1N4148
NSENSE
(INTERNALLY
CONNECTED TO V
)
SS
V
DD
REGLS
MAX9742
7V REGULATOR
(WITH RESPECT TO V
)
SS
L
F
OUT_
GATE DRIVE LOGIC
V
REGLS
C
F
V
SS
V
SS
DUAL-SUPPLY CONFIGURATION SHOWN
ꢀigure 2. Simplified Block Diagram of the MAX9742 Output Stage
14 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
1
INTERNAL TRIANGLE
WAVE OSCILLATOR
f
SW
INPUT
SIGNAL
V
V
DD
V
OUT_
+ V
2
DD
SS
V
SS
NOTE: FOR CLARITY, SIGNAL PERIODS ARE NOT SHOWN TO ACTUAL SCALE.
ꢀigure 3a. MAX9742 Output with an Applied Input Signal
V
OUT_
V
V
DD
AVERAGE VALUE
OF V
OUT_
+ V
SS
DD
2
V
SS
NOTE: FOR CLARITY, SIGNAL PERIODS ARE NOT SHOWN TO ACTUAL SCALE.
ꢀigure 3b. MAX9742 Output with Resulting Output After ꢀiltering
______________________________________________________________________________________ 15
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Shutdown Mode
The MAX9742 features a low-power shutdown mode
that reduces quiescent current consumption to less
than 0.5mA in single-supply mode and less than 1µA in
dual-supply mode. Drive SHDN low to place the device
into shutdown mode. Connect SHDN to a logic-high for
normal operation.
Supply Undervoltage and
Overvoltage Protection
The MAX9742 features an undervoltage protection
function that prevents the device from operating if V
DD
is less than +7V with respect to V
input or if V is
MID
SS
greater than -7V with respect to V
. This feature pre-
MID
vents improper operation when insufficient supply volt-
ages are present. Once the supply voltage exceeds the
undervoltage threshold, the MAX9742 is turned on and
the amplifiers are powered, provided that SHDN is high
and the outputs are unmuted.
The maximum voltage that may be applied to the SHDN
input is 4V (see the Absolute Maximum Ratings sec-
tion). If the SHDN input must be controlled by a 5V
logic signal, limit the maximum voltage that can be
applied to the SHDN input to 4V through an external
resistive divider.
MAX9742
The MAX9742 also features an overvoltage protection
function that prevents the device from operating if the
potential difference between V
and V
exceeds
SS
DD
Click-and-Pop Suppression
The MAX9742 features comprehensive click-and-pop
suppression that minimizes audible transients on start-
up and shutdown. While in shutdown, the half-bridge
output transistor switches are turned off, causing each
output to go high impedance. During startup, or power-
up, the input amplifiers are muted and an internal loop
sets the modulator bias voltages to the correct levels,
minimizing audible clicks and pops when the output
half-bridge is enabled. The value of the soft-start
+46V. This feature prevents the MAX9742 from damag-
ing itself due to excessive supply pumping effects (see
the Supply Pumping Effects section). The device
returns to normal operation once the potential differ-
ence between V
and V drops below +46V.
SS
DD
Applications Information
Output Dynamic Range
Dynamic range is the difference between the noise
floor of the system and the output level at 10% THD+N.
It is essential that a system’s dynamic range be known
before setting the maximum output gain. Output clip-
ping occurs if the output signal is greater than the
dynamic range of the system.
capacitor, C
, affects the click-and-pop performance
SꢀT
and startup time of the MAX9742 (see the Soft-Start
Capacitor (C section). To maximize click-and-pop
SꢀT)
suppression when powering up an audio system, drive
SHDN or SꢀT (see the Mute ꢀunction section) to 0V
until the rest of the circuitry in the system has had
enough time to stabilize. This ensures the MAX9742 is
the last device to be activated in the system and pre-
vents transients caused by circuitry preceding the
MAX9742 from being amplified at the outputs.
Use the THD+N vs. Output Power graph in Typical
Operating Characteristics to identify the system’s
dynamic range. Given the system’s supply voltage, find
the output power that causes 10% THD+N for a given
load. Use the following equation to determine the peak-
Mute Function
The MAX9742 features a clickless/popless mute mode.
When the device is muted, the outputs stop switching,
muting the speaker. The mute function only affects the
output stage and does not shutdown the device. To
mute the MAX9742, drive SꢀT to ground. ꢀigure 4
shows how an external transistor (MOSꢀET or BJT) can
be used to easily mute the MAX9742.
TO
OUTPUT
STAGE
CONTROL
LOGIC/POWER-UP
SEQUENCING
SFT
MUTE
UN-MUTE
C
SFT
MAX9742
10kΩ
Thermal-Overload Protection
Thermal-overload protection limits total power dissipa-
tion in the MAX9742. When the junction temperature
exceeds approximately +160°C, the thermal protection
circuitry disables the amplifier output stage. The ampli-
fiers are enabled once the junction temperature cools
by approximately 15°C. This results in a pulsing output
under continuous thermal-overload conditions.
ꢀigure 4. MAX9742 Mute Circuit
16 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
to-peak output voltage that causes 10% THD+N for a
When using the differential input configuration, the
common-mode rejection ratio (CMRR) is primarily limit-
ed by the external resistor tolerances. Ideally, to
achieve the highest possible CMRR, the resistors
should be perfectly matched and the following condi-
tion should be met:
given load.
V
= 2 2 P
× R (V)
(
)
OUT_P−P
OUT_10%
L
where P
is the output power that causes 10%
OUT_10%
R
R
R
R
ꢀ1
ꢀ2
THD+N, R is the load resistance, and V
is the
L
OUT_P-P
=
peak-to-peak output voltage. Determine the voltage
IN1
IN2
gain (A ) necessary to attain this output voltage based
V
on the maximum peak-to-peak input voltage (V
):
To ensure the MAX9742 input amplifiers operate as
fully differential integrators, connect a capacitor
between IN_+ and MID whose value is equal to C (see
ꢀ
the ꢀeedback Capacitor (CꢀB_) section).
IN_P-P
V
OUT_P−P
A
=
(V/V)
V
V
IN_P−P
Single-Ended Input
Each channel of the MAX9742 can be configured as a
single-ended input amplifier by connecting IN_+ to MID
Set the closed-loop voltage gain of the MAX9742 less
than or equal to A to prevent clipping of the output,
V
unless audible clipping is acceptable for the application.
(through an external resistor, R ) and driving IN_- with
OS
the input source (see ꢀigure 5). In this configuration,
the MAX9742 is configured as a single-ended amplifier
whose voltage gain is equal to:
Input Amplifier
The external feedback networks of the MAX9742 input
amplifiers allow custom gain settings while maximizing
dynamic range. The input amplifiers also accommodate
a variety of standard amplifier configurations including
differential input, single-ended input, and summing
amplifiers. Due to the output current limitations of the
internal input amplifiers, always select feedback resistors
R
R
ꢀ
A
= −
(V/V)
V
IN
where A is the desired voltage gain in V/V.
V
(R , see the Typical Application Circuits/ꢀunctional
ꢀ1
To minimize output offset voltages due to input bias cur-
Diagrams) with values greater than or equal to 400kΩ. To
preserve gain accuracy, avoid using feedback resistors
with values greater than 1MΩ. ꢀor proper operation, limit
common-mode input voltages to 3V.
rents, connect a resistor, R , (see ꢀigure 5) between
OS
IN_+ and MID. Select the value of R
so that the DC
OS
resistances looking out of inputs of the amplifier (IN_+
and IN_-) are equal. ꢀor example, when using the dual-
supply configuration with a DC-coupled input source, the
Differential Input Configuration
The Typical Application Circuits/ꢀunctional Diagrams
show each channel of the MAX9742 configured as dif-
ferential input amplifiers. A differential input offers
improved noise immunity over a single-ended input. In
systems that include high-speed digital circuitry, high-
frequency noise can couple into the amplifier’s input
traces. The signals appear at the amplifier’s inputs as
common-mode noise. A differential input amplifier
amplifies the difference of the two inputs, and signals
common to both inputs are subtracted out. When con-
figured for differential inputs, the voltage gain of the
MAX9742 is set by:
value of R should be equal to R ||R .
OS
ꢀ
IN
R
F
OUT_
C
FB_
FB_
C
IN
R
IN
IN_-
IN_+
MAX9742
TO CLASS D
MODULATOR
V
IN
R
ꢀ1
A
=
(V/V)
R
OS
V
R
IN1
MID
where A is the desired voltage gain in V/V. R
V
IN1
should be equal to R , and R should be equal to
IN2
ꢀ1
ꢀigure 5. Single-Ended Input Configuration
R
.
ꢀ2
______________________________________________________________________________________ 17
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Summing Configuration (Audio Mixer)
ꢀigure 6 shows the MAX9742 configured as a summing
amplifier, which allows multiple audio sources to be lin-
early mixed together. Using this configuration, the out-
put of the MAX9742 is equal to the weighted sum of the
input signals:
Mono Bridge-Tied-Load (BTL)
Configuration
The MAX9742 also accommodates a mono bridge-tied-
load (BTL) configuration that can be used in single-
supply and dual-supply applications. In the BTL
configuration, the speaker load is driven differentially
by connecting the half-bridge outputs as a full H-bridge
driver. To drive the speaker differentially, the inputs of
both channels must be driven by the same audio signal
with one channel 180° out-of-phase with the other
channel. ꢀigure 7 shows the connections required for
BTL operation.
R
R
R
ꢀ
R
IN3
ꢀ
ꢀ
V
OUT_
= − (V
+ V
+ V
)
IN2
IN3
IN1
R
R
IN1
IN2
MAX9742
As shown in the above equation, the weighting or
amount of gain applied to each input signal source is
determined by the ratio of R and the respective input
The advantages of BTL operation include reduced
component count due to the elimination of the output-
coupling capacitors when using single-supply opera-
tion, a 6dB increase in gain due to the load being
driven differentially, increased output power into a sin-
gle load, and the minimization of the supply-pumping
since each half bridge is driven 180° out-of-phase (see
the Supply Pumping Effects section). ꢀor single-supply
applications, the output-coupling capacitors are not
needed for BTL operation since the DC voltage present
at each half-bridge output is equal in value and applies
to each side of the load. This means no DC voltage
appears across the load, and therefore, no DC current
flows into the speaker.
ꢀ
resistor (R , R , R ) connected to each signal
IN1
IN2
ꢀ
IN3
IN_
source. Select R and R
so that the dynamic range
of the MAX9742 is not exceeded when the input signals
are at their maximum values and in phase with each
other (see the Output Dynamic Range section).
To minimize output offset voltages due to input bias
currents, connect a resistor, R , (see ꢀigure 6)
OS
between IN_+ and MID. Select the value of R
such
OS
that the DC resistances looking out of inputs of the
amplifier (IN_+ and IN_-) are equal. ꢀor example, when
using the dual-supply configuration with a DC-coupled
input source, the value of R
should be equal to
OS
R ||R ||R || ||R .
INn
ꢀ
IN1 IN2
R
F
OUT_
C
FB_
FB_
C
IN
R
IN1
MAX9742
C
IN
R
IN2
IN_-
IN_+
V
IN1
C
TO CLASS D
MODULATOR
IN
R
IN3
V
IN2
V
IN3
R
OS
R
R
R
F
F
F
V
(V
× V
IN2
× V
IN3
)
OUT_ IN1
R
R
IN2
R
IN3
IN1
MID
ꢀigure 6. Summing Amplifier Configuration
18 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Since each half-bridge output stage is only capable of
Component Selection
Feedback Capacitor (C
To maximize dynamic range, an external feedback
capacitor (C ) is needed to generate an error signal
for the Class D modulator. The feedback capacitor con-
figures the input amplifier stage as an integrator whose
output is equal to an error signal consisting of the sum
of the integrated input audio and PWM output signals.
The integrator provides a noise-shaping function for the
closed-loop response of the amplifier.
driving loads as small as 4Ω and each half-bridge sees
half of the differential load resistance when configured
for BTL, only use the BTL configuration with loads
greater than or equal to 8Ω. The MAX9742 may be ther-
mally limited when using the BTL configuration with
high supply voltages due to the decreased load resis-
tance seen by each half bridge. ꢀor optimum perfor-
mance, the PCB should be thermally optimized to
achieve the continuous output powers required for the
application (see the Thermal Considerations section).
)
FB_
ꢀB_
R
F1
C
FBL
FBL
V
DD
MAX9742
C
C
IN
R
R
IN1
INL-
INL+
L
F
CLASS D
MODULATOR
AND GATE DRIVE
OUTL
DIFFERENTIAL
AUDIO INPUT
V
V
DD
/2
OUT_P-P
IN
IN2
C
ZBL
C
F
C
C
R
R
F
F2
R
ZBL
V
V
SS
MID
2 x V
OUT_P-P
0V
DD
R
ZBL
F2
F
C
C
IN
R
R
IN2
C
F
INR+
INR-
C
ZBL
L
F
CLASS D
MODULATOR
AND GATE DRIVE
OUTR
V
OUT_P-P
V /2
DD
IN
IN1
V
SS
FBR
C
FBR
R
F1
R
F_
A
R
= 2 ×
V_BTL
R
IN_
= R , R = R
IN2 F1 F2
IN1
ꢀigure 7. Input Signal Source and Load Connections for BTL Operation
______________________________________________________________________________________ 19
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
To guarantee stability and minimize distortion, select
the external feedback resistor (R ) and capacitor
film dielectric capacitors are good choices for AC-cou-
pling capacitors. Capacitors with high-voltage coeffi-
cients, such as ceramics (non-C0G dielectrics), can
result in increased distortion at low frequencies.
ꢀ_
(C
) so that the following conditions are met:
ꢀB_
21.5
R
× C
≥
and R
> 400kΩ
ꢀ_
ꢀ_
ꢀB_
Single-Ended LC Output Filter Design (L and C )
F
F
f
SW
An LC output filter is needed to extract the amplified
audio signal from the PWM output (see ꢀigure 8). The LC
circuit forms an LCR lowpass filter (neglecting voice coil
inductance) with the impedance of the speaker. To pro-
vide a maximally flat-frequency response, the LCR filter
should be designed to have a Butterworth response and
should be optimized for a specific speaker load. Table 1
where f
is the output switching frequency deter-
SW
mined by R
(see the Setting the Switching
REꢀ
MAX9742
ꢀrequency and Output Current Limit (R
) section).
REꢀ
Setting the Switching Frequency and
Output Current Limit (R
)
REF
provides some recommended standard L and C com-
ꢀ
ꢀ
Resistor R
SW
determines the output switching frequency
REꢀ
ponent values for 4Ω, 6Ω, and 8Ω speaker loads. The
(f ) and the output short-circuit current-limit value (I ).
SC
component values given in Table 1 provide an approxi-
Set f
and I with the following equations:
SC
SW
mate -3dB cutoff frequency (f ) of 40kHz. The following
C
paragraph provides information on calculating filter com-
ponent values for cutoff frequencies other than 40kHz
and speaker loads not listed in Table 1.
1
f
=
(Hz)
(A)
SW
68kΩ
3.3µs ×
R
REꢀ
The LCR filter has the following 2nd order transfer function:
68kΩ
I
= 3.6A ×
SC
1
R
REꢀ
L
1
× C
ꢀ
ꢀ
H(s) =
1
ꢀor example, selecting a 68kΩ resistor for R
in a switching frequency of 303kHz and an output
short-circuit current limit of 4.5A.
results
REꢀ
2
s
+
s +
R
× C
L
ꢀ
× C
ꢀ
SPKR
ꢀ
To prevent damage to the MAX9742 during output
short-circuit conditions and to utilize its full output
power capabilities, use resistor values greater than or
where L is the value of the filter inductor, C is the
ꢀ
ꢀ
value of the filter capacitor, and R
is the DC resis-
SPKR
tance of the speaker. The voice coil inductance of the
speaker has been neglected to simplify filter calcula-
tions (see the Zobel Network section). The above trans-
fer function is presented in the general 2nd order
transfer function format given below:
equal to 58kΩ and less than or equal to 75kΩ for R
.
REꢀ
Input-Coupling Capacitor
The AC-coupling capacitors (C ) and input resistors
IN
(R ) form highpass filters that remove any DC bias
IN_
from an input signal (see the Typical Application
2
ω
n
Circuits/ꢀunctional Diagrams). C prevents any DC
IN
H(s) =
2
2
s
+ 2 × ζ × ω × s + ω
n n
components from the input-signal source from appear-
ing at the amplifier outputs. The -3dB point of the high-
pass filter, assuming zero source impedance due to the
input signal source, is given by:
where w is the natural frequency in radians/s and ζ is
n
the damping ratio of the 2nd order system. ꢀor an ideal
Butterworth response, ζ is equal to 0.707 and ω is
C
1
equal to the -3dB cutoff frequency, ω . Using the above
c
f
=
(Hz)
−3dB
transfer functions and converting to Hertz, the -3dB cut-
off frequency of the filter is:
2π × R × C
IN
IN
Choose C so that f
is well below the lowest frequen-
too high affects the amplifier’s
IN
-3dB
-3dB
1
cy of interest. Setting f
f
C
=
(Hz)
2 × π × L ×C
low-frequency response. Use capacitors with low-voltage
coefficient dielectrics. Aluminum electrolytic, tantalum, or
ꢀ
ꢀ
20 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Using the transfer functions and the equation for f , the
upper frequency limit of the inductor should also be
taken into account. The load connected to the output of
the half-bridge (LC filter and speaker) should remain
inductive at the switching frequency of the MAX9742. If
not, a significant amount of high-frequency energy is
dissipated in the resistive load, therefore, increasing
the supply current to excessive levels. To prevent this
from occurring, select an output inductor whose self-
resonant frequency is substantially higher than the
switching frequency of the MAX9742.
c
following expressions for L and C can be derived:
ꢀ
ꢀ
1
C
=
(ꢀ)
ꢀ
4 × π × f × R
× ζ
SPKR
C
1
L
ꢀ
=
(H)
2
2
4 × π × f
× C
ꢀ
C
Since the frequency response of the output filter is
dependent on the speaker resistance, it is best to opti-
mize the LC filter for a particular load resistance. To
calculate the component values of the LC filter for a
given speaker load resistance, first select an appropri-
ate cutoff frequency for the filter. The cutoff frequency
should be high enough so that upper audio frequency
band attenuation is kept to a minimum while providing
To minimize possible EMI radiation, place the LC filter
near the MAX9742 on the PCB.
Table 2 provides some suggested inductor manufac-
turers.
BTL LC Output Filter Design
When using the BTL configuration, optimize the output fil-
ter for fully differential operation (see ꢀigure 9 and Table
3). ꢀollow the design criteria provided for the single-
ended filter except use half the value of the BTL resis-
tance for the output filter calculations. This is because
each half-bridge output sees half of the BTL resistance.
ꢀor example, with a BTL resistance of 8Ω the ideal filter
component values are C = 0.7µꢀ and L = 22.5µH for a
sufficient attenuation at the switching frequency (f ) of
SW
the MAX9742. Once the cutoff frequency is determined,
calculate C using the DC resistance of the speaker
ꢀ
(R
) and a damping ratio (ζ) equal to 0.707. ꢀinally,
SPKR
calculate L using the resulting C value.
ꢀ
ꢀ
When selecting C , use capacitors with DC voltage rat-
ꢀ
ings greater than V
.
DD
ꢀ
ꢀ
maximally flat differential filter response with an approxi-
mate cutoff frequency of 40kHz. Rounding to the nearest
When selecting L , it is important to take into account
ꢀ
the DC resistance, current capabilities, and upper fre-
quency limitations of the inductor. Choosing an induc-
tor with minimum DC resistance minimizes I2R losses
due to the filter inductor and therefore preserves power
efficiency. The inductor current rating should be
greater than the maximum peak output current to pre-
vent the inductor from going into saturation. Output
inductor saturation introduces nonlinearities into the
output signal and therefore increases distortion. The
standard component values yields C = 0.68µꢀ and L =
ꢀ
ꢀ
22µH. Also connect ground-terminated Zobel networks
on each side of the speaker load (see the Zobel Network
section). Ground terminating the Zobel networks pre-
vents excessive peaking in the common-mode frequen-
cy response of the filter.
SINGLE-ENDED OUTPUT FILTER
L
F
OUT_
Table 1. Recommended LC Filter
Component Values for Various Speaker
Loads (fC = 40kHz)
R
SPKR
C
F
DC RESISTANCE OF SPEAKER (Ω)
L (µH)
F
C (µF)
F
4
6
8
22
33
47
0.68
0.47
0.33
NOTE: AN OUTPUT-COUPLING CAPACITOR (C ) IS NEEDED FOR SINGLE-SUPPLY,
OUT
SINGLE-ENDED OUTPUT CONFIGURATION.
ꢀigure 8. Single-Ended LC Output ꢀilter
Table 2. Suggested Inductor Manufacturers
DIMENSIONS
MODEL
MANUFACTURER
Coilcraft
WEBSITE
www.coilcraft.com
DO3340P
CDRH127
11RHBP
12.95mm x 9.4mm x 11.43mm
12.3mm x 12.3mm x 8mm
11mm x 11mm x 13.75mm
12.5mm x 12.5mm x 7.5mm
Sumida
Toko
www.sumida.com
www.tokoam.com
SLꢀ12575
TDK
www.component.tdk.com
______________________________________________________________________________________ 21
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
To maximize the performance of the differential output
filter and minimize EMI radiation, keep the ground con-
the LC filter. ꢀor the BTL configuration, use half of the
BTL resistance for the Zobel network calculations.
Connect a ground-terminated Zobel network on each
side of the BTL resistance to prevent excessive peak-
ing in the common-mode response of the output filter.
nections of the C capacitors close together on the
ꢀ
PCB and place the filter near the MAX9742.
The component ratings for C and L follow the same
ꢀ
ꢀ
ꢀor most applications, R
should have a minimum
ZBL
requirements mentioned in the Single-Ended LC Output
ꢀilter Design (L and C ) section.
power rating of 1/4W or greater. C
should have a
ZBL
ꢀ
ꢀ
voltage rating greater than or equal to V
.
DD
Zobel Network
MAX9742
ꢀor speaker loads that have appreciable amounts of
voice coil inductance (> 33µH), peaking in the frequen-
cy response of the output may occur near the cutoff fre-
quency of the LC filter, which may cause the device to
go into current limit at high output powers. This peaking
is due to the resonant circuit formed by the LC output
filter and complex impedance of the speaker. To nullify
the peaking in the frequency response, connect a
Zobel network (series RC circuit) in parallel with the
speaker load as shown in ꢀigure 10. The Zobel circuit
reduces the peaking by dampening the reactive behav-
ior of the speaker. ꢀor the single-ended output configu-
ration, use the following equations to calculate the
component values for the Zobel network:
Table 3. Recommended Differential LC
Filter Component Values for an 8Ω BTL
Speaker Load (fC = 40kHz)
DC Resistance of Speaker (Ω)
L (µH)
F
C (µF)
F
8
22
0.68
L
F
OUT_
L
SPKR
R
ZBL
R
= 1.2 × R
(Ω)
SPKR
ZBL
SPEAKER
LOAD
C
F
1
C
=
(ꢀ)
R
ZBL
SPKR
C
ZBL
2π × R
× f
C
SPKR
where R
is the value of the Zobel resistor, C
is
ZBL
ZBL
the value of the Zobel capacitor, R
is the DC resis-
SPKR
L
F
tance of the speaker, and f is the cutoff frequency of
C
OUTL
R
ZBL
C
C
F
BRIDGE-TIED-LOAD (BTL) OUTPUT FILTER
L
SPKR
C
ZBL
ZBL
L
F
SPEAKER
LOAD
OUTL
C
R
SPKR
C
C
F
F
R
ZBL
R
SPKR
L
F
OUTR
F
L
F
NOTE: AN OUTPUT-COUPLING CAPACITOR (C ) IS NEEDED FOR SINGLE-SUPPLY,
OUT
OUTR
SINGLE-ENDED OUTPUT CONFIGURATION.
ꢀigure 10. Zobel Network Connections for High-Inductance
Speakers
ꢀigure 9. BTL LC Output ꢀilter
22 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Bootstrap Diode (D
)
capacitor that has an appropriate ripple current rating.
To prevent damage to the output-coupling capacitor,
use the following equation to calculate the required
BOOT
To provide sufficient gate drive voltage to the high-side
transistor of the half-bridge output stage, an external
diode (D
) and capacitor (C
) are needed for
RMS ripple current rating for C
OUT
:
BOOT
BOOT
the internal bootstrapping circuitry (see ꢀigure 2). To
maintain high power efficiencies and maximum output
power at low audio frequencies, use fast-recovery
V
DD
I
=
(A)
RMS_RIPPLE
2.83 × R
SPKR
switching diodes for D
. Silicon diodes equivalent
BOOT
to 1N914, BAS16, or 1N4148 work well.
where I
is the minimum required RMS ripple
RMS_RIPPLE
current rating for C
and R
is the DC resistance
OUT
SPKR
Capacitor (C
BOOT
)
BOOT
capacitor ≥ 0.1µꢀ
of the speaker. The ripple current ratings of capacitors
are frequency dependent, so be sure to select a
capacitor based on its ripple current rating within the
audio frequency range.
ꢀor most applications, use a C
and ≤ 0.22µꢀ. ꢀor proper operation, use capacitors with
low ESR and voltage ratings greater than 7V for C
.
BOOT
Output-Coupling Capacitors
, Single-Ended, Single-Supply Operation)
Select output-coupling capacitors with DC voltage rat-
(C
OUT
ings greater than V
.
DD
The MAX9742 requires output-coupling capacitors for
single-supply operation. Since the MAX9742 outputs
In single-supply operation with single-ended outputs, the
leakage current of C can affect the startup time of
OUT
switch between V
and ground in single-supply opera-
DD
the MAX9742. To minimize startup time delays due to
, use capacitors with leakage current ratings less
tion, there is a DC component equal to 0.5 x V
pre-
DD
C
OUT
than 1µA for C
sent at the outputs. The output-coupling capacitor
blocks this DC component, preventing DC current from
flowing into the load. The output capacitor and the load
resistance of the speaker form a highpass filter. The
-3dB point of the highpass filter can be approximated by:
. See the Startup Time Considerations
OUT
section for more information on optimizing the startup
time of the MAX9742.
Setting V
MID
The voltage present at the MID input biases the internal
amplifiers and should be set to the average value of
DD
1
f
=
(Hz)
−3dB
2π × R
× C
OUT
V
and V
for maximum dynamic range. ꢀor dual-
SS
SPKR
supply operation, connect MID to ground. ꢀor single-
supply operation, set MID to 0.5 x V through an
where f
SPKR
is the -3dB cutoff frequency of the filter,
DD
-3dB
external resistive divider. To minimize power dissipation
while providing enough input bias current for the MID
input, select divider-resistors with values greater than
or equal to 10kΩ and less than or equal to 20kΩ.
Connect a decoupling network between MID and the
SGND plane (see the Supply Bypassing/Layout sec-
tion) to provide a sufficient low- and high-frequency AC
ground for the internal amplifiers. ꢀigure 11 shows the
recommended decoupling networks for bypassing the
MID input.
R
is the DC resistance of the speaker, and C
is
OUT
the value of the output-coupling capacitor. As with the
input capacitor, choose C such that f is well
below the lowest frequency of interest. Setting f
high affects the amplifier‘s low-frequency response.
Select capacitors with low ESR to minimize power loss-
es. Since the output-coupling capacitor has a large
amplitude AC current (resulting average output current
due to the LC filter) flowing through it at high output
powers, it is important to select an output-coupling
OUT
-3dB
too
-3dB
______________________________________________________________________________________ 23
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Multiple-Pole MID Network vs.
Single-Pole VMID Network for Increased PSRR
Performance (Single-Supply Operation)
Soft-Start Capacitor (C
)
SFT
The soft-start capacitor determines the timing for the
soft-start power-up sequencing that minimizes audible
clicks-and-pops during power-up/power-down transi-
tions and when entering/exiting shutdown mode.
Connect a capacitor between SꢀT and ground for
proper operation. ꢀor optimum performance, this
capacitor should equal 0.22µꢀ. Using capacitor values
much smaller than these values degrade click-and-
pop performance and values much greater lengthen
startup time.
A multiple-pole MID network improves PSRR perfor-
mance over a single-pole network. Since the input
amplifiers of the MAX9742 are biased at V
, any
MID
noise coupled into the MID input using the MID bias
network supply appears at the outputs of the MAX9742.
Increasing the number of poles in the MID network pro-
vides further attenuation of low-frequency noise at the
MID input, and therefore, improving the AC PSRR per-
formance of the MAX9742. ꢀigure 11 shows the recom-
mended single-pole and two-pole MID input bias
networks. ꢀigure 12 illustrates the differences of the
MAX9742’s low-frequency AC PSRR performance with
the single-pole and two-pole networks shown in ꢀigure
11.
MAX9742
Startup Time Considerations
At the beginning of the soft-start sequence, the
MAX9742 ensures V
MID
is approximately equal to
OUT_
V
before continuing the soft-start sequence. ꢀor sin-
gle-supply operation with single-ended outputs, the
output-coupling capacitors (C ) are first gradually
OUT
charged up to V
before continuing soft-start
MID
sequencing. This gradual charging up of C
mini-
OUT
SINGLE-POLE NETWORK
mizes audible transients that may appear across the
V
DD
R1
10kΩ
TO
MID
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
C
22µF
C
MID2
1µF
R2
10kΩ
MID1
20
SINGLE SUPPLY
V
= 24V + 500mV
DD
P-P
0
-20
R = 8Ω
L
1-POLE MID NETWORK
TWO-POLE NETWORK
-40
V
DD
-60
R1
10kΩ
-80
R3
10kΩ
2-POLE MID NETWORK
-100
-120
TO
MID
C
10µF
C
10µF
R2
10kΩ
MID1
MID2
10
100
1k
10k
100k
FREQUENCY (Hz)
ꢀigure 11. Recommended MID Input Bias Networks
ꢀigure 12. Comparison of MAX9742 AC PSRR with Single-Pole
and Two-Pole MID Networks
24 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
speaker loads during mode transitions. After C
is
Supply Pumping Effects
OUT
charged up to V
, the MAX9742 concludes the soft-
When using the MAX9742 in the single-ended output
MID
start sequence by precharging C
, C
, and
configuration, the power-supply voltages (V
and
DD
REGLS
BOOT
C
. Once the soft-start sequence is complete, the
V
SS
) may increase if the supplies cannot sink current.
IN
MAX9742 begins normal operation.
This “supply pumping” is primarily due to the inductive
loading of the LC filter and the voice coil inductance of
the speaker. The inductive load connected to the out-
put of the device prevents the output current from
changing instantaneously. When the MAX9742 drives
this inductive load, a continuous current flows at the
output whose value is equal to the running average of
the output switching currents, or in other words, the
amplified audio signal. This averaged current continues
to flow during both switching cycles of the half-bridge,
which means that some of the current is pumped back
towards the opposite power supply. If the respective
supply cannot sink this current, it flows into supply
bypass capacitor causing the voltage across the
capacitor to increase.
ꢀor dual-supply operation, the startup time of the
MAX9742 is primarily dependent on the value of C
since it controls the rate of the soft-start sequencing.
SꢀT
In single-supply operation, the overall startup time is
affected by the values of C , C , C , C
OUT
MID1
MID2
SꢀT
(single-ended outputs) and the value of the resistors
used to bias the MID input. This is because soft-start
power-up sequencing is dependent on the charging-up
of the MID input bias network and the charging rate of
C
. As with dual-supply operation, the startup time is
OUT
also affected by the value of C
since it controls the
SꢀT
rate of the soft-start sequencing. Using the component
values shown in ꢀigure 11 and a C capacitor value
SꢀT
of 0.22µꢀ yields a typical single-supply power-up time
of 1.5s.
The amount of current pumped back into the opposite
supply is proportional to the duty cycle of the switching
period. ꢀor example, if the magnitude of the average
(continuous) current during a single switching cycle is
equal to -1A and the duty cycle of the output is equal to
ꢀor single-supply operation with single-ended outputs,
the leakage current of C
can also affect the startup
OUT
time of the MAX9742. To minimize startup time delays
due to C , use capacitors with leakage current rat-
OUT
25%, this means the V supply provides 0.75A of cur-
SS
ings less than 1µA for C
.
OUT
rent while the V
DD
supply must sink 0.25A. Since the
DD
V
supply cannot sink this current, it flows into the
bypass capacitor causing the V
supply voltage to be
DD
pumped up. ꢀigures 13a and 13b illustrates the contin-
uous output current flow that causes the supply pump-
ing action.
______________________________________________________________________________________ 25
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
I
= DUTY CYCLE x I
AVG
PUMP
V
V
DD
DD
C
C
VDD
VDD
OFF
ON
L
L
F
F
MAX9742
I
AVG
I
AVG
C
C
F
F
OFF
ON
V
V
SS
SS
C
C
VSS
VSS
CASE 1: I FLOWING INTO HALF-BRIDGE CAUSING VOLTAGE ACROSS C
TO INCREASE (DUTY CYCLE < 50%).
AVG
VDD
I
I
= AVERAGE (CONTINUOUS) OUTPUT CURRENT DURING ONE SWITCHING CYCLE.
AVG
= AMOUNT OF CURRENT PUMPED INTO SUPPLY BYPASS CAPACITOR.
PUMP
ꢀigure 13a. Continuous Output Current ꢀlow for Positive Supply Pumping
V
V
DD
DD
C
C
VDD
VDD
OFF
ON
L
L
F
F
I
AVG
I
AVG
C
C
F
F
ON
OFF
V
V
SS
SS
I
= DUTY CYCLE x I
C
C
VSS
PUMP
AVG
VSS
CASE 2: I FLOWING OUT OF HALF-BRIDGE CAUSING VOLTAGE ACROSS C TO INCREASE (DUTY CYCLE > 50%).
AVG
VSS
I
I
= AVERAGE (CONTINUOUS) OUTPUT CURRENT DURING ONE SWITCHING CYCLE.
AVG
= AMOUNT OF CURRENT PUMPED INTO SUPPLY BYPASS CAPACITOR.
PUMP
ꢀigure 13b. Continuous Output Current ꢀlow for Negative Supply Pumping
26 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Worst-case supply pumping occurs at high output pow-
capacitor decreases the supply voltage variations due
to supply pumping. Using large bypass capacitors
helps minimize supply voltage variations by providing
sufficient supply decoupling at low output frequencies.
To prevent the MAX9742 from entering supply overvolt-
age protection mode at low output frequencies (as low
as 20Hz), use supply bypass capacitors with values of
at least 1000µꢀ for dual-supply operation and 660µꢀ for
single-supply operation.
ers with low-frequency signals and small load resis-
tances. Since the period is longer for low-frequency
signals, the continuous output current has more time to
pump up the supply rails during each cycle of the
audio signal. Additionally, for most stereo audio
sources the low-frequency audio content (bass) is pri-
marily monophonic. This means both output channels
are basically equal in magnitude and in phase at low
frequencies causing twice as much pump-up current to
flow into the supply bypass capacitors and therefore
doubling the supply pump-up voltages. Assuming
purely sinusoidal output signals, the worst-case supply
voltage increase due to supply pumping can be
approximated using the following equation:
Alternate Methods for Mitigating Supply Pumping
Using the BTL configuration minimizes the supply
pumping effect since the outputs are driven 180° out-
of-phase with each other. Driving the outputs 180° out-
of-phase causes each half-bridge to pump up and
draw current from opposite supplies, which reduces
the magnitude of the of the supply pumping.
⎛
⎞
V
1
⎛
⎞
SUPPLY
2π2
V
=
×
PUMP_MAX
⎜
⎝
⎟
⎠
⎜
⎟
ꢀor the single-ended output configuration, the supply
pumping can be minimized by driving the channels
180° out-of-phase and reversing the polarity of one
speaker connection (see ꢀigure 14). Reversing the
polarity of one speaker minimizes any adverse affects
on the audio quality by ensuring that the physical dis-
placement of the speaker cones matches the physical
displacement of the speakers when driven with in
phase signals.
f
× R
× C
SPKR SUPPLY
OUT
⎝
⎠
where V
is the magnitude increase of the
is the nominal voltage magnitude
PUMP_MAX
supply rail, V
SUPPLY
of the respective supply, f
audio signal, and C
is the frequency of the
OUT
is the value of the respec-
SUPPLY
tive supply bypass capacitor. The above equation
shows that increasing the value of the supply bypass
R
F1
C
FBL
V
DD
C
C
IN
IN
R
R
IN1
IN2
FBL
INL-
INL+
+
-
LEFT-CHANNEL
AUDIO INPUT
L
F
-
OUTL
C
F
C
R
R
FBL
F2
+
MAX9742
MID
C
F2
FBR
C
C
IN
R
R
L
F
IN2
IN1
+
-
OUTR
INR+
INR-
+
-
C
F
RIGHT-CHANNEL
AUDIO INPUT
IN
FBR
C
R
FBR
F
A
R
-
V
R
IN_
R
F1
V
SS
= R , R = R
F2
IN1
IN2 F1
DUAL-SUPPLY CONFIGURATION
ꢀigure 14. Circuit Configuration for Minimizing Supply Pumping
______________________________________________________________________________________ 27
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
T-Network for Low THD Performance
at Low Output Powers (Optional)
Output Limiting Diodes (Optional)
In applications where the output can be driven to clip-
ping, a pair of diodes around the feedback capacitor
helps reduce distortion. Clipping is most likely to hap-
pen when driving high-impedance speakers with lower
supply voltages, for example, 8Ω loads with a 24V sin-
gle supply. Diodes such as BAV99, a dual series silicon
switching diode, are a good choice. Connect these
diodes around the feedback capacitor as shown in
ꢀigure 16.
If low THD+N performance is needed at low-output pow-
ers, replace the feedback resistor (R ) in each channel
ꢀ1
with the T-network shown in ꢀigure 15. The T-network
provides additional attenuation of audio band noise,
therefore, providing improved THD+N performance at
lower output powers. Use the following expressions to
select R , R , R , R , and R
:
ꢀ2
IN1 IN2 ꢀ1a ꢀ1b
MAX9742
R
+ R
ꢀ1b
121kΩ + 562kΩ
683kΩ
A
V
ꢀ1a
R
=
=
=
(Ω)
IN1
A
A
V
V
R
= R
(Ω)
IN1
IN2
R
= R
+R
(Ω)
ꢀ1b
ꢀ2
ꢀ1a
C
FB_
where A is the desired voltage gain in V/V. To maxi-
V
mize CMRR and minimize gain mismatch between
channels, use the closest 1% tolerance resistor values
TO IN_-
TO FB_
available for R , R , R , R
, and R .
ꢀ2
IN1 IN2 ꢀ1a ꢀ1b
See the THD+N vs. Output Power With and Without
T-Network plot in the Typical Operating Characteristics
for a comparison of the THD+N performance with and
without the optional T-network.
ꢀigure 16. Connection of Output Limiting Diodes
R
F1a
R
F1b
121kΩ
562kΩ
TO OUT_
C
10pF
FB_2
R
+ R
IN1
F1a
F1b
A =
V
R
R
R
= R + R = 688kΩ
F1a F1b
F2
= R
IN2
IN1
C
FB_1
150pF
FB_
MAX9742
C
IN
R
R
IN1
IN_-
IN_+
NEGATIVE
AUDIO INPUT
TO CLASS D
MODULATOR
C
IN
IN2
POSITIVE
AUDIO INPUT
C
R
F2
FB_1
150pF
681kΩ
TO MID
ꢀigure 15. Optional T-Network for Minimizing THD+N at Low Output Powers
28 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Supply Bypassing/Layout
To maximize output power and minimize distortion,
proper layout and supply bypassing is essential. To
prevent ground-loop-induced noise and minimize noise
due to parasitic ground inductance, use separate
ground planes for input-signal ground connections
(SGND plane) and output-power ground connections
(PGND plane). ꢀor dual-supply applications, connect
MID to the SGND plane. ꢀor single-supply operation,
connect MID to an external voltage-divider and bypass
MID to the SGND plane with a decoupling network (see
ꢀigure 11). This provides a sufficient low- and high-fre-
quency AC ground for the internal amplifiers. Connect
the SGND and PGND planes together at a single point
in the PCB near the MAX9742. Minimize the parasitic
trace inductances and resistances associated with the
Thermal Considerations
Class D amplifiers provide much better efficiency and
thermal performance than a comparable Class AB
amplifier. However, the system’s thermal performance
must be considered with realistic expectations along
with its many parameters.
Continuous Sine Wave vs. Music
When a Class D amplifier is evaluated in the lab, often
a continuous sine wave is used as the signal source.
While this is convenient for measurement purposes, it
represents a worst-case scenario for thermal loading
on the amplifier. It is not uncommon for a Class D
amplifier to enter thermal shutdown if driven near maxi-
mum output power with a continuous sine wave. The
PCB must be optimized for best dissipation (see the
PCB Thermal Considerations section). Audio content,
both music and voice, has a much lower RMS value rel-
ative to its peak output power. Therefore, while an
audio signal may reach similar peaks as a continuous
sine wave, the actual thermal impact on the Class D
amplifier is highly reduced. If the thermal performance
of a system is being evaluated, it is important to use
actual audio signals instead of sine waves for testing. If
sine waves must be used, the thermal performance is
less than the system’s actual capability for real music
or voice.
V
and V connections, by using wide traces of min-
SS
DD
imal length.
Proper power-supply bypassing is essential to ensure
low distortion operation and to prevent excessive sup-
ply pumping when using the single-ended output con-
figuration. ꢀor dual-supply operation, bypass V
and
DD
V
to PGND with 1000µꢀ aluminum electrolytic capac-
SS
itors. V
and V should also be bypassed to PGND
SS
DD
with 0.1µꢀ capacitors as physically close as possible to
and V pins to provide sufficient high-frequency
V
DD
SS
decoupling. Also, connect an additional 1µꢀ capacitor
between V
bypass V
and V . ꢀor single-supply operation,
PCB Thermal Considerations
The exposed paddle is the primary route for conducting
heat away from the IC. With a bottom-side exposed pad-
dle, the PCB and its copper becomes the primary
heatsink for the Class D amplifier. Solder the exposed
paddle to a copper polygon. Add as much copper as
possible from this polygon to any adjacent pin on the
Class D amplifier as well as to any adjacent components,
provided these connections are at the same potential.
DD
SS
to PGND with two 330µꢀ capacitors. V
DD
DD
should also be bypassed to PGND with an additional
0.1µꢀ capacitor as physically close as possible to the
V
DD
pin.
The MAX9742 includes voltage regulators for the inter-
nal amplifiers, logic circuitry, and gate-drive circuitry
that require external bypassing. Bypass REGP and
REGM to the SGND plane with 1µꢀ capacitors. Bypass
REGLS to NSENSE with a 1µꢀ capacitor. Bypass LV
DD
to LGND with a 0.1µꢀ capacitor. The voltage rating
requirements of the external bypass capacitors must
be taken into account. This is especially important
when selecting the REGP and REGM bypass capaci-
tors since the ground-referenced voltages present at
these regulator outputs are dependent on the voltage
applied to the MID input. The minimum required volt-
age ratings for the regulator bypass capacitors are
summarized in Table 4.
Table 4. Minimum Required Voltage
Ratings for Regulator Bypass Capacitors
CAPACITOR
VOLTAGE RATING (V)
C
V
+ 5
- 5
REGP
REGM
REGLS
MID
C
V
MID
7
C
C
5
LVDD
______________________________________________________________________________________ 29
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
These copper paths must be as wide as possible. Each
of these paths contributes to the overall thermal capa-
bilities of the system.
Pin Configuration
TOP VIEW
The copper polygon to which the exposed paddle is
attached should have multiple vias to the opposite side
of the PCB, where they connect to another copper poly-
gon. Make this polygon as large as possible within the
system’s constraints for signal routing.
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
N.C.
N.C.
+
OUTL
OUTL
SUB
OUTR
OUTR
BOOTR
REGLS
NSENSE
INR+
7
Additional improvements are possible if all the traces
from the device are made as wide as possible.
Although the IC pins are not the primary thermal path
out of the package, they do provide a small amount.
The total improvement would not exceed approximately
10%, but it could make the difference between accept-
able performance and thermal problems.
BOOTL
N.C.
MAX9742
INL+
INL-
INR-
FBL
FBR
Auxiliary Heatsinking
If operating in higher ambient temperatures, it is possi-
ble to improve the thermal performance of a PCB with
the addition of an external heatsink. The thermal resis-
tance to this heatsink must be kept as low as possible
to maximize its performance. With a bottom-side
exposed paddle, the lowest resistance thermal path is
on the bottom of the PCB. The topside of the IC is not a
significant thermal path for the device, and therefore, is
not a cost-effective location for a heatsink. Place the
inductor of the external LC output filter in close proximi-
ty to the IC. This not only helps minimize EMI radiation
at the output traces, but also helps draw heat away
from the MAX9742.
TQFN
(6mm × 6mm × 0.8mm)
Chip Information
PROCESS: BCD
30 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Simplified Block Diagram (continued)
R
F1
C
FBL
10V TO 20V
FBL
V
DD
C
C
IN
IN
R
R
IN1
IN2
INL-
INL+
LEFT NEGATIVE
AUDIO INPUT
MAX9742
L
F
CLASS D
MODULATOR AND
HALF-BRIDGE
OUTL
LEFT POSITIVE
AUDIO INPUT
R
ZBL
C
C
R
R
FBL
F2
F2
C
F
C
MID
ZBL
FBR
L
F
CLASS D
MODULATOR AND
HALF-BRIDGE
OUTR
C
C
IN
IN
R
R
IN2
IN1
INR+
INR-
RIGHT POSITIVE
AUDIO INPUT
R
ZBL
C
RIGHT NEGATIVE
AUDIO INPUT
F
CONTROL LOGIC/
POWER-UP
C
ZBL
SEQUENCING
V
SS
FBR
SFT
SHDN
C
FBR
C
ON
SFT
-10V TO -20V
OFF
R
F1
DUAL SUPPLY CONFIGURATION
______________________________________________________________________________________ 31
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Application Circuits/Functional Diagrams
MAX9742
32 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Typical Application Circuits/Functional Diagrams (continued)
______________________________________________________________________________________ 33
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Typical Application Circuits/Functional Diagrams (continued)
MAX9742
34 ______________________________________________________________________________________
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
MAX9742
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. ꢀor the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 35
Single-/Dual-Supply, Stereo 16W,
Class D Amplifier with Differential Inputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. ꢀor the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9742
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
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相关型号：
MAX9742ETX+T
Audio Amplifier, 21W, 2 Channel(s), 1 Func, Bipolar, 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WJJD-1, TQFN-36
MAXIM
MAX9744ETH+
Volume Control Circuit, 2 Channel(s), BICMOS, 7 X 7 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220, TQFN-44
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