MAX9744_V01 [MAXIM]
20W Stereo Class D Speaker Amplifier with Volume Control;
| 型号： | MAX9744_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 20W Stereo Class D Speaker Amplifier with Volume Control |
| 文件： | 总28页 (文件大小：603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4078; Rev 1; 9/08
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
General Description
Features
The MAX9744 20W stereo Class D audio power amplifi-
er provides Class AB amplifier performance with Class
D efficiency, conserving board space and eliminating
the need for a bulky heatsink. This device features sin-
gle-supply operation, adjustable gain, shutdown mode,
a SYNC output, speaker mute, and industry-leading
click-and-pop suppression.
♦ Wide 4.5V to 14V Power-Supply Voltage Range
♦ Filterless Spread-Spectrum Modulation Lowers
Radiated RF Emissions from Speaker Cables
♦ 20W Stereo Output (4Ω, V
= 12V, THD+N = 10%)
DD
2
♦ Integrated Volume Control (I C or Analog)
♦ Low 0.04% THD+N
The MAX9744 features a 64-step dual-mode (analog or
digital), programmable volume control and mute func-
tion. The MAX9744 operates from a 4.5V to 14V single
supply and can deliver up to 20W per channel into a
4Ω speaker with a 14V supply.
The MAX9744 offers two modulation schemes: a fixed-
frequency modulation mode that allows one of several
preset switching frequencies to be selected, and a
spread-spectrum modulation mode that helps to
reduce EMI-radiated emissions.
♦ High 75dB PSRR
♦ High 93% Efficiency
♦ Integrated Click-and-Pop Suppression
♦ Low-Power Shutdown Mode
♦ Short-Circuit and Thermal-Overload Protection
♦ Available in a 44-Pin Thin QFN-EP (7mm x 7mm x
0.8mm)
The MAX9744 features high 75dB PSRR, low 0.04%
THD+N, and SNR in excess of 90dB. Robust short-cir-
cuit and thermal-overload protection prevent device
damage during a fault condition. The MAX9744 is avail-
able in a 44-pin thin QFN-EP (7mm x 7mm x 0.8mm)
package and is specified over the extended -40°C to
+85°C temperature range.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9744ETH+
-40°C to +85°C
44 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
Flat-Panel Televisions
PC Speaker Systems
Multimedia Docking Stations
Pin Configuration appears at end of data sheet.
Simplified Block Diagram
3V TO 3.6V
4.5V TO 14V
MAX9744 EMI WITH FERRITE BEAD FILTERS
MAX9744
(V = 12V, 1m CABLE, 8Ω LOAD)
DD
40
35
VOLUME
CONTROL
EN5022 B LIMIT
BIAS
30
25
20
MUTE
SHUTDOWN
CONTROL
15
10
2
I C
ANALOG
CONTROL
5
SYNC
SYNCOUT
30
60
100
260
240
140 180 220
300
280
OSCILLATOR
80
120 160
200
FREQUENCY (MHz)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
20W Stereo Class D Speaker Amplifier
with Volume Control
ABSOLUTE MAXIMUM RATINGS
PVDD to PGND ....................................................................+16V
44-Pin Thin QFN (derate 37mW/°C above +70°C,
multilayer board) ......................................................2963mW
V
DD
to GND ...........................................................................+4V
FB_, SYNCOUT, SYNC, SDA/VOL, ADDR1,
ADDR2 to GND........................................-0.3V to (V
θ
JA
, Single-Layer Board................................................37°C/W
, Multilayer Board................................................….27°C/W
JA
θ
+ 0.3V)
DD
BOOT_ to V ..........................................................-0.3V to +6V
Continuous Input Current (PVDD, PGND).............................6.4A
Continuous Output Current (OUT_) ......................................3.2A
Continuous Input Current (except OUT_)......................... 20mA
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
BOOT_ to OUT_........................................................-0.3V to +6V
OUT_ to GND ..........................................-0.3V to (PVDD + 0.3V)
PGND to GND .......................................................-0.3V to +0.3V
Any Other Pin to GND ..............................................-0.3V to +4V
OUT_, Short-Circuit Duration......................................Continuous
MAX974
Continuous Power Dissipation (T = +70°C)
A
44-Pin Thin QFN (derate 27mW/°C above +70°C,
single-layer board)...................................................2162mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
PVDD
DD
GND
PGND
OUT_+ and OUT_-, R = ∞, unless otherwise stated, C
= 0.1µF, C
= 2.2µF, C = 0.47µF, R = 20kΩ, R = 20kΩ, spread-
L
BOOT_
BIAS
IN
IN
F_
spectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. T = T
to T , unless oth-
A
MIN
MAX
erwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
GENERAL
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Speaker Amplifier Supply Voltage
Range
PVDD
Inferred from PSRR test
Inferred from PSRR test
4.5
2.7
14
V
V
Supply Voltage Range
V
3.6
35
20
1
DD
I
20
10
DD
Quiescent Current
mA
I
PVDD
VDDSHDN
I
T
T
= +25°C
= +25°C
0.1
0.1
200
1.5
A
A
Shutdown Current
µA
I
1
PVDDSHDN
Turn-On Time
t
ms
V
ON
Common-Mode Bias Voltage
V
BIAS
Input Amplifier Output-Voltage
Swing High
Specified as V
connected to 1.5V
– V , R = 2kΩ
DD OH L
V
20
20
60
1.8
mV
mV
OH
Input Amplifier Output-Voltage
Swing Low
Specified as V – GND, R = 2kΩ
OL L
connected to 1.5V
V
OL
Input Amplifier Output Short-
Circuit Current Limit
mA
Input Amplifier Gain-Bandwidth
Product
GBW
MHz
SPEAKER AMPLIFIERS
Output stage gain
Total gain (Note 2)
29.5
29.5
2
Maximum
volume setting
Gain
A
dB
VMAX
Output Offset
V
T
= 25°C
A
15
mV
OS
2
_______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
ELECTRICAL CHARACTERISTICS (continued)
(V
= 12V, V
= 3.3V, V
L
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
PVDD
DD
GND
PGND
OUT_+ and OUT_-, R = ∞, unless otherwise stated, C
spectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. T = T
= 0.1µF, C
= 2.2µF, C = 0.47µF, R = 20kΩ, R = 20kΩ, spread-
BOOT_
BIAS
IN
IN
F_
to T , unless oth-
A
MIN
MAX
erwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
= 10W, f = 1kHz,
MIN
TYP
MAX
UNITS
P
OUT
IN
93
87
92
88
8Ω load
Filterless
modulation
%
%
P
= 15W, f = 1kHz,
OUT
IN
4Ω load
Efficiency (Note 3)
η
P
= 10W, f = 1kHz,
OUT
IN
8Ω load
PWM
P
= 15W, f = 1kHz,
OUT
IN
4Ω load
R = 8Ω, THD+N = 1%
1.4
1.8
2.6
3.6
8
L
R = 8Ω, THD+N = 10%
L
V
= 5V,
= 1kHz
PVDD
PVDD
PVDD
f
IN
R = 4Ω, THD+N = 1%
L
R = 4Ω, THD+N = 10%
L
R = 8Ω, THD+N = 1%
L
R = 8Ω, THD+N = 10%
10
L
V
= 12V,
= 1kHz
Output Power
P
W
OUT
f
IN
R = 4Ω, THD+N = 1%
L
14
R = 4Ω, THD+N = 10%
L
17
R = 8Ω, THD+N = 1%
L
10
R = 8Ω, THD+N = 10%
L
13
V
= 14V,
f
= 1kHz
IN
R = 4Ω, THD+N = 1%
17.5
22.5
5.5
0.04
L
R = 4Ω, THD+N = 10%
L
Hard Output Current Limit
I
3.9
A
SC
f = 1kHz, R =
8Ω, P
Filterless modulation
PWM
L
Total Harmonic Distortion Plus
Noise
THD+N
%
= 5W,
OUT
0.04
91
f
= 1kHz
IN
Fixed-frequency
modulation, unweighted
P
= 10W,
OUT
Spread-spectrum,
unweighted
R = 8Ω,
filterless
modulation
mode, BW =
22Hz to 22kHz
L
90
94
94
91
81
94
89
dB
Fixed-frequency
modulation, A-weighted
Spread-spectrum,
A-weighted
Signal-to-Noise Ratio
SNR
Fixed-frequency
modulation, unweighted
Spread-spectrum,
unweighted
P
= 10W,
OUT
R = 8Ω, PWM
L
dB
mode, BW =
22Hz to 22kHz
Fixed-frequency
modulation, A-weighted
Spread-spectrum,
A-weighted
_______________________________________________________________________________________
3
20W Stereo Class D Speaker Amplifier
with Volume Control
ELECTRICAL CHARACTERISTICS (continued)
(V
= 12V, V
= 3.3V, V
L
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
PVDD
DD
GND
PGND
OUT_+ and OUT_-, R = ∞, unless otherwise stated, C
spectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. T = T
= 0.1µF, C
= 2.2µF, C = 0.47µF, R = 20kΩ, R = 20kΩ, spread-
BOOT_
BIAS
IN
IN
F_
to T , unless oth-
A
MIN
MAX
erwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1kHz
85
68
Crosstalk
dB
20Hz to 20kHz
MAX974
V
= 2.7V to 3.6V, T = 25°C,
A
DD
68
MUTE = high
PV = 4.5V to 14V
50
83
70
Power-Supply Rejection Ratio
SYNC Frequency
PSRR
dB
DD
f = 1kHz, V
f = 1kHz, V
= 100mV
= 200mV
on V
DD
RIPPLE
P-P
on PVDD
75
RIPPLE
P-P
SYNC = GND
SYNC = unconnected
1020
1280
1200
1440
1355
1640
f
kHz
kHz
SYNC
1200
30
SYNC = V
(spread-spectrum mode)
DD
SYNC = GND
SYNC = unconnected
255
320
300
360
338
410
Class D Switching Frequency
SYNC Frequency Lock Range
f
SW
300
6
SYNC = V
(spread-spectrum mode)
DD
1000
1600
kHz
%
Minimum SYNC Frequency Lock
Duty Cycle
40
60
Maximum SYNC Frequency Lock
Duty Cycle
%
Gain Matching
Full volume (ideal matching for R and R )
0.2
-43
-43
-46
-57
dB
IN
F
Into shutdown
Out of shutdown
Into mute
Peak voltage, 32
samples/second,
A-weighted (Note 4)
Click-and-Pop Level
K
dBV
CP
Out of mute
VOLUME CONTROL
VOL Input Leakage Current
Input Hysteresis
5
µA
mV
V
DC volume control mode
DC volume control mode
DC volume control mode
f = 1kHz, relative to 9.5dB setting
11
9.5dB Gain Voltage
Full Mute Voltage
0.1 x V
0.9 x V
DD
DD
V
Full Mute Attenuation
-115
dB
DIGITAL INPUTS/OUTPUT (SHDN, MUTE, ADDR1, ADDR2, SCLK, SDA/VOL)
Input-Voltage High
Input-Voltage Low
Input Leakage Current
Input Hysteresis
V
0.7 x V
V
IH
DD
V
0.3 x V
V
µA
V
IL
DD
I
LK
T
= +25°C
A
1
SCLK, SDA/VOL
0.1 x V
5
DD
Input Capacitance
Output-Voltage Low
C
V
pF
V
IN
IL
I
= 3mA
0.4
OL
4
_______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
ELECTRICAL CHARACTERISTICS (continued)
(V
= 12V, V
= 3.3V, V
L
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
PVDD
DD
GND
PGND
OUT_+ and OUT_-, R = ∞, unless otherwise stated, C
spectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. T = T
= 0.1µF, C
= 2.2µF, C = 0.47µF, R = 20kΩ, R = 20kΩ, spread-
BOOT_
BIAS
IN
IN
F_
to T , unless oth-
A
MIN
MAX
erwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
DIGITAL INPUT (SYNC)
Input-Voltage High
SYMBOL
CONDITIONS
MIN
2.3
TYP
MAX
UNITS
V
V
V
SYNCIH
Input-Voltage Low
V
0.8
13
SYNCIL
SYNCIN
SYNC Input Leakage
DIGITAL OUTPUT (SYNCOUT)
I
T
= +25°C
7.5
µA
A
V
0.3
-
DD
Output-Voltage High
V
I
= 1mA
V
SYNCOUTIH SOURCE
Output-Voltage Low
V
I
= 1mA
0.3
V
SYNCOUTIL SINK
Rise/Fall Time
C = 10pF
L
50
V/µs
THERMAL PROTECTION
Thermal-Shutdown Threshold
+165
15
°C
°C
Thermal-Shutdown Hysteresis
2
I C TIMING CHARACTERISTICS (Figure 3)
Serial Clock
f
400
kHz
µs
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
0.6
0.6
BUF
Hold Time (Repeated) START
Condition
t
(Note 5)
µs
µs
HD, STA
Repeated START Condition
Setup Time
t
SU, STA
STOP Condition Setup Time
Data Hold Time
t
0.6
0
µs
µs
ns
µs
µs
SU, STO
t
0.9
HD,DAT
Data Setup Time
t
100
1.3
0.6
SU,DAT
SCL Clock Low Period
SCL Clock High Period
t
LOW
t
HIGH
Rise Time of SDA and SCL,
Receiving
20 +
t
(Note 6)
(Note 6)
300
ns
R
0.1C
B
Fall Time of SDA and SCL,
Receiving
20 +
t
300
50
ns
ns
pF
F
0.1C
B
Pulse Width of Spike Suppressed
t
SP
0
Capacitive Load for Each Bus
Line
C
400
B
Note 1: All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
Note 2: See the Gain-Setting Resistors section.
Note 3: Measured on the MAX9744 Evaluation Kit.
Note 4: Testing performed with an 8Ω resistive load connected across BTL output. Mode transitions are controlled by SHDN or
MUTE pin, respectively.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the
SCL’s falling edge.
Note 6: C = total capacitance of one bus line in pF.
B
_______________________________________________________________________________________
5
20W Stereo Class D Speaker Amplifier
with Volume Control
Typical Operating Characteristics
(V
PVDD
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
DD
GND
PGND
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. R = ∞, unless otherwise stated, C
= 2.2µF,
L
BIAS
C
= 0.47µF, R = 20kΩ, R = 20kΩ, spread-spectrum mode, T = +25°C, unless otherwise noted.)
IN
IN
F_
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
100
100
100
PVDD = 12V
PVDD = 12V
PVDD = 12V
R = 4Ω
R = 4Ω
L
L
R = 8Ω
L
MAX974
PWM MODE
FILTERLESS MODULATION
FILTERLESS MODULATION
10
1
10
1
10
1
f
= 6kHz
f
IN
= 6kHz
IN
f
IN
= 6kHz
0.1
0.1
0.1
f
= 1kHz
f = 1kHz
IN
IN
f
= 1kHz
IN
0.01
0.001
0.01
0.01
0.001
f
= 100Hz
8
f
= 100Hz
IN
IN
f
= 100Hz
IN
0.001
0
3
6
9
12
0
2
4
6
8
10 12 14 16 18 20
0
4
12
16
20
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
100
100
100
PVDD = 5V
PVDD = 12V
PVDD = 5V
R = 4Ω
R = 8Ω
R = 4Ω
L
L
L
PWM MODE
PWM MODE
FILTERLESS MODULATION
10
1
10
1
10
1
f
IN
= 6kHz
f
= 6kHz
f
IN
= 6kHz
IN
0.1
0.1
0.1
f
IN
= 1kHz
f
= 1kHz
IN
0.01
0.001
0.01
0.001
0.01
0.001
f
= 1kHz
IN
f
= 100Hz
1
f
IN
= 100Hz
3
IN
f
= 100Hz
IN
0
1
2
3
4
0
6
9
12
0
2
3
4
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
100
100
PVDD = 12V
PVDD = 12V
R = 4Ω
L
R = 8Ω
L
f
= 1kHz
IN
f
= 1kHz
10
1
10
1
IN
FILTERLESS MODULATION
FILTERLESS MODULATION
FFM
FFM
0.1
0.01
0.1
SSM
0.01
SSM
0.001
0.001
0
4
8
12
16
20
0
2
4
6
8
10
12
OUTPUT POWER (W)
OUTPUT POWER (W)
6
_______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Typical Operating Characteristics (continued)
(V
PVDD
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
DD
GND
PGND
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. R = ∞, unless otherwise stated, C
= 2.2µF,
L
BIAS
C
= 0.47µF, R = 20kΩ, R = 20kΩ, spread-spectrum mode, T = +25°C, unless otherwise noted.)
IN
IN
F_
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
100
100
100
PVDD = 12V
PVDD = 12V
PVDD = 12V
R = 4Ω
R = 4Ω
R = 4Ω
L
L
L
PWM MODE
f
= 1kHz
FILTERLESS MODULATION
IN
10
1
10
1
10
1
PWM MODE
OUTPUT POWER = 10W
FFM
OUTPUT POWER = 10W
0.1
0.1
0.1
OUTPUT POWER = 5W
0.01
0.01
0.001
0.01
0.001
OUTPUT POWER = 5W
SSM
4
0.001
0
8
12
16
20
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
100
100
100
PVDD = 5V
PVDD = 12V
PVDD = 12V
R = 4Ω
R = 8Ω
R = 8Ω
L
L
L
FILTERLESS MODULATION
FILTERLESS MODULATION
PWM MODE
10
1
10
1
10
1
OUTPUT POWER = 6W
OUTPUT POWER = 1.5W
OUTPUT POWER = 6W
0.1
0.1
0.1
0.01
0.001
0.01
0.001
0.01
0.001
OUTPUT POWER = 500mW
OUTPUT POWER = 3W
OUTPUT POWER = 3W
10
100
1k
10k
100k
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
100
100
PVDD = 5V
PVDD = 12V
R = 4Ω
R = 4Ω
L
L
PWM MODE
FILTERLESS MODULATION
10
10
1
P
= 5W
OUT
1
0.1
OUTPUT POWER = 500mW
SSM
0.1
0.01
0.001
0.01
0.001
OUTPUT POWER = 1.5W
FFM
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
7
20W Stereo Class D Speaker Amplifier
with Volume Control
Typical Operating Characteristics (continued)
(V
PVDD
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
DD
GND
PGND
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. R = ∞, unless otherwise stated, C
= 2.2µF,
L
BIAS
C
= 0.47µF, R = 20kΩ, R = 20kΩ, spread-spectrum mode, T = +25°C, unless otherwise noted.)
IN
IN
F_
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY vs. OUTPUT POWER
MAX9744 toc19
MAX9744 toc18
100
90
80
70
60
50
5W
100
90
80
70
60
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
1
0
100
PVDD = 12V
FILTERLESS MODULATION
PWM MODE
R = 8Ω
FILTERLESS MODULATION
PWM MODE
L
FILTERLESS MODULATION
MAX974
10
P
= 3W
OUT
1
0.1
FFM
40
30
20
0.01
0.001
SSM
1k
PVDD = 12V
= 1kHz
PVDD = 12V, f = 1kHz, R = 4Ω
IN
L
f
IN
10
0
R = 8Ω
L
0W
0
2
4
6
8
10
0
4
8
12
16
10
100
10k
100k
OUTPUT POWER (W)
(PER CHANNEL)
OUTPUT POWER (W)
FREQUENCY (Hz)
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY vs. SUPPLY VOLTAGE
EFFICIENCY vs. SUPPLY VOLTAGE
MAX9744 toc20
100
90
80
70
60
50
2W
100
95
100
95
FILTERLESS MODULATION
PWM MODE
THD+N = 10%
THD+N = 1%
THD+N = 10%
THD+N = 1%
90
85
80
90
85
80
40
30
20
PVDD = 5V
= 1kHz
R = 4Ω
L
f
= 1kHz
f
= 1kHz
IN
L
IN
L
75
70
75
70
f
IN
R = 8Ω
FILTERLESS MODULATION
R = 4Ω
FILTERLESS MODULATION
10
0
0W
0
0.5
1.0
1.5
2.0
2.5
3.0
4
6
8
10
12
14
4
6
8
10
12
14
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
EFFICIENCY vs. SUPPLY VOLTAGE
OUTPUT POWER vs. SUPPLY VOLTAGE
100
95
90
85
80
75
70
24
f
= 1kHz
f
= 1kHz
IN
L
IN
L
R = 4Ω
PWM MODE
R = 4Ω
PWM MODE
20
16
12
8
THD+N = 10%
THD+N = 1%
THD+N = 10%
THD+N = 1%
4
0
4
6
8
10
12
14
4
6
8
10
12
14
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Typical Operating Characteristics (continued)
(V
PVDD
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
DD
GND
PGND
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. R = ∞, unless otherwise stated, C
= 2.2µF,
L
BIAS
C
= 0.47µF, R = 20kΩ, R = 20kΩ, spread-spectrum mode, T = +25°C, unless otherwise noted.)
IN
IN
F_
A
OUTPUT POWER vs. LOAD RESISTANCE
OUTPUT POWER vs. LOAD RESISTANCE
OUTPUT POWER vs. SUPPLY VOLTAGE
4
3
2
20
16
12
8
16
12
8
PVDD = 5V
f = 1kHz
PWM MODE
PVDD = 12V
f = 1kHz
FILTERLESS MODULATION
R = 8Ω
L
f
= 1kHz
IN
PWM MODE
THD+N = 10%
THD+N = 10%
THD+N = 10%
1
0
4
THD+N = 1%
THD+N = 1%
4
THD+N = 1%
0
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
4
6
8
10
12
14
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
SUPPLY VOLTAGE (V)
CASE TEMPERATURE
vs. OUTPUT POWER
CASE TEMPERATURE
vs. OUTPUT POWER
POWER-SUPPLY REJECTION RATIO (PVDD)
vs. FREQUENCY
75
50
25
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
125
100
75
f
= 1kHz
f
= 1kHz
IN
L
PVDD = 12V
IN
L
R = 8Ω
R = 4Ω
V = 200mV
RIPPLE P-P
PVDD = 14V
PWM MODE
PVDD = 14V
PWM MODE
PVDD = 12V
PWM MODE
PVDD = 12V
PWM MODE
PWM MODE
50
25
0
PVDD = 12V
FILTERLESS MODULATION
PVDD = 12V
FILTERLESS MODULATION
PVDD = 14V
FILTERLESS MODULATION
FILTERLESS MODULATION
PVDD = 14V
FILTERLESS MODULATION
0
2
4
6
8
10
12
10
100
1k
10k
100k
0
3
6
9
12
15
18
OUTPUT POWER (W)
FREQUENCY (Hz)
OUTPUT POWER (W)
EMI WITH FERRITE BEAD FILTERS
(V = 12V, 1m CABLE, 8Ω LOAD)
DD
POWER-SUPPLY REJECTION RATIO (V
vs. FREQUENCY
)
DD
40
35
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
V
= 3.3V
= 100mV
DD
RIPPLE
P-P
EN5022 B LIMIT
30
25
20
PWM MODE
15
10
FILTERLESS MODULATION
5
30
60
100
260
240
140 180 220
300
280
10
100
1k
10k
100k
80
120 160
200
FREQUENCY (Hz)
FREQUENCY (MHz)
_______________________________________________________________________________________
9
20W Stereo Class D Speaker Amplifier
with Volume Control
Typical Operating Characteristics (continued)
(V
PVDD
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
DD
GND
PGND
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. R = ∞, unless otherwise stated, C
= 2.2µF,
L
BIAS
C
= 0.47µF, R = 20kΩ, R = 20kΩ, spread-spectrum mode, T = +25°C, unless otherwise noted.)
IN
IN
F_
A
OUTPUT WAVEFORM
(FILTERLESS MODULATION)
OUTPUT WAVEFORM (PWM)
OUTPUT FREQUENCY SPECTRUM
MAX9744 toc34
MAX9744 toc33
0
-20
FFM MODE
V
= -60dBV
IN
f = 1kHz
MAX974
2V/div
2V/div
2V/div
2V/div
R = 4Ω
L
-40
UNWEIGHTED
-60
LEFT
-80
-100
-120
-140
RIGHT
10
0
5
15
20
FREQUENCY (kHz)
1μs/div
1μs/div
WIDEBAND OUTPUT SPECTRUM
(FIXED-FREQUENCY MODULATION MODE)
WIDEBAND OUTPUT SPECTRUM
(FIXED-FREQUENCY MODULATION MODE)
OUTPUT FREQUENCY SPECTRUM
0
-20
20
0
20
0
RBW = 1kHz
INPUT AC GROUNDED
FILTERLESS MODULATION
RBW = 1kHz
INPUT AC GROUNDED
PWM MODE
SSM MODE
V
= -60dBV
IN
f = 1kHz
R = 4Ω
L
-40
-20
-40
-60
-80
-20
-40
-60
-80
-100
-120
UNWEIGHTED
-60
LEFT
-80
-100
-120
-140
-100
-120
RIGHT
0
5
10
FREQUENCY (kHz)
15
20
0
1
10
100
0
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
WIDEBAND OUTPUT SPECTRUM
WIDEBAND OUTPUT SPECTRUM
(SPREAD-SPECTRUM MODULATION MODE)
(SPREAD-SPECTRUM MODULATION MODE)
20
0
20
0
RBW = 1kHz
INPUT AC GROUNDED
PWM MODE
RBW = 1kHz
INPUT AC GROUNDED
FILTERLESS MODULATION
-20
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
0
1
10
100
0
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
10 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Typical Operating Characteristics (continued)
(V
PVDD
= 12V, V
= 3.3V, V
= V
= 0V, V
= 0V; max volume setting; all speaker load resistors connected between
MUTE
DD
GND
PGND
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. R = ∞, unless otherwise stated, C
= 2.2µF,
L
BIAS
C
= 0.47µF, R = 20kΩ, R = 20kΩ, spread-spectrum mode, T = +25°C, unless otherwise noted.)
IN
IN
F_
A
CROSSTALK vs. FREQUENCY
CROSSTALK vs. AMPLITUDE
TURN-ON/OFF RESPONSE
MAX9744 toc43
0
-20
-40
-60
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= 200mV
RMS
IN
R = 8Ω
L
f = 1kHz
SHDN
2V/div
RIGHT TO LEFT
LEFT TO RIGHT
LEFT TO RIGHT
OUTPUT
-100
-120
RIGHT TO LEFT
10
100
1k
10k
100k
-60 -50 -40 -30 -20 -10
AMPLITUDE (dBV)
0
10 20
100ms/div
FREQUENCY (Hz)
VOLUME CONTROL LEVEL
vs. VOLUME CONTROL VOLTAGE
SUPPLY CURRENT (PVDD)
vs. SUPPLY VOLTAGE
20
16
14
12
10
8
0
-20
VOLUME CONTROL LEVEL
PWM MODE
-40
-60
6
FILTERLESS MODULATION
-80
4
-100
-120
2
0
4
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
(V)
6
8
10
12
14
V
SUPPLY VOLTAGE (V)
VOL
SUPPLY CURRENT (V
vs. SUPPLY VOLTAGE
)
DD
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
30
25
20
15
10
5
0.8
SHUTDOWN CURRENT = I
+ I
PVDD DD
V
DD
= 3.3V
0.7
0.6
0.5
FILTERLESS MODULATION
PWM MODE
0.4
4
3.0
3.2
3.4
3.6
3.8
4.0
6
8
10
12
14
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
______________________________________________________________________________________ 11
20W Stereo Class D Speaker Amplifier
with Volume Control
Pin Description
PIN
NAME
FUNCTION
Left-Channel Positive Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTL+ and OUTL+.
1
BOOTL+
2, 3
4, 5, 29, 30
6, 10, 21, 28
7, 11, 12, 15, 27
8
OUTL+
PVDD
Left-Channel Speaker Output, Positive Phase
Speaker Amplifier Power-Supply Input. Bypass each with a 1µF capacitor to PGND.
Power-Supply Input. Bypass each with a 1µF capacitor to GND.
MAX974
V
DD
GND
Ground
2
SDA/VOL I C Serial Data I/O and Analog Volume Control Input
2
2
I C Serial Clock Input and Modulation Scheme Select. In I C mode (ADDR1 and ADDR2 ≠ GND),
2
9
SCLK/PWM acts as I C serial clock input. When ADDR1 and ADDR2 = GND, set SCLK = 1 for standard PWM
output scheme, or set SCLK = 0 for filterless modulation output scheme.
2
Address Select Input 1. Sets device address for I C address option. Connect ADDR1 and ADDR2
to GND to select analog volume control mode.
13
ADDR1
2
Address Select Input 2. Sets device address for I C address option. Connect ADDR1 and ADDR2
to GND to select Analog Volume Control mode.
14
16
17
ADDR2
INL
Left-Channel Audio Input
Left-Channel Feedback. Connect feedback resistor between FBL and INL to set amplifier gain. See
FBL
the Gain-Setting Resistors section.
Right-Channel Feedback. Connect feedback resistor between FBR and INR to set amplifier gain.
See the Gain-Setting Resistors section.
18
FBR
19
20
INR
Right-Channel Input
BIAS
Common-Mode Bias Voltage. Bypass with a 2.2µF capacitor to GND.
Shutdown Input. Drive SHDN low to disable the audio amplifiers. Connect SHDN to V
high for normal operation.
or drive
DD
22
23
24
SHDN
N.C.
No Connection. Not internally connected.
Mute Input. Drive MUTE high to mute the speaker outputs. Connect MUTE to GND for normal
operation (mute function controls speaker outputs only).
MUTE
Frequency Select and External Clock Input.
SYNC = GND: Fixed-frequency mode with f
= 1200kHz
SYNC
SYNC = Unconnected: Fixed-frequency mode with f
= 1440kHz
SYNC
25
SYNC
SYNC = V : Spread-spectrum mode with f
= 1200kHz 30kHz
SYNC
DD
SYNC = Clocked: Fixed-frequency mode with f
= external clock frequency. f
= 1/4 the
SYNC
SW
value of f
.
SYNC
12 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Pin Description (continued)
PIN
26
NAME
SYNCOUT SYNC Signal Output
FUNCTION
31, 32
OUTR+
Right-Channel Positive Speaker Output
Right-Channel Positive Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTR+ and OUTR+.
33
BOOTR+
34, 35, 39,
43, 44
PGND
OUTR-
Power Ground
36, 37
Right-Channel Negative Speaker Output
Right-Channel Negative Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTR- and OUTR-.
38
BOOTR-
Left-Channel Negative Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTL- and OUTL-.
40
41, 42
—
BOOTL-
OUTL-
EP
Left-Channel Negative Speaker Output
Exposed Pad. The external pad lowers the package’s thermal impedance by providing a direct
heat conduction path from the die to the PCB. Connect the exposed thermal pad to PGND.
modulation scheme uses minimum pulse outputs when
Detailed Description
the audio inputs are at the zero crossing. As the input
voltage increases or decreases, the duration of the
pulse at one output increases while the other output
pulse duration remains the same. This causes the net
The MAX9744 20W filterless, stereo Class D audio
power amplifier offers Class AB performance with Class
D efficiency with a minimal board space solution. The
MAX9744 features a spread-spectrum modulation
scheme offering significant improvements to switch-
mode amplifier technology. This device features analog
or digitally adjustable volume control, externally set
input gain, shutdown mode, SYNC input and output,
mute, and industry-leading click-and-pop suppression.
voltage across the speaker (V
- V
) to change.
OUT+
OUT-
The minimum-width pulse topology reduces EMI and
increases efficiency.
Operating Modes
Fixed-Frequency Modulation Mode
The MAX9744 features two fixed-frequency modes:
300kHz and 360kHz. Connect SYNC to GND to select
300kHz switching frequency; leave SYNC unconnected
to select the 360kHz switching frequency. The
MAX9744 frequency spectrum consists of the fundamen-
tal switching frequency and its associated harmonics
(see the Wideband Output Spectrum graphs in the Typical
Operating Characteristics). For applications where exact
spectrum placement of the switching fundamental is
important, program the switching frequency so that the
harmonics do not fall within a sensitive frequency band
(Table 1). Audio reproduction is not affected by chang-
ing the switching frequency.
The MAX9744 features extensive click-and-pop sup-
pression circuitry that eliminates audible clicks-and-
pops at startup and shutdown.
The MAX9744 features a 64-step, dual-mode (analog
or I2C) volume control and mute function. In analog vol-
ume control mode, the voltage applied to SDA/VOL
sets the volume level. Two address inputs (ADDR1,
ADDR2) set the volume control function between ana-
log and I2C mode and set the slave address. In I2C
mode, there are three selectable slave addresses
allowing for multiple devices on a single bus.
The MAX9744 offers spread-spectrum and fixed-fre-
quency modes of operation with classic PWM or filter-
less modulation output schemes. The filterless
______________________________________________________________________________________ 13
20W Stereo Class D Speaker Amplifier
with Volume Control
Spread-Spectrum Modulation Mode
The MAX9744 features a unique spread-spectrum
mode that flattens the wideband spectral components,
improving EMI emissions that may be radiated by the
speaker and cables. This mode is enabled by setting
SYNCOUT allows several Maxim amplifiers to be cas-
caded (Figure 1). The synchroniHed output minimiHes
interference due to clock intermodulation caused by the
switching spread between single devices. Using
SYNCOUT and SYNC does not affect the audio perfor-
mance of the MAX9744.
SYNC = V
(Table 1). In spread-spectrum mode, the
DD
switching frequency varies randomly by 7.ꢀkꢁH
around the center frequency (300kꢁH). The modulation
scheme remains the same, but the period of the trian-
gle waveform changes from cycle to cycle. Instead of a
large amount of spectral energy present at multiples of
the switching frequency, the energy is now spread over
a bandwidth that increases with frequency. Above a
few megahertH, the wideband spectrum looks like white
noise for EMI purposes. A proprietary amplifier topolo-
gy ensures this does not corrupt the noise floor in the
audio bandwidth.
Filterless Modulation/PWM Modulation
The MAX9744 features two output modulation schemes:
filterless modulation or classic PWM. The MAX9744 out-
put modulation schemes are selectable through
SCLK/PWM when the device is in analog mode (ADDR1
and ADDR2 = GND, Table 2) or through the I2C inter-
face (Table 8). Maxim’s unique, filterless modulation
scheme eliminates the LC filter required by traditional
Class D amplifiers, reducing component count and con-
serving board space and system cost. Although the
MAX9744 meets FCC and other EMI limits with a low-
cost ferrite bead filter, many applications still may want
to use a full LC-filtered output. If using a full LC filter,
audio performance is best with the MAX9744 configured
for classic PWM output.
MAX974
External Clock Mode
The SYNC input allows the MAX9744 to be synchro-
niHed to an external clock or another Maxim Class D
amplifier, creating a fully synchronous system. This
minimiHes clock intermodulation and allocates spectral
components of the switching harmonics to insensitive
frequency bands. Applying a clock signal between
1MꢁH and 1.6MꢁH to SYNC synchroniHes the
MAX9744. The MAX9744 Class D amplifier operates at
1/4 of the SYNC frequency. For example, if SYNC is
1.6MꢁH, the Class D amplifier operates at 400kꢁH.
Switching between schemes, the output is not click-and-
pop protected. To have click-and-pop protection when
switching between output schemes, the device must
enter shutdown mode and be configured to the new out-
put scheme before the startup sequence is finished.
The external SYNC signal can be any CMOS clock
source with a 40% to 60% duty cycle. Spread-spectrum
clocks work well to reduce EMI; therefore, the
SYNCOUT signal from another MAX9744 in spread-
spectrum mode is an excellent SYNC input.
OUTL+
MAX9744
OUTL-
SYNC INPUT
SYNC
Table 1. Operating Modes
OUTR+
OUTR-
SYNC
MODE
f
(kHz)
f
(kHz)
SW
SYNC
Fixed-frequency
modulation
SYNCOUT
GND
1200
300
Fixed-frequency
modulation
Unconnected
1440
360
Spread-spectrum
modulation
V
1200 30
300 7.ꢀ
DD
MAX9709
1000 to
1600
2ꢀ0 to
400
OUT+
Clocked
EXT
SYNC
OUT-
Figure 1. Cascading Two Amplifiers’ External Clock Mode
14 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Table 2. Modulation Scheme Selection
ADDR2
ADDR1
SDA/VOL
SCLK/PWM
FUNCTION
Filterless modulation
Classic PWM (50% duty cycle)
0
0
0
0
Analog volume control
Analog volume control
0
1
Efficiency
Thermal Shutdown
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current-
steering switches and consume negligible additional
power. Any power loss associated with the Class D out-
When the die temperature exceeds the thermal-shut-
down threshold, +165°C (typ), the MAX9744 outputs
are disabled. Normal operation resumes when the die
temperature decreases by a factor equal to the
thermal-shutdown threshold minus the thermal-shut-
down hysteresis, (typically below +150°C). The effect of
thermal shutdown is an output signal turning off for
approximately 3s in most applications, depending on
the thermal time constant of the audio system. Most
applications should never enter thermal shutdown.
Some of the possible causes of thermal shutdown are
too low of a load impedance, bad thermal contact
between the MAX9744’s exposed pad and PCB, high
ambient temperature, poor PCB layout and assembly,
or excessive output overdrive.
2
put stage is mostly due to the I R loss of the MOSFET
on-resistance, and quiescent current overhead.
The theoretical best efficiency of a linear amplifier is
78% at peak output power. Under normal operating lev-
els (typical music reproduction levels), the efficiency
falls below 30%, whereas the MAX9744 exhibits > 80%
efficiency under the same conditions (Figure 2).
Current Limit
When the output current exceeds the current limit, 5.5A
(typ), the MAX9744 disables the outputs and initiates a
220µs startup sequence. The shutdown and startup
sequence is repeated until the output fault is removed.
Since the retry repetition is slow, the average supply
current is low. Most applications do not enter current-
limit mode unless the output is short circuited or incor-
rectly connected.
Shutdown
The MAX9744 features a shutdown mode that reduces
power consumption and extends battery life. Driving
SHDN low places the device in low-power shutdown
mode. Connect SHDN to digital high for normal opera-
tion. In shutdown mode, the outputs are high imped-
ance, SYNCOUT is pulled high, BIAS voltage decays to
zero, and the common-mode input voltage decays to
2
zero. The I C register does not retain its contents dur-
EFFICIENCY
vs. OUTPUT POWER
100
ing shutdown (MAX9744).
Mute Function
The MAX9744 features a clickless-and-popless mute
mode. When the device is muted, the outputs do not
stop switching; only the volume level is muted to the
speaker. Mute only affects the output stage and does
not shut down the device. To mute the MAX9744, drive
MUTE to logic-high. MUTE should be held high during
system power-up and power-down to ensure that pops
caused by circuits before the MAX9744 are eliminated.
To reduce clicks and pops, the device enters or exits
mute at zero crossing.
90
80
70
60
50
40
30
20
10
0
MAX9744
CLASS AB
PVDD = 12V
= 1kHz
R = 4Ω
L
f
IN
0
2
4
6
8
10
OUTPUT POWER (W)
Figure 2. MAX9744 Efficiency vs. Class AB Efficiency
______________________________________________________________________________________ 15
20W Stereo Class D Speaker Amplifier
with Volume Control
to 400kHz. Figure 3 shows the 2-wire interface timing
Volume Control
For maximum flexibility, the MAX9744 features volume
control operation using an analog voltage input or
diagram. The MAX9744 is a receive-only slave device,
relying on the master to generate the SCL signal. The
MAX9744 cannot write to the SDA bus except to
acknowledge the receipt of data from the master. The
master, typically a microcontroller, generates SCL and
initiates data transfer on the bus.
2
through the I C interface. To set the device to analog
mode, connect ADDR1 and ADDR2 to GND. In analog
mode, SDA/VOL is an analog input for volume control.
The analog input range is ratiometric between 0.9 x
V
and 0.1 x V
DD
where 0.9 x V
= full mute and 0.1
DD
x V
DD
DD
A master device communicates to the MAX9744 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or Repeated START (Sr) condition and a STOP (P) condi-
tion. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
= full volume (Table 7).
MAX974
Use ADDR1 and ADDR2 to select I2C mode. There are
three addresses that can be chosen, allowing for multi-
ple devices on a single bus (Table 4). In I2C mode, vol-
ume is controlled by choosing the speaker volume
control register in the command byte (Table 5). There
are 64 volume settings, where the lowest setting is full
mute (Table 6). See the Write Byte section for more
information on formatting data and tables to set volume
levels. The default volume after power-up is position 40
(-7.1dB) (see Table 7).
The MAX9744 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9744 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. The SCL and SDA
inputs have Schmitt trigger and filter circuits that sup-
press noise spikes to assure proper device operation
even on a noisy bus.
2
I C Interface
2
The MAX9744 features an I C 2-wire serial interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate communication
between the MAX9744 and the master at clock rates up
SDA
t
BUF
t
t
SU, STA
SU, DAT
t
t
SP
HD, STA
t
SU, STO
t
t
HD, DAT
LOW
SCL
t
HIGH
t
HD, STA
t
t
F
R
START
CONDITION
REPEATED
START
STOP
CONDITION
START
CONDITION
CONDITION
Figure 3. 2-Wire Serial-Interface Timing Diagram
16 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
Early STOP Conditions
The MAX9744 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Slave Address
The slave address of the MAX9744 is 8 bits and con-
sists of 3 fields: the first field is 5 bits wide and is fixed
(10010), the second is a 2 bit field which is set through
ADDR1 and ADDR2 (externally connected as logic-high
or logic-low), and the third field is a R/W flag bit. Set
R/W = 0 to write to the slave. A representation of the
slave address is shown in Table 3.
START and STOP Conditions
A master device initiates communication by issuing a
START condition. A START condition is a high to low
transition on SDA with SCL high. A STOP condition is a
low to high transition on SDA while SCL is high (Figure
4). A START (S) condition from the master signals the
beginning of a transmission to the MAX9744. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP (P) condition. The bus remains active if a
Repeated START (Sr) condition is generated instead of
a STOP condition.
When ADDR1 and ADDR2 are connected to GND, seri-
al interface communication is disabled. Table 4 sum-
marizes the slave address of the device as a function of
ADDR1 and ADDR2.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9744 uses to handshake receipt of each byte of
data (see Figure 5). The MAX9744 pulls down SDA dur-
ing the master-generated 9th clock pulse. The SDA line
must remain stable and low during the high period of
the acknowledge clock pulse. Monitoring ACK allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may reat-
tempt communication.
S
Sr
P
SCL
SDA
Figure 4. START, STOP, and Repeated START Conditions
Table 3. Slave Address Block
SA7 (MSB)
SA6
SA5
SA4
SA3
SA2
SA1
SA0 (LSB)
1
0
0
1
0
ADDR2
ADDR1
R/W
Table 4. Slave Address
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
ADDR2
ADDR1
SLAVE ADDRESS
2
0
0
1
1
0
1
0
1
I C disabled
SCL
1
2
8
9
1001001_
1001010_
1001011_
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 5. Acknowledge
______________________________________________________________________________________ 17
20W Stereo Class D Speaker Amplifier
with Volume Control
Write Byte
A write to the MAX9744 includes transmission of a
WRITE BYTE FORMAT
START condition, the slave address with the R/W bit set
to 0 (see Table 3), one byte of data to the command
register, and a STOP condition. Figure 6 illustrates the
proper format for one frame.
S
SLAVE
ADDRESS
7 BITS
WR
0
ACK
DATA
ACK
P
8 BITS
A write to the MAX9744 consists of a 6-step sequence
as seen below:
SLAVE ADDRESS:
DATA BYTE: GIVES A COMMAND.
EQUIVALENT TO CHIP-
SELECT LINE OF A
3-WIRE INTERFACE.
9
1) The master sends a START condition.
2) The master sends the 7 bits slave ID plus a write
Figure 6. Write Byte Format Example
bit (low).
3) The addressed slave asserts an ACK on the data
Filterless Modulation/PWM
The MAX9744 features two output modulation schemes:
filterless modulation or classic PWM, selectable through
the I2C interface. Table 6 shows the register command
to set the output scheme.
line.
4) The master sends 8 data bits.
5) The active slave asserts an ACK (or NACK) on the
data line.
When switching between schemes, the output is not
click-and-pop protected. To have click-and-pop protec-
tion when switching between output schemes, the
device must enter shutdown mode and be configured
to the new output scheme before the 220ms startup
sequence is terminated.
6) The master generates a stop condition.
Speaker Volume Control
The command register is used to control the volume
level of the speaker amplifier. The two MSBs (A1 and
A0) are set to 00, while V5–V0 is the data that is written
into the addresses register to set the volume level
(Tables 5 and 6).
Table 5. Data Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
A1
A0
V5
V4
V3
V2
V1
V0
Table 6. Command Register Programming
A A
0
V5–V0
SETTING
Reserved
A A
0
V5–V0
XXXXXX
000000
000001
SETTING
Volume level (Table 7)
Filterless modulation
Classic PWM
1
1
10
11
11
XXXXXX
000100
000101
00
01
01
Increased volume
Decreased volume
18 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Table 7. Speaker Volume Levels
SDA/VOL
VOLUME
VOLUME
POSITION
V5
V4
V3
V2
V1
V0
VOLUME INPUT VOLTAGE (V)
ATTENUATION (dB)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
0.100 x V
0.113 x V
0.125 x V
0.138 x V
0.151 x V
0.163 x V
0.176 x V
0.189 x V
0.202 x V
0.214 x V
0.227 x V
0.240 x V
0.252 x V
0.265 x V
0.278 x V
0.290 x V
0.303 x V
0.316 x V
0.329 x V
0.341 x V
0.354 x V
0.367 x V
0.379 x V
0.392 x V
0.405 x V
0.417 x V
0.430 x V
0.443 x V
0.456 x V
0.468 x V
0.481 x V
0.494 x V
9.5
8.8
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
8.2
7.6
7.0
6.5
5.9
5.4
4.9
4.4
3.9
3.4
2.9
2.4
2.0
1.6
1.2
0.5
-0.5
-1.9
-3.4
-5.0
-6.0
-7.1
-8.9
-9.9
-10.9
-12.0
-13.1
-14.4
-15.4
-16.4
______________________________________________________________________________________ 19
20W Stereo Class D Speaker Amplifier
with Volume Control
Table 7. Speaker Volume Levels (continued)
SDA/VOL
VOLUME
ATTENUATION (dB)
-17.5
VOLUME
POSITION
V5
V4
V3
V2
V1
V0
VOLUME INPUT VOLTAGE (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1`
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
0.506 x V
0.519 x V
0.532 x V
0.544 x V
0.557 x V
0.570 x V
0.583 x V
0.595 x V
0.608 x V
0.621 x V
0.633 x V
0.646 x V
0.659 x V
0.671 x V
0.684 x V
0.697 x V
0.710 x V
0.722 x V
0.735 x V
0.748 x V
0.760 x V
0.773 x V
0.786 x V
0.798 x V
0.811 x V
0.824 x V
0.837 x V
0.849 x V
0.862 x V
0.875 x V
0.887 x V
0.900 x V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
-19.7
-21.6
-23.5
MAX974
-25.2
-27.2
-29.8
-31.5
-33.4
-36.0
-37.6
-39.6
-42.1
-43.7
-45.6
-48.1
-50.6
-54.2
-56.7
-60.2
-62.7
-66.2
-68.7
8
-72.2
7
-74.7
6
-78.3
5
-80.8
4
-84.3
3
-86.8
2
-90.3
1
-92.8
0
MUTE
20 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Inductor-Based Output Filters
Some applications use the MAX9744 with a full induc-
Applications Information
Filterless Class D Operation
The MAX9744 meets common EMC radiation limits with-
out a filter when the speaker leads are less than approxi-
mately 10cm. Using lengths beyond 10cm is possible
verifying against the appropriate EMC standard.
tor/capacitor-based (LC) output filter. This is common
for longer speaker lead lengths and to gain increased
margin to EMC limits. Select the PWM output mode and
use fixed-frequency modulation mode for best audio
performance. See Figure 8 for the correct connections
of these components.
For longer speaker wire lengths, up to approximately
1m, use a simple ferrite bead and capacitor filter to
meet EMC limits. Select a ferrite bead with 100Ω to
600Ω impedance, and rated for at least 3A. The capaci-
tor value varies based on the ferrite bead chosen and
the actual speaker lead length. Select the capacitor
value based on EMC performance. See Figure 7 for the
correct connections of these components.
The component selection is based on the load imped-
ance of the speaker. Table 8 lists suggested values for
a variety of load impedances.
Inductors L1 and L2 and capacitor C1 form the primary
output filter. In addition to these primary filter compo-
nents, other components in the filter improve its func-
tionality. Capacitors C4 and C5 plus resistors R1 and
R2 form a Zobel at the output. A Zobel corrects the out-
put loading to compensate for the rising impedance of
the loudspeaker. Without a Zobel, the filter has a peak
in its response near the cutoff frequency. Capacitors
C2 and C3 provide common-mode noise suppression
to reduce radiated emissions.
When evaluating the device without a filter or a ferrite
bead filter, include a series inductor (68µH for 8Ω load
and 33µH for 4Ω load) to model the actual loudspeak-
er’s behavior. Omitting this inductor reduces the effi-
ciency, the THD+N performance, and the output power
of the MAX9744.
Table 8. Suggested Values for LC filter
BOOT_+
L1, L2
(µH)
C2, C3
(µF)
R1, R2
(Ω)
C4, C5
(µF)
R (Ω)
C1 (µF)
L
C
0.1μF
BOOT
OUT_+
4
6
8
10
15
22
0.47
0.33
0.22
0.47
0.22
0.22
10
15
22
0.47
0.33
0.22
MAX9744
C
470pF
FILT
OUT_-
C
470pF
FILT
C
0.1μF
BOOT
BOOT_-
Figure 7. Ferrite Bead Filter
BOOT+
4
C
BOOT
0.1μF
L1
L2
OUT+
1, 2
MAX9744
C2
C3
C4
C1
R1
R2
R
L
OUT-
14, 18
15
C
0.1μF
BOOT
C5
BOOT-
Figure 8. Output Filter for PWM Mode
______________________________________________________________________________________ 21
20W Stereo Class D Speaker Amplifier
with Volume Control
Choose C that f
is well below the lowest frequen-
-3dB
Component Selection
IN
cy of interest. Use capacitors whose dielectrics have
low-voltage coefficients, such as tantalum or aluminum
electrolytic. Capacitors with high-voltage coefficients,
such as ceramics, may result in increased distortion at
low frequencies.
Gain-Setting Resistors
External feedback resistors set the gain of the
MAX9744. The output stage has an internal 20dB gain
in addition to the externally set input stage gain. Set the
maximum gain by using resistors R and R (Figure 9)
F
IN
as follows:
DC-Coupled Input
The input amplifier can accept DC-coupled inputs that
are biased to the amplifier’s bias voltage. DC-coupling
eliminates input-coupling capacitors, reducing compo-
nent count to potentially one external component. In this
configuration the highpass filtering effect of the capacitors
is lost, allowing low-frequency signals to be amplified.
⎛
⎝
⎞
⎠
R
MAX974
F
A
= −30
V / V
V
⎜
⎟
R
IN
Choose R between 10kΩ and 50kΩ. Note that the
F
actual gain of the amplifier is dependent on the volume
level setting. For example, with the volume set to
+9.5dB, the amplifier gain would be 9.5dB plus 20dB,
Power Supplies
The MAX9744 features separate supplies for each por-
tion of the device, allowing for the optimum combination
of headroom power dissipation and noise immunity. The
speaker amplifier is powered from PVDD and can range
from 4.5V to 14V. The remainder of the device is pow-
assuming R = R .
IN
F
The input amplifier can be configured into a variety of
circuits. The FB terminal is an actual operational ampli-
fier output, allowing the MAX9744 to be configured as a
summing amplifier, a filter, or an equalizer, for example.
ered by V . Power supplies are independent of each
DD
other so sequencing is not necessary. Power may be
supplied by separate sources or derived from a single
higher source using a linear regulator (Figure 10).
Input Capacitor
An input capacitor (C ) in conjunction with the input
IN
impedance of the MAX9744 form a highpass filter that
removes the DC bias from an incoming signal. The AC-
coupling capacitor allows the amplifier to automatically
bias the signal to an optimum DC level. Assuming zero
source impedance, the -3dB point of the highpass filter
is given by:
BIAS Capacitor
BIAS is the output of the internally generated DC bias
voltage. The BIAS bypass capacitor, C
, improves
BIAS
PSRR and THD+N by reducing power supply and other
noise sources at the common-mode bias node, and
also generates the clickless/popless, startup/shutdown,
DC bias waveforms for the speaker amplifiers. Bypass
BIAS with a 2.2µF capacitor to GND.
1
f−3dB
=
2πR C
IN IN
4.5V TO 14.5V
MAX9744
BOOT+
OUT+
IN
PV
DD
AUDIO
INPUT
1μF
1μF
C
IN
R
IN
OUT
3.3V
SHDN
IN
V
DD
MAX1615
VOLUME
CONTROL
9.5dB (max)
MAX9744
R
F
FB
OUT-
GND
BOOT-
GND
Figure 9. Setting Gain
Figure 10. Using a Linear Regulator to Produce 3.3V from a
Higher Power Supply
22 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Use large, low-resistance output traces. Current drawn
from the outputs increase as load impedance decreas-
es. High output trace resistance decreases the power
delivered to the load. Large output, supply, and GND
traces allow more heat to move from the MAX9744 to
the air, decreasing the thermal impedance of the circuit.
Supply Bypassing, Layout,
and Grounding
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in mov-
ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
The MAX9744 thin QFN package features an exposed
thermal pad on its underside. This pad lowers the pack-
age’s thermal resistance by providing a direct heat con-
duction path from the die to the PCB. Connect the
exposed thermal pad to PGND by using a large pad and
multiple vias to the PGND plane. The exposed pad must
be connected to PGND for proper device operation.
Connect all PVDD power supplies together and bypass
with a 1µF capacitor to PGND. Connect all V
power
DD
supplies together and bypass with a 1µF capacitor to
GND. Place a bulk capacitor between PVDD and PGND
if needed.
Pin Configuration
TOP VIEW
32 31 30 29 28 27 26 25 24
33
23
SHDN
PGND
PGND
OUTR-
22
21
20
34
35
36
V
DD
BIAS
19 INR
18 FBR
17 FBL
OUTR- 37
BOOTR- 38
PGND
39
40
MAX9744
16
INL
BOOTL-
15 GND
OUTL- 41
OUTL- 42
14 ADDR2
ADDR1
PGND
PGND
13
43
44
+
12 GND
2
3
4
5
6
7
8
9
10
11
1
TQFN
(7mm x 7mm)
______________________________________________________________________________________ 23
20W Stereo Class D Speaker Amplifier
with Volume Control
Functional Diagrams/Typical Application Circuits
2
I C MODE
3V TO 3.6V
4.5V TO 14V
PVDD
1μF
100μF
1μF
V
DD
MAX974
6, 10, 21, 28
4, 5, 29, 30
R
1
BOOTL+
F
20kΩ
MAX9744
C
0.1μF
BOOT
FBL 17
INL 16
C
IN
R
IN
20kΩ
2, 3 OUTL+
0.47μF
41, 42 OUTL-
40 BOOTL-
C
BOOT
0.1μF
BIAS
VOLUME
CONTROL
C
IN
R
IN
20kΩ
0.47μF
PV
DD
INR 19
FBR 18
33 BOOTR+
C
BOOT
31, 32 OUTR+
36, 37 OUTR-
0.1μF
R
F
20kΩ
MUTE 24
MUTE
C
0.1μF
BOOT
22
8
SHDN
38 BOOTR-
SHUTDOWN
CONTROL
SDA/VOL
SCLK
TO μC
9
2
I C
ADDR1 13
ADDR2 14
ANALOG
CONTROL
V
DD
SYNCOUT
SYNC 25
26
V
DD
OSCILLATOR
20 BIAS
N.C.
23
BIAS
C
2.2μF
BIAS
7, 11, 12,
15, 27
34, 35, 39, 43, 44
PGND
GND
2
(SHOWN IN I C MODE, A = 29.5dB, f
= 17Hz, SPREAD-SPECTRUM MODE, MUTE OFF, SLAVE ADDRESS = 1001011_)
V
-3dB
24 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Functional Diagrams/Typical Application Circuits (continued)
ANALOG MODE
3V TO 3.6V
4.5V TO 14V
PVDD
100μF
1μF
1μF
V
DD
6, 10, 21, 28
4, 5, 29, 30
R
1
BOOTL+
F
20kΩ
MAX9744
C
0.1μF
BOOT
FBL 17
INL 16
C
IN
R
IN
20kΩ
2, 3 OUTL+
0.47μF
41, 42 OUTL-
40 BOOTL-
C
BOOT
0.1μF
BIAS
VOLUME
CONTROL
C
IN
R
IN
20kΩ
0.47μF
PV
DD
INR 19
FBR 18
33 BOOTR+
C
BOOT
31, 32 OUTR+
36, 37 OUTR-
0.1μF
R
F
20kΩ
MUTE 24
MUTE
C
BOOT
22
8
SHDN
SHUTDOWN
CONTROL
38 BOOTR-
V
DD
0.1μF
SDA/VOL
2
I C
SCLK/PWM
9
OUTPUT
MODULATION
ADDR1 13
ADDR2 14
ANALOG
CONTROL
SYNCOUT
SYNC 25
26
V
DD
OSCILLATOR
20 BIAS
N.C.
23
BIAS
C
2.2μF
BIAS
7, 11, 12,
15, 27
34, 35, 39, 43, 44
PGND
GND
(SHOWN IN ANALOG MODE, A = 29.5dB, f
= 17Hz, SPREAD-SPECTRUM MODE, MUTE OFF, SLAVE ADDRESS = 1001011_)
V
-3dB
______________________________________________________________________________________ 25
20W Stereo Class D Speaker Amplifier
with Volume Control
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
E
DETAIL A
(NE-1) X
e
E/2
MAX974
k
e
e
D/2
C
(ND-1) X
D
D2
L
D2/2
b
L
E2/2
C
L
k
E2
C
C
L
L
L
L
e
e
A
A1
A2
PACKAGE OUTLINE,
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
1
21-0144
G
2
26 ______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX974
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE OUTLINE,
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
2
21-0144
G
2
Chip Information
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
44 TQFN-EP T4477-3
21-0144
PROCESS: BICMOS
______________________________________________________________________________________ 27
20W Stereo Class D Speaker Amplifier
with Volume Control
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
3/08
9/08
Initial release
Updated EC table for single pass flow
—
2, 4, 5
MAX974
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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