MAX9763EUI+T [MAXIM]
Audio Amplifier, 3W, 2 Channel(s), 1 Func, BICMOS, PDSO28, 4.40 MM, ROHS COMPLIANT, MO-153AET, TSSOP-28;
| 型号： | MAX9763EUI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Audio Amplifier, 3W, 2 Channel(s), 1 Func, BICMOS, PDSO28, 4.40 MM, ROHS COMPLIANT, MO-153AET, TSSOP-28 复用器 放大器 功率放大器 驱动 |
| 文件： | 总31页 (文件大小：904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2744; Rev 0; 1/03
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
General Description
Features
The MAX9760–MAX9763 family combines a stereo or
mono 3W bridge-tied load (BTL) audio power amplifier,
stereo single-ended headphone amplifier, headphone
sensing, and a 2:1 input multiplexer all in a tiny 28-pin
thin QFN package. These devices operate from a sin-
gle 4.5V to 5.5V supply and feature an industry-leading
100dB PSRR, allowing these devices to operate from
noisy supplies without the addition of a linear regulator.
An ultra-low 0.002% THD+N ensures clean, low-distor-
tion amplification of the audio signal. Patented click-
and-pop suppression eliminates audible transients on
power and shutdown cycles. Power-saving features
ꢀ Industry-Leading, Ultra-High 100dB PSRR
ꢀ PC99/01 Compliant
ꢀ 3W BTL Stereo Speaker Amplifier
ꢀ 200mW Stereo Headphone Amplifier
ꢀ Low 0.002% THD+N
ꢀ Patented Click-and-Pop Suppression
ꢀ ESD-Protected Outputs
ꢀ Low Quiescent Current: 13mA
ꢀ Low-Power Shutdown Mode: 10µA
ꢀ MUTE Function
include low 4mV V
(minimizes DC current drain
OS
through the speakers), low 13mA supply current, and a
10µA shutdown mode. A MUTE function allows the out-
puts to be quickly enabled or disabled.
ꢀ Headphone Sense Input
ꢀ Stereo 2:1 Input Multiplexer
A headphone sense input detects the presence of a
headphone jack and automatically configures the
amplifiers for either speaker or headphone mode. In
speaker mode, the amplifiers can deliver up to 3W of
continuous average power into a 3Ω load. In head-
phone mode, the amplifier can deliver up to 200mW of
continuous average power into a 16Ω load. The gain of
the amplifiers is externally set, allowing maximum flexi-
bility in optimizing output levels for a given load. The
amplifiers also feature a 2:1 input multiplexer, allowing
multiple audio sources to be selected. The multiplexer
can also be used to compensate for limitations in the
frequency response of the loud speakers by selecting
an external equalizer network. The various functions are
controlled by either an I2C-compatible or simple parallel
control interface.
ꢀ Optional 2-Wire, I2C-Compatible or Parallel
Interface
ꢀ Tiny 28-Pin Thin QFN (5mm ✕ 5mm ✕ 0.8mm) and
TSSOP-EP Packages
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 Thin QFN-EP*
28 TSSOP-EP*
MAX9760ETI
MAX9760EUI
*EP = Exposed paddle.
Ordering Information continued at end of data sheet.
Simplified Block Diagram
The MAX9760–MAX9763 are available in either a ther-
mally efficient 28-pin thin QFN package (5mm ✕ 5mm ✕
0.8mm) or a TSSOP-EP package. All devices have ther-
mal overload protection (OVP) and are specified over
the extended -40°C to +85°C temperature range.
SINGLE SUPPLY
4.5V TO 5.5V
LEFT IN1
LEFT IN2
Applications
Notebooks
SE/
BTL
Portable DVD Players
Tablet PCs
RIGHT IN1
RIGHT IN2
PC Audio Peripherals
Camcorders
I2C-
CONTROL
COMPATIBLE
Pin Configurations and Functional Diagrams appear at end
of data sheet.
MAX9760
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND ...........................................................................+6V
Continuous Power Dissipation
SV
SV
PV
to GND .........................................................................+6V
28-Pin Thin QFN (derate 20.8ꢀW/°C above +70°C)....1667ꢀW
28-Pin TSSOP-EP (derate 23.8ꢀW/°C above +70°C) ..1905ꢀW
Operating Teꢀperature Range ...........................-40°C to +85°C
Storage Teꢀperature Range.............................-65°C to +150°C
Junction Teꢀperature......................................................+150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
DD
DD
DD
to V .........................................................................-0.3V
DD
DD
to V
....................................................................... 0.3V
PGND to GND..................................................................... 0.3V
All Other Pins to GND.................................-0.3V to (V + 0.3V)
Continuous Input Current (into any pin except power-supply
DD
and output pins) ............................................................... 20ꢀA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= PV
= 5.0V, GND = PGND = 0V, SHDN = 5V, C
= 1µF, R = R = 15kΩ, R = ∞. T = T
to T
, unless otherwise
MAX
DD
DD
BIAS
IN
F
L
A
MIN
noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
Inferred froꢀ PSRR test
MIN
TYP
MAX
5.5
32
UNITS
Supply Voltage Range
V
/PV
4.5
V
DD
DD
MAX9760/MAX9761
MAX9762/MAX9763
13
7
BTL ꢀode,
HPS = 0V
Quiescent Supply Current
I
18
ꢀA
DD
(I
+ I
)
VDD
PVDD
Single-ended ꢀode, HPS = V
SHDN = GND
7
18
DD
Shutdown Current
Switching Tiꢀe
I
10
10
300
30
160
15
50
µA
µs
SHDN
t
Gain or input switching
SW
C
C
= 1µF
BIAS
BIAS
Turn-On Tiꢀe
t
ꢀs
ON
= 0.1µF
Therꢀal Shutdown Threshold
Therꢀal Shutdown Hysteresis
oC
oC
OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND)
Output Offset Voltage
V
OUT_+ - OUT_-, A = 1V/V
4
32
ꢀV
dB
OS
V
V
= 4.5V to 5.5V
75
100
DD
f = 1kHz, V
=
RIPPLE
82
70
200ꢀV
P-P
Power-Supply Rejection Ratio
PSRR
(Note 2)
f = 20kHz, V
200ꢀV
=
RIPPLE
P-P
R = 8Ω
1
1.4
2.6
3
L
f
= 1kHz,
IN
Output Power
P
W
%
THD+N < 1%,
T
R = 4Ω
L
OUT
= +25°C
A
R = 3Ω
L
P
P
= 1W, R = 8Ω
0.005
0.01
95
OUT
OUT
L
Total Harꢀonic Distortion Plus
Noise
f
= 1kHz, BW =
IN
THD+N
22Hz to 22kHz
= 2W, R = 4Ω
L
Signal-to-Noise Ratio
Slew Rate
SNR
SR
R = 8Ω, P
= 1W, BW = 22Hz to 22kHz
OUT
dB
V/µs
nF
L
1.6
1
Maxiꢀuꢀ Capacitive Load Drive
Crosstalk
C
No sustained oscillations
= 10kHz
L
f
73
dB
IN
2
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(V
= PV
= 5.0V, GND = PGND = 0V, SHDN = 5V, C
= 1µF, R = R = 15kΩ, R = ∞. T = T
to T
, unless otherwise
MAX
DD
DD
BIAS
IN
F
L
A
MIN
noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = V
)
DD
V
= 4.5V to 5.5V
75
106
88
DD
f = 1kHz, V
200ꢀV
=
RIPPLE
Power-Supply Rejection Ratio
Output Power
PSRR
(Note 2)
P-P
dB
f = 20kHz, V
=
RIPPLE
76
200ꢀV
P-P
R = 32Ω
= 1kHz, THD+N <
88
L
f
IN
P
ꢀW
%
OUT
1%, T = +25°C
A
R = 16Ω
L
120
200
P
= 60ꢀW,
OUT
0.002
0.002
92
R = 32Ω
L
Total Harꢀonic Distortion Plus
Noise
f
= 1kHz, BW =
IN
THD+N
22Hz to 22kHz
P
= 125ꢀW,
OUT
R = 16Ω
L
R = 32Ω, BW = 22Hz to 22kHz,
L
Signal-to-Noise Ratio
SNR
SR
dB
V
= 1V
OUT
RMS
Slew Rate
1.8
2
V/µs
nF
Maxiꢀuꢀ Capacitive Load Drive
Crosstalk
C
No sustained oscillations
= 10kHz
L
f
78
dB
IN
STANDBY SUPPLY (SV ) (Note 3)
DD
V
V
= 1.25V, V
= 0V
425
750
15
BIAS
BIAS
DD
SV
DD
Current
I
µA
SVDD
= 2.5V, V
= 5V
DD
BIAS VOLTAGE (BIAS)
BIAS Voltage
V
R
2.35
2
2.5
50
2.65
V
BIAS
Output Resistance
kΩ
BIAS
1
DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN /2)
Input Voltage High
V
V
V
IH
Input Voltage Low
V
0.8
1
IL
Input Leakage Current
HEADPHONE SENSE INPUT (HPS)
I
IN
µA
0.9 x
Input Voltage High
V
V
IH
V
DD
0.7 x
Input Voltage Low
V
V
IL
V
DD
Input Leakage Current
I
IN
1
µA
_______________________________________________________________________________________
3
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(V
= PV
= 5.0V, GND = PGND = 0V, SHDN = 5V, C
= 1µF, R = R = 15kΩ, R = ∞. T = T
to T
, unless otherwise
MAX
DD
DD
BIAS
IN
F
L
A
MIN
noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9760/MAX9762)
Input Voltage High
V
2.6
V
V
IH
Input Voltage Low
V
0.8
IL
Input Hysteresis
0.2
10
V
Input High Leakage Current
Input Low Leakage Current
Input Capacitance
I
V
V
= 5V
= 0V
1
1
µA
µA
pF
V
IH
IN
IN
I
IL
C
IN
OL
OH
Output Voltage Low
Output Current High
V
I
= 3ꢀA
0.4
1
OL
I
V
= 5V
µA
OH
TIMING CHARACTERISTICS (MAX9760/MAX9762)
Serial Clock Frequency
f
400
kHz
µs
SCL
Bus Free Tiꢀe Between STOP
and START Conditions
t
1.3
BUF
START Condition Hold Tiꢀe
START Condition Setup Tiꢀe
Clock Period Low
t
0.6
0.6
1.3
0.6
100
0
µs
µs
µs
µs
ns
µs
HD:STA
t
SU:STA
t
LOW
Clock Period High
t
HIGH
Data Setup Tiꢀe
t
SU:DAT
HD:DAT
Data Hold Tiꢀe
t
(Note 4)
0.9
20 +
Receive SCL/SDA Rise Tiꢀe
Receive SCL/SDA Fall Tiꢀe
Transꢀit SDA Fall Tiꢀe
t
t
t
(Note 5)
(Note 5)
(Note 5)
(Note 6)
300
ns
ns
ns
ns
r
f
f
0.1C
B
20 +
0.1C
300
250
B
20 +
0.1C
B
Pulse Width of Suppressed
Spike
t
50
SP
Note 1: All devices are 100% production tested at +25°C. All teꢀperature liꢀits are guaranteed by design.
Note 2: PSRR is specified with the aꢀplifier inputs connected to GND through R and C
.
IN
IN
Note 3: Refer to the SV
section.
DD
Note 4: A ꢀaster device ꢀust provide a hold tiꢀe of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 5: C = total capacitance of one of the bus lines in picofarads. Device tested with C = 400pF. 1kΩ pullup resistors connected
B
B
froꢀ SDA/SCL to V
.
DD
Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
4
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics
(V
= PV
= 5V, T = +25°C, unless otherwise noted.)
DD
DD
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
1
1
R = 3Ω
R = 4Ω
L
L
R = 3Ω
L
V
A
= 4V/V
A = 2V/V
V
V
A
= 2V/V
0.1
0.1
0.01
0.1
0.01
P
= 500mW
= 1W
P
OUT
P
OUT
P
= 1W
P
= 500mW
OUT
OUT
P
= 250mW
P
OUT
= 500mW
OUT
0.01
= 2.5W
OUT
P
= 2W
100
OUT
P
= 2W
P
= 2.5W
1k
OUT
OUT
P
= 2W
OUT
P
= 1W
100
OUT
0.001
0.001
0.001
10
100
10k
100k
10
1k
FREQUENCY (Hz)
10k
100k
10
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
1
1
1
R = 8Ω
R = 4Ω
R = 8Ω
L
L
L
A
= 4V/V
A
= 4V/V
A
= 2V/V
V
V
V
0.1
0.01
0.1
0.01
0.1
0.01
P
= 250mW
P
= 500mW
OUT
OUT
P
= 250mW
P
= 500mW
OUT
OUT
P
= 250mW
OUT
P
= 500mW
OUT
P
= 2W
OUT
1k
P
= 1W
100
OUT
P
= 1.2W
OUT
P
= 1W
100
OUT
P
= 1W
= 1.2W
OUT
P
OUT
0.001
0.001
0.001
10
10k
100k
10
100
1k
10k
100k
10
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
100
100
100
A = 4V/V
V
L
A
= 2V/V
A
= 2V/V
V
V
R = 3Ω
R = 3Ω
L
R = 4Ω
L
10
10
10
1
1
1
f = 10kHz
f = 1kHz
f = 10kHz
f = 10kHz
0.1
0.1
0.1
f = 20Hz
f = 1kHz
1
f = 1kHz
0.01
0.001
0.01
0.001
0.01
0.001
f = 20Hz
f = 20Hz
0
2
3
4
0
1
2
OUTPUT POWER (W)
3
4
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT POWER (W)
OUTPUT POWER (W)
_______________________________________________________________________________________
5
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
= PV
= 5V, T = +25°C, unless otherwise noted.)
DD
A
DD
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
100
100
100
A
= 4V/V
A
= 2V/V
A
= 4V/V
V
V
V
R = 4Ω
R = 8Ω
R = 8Ω
L
L
L
10
1
10
10
f = 10kHz
1
1
f = 10kHz
f = 1kHz
f = 20Hz
f = 10kHz
0.1
0.01
0.1
0.1
f = 1kHz
f = 1kHz
0.01
0.001
0.01
0.001
f = 20Hz
0.5
f = 20Hz
0.5
0.001
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT POWER (W)
0
1.0
1.5
2.0
0
1.0
1.5
2.0
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)
OUTPUT POWER vs. TEMPERATURE
(SPEAKER MODE)
4
3
2
1
0
4
3
2
1
0
2.0
1.5
1.0
0.5
0
THD+N = 10%
THD+N = 10%
THD+N = 10%
THD+N = 1%
THD+N = 1%
THD+N = 1%
f = 1kHz
f = 1kHz
f = 1kHz
R = 3Ω
R = 4Ω
R = 8Ω
L
L
L
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT POWER vs. LOAD RESISTANCE
(SPEAKER MODE)
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
5
4
3
2
1
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
f = 1kHz
THD+N = 10%
THD+N = 1%
R = 4Ω
L
f = 1kHz
1
10
100
1k
10k
100k
0
0.5
1.0
1.5
2.0
2.5
LOAD RESISTANCE (Ω)
OUTPUT POWER (W)
6
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
= PV
= 5V, T = +25°C, unless otherwise noted.)
DD
DD
A
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPEAKER MODE)
CROSSTALK vs. FREQUENCY
(SPEAKER MODE)
40
50
-40
-50
V
= 200mV
P-P
RIPPLE
V = 200mV
IN P-P
R = 8Ω
L
-60
60
-70
RIGHT TO LEFT
70
-80
-90
80
-100
-110
-120
LEFT TO RIGHT
90
100
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
ENTERING SHUTDOWN (SPEAKER MODE)
EXITING SHUTDOWN (SPEAKER MODE)
MAX9760 toc20
MAX9760 toc21
SHDN
SHDN
2V/div
2V/div
OUT_+
AND OUT_-
OUT_+
AND OUT_-
1V/div
1V/div
OUT_+
- OUT_-
OUT_+
- OUT_-
200mV/div
200mV/div
100ms/div
100ms/div
R = 8Ω
R = 8Ω
L
L
INPUT AC-COUPLED TO GND
INPUT AC-COUPLED TO GND
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
1
ENTERING POWER-DOWN
(SPEAKER MODE)
MAX9760 toc22
R = 16Ω
L
V
A
= 1V/V
V
DD
2V/div
0.1
P
= 25mW
OUT
P
= 50mW
OUT
0.01
OUT_+
AND OUT_-
1V/div
0.001
0.0001
P
= 100mW
100
OUT
OUT_+
- OUT_-
P
= 150mW
10k
OUT
200mV/div
10
1k
100k
100ms/div
R = 8Ω
L
FREQUENCY (Hz)
INPUT AC-COUPLED TO GND
_______________________________________________________________________________________
7
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
= PV
= 5V, T = +25°C, unless otherwise noted.)
DD
A
DD
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
1
R = 32Ω
R = 32Ω
V
R = 16Ω
L
V
L
L
V
A
= 1V/V
A
= 2V/V
A
= 2V/V
0.1
0.1
0.01
0.1
0.01
P
= 25mW
OUT
P
= 25mW
OUT
P
P
= 50mW
P
= 50mW
OUT
OUT
OUT
P
= 25mW
OUT
0.01
0.001
P
= 50mW
OUT
0.001
0.0001
P
= 100mW
P
= 150mW
10k
OUT
OUT
0.001
0.0001
= 100mW
P
= 150mW
100
OUT
P
= 100mW
100
OUT
P
= 150mW
10k
OUT
0.0001
10
100
1k
FREQUENCY (Hz)
100k
10
1k
100k
10
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
100
100
100
A
= 1V/V
A
= 2V/V
A
= 1V/V
V
V
V
R = 32Ω
R = 16Ω
R = 16Ω
L
L
L
10
10
10
1
1
1
f = 10kHz
f = 20Hz
f = 10kHz
f = 10kHz
0.1
0.1
0.1
f = 20Hz
f = 20Hz
0.01
0.001
0.0001
0.01
0.001
0.0001
0.01
0.001
0.0001
f = 1kHz
f = 1kHz
f = 1kHz
75
OUTPUT POWER (mW)
0
50
100
150
200
250
300
0
50
100
150
200
250
300
0
25
50
100
125
OUTPUT POWER (mW)
OUTPUT POWER (mW)
OUTPUT POWER vs. TEMPERATURE
(HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
OUTPUT POWER vs. TEMPERATURE
(HEADPHONE MODE)
150
125
100
75
100
300
250
200
150
100
50
A
= 2V/V
V
R = 32Ω
L
THD+N = 10%
THD+N = 1%
THD+N = 10%
THD+N = 1%
10
f = 1kHz
1
f = 10kHz
f = 20Hz
0.1
50
0.01
0.001
0.0001
25
f = 1kHz
f = 1kHz
R = 32Ω
R = 16Ω
L
L
0
0
-40
-15
10
35
60
85
0
25
50
75
100
125
-40
-15
10
35
60
85
TEMPERATURE (°C)
OUTPUT POWER (mW)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
= PV
= 5V, T = +25°C, unless otherwise noted.)
DD
DD
A
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
600
500
400
300
200
100
0
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
f = 1kHz
THD+N = 10%
THD+N = 1%
R = 32Ω
L
R = 16Ω
L
f = 1kHz
f = 1kHz
1
10
100
1k
10k
0
20
40
60
80
100
0
50
100
150
200
LOAD RESISTANCE (Ω)
OUTPUT POWER (mW)
OUTPUT POWER (mW)
CROSSTALK vs. FREQUENCY
(HEADPHONE MODE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
EXITING SHUTDOWN (HEADPHONE MODE)
MAX9760 toc38
-40
-50
40
50
V
= 200mV
P-P
R = 16Ω
V
= 200mV
P-P
IN
L
RIPPLE
SHDN
2V/div
1V/div
-60
60
-70
-80
70
RIGHT TO LEFT
OUT_+
-90
80
-100
-110
-120
90
HP JACK
200mV/div
LEFT TO RIGHT
100
100ms/div
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
R = 16Ω
L
FREQUENCY (Hz)
INPUT AC-COUPLED TO GND
EXITING POWER-DOWN
(HEADPHONE MODE)
ENTERING SHUTDOWN (HEADPHONE MODE)
MAX9760 toc39
MAX9760 toc40
2V/div
1V/div
V
SHDN
DD
2V/div
OUT_+
OUT_+
1V/div
200mV/div
HP JACK
200mV/div
HP JACK
100ms/div
INPUT AC-COUPLED TO GND
100ms/div
R = 16Ω
L
R = 16Ω
L
INPUT AC-COUPLED TO GND
_______________________________________________________________________________________
9
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
= PV
= 5V, T = +25°C, unless otherwise noted.)
DD
A
DD
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SPEAKER MODE)
ENTERING POWER-DOWN
(HEADPHONE MODE)
MAX9760 toc41
25
20
15
10
5
T
= +85°C
A
V
2V/div
DD
T
= +25°C
A
OUT_+
1V/div
T
= -40°C
A
HP JACK
200mV/div
0
4.50
4.75
5.00
5.25
5.50
100ms/div
R = 16Ω
L
SUPPLY VOLTAGE (V)
INPUT AC-COUPLED TO GND
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
12
10
8
20
15
10
5
T
= +85°C
A
T
= +85°C
A
T
T
= +25°C
A
6
T
= +25°C
A
4
T
= -40°C
A
= -40°C
A
2
0
0
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
EXITING POWER-DOWN
(SPEAKER MODE)
MAX9760 toc46
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
DD
2V/div
OUT_+
AND OUT_-
1V/div
OUT_+
- OUT_-
200mV/div
R = 8Ω
L
f = 1kHz
0
0.25 0.50 0.75 1.00 1.25 1.50
OUTPUT POWER (W)
100ms/div
R = 8Ω
L
INPUT AC-COUPLED TO GND
10 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Pin Description
PIN
NAME
FUNCTION
MAX9760
MAX9761
MAX9762
MAX9763
QFN
TSSOP
26
QFN
TSSOP
—
QFN
TSSOP
26
QFN
TSSOP
—
1
2
3
—
—
3
1
2
3
—
—
3
SDA
Bidirectional Serial Data I/O
µC Interrupt Output
Power Supply
27
—
27
—
INT
28
28
28
28
V
DD
Standby Power Supply. Connect
to a standby power supply that is
always on, or connect to V
DD
4
1
4
1
4
1
4
1
SV
DD
through a Schottky diode and
bypass with 220µF capacitor to
GND. Short to V if clickless
DD
operation is not essential.
Left-Channel Input 1
Left-Channel Input 2
5
6
7
8
2
3
4
5
5
6
7
8
2
3
4
5
5
6
7
8
2
3
4
5
5
6
7
8
2
3
4
5
INL1
INL2
GAINLA Left-Channel Gain Set A
GAINLB Left-Channel Gain Set B
9, 13,
23, 27
6, 10,
20, 24
9, 13, 6, 10, 20, 9, 23,
6, 20, 24 9, 23, 27 6, 20, 24
PGND
Power Ground
23, 27
24
27
Left-Channel Bridged Aꢀplifier
Positive Output. OUTL+ also
serves as the left-channel
10
7
10
7
10
7
10
7
OUTL+
headphone aꢀplifier output.
11, 25
12
8, 22
9
11, 25
12
8, 22
9
11, 25
8, 22
11, 25
8, 22
PV
Output Aꢀplifier Power Supply
DD
Left-Channel Bridged Aꢀplifier
Negative Output
—
—
—
—
OUTL-
Active-Low Shutdown. Connect
14
15
11
12
14
11
14
15
11
12
14
11
SHDN
SHDN to V
for norꢀal operation.
DD
Address Select. A logic high sets
the address LSB to 1, a logic low
sets the address LSB to zero.
—
—
—
—
ADD
HPS
Headphone Sense Input. A logic
high configures the device as a
single-ended headphone aꢀp. A
logic low configures the device as
a BTL speaker aꢀp.
16
13
16
13
16
13
16
13
DC Bias Bypass. See BIAS
Capacitor Selection section for
capacitor selection. Connect
17
18
14
15
17
18
14
15
17
13
14
10
17
13
14
10
BIAS
GND
C
froꢀ BIAS to GND.
BIAS
Ground
______________________________________________________________________________________ 11
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9760
MAX9761
QFN TSSOP
MAX9762
MAX9763
QFN
TSSOP
16
QFN
TSSOP
16
QFN
TSSOP
16
19
20
21
22
19
20
21
22
16
17
18
19
19
20
21
22
19
20
21
22
INR1
INR2
Right-Channel Input 1
Right-Channel Input 2
17
17
17
18
18
18
GAINRA Right-Channel Gain Set A
GAINRB Right-Channel Gain Set B
19
19
19
Right-Channel Bridged Aꢀplifier
Positive Output. OUTR+ also
serves as the right-channel
24
21
24
21
24
21
24
21
OUTR+
headphone aꢀplifier output.
Right-Channel Bridged Aꢀplifier
Negative Output
26
28
—
23
25
—
26
—
—
23
—
—
26
28
12
23
25
9
26
—
12
23
—
9
OUTR-
SCL
N.C.
Serial Clock Line
No Connection. Not internally
connected.
—
—
—
—
—
—
18
15
18
1
15
26
GAINM Mono Gain Set
1
26
—
—
MUTE
Active-High Mute Input
Headphone Enable. A logic high
enables HPS. A logic low disables
HPS and the device is always
—
—
2
27
—
—
2
27
HPS_EN
configured as a BTL speaker aꢀp.
Gain Select. A logic low selects
the gain set by GAIN_A. A logic
high selects the gain set by
GAIN_B.
—
—
—
—
15
28
12
25
—
—
—
—
15
28
12
25
GAINA/B
IN1/2
Input Select. A logic low selects
aꢀplifier input 1. A logic high
selects aꢀplifier input 2.
devices to operate froꢀ noisy digital supplies without
the need for a linear regulator.
Detailed Description
The MAX9760–MAX9763 feature 3W BTL speaker
aꢀplifiers, 200ꢀW headphone aꢀplifiers, input ꢀulti-
plexers, headphone sensing, and coꢀprehensive click-
and-pop suppression. The MAX9760/ MAX9761 are
stereo BTL/headphone aꢀplifiers. The MAX9762/
MAX9763 are ꢀono BTL/stereo headphone aꢀplifiers.
The MAX9760/MAX9762 are controlled through an I2C-
coꢀpatible, 2-wire serial interface. The MAX9761/
MAX9763 are controlled through five logic inputs:
MUTE, SHDN, HPS_EN, GAINA/B, and IN1/2 (see
Selector Guide). The MAX9760–MAX9763 feature
exceptional PSRR (100dB at 1kHz), allowing these
The speaker aꢀplifiers use a BTL configuration. The
signal path is coꢀposed of an input aꢀplifier and an
output aꢀplifier. Resistor R sets the input aꢀplifier’s
IN
gain, and resistor R sets the output aꢀplifier’s gain.
F
The output of these two aꢀplifiers serves as the input to
a slave aꢀplifier configured as an inverting unity-gain
follower. This results in two outputs, identical in ꢀagni-
tude, but 180° out of phase. The overall gain of the
speaker aꢀplifiers is twice the product of the two
aꢀplifier gains (see Gain-Setting Resistor section). A
feature of this architecture is that there is no phase
inversion froꢀ input to output.
12 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Input Multiplexer
Each aꢀplifier features a 2:1 input ꢀultiplexer, allowing
input selection between two stereo sources. Both ꢀulti-
MAX9760
plexers are controlled by bit 1 in the control register
(MAX9760/MAX9762) or by the IN1/2 pin (MAX9761/
MAX9763). A logic low selects input IN_1 and a logic
high selects input IN_2.
15kΩ
30kΩ
IN_1
AUDIO
INPUT
IN_2
The input ꢀultiplexer can also be used to further
expand the nuꢀber of gain options available froꢀ the
MAX9760–MAX9763 faꢀily. Connecting the audio
source to the device through two different input resis-
tors (Figure 1) increases the nuꢀber of gain options
froꢀ two to four (MAX9760/MAX9761) and froꢀ three to
six (MAX9762/MAX9763). Additionally, the input ꢀulti-
plexer allows a speaker equalization network to be
switched into the speaker signal path. This is typically
useful in optiꢀizing acoustic response froꢀ speakers
with sꢀall physical diꢀensions.
Figure 1. Using the Input Multiplexer for Gain Setting
When configured as a headphone (single-ended) aꢀpli-
fier, the slave aꢀplifier is disabled, ꢀuting the speaker
and the ꢀain aꢀplifier drives the headphone. The
MAX9760–MAX9763 can deliver 3W of continuous aver-
age power into a 3Ω load with less than 1% THD+N in
speaker ꢀode, and 200ꢀW of continuous average
power into a 16Ω load with less than 1% THD+N in
headphone ꢀode. These devices also feature therꢀal
overload protection.
Headphone Sense Enable
The HPS pin is enabled by HPS_EN (MAX9762/
MAX9763) or the HPSD bit (MAX9760/MAX9761).
HPSD or HPS_EN deterꢀines whether the device is in
autoꢀatic detection ꢀode or fixed ꢀode operation (see
Tables 1a and 1b).
Mono Mode
The MAX9762/MAX9763 are 3W ꢀono speaker aꢀpli-
fiers, 200ꢀW stereo headphone aꢀplifiers, and a
ꢀixer/attenuator (see the MAX9762/MAX9763 Functional
Diagram). In speaker (ꢀono) ꢀode, the ꢀixer/attenuator
coꢀbines the two stereo inputs (INL_ and INR_) and
attenuates the resultant signal by a factor of 2. This
allows for full reproduction of a stereo signal through a
single speaker, while ꢀaintaining optiꢀuꢀ headrooꢀ.
The resistor connected between GAINM and OUTR+,
sets the gain of the devices in speaker ꢀode (see the
MAX9762 Functional Diagram). This allows the speaker
aꢀplifier to have a different gain and feedback network
froꢀ the headphone aꢀplifier.
Headphone Sense Input (HPS)
A voltage on HPS less than 0.7 ✕ V
sets the device
DD
to speaker ꢀode. A voltage greater than 0.9 ✕ V
dis-
DD
ables the inverting bridge aꢀplifier (OUT_-), which
ꢀutes the speaker aꢀplifier and sets the device into
headphone ꢀode.
For autoꢀatic headphone detection, connect HPS to the
control pin of a 3-wire headphone jack as shown in
Figure 2. With no headphone present, the resistive volt-
age-divider created by R1 and R2 sets the voltage on
HPS to be less than 0.7 ✕ V , setting the device to
DD
speaker ꢀode and the gain setting defaults to GAINA
(MAX9760/MAX9762). When a headphone plug is insert-
ed into the jack, the control pin is disconnected froꢀ the
BIAS
These devices operate froꢀ a single 5V supply, and
feature an internally generated, power-supply indepen-
dent, coꢀꢀon-ꢀode bias voltage of 2.5V referenced to
GND. BIAS provides both click-and-pop suppression
and sets the DC bias level for the audio outputs. BIAS
is internally connected to the noninverting input of each
speaker aꢀplifier (see Typical Application Circuit/
Functional Diagram). Choose the value of the bypass
capacitor as described in the BIAS Capacitor section.
No external load should be applied to BIAS. Any load
lowers the BIAS voltage, affecting the overall perfor-
ꢀance of the device.
tip contact, and HPS is pulled to V
through R1, setting
DD
the device into headphone ꢀode and the gain-setting
defaults to GAINB (MAX9760/MAX9762) (see Gain
Select section). Place a resistor in series with the control
pin and HPS (R3) to prevent any audio signal froꢀ cou-
pling into HPS when the device is in speaker ꢀode.
Shutdown
The MAX9760–MAX9763 feature a 10µA, low-power
shutdown ꢀode that reduces quiescent current con-
suꢀption and extends battery life. The drive aꢀplifiers
and bias circuitry are disabled, the aꢀplifier outputs
(OUT_) go high iꢀpedance, and BIAS is driven to
______________________________________________________________________________________ 13
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
GND. Driving SHDN low places the devices into shut-
V
DD
down ꢀode, disables the interface, and resets the I2C
registers to a default state. A logic high on SHDN
enables the devices.
R1
680kΩ
R3
47kΩ
MAX9760–
MAX9763
HPS
MAX9760/MAX9762 Software Shutdown
A logic high on bit 0 of the SHDN register places the
MAX9760/MAX9762 in shutdown ꢀode. A logic low
enables the device. The digital section of the
MAX9760/MAX9762 reꢀains active when the device is
shut down through the interface. All devices feature a
logic low on the SHDN input.
OUTL+
OUTR+
R2
10kΩ
MUTE
All devices feature a ꢀute ꢀode. When the device is
ꢀuted, the input is disconnected froꢀ the aꢀplifiers.
MUTE does not shut down the device.
Figure 2. HPS Configuration Circuit
Table 1a. HPS Setting (MAX9760/MAX9761)
INPUTS
MAX9760/MAX9762 MUTE
The MAX9760/MAX9762 MUTE ꢀode is selected by
writing to the MUTE register (see the Command Byte
Definitions section). The left and right channels can be
independently ꢀuted.
MAX9760 MAX9762
GAIN
GAIN
MODE
HPSD HPS
SPKR/HP
PATH*
PATH*
0
0
1
X
X
X
X
0
1
BTL
SE
A
M
B
MAX9761/MAX9763 MUTE
The MAX9761/MAX9763 feature an active-high MUTE
input that ꢀutes both channels.
0
B
1
1
BTL
SE
A or B
A or B
M
A or B
Click-and-Pop Suppression
The MAX9760–MAX9763 feature Maxiꢀ’s patented
coꢀprehensive click-and-pop suppression. During
startup and shutdown, the coꢀꢀon-ꢀode bias voltage
of the aꢀplifiers is slowly raꢀped to and froꢀ the DC
bias point using an S-shaped waveforꢀ. In headphone
ꢀode, this waveforꢀ shapes the frequency spectruꢀ,
ꢀiniꢀizing the aꢀount of audible coꢀponents present
at the headphone. In speaker ꢀode, the BTL aꢀplifiers
start up in the saꢀe fashion as in headphone ꢀode.
When entering shutdown, both aꢀplifier outputs raꢀp
to GND quickly and siꢀultaneously. The MAX9760–
MAX9763 can also be connected to a standby power
source that ensures that the device undergoes its full
shutdown cycle even after power has been reꢀoved.
*Note:
A – GAINA path selected
B – GAINB path selected
M – GAINM path selected
A or B – Gain path selected by GAINAB control bit in register
02h
Table 1b. HPS Setting (MAX9762/MAX9763)
INPUTS
MAX9761
GAIN PATH*
MAX9763
GAIN PATH*
MODE
HPSEN HPS
0
X
0
1
BTL
BTL
SE
A or B
A or B
A or B
M
M
1
1
Standby Power Supply (SV
)
DD
A or B
The MAX9760–MAX9763 feature a patented systeꢀ
*Note:
that provides clickless power-down when power is
A or B – Gain path selected by external GAINAB
M – GAINM path selected
inadvertently reꢀoved froꢀ the device. SV
is an
DD
optional secondary supply that powers the device
through its shutdown cycle when V is reꢀoved.
DD
During this cycle, the aꢀplifier output DC level slowly
raꢀps to GND, ensuring clickless power-down. If click-
need to be connected to either a secondary power
supply or reservoir capacitor for norꢀal device opera-
tion. If click-and-pop suppression during power-down
less power-down is required, connect SV
to either a
DD
secondary power supply that is always on, or connect a
reservoir capacitor froꢀ SV to GND. SV does not
is not required, connect SV
to V
directly.
DD
DD
DD
DD
14 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
SDA
SCL
t
BUF
t
t
HD, STA
SU, DAT
t
t
SP
HD, STA
t
SU, STO
t
t
HD, DAT
LOW
t
HIGH
t
HD, STA
t
t
F
R
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 3. 2-Wire Serial Interface Timing Diagram
The clickless power-down cycle only occurs when the
device is in headphone ꢀode. The speaker ꢀode is
inherently clickless, the differential architecture cancels
the DC shift across the speaker. The MAX9760–
MAX9763 BTL outputs are pulled to GND quickly and
siꢀultaneously, resulting in no audible coꢀponents. If
the MAX9760–MAX9763 are only used as speaker
aꢀplifiers, then reservoir capacitors or secondary sup-
plies are not necessary.
S
Sr
P
SCL
SDA
When using a reservoir capacitor, a 220µF capacitor
provides optiꢀuꢀ charge storage for the shutdown
cycle for all conditions. If a sꢀaller reservoir capacitor
Figure 4. START/STOP Conditions
is desired, decrease the size of C
. A sꢀaller C
BIAS
BIAS
causes the output DC level to decay at a faster rate,
increasing the audible content at the speaker, but
reducing the duration of the shutdown cycle.
The MAX9760/MAX9762 SDA and SCL aꢀplifiers are
open-drain outputs requiring a pullup resistor (500Ω or
greater) to generate a logic high voltage. Series resis-
tors in line with SDA and SCL are optional. These series
resistors protect the input stages of the devices froꢀ
high-voltage spikes on the bus lines, and ꢀiniꢀize
crosstalk and undershoot of the bus signals.
Digital Interface
The MAX9760/MAX9762 feature an I2C/SMBus-coꢀpat-
ible 2-wire serial interface consisting of a serial data
line (SDA) and a serial clock line (SCL). SDA and SCL
facilitate bidirectional coꢀꢀunication between the
MAX9760/MAX9762 and the ꢀaster at clock rates up to
400kHz. Figure 3 shows the 2-wire interface tiꢀing dia-
graꢀ. The MAX9760/MAX9762 are transꢀit/receive
slave-only devices, relying upon a ꢀaster to generate a
clock signal. The ꢀaster (typically a ꢀicrocontroller) ini-
tiates data transfer on the bus and generates SCL to
perꢀit that transfer.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA ꢀust reꢀain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions section). SDA and SCL idle high
when the I2C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A ꢀaster device initiates coꢀꢀunication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition froꢀ the ꢀaster signals
the beginning of a transꢀission to the MAX9760/
A ꢀaster device coꢀꢀunicates to the MAX9760/
MAX9762 by transꢀitting the proper address followed
by a coꢀꢀand and/or data words. Each transꢀit
sequence is fraꢀed by a START (S) or REPEATED
START (S ) condition and a STOP (P) condition. Each
r
word transꢀitted over the bus is 8 bits long and is
always followed by an acknowledge clock pulse.
______________________________________________________________________________________ 15
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9760/MAX9762 generate an ACK
when receiving an address or data by pulling SDA low
during the night clock period. When transꢀitting data,
the MAX9760/MAX9762 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
teꢀ fault has occurred. In the event of an unsuccessful
data transfer, the bus ꢀaster should reatteꢀpt coꢀꢀu-
nication at a later tiꢀe.
SCL
SDA
STOP
START
LEGAL STOP CONDITION
SCL
SDA
Slave Address
The bus ꢀaster initiates coꢀꢀunication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9760/
MAX9762 wait for a START condition followed by its
slave address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the ꢀaster
is writing to or reading froꢀ the MAX9760/MAX9762
(R/W = 0 selects the write condition, R/W = 1 selects
the read condition). After receiving the proper address,
the MAX9760/MAX9762 issue an ACK by pulling SDA
low for one clock cycle.
START
ILLEGAL
STOP
ILLEGAL EARLY STOP CONDITION
Figure 5. Early STOP Condition
S
A6
A5
A4
A3
A2
A1
A0
R/W
The MAX9760/MAX9762 have a factory-/user-pro-
graꢀꢀed address. Address bits A6–A2 are preset,
while A0 and A1 is set by ADD. Connect ADD to either
Figure 6. Slave Address Byte Definition
V
, GND, SCL, or SDA to change the last 2 bits of the
DD
MAX9762. The ꢀaster terꢀinates transꢀission by issu-
ing the STOP condition, this frees the bus. If a REPEAT-
ED START condition is generated instead of a STOP
condition, the bus reꢀains active.
slave address (Table 2).
Write Data Format
There are three registers that configure the
MAX9760/MAX9762: the MUTE register, SHDN register,
and control register. In write data ꢀode (R/W = 0), the
register address and data byte follow the device
address (Figure 7).
Early STOP Conditions
The MAX9760/MAX9762 recognize a STOP condition at
any point during the transꢀission except if a STOP con-
dition occurs in the saꢀe high pulse as a START condi-
tion (Figure 5). This condition is not a legal I2C forꢀat,
at least one clock pulse ꢀust separate any START and
STOP conditions.
MUTE Register
The MUTE register (01hex) is a read/write register that
sets the MUTE status of the device. Bit 3 (MUTEL) of
the MUTE register controls the left channel, bit 4
(MUTER) controls the right channel. A logic high ꢀutes
the respective channel, a logic low brings the channel
out of ꢀute.
REPEATED START Conditions
A REPEATED START (S ) condition ꢀay indicate a
r
change of data direction on the bus. Such a change
occurs when a coꢀꢀand word is required to initiate a
SHDN Register
The SHDN register (02hex) is a read/write register that
controls the power-up state of the device. A logic high
in bit 0 of the SHDN register shuts down the device; a
logic low turns on the device. A logic high is required in
bits 2 to 7 to reset all registers to their default settings.
read operation. S ꢀay also be used when the bus
r
ꢀaster is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX9760/
MAX9762 serial interface supports continuous write
operations with or without an S condition separating
r
theꢀ. Continuous read operations require S conditions
r
because of the change in direction of data flow.
16 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
S
ADDRESS
7 BITS
WR ACK
COMMAND
8 BITS
ACK
DATA
ACK
P
1
8 BITS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
REGISTER ADDRESS.
SELECTS REGISTER TO BE
WRITTEN TO.
REGISTER DATA
S
ADDRESS
7 BITS
WR ACK
COMMAND
8 BITS
ACK
S
ADDRESS
WR ACK
DATA
P
1
7 BITS
2
8 BITS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
REGISTER ADDRESS.
SELECTS REGISTER
TO BE READ.
I C SLAVE ADDRESS.
SELECTS DEVICE.
DATA FROM
SELECTED REGISTER
Figure 7. Write/Read Data Format Example
2
Table 4. SHDN Register Format
Table 2. I C Slave Addresses
ADD CONNECTION
I2C ADDRESS
REGISTER
0000 0010
ADDRESS
GND
100 1000
100 1001
100 1010
100 1011
BIT
NAME
VALUE
DESCRIPTION
V
DD
0*
—
Reset device
—
SDA
SCL
7
RESET
1
0*
6
5
4
3
RESET
RESET
RESET
RESET
Table 3. MUTE Register Format
1
Reset device
—
0*
REGISTER
0000 0001
ADDRESS
1
Reset device
—
0*
BIT
7
NAME
VALUE
Don’t Care
Don’t Care
Don’t Care
0*
DESCRIPTION
1
Reset device
—
X
X
X
—
0*
6
—
1
Reset device
—
5
—
0*
Unꢀute right channel
2
1
0
RESET
X
4
3
MUTER
MUTEL
1
Reset device
—
1
Mute right channel
Don’t Care
0*
Unꢀute left channel
0*
1
Norꢀal operation
Shutdown
1
Mute left channel
SHDN
2
1
0
X
X
X
Don’t Care
Don’t Care
Don’t Care
—
—
—
*Default state.
in autoꢀatic headphone detection ꢀode. A logic high
disables the HPS input. Bit 3 (GAINA/B) controls the
gain-select ꢀultiplexer. A logic low selects GAINA. A
logic high selects GAINB. GAINA/B is ignored when
HPS_D = 0. Bit 4 (SPKR/HP) selects the aꢀplifier oper-
ating ꢀode when HPS_D = 1. A logic high selects
speaker ꢀode and a logic low selects headphone
ꢀode.
*Default state.
Control Register
The control register (03hex) is a read/write register that
deterꢀines the device configuration. Bit 1 (IN1/IN2)
controls the input ꢀultiplexer, a logic high selects input
1, a logic low selects input 2. Bit 2 (HPS_D) controls the
headphone sensing. A logic low configures the device
______________________________________________________________________________________ 17
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Table 5. Control Register Format
REGISTER
ADDRESS
0000 0011
V
+1
OUT(P-P)
BIT
7
NAME
VALUE
Don’t Care
Don’t Care
Don’t Care
0*
DESCRIPTION
X
X
X
—
2 x V
V
OUT(P-P)
6
—
5
—
-1
OUT(P-P)
Speaker ꢀode selected
4
3
SPKR/HP
GAINA/B
Headphone ꢀode
selected
1
Figure 8. Bridge-Tied Load Configuration
0*
1
Gain-setting A selected
Gain-setting B selected
Applications Information
Autoꢀatic headphone
detection enabled
0*
BTL Speaker Amplifiers
The MAX9760–MAX9763 feature speaker aꢀplifiers
designed to drive a load differentially, a configuration
referred to as bridge-tied load (BTL). The BTL configu-
ration (Figure 8) offers advantages over the single-
ended configuration, where one side of the load is
connected to ground. Driving the load differentially
doubles the output voltage coꢀpared to a single-
ended aꢀplifier under siꢀilar conditions. Thus, the
devices’ differential gain is twice the closed-loop gain
of the input aꢀplifier. The effective gain is given by:
2
HPS_D
Autoꢀatic headphone
detection disabled
(HPS ignored).
1
0*
1
Input 1 selected
Input 2 selected
—
1
0
IN1/IN2
X
Don’t Care
Read Data Format
In read ꢀode (R/W = 1), the MAX9760/MAX9762 write
the contents of the selected register to the bus. The
direction of the data flow reverses following the
address acknowledge by the MAX9760/MAX9761. The
ꢀaster device reads the contents of all registers,
including the read-only status register. Table 6 shows
the status register forꢀat.
R
F
A
= 2×
VD
R
IN
Substituting 2 x V
for V
into the follow-
OUT(P-P)
OUT(P-P)
ing equations yields four tiꢀes the output power due to
doubling of the output voltage:
Interrupt Output (INT)
The MAX9760/MAX9762 include an interrupt output
(INT) that can indicate to a ꢀaster device that an event
has occurred. INT is triggered when the state of HPS
changes. During norꢀal operation, INT idles high. If a
headphone is inserted/reꢀoved froꢀ the jack and that
action is detected by HPS, INT pulls the line low. INT
reꢀains low until a read data operation is executed.
V
OUT(P−P)
V
=
=
RMS
2 2
2
V
RMS
P
OUT
R
L
Since the differential outputs are biased at ꢀidsupply,
there is no net DC voltage across the load. This eliꢀi-
nates the need for DC-blocking capacitors required for
single-ended aꢀplifiers. These capacitors can be
large, expensive, consuꢀe board space, and degrade
low-frequency perforꢀance.
I2C Compatibility
The MAX9760/MAX9762 are coꢀpatible with existing I2C
systeꢀs. SCL and SDA are high-iꢀpedance inputs; SDA
has an open drain that pulls the data line low during the
ninth clock pulse. The coꢀꢀunication protocol supports
the standard I2C 8-bit coꢀꢀunications. The general call
address is ignored. The MAX9760/MAX9762 addresses
are coꢀpatible with the 7-bit I2C addressing protocol
only. No 10-bit forꢀats are supported.
18 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Table 6. Status Register Format
REGISTER ADDRESS
0000 0000
DESCRIPTION
BIT
NAME
VALUE
0
Device teꢀperature below therꢀal liꢀit
Device teꢀperature exceeding therꢀal liꢀit
OUTR- current below current liꢀit
OUTR- current exceeding current liꢀit
OUTR+ current below current liꢀit
OUTR+ current exceeding current liꢀit
OUTL- current below current liꢀit
OUTL- current exceeding current liꢀit
OUTL+ current below current liꢀit
OUTL+ current exceeding current liꢀit
Device in speaker ꢀode
7
6
5
4
3
2
THRM
1
0
AMPR-
AMPR+
AMPL-
AMPL+
HPSTS
1
0
1
0
1
0
1
0
1
Device in headphone ꢀode
1
0
X
X
Don’t Care
Don’t Care
—
—
When the MAX9760/MAX9762 are configured to auto-
ꢀatically detect the presence of a headphone jack, the
device defaults to gain setting A when the device is in
speaker ꢀode. When the MAX9762/MAX9763 are con-
figured as speaker aꢀplifiers, the gain setting defaults
to the ꢀono setting (GAINM).
where T
is +150°C, T is the aꢀbient teꢀpera-
J(MAX) A
ture, and θ is the reciprocal of the derating factor in
JA
°C/W as specified in the Absolute Maximum Ratings
section. For exaꢀple, θ
+42°C/W.
of the QFN package is
JA
The increase in power delivered by the BTL configura-
tion directly results in an increase in internal power dis-
sipation over the single-ended configuration. The
ꢀaxiꢀuꢀ power dissipation for a given V
given by the following equation:
Single-Ended Headphone Amplifier
The MAX9760–MAX9763 can be configured as single-
ended headphone aꢀplifiers through software or by
sensing the presence of a headphone plug (HPS). In
headphone ꢀode, the inverting output of the BTL
aꢀplifier is disabled, ꢀuting the speaker. The gain is
1/2 that of the device in speaker ꢀode, and the output
power is reduced by a factor of 4.
and load is
DD
2
2V
DD
P
=
DISS(MAX)
2
π R
L
If the power dissipation for a given application exceeds
the ꢀaxiꢀuꢀ allowed for a given package, either reduce
DD
teꢀperature, or add heat sinking to the device. Large
output, supply, and ground PC board traces iꢀprove the
ꢀaxiꢀuꢀ power dissipation in the package.
In headphone ꢀode, the load ꢀust be capacitively
coupled to the device, blocking the DC bias voltage
froꢀ the load (see Typical Application Circuit).
V
, increase load iꢀpedance, decrease the aꢀbient
Power Dissipation and Heat Sinking
Under norꢀal operating conditions, the MAX9760–
MAX9763 can dissipate a significant aꢀount of power.
The ꢀaxiꢀuꢀ power dissipation for each package is
given in the Absolute Maximum Ratings section under
Continuous Power Dissipation or can be calculated by
the following equation:
Therꢀal overload protection liꢀits total power dissipa-
tion in these devices. When the junction teꢀperature
exceeds +160°C, the therꢀal protection circuitry dis-
ables the aꢀplifier output stage. The aꢀplifiers are
enabled once the junction teꢀperature cools by 15°C.
This results in a pulsing output under continuous ther-
ꢀal-overload conditions as the device heats and cools.
T
− T
A
J(MAX)
P
=
DISSPKG(MAX)
θ
JA
______________________________________________________________________________________ 19
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Output-Coupling Capacitor
Component Selection
The MAX9760/MAX9763 require output-coupling
capacitors to operate in single-ended (headphone)
ꢀode. The output-coupling capacitor blocks the DC
coꢀponent of the aꢀplifier output, preventing DC cur-
rent froꢀ flowing to the load. The output capacitor and
the load iꢀpedance forꢀ a highpass filter with a -3dB
point deterꢀined by:
Gain-Setting Resistors
External feedback coꢀponents set the gain of the
MAX9760–MAX9763. Resistor R sets the gain of the
IN
input aꢀplifier (A ) and resistor R sets the gain of
VIN
F
the second stage aꢀplifier (A
):
VOUT
10kΩ
R
F
10kΩ
A
= −
, A
= −
VOUT
VIN
R
IN
1
f
=
−3dB
2πR C
L
OUT
Coꢀbining A
and A
, R and R set the single-
VIN
VOUT IN
F
ended gain of the device as follows:
As with the input capacitor, choose C
-3dB
such that
OUT
f
is well below the lowest frequency of interest.
10kΩ
R
10kΩ
R
F
F
A
= A
× A = −
VOUT
× −
= +
Setting f too high affects the aꢀplifier‘s low-fre-
-3dB
V
VIN
R
R
IN
IN
quency response.
Load iꢀpedance is a concern when choosing C
.
OUT
As shown, the two-stage aꢀplifier architecture results
in a noninverting gain configuration, preserving
absolute phase through the MAX9760–MAX9763. The
gain of the device in BTL ꢀode is twice that of the sin-
Load iꢀpedance can vary, changing the -3dB point of
the output filter. A lower iꢀpedance increases the cor-
ner frequency, degrading low-frequency response.
Select C
such that the worst-case load/C
coꢀ-
OUT
OUT
gle-ended ꢀode. Choose R between 10kΩ and 15kΩ
IN
bination yields an adequate response. Select capaci-
tors with low ESR to ꢀiniꢀize resistive losses and
optiꢀize power transfer to the load.
and R between 15kΩ and 100kΩ.
F
Input Filter
The input capacitor (C ), in conjunction with R , forꢀs
IN
IN
BIAS Capacitor
a highpass filter that reꢀoves the DC bias froꢀ an
incoꢀing signal. The AC-coupling capacitor allows the
aꢀplifier to bias the signal to an optiꢀuꢀ DC level.
Assuꢀing zero-source iꢀpedance, the -3dB point of
the highpass filter is given by:
BIAS is the output of the internally generated 2.5VDC
bias voltage. The BIAS bypass capacitor, C
,
BIAS
iꢀproves PSRR and THD+N by reducing power supply
and other noise sources at the coꢀꢀon-ꢀode bias
node, and also generates the clickless/popless, start-
up/shutdown DC bias waveforꢀs for the speaker aꢀpli-
fiers. Bypass BIAS with a 1µF capacitor to GND.
1
f
=
−3dB
2πR C
IN IN
Supply Bypassing
Proper power-supply bypassing ensures low-noise,
low-distortion perforꢀance. Place a 0.1µF ceraꢀic
Choose R according to the Gain-Setting Resistors
IN
section. Choose the C such that f
is well below
-3dB
IN
capacitor froꢀ V
to GND. Add additional bulk
the lowest frequency of interest. Setting f
too high
DD
-3dB
capacitance as required by the application, typically
100µF. Bypass PV with a 100µF capacitor to GND.
Locate bypass capacitors as close to the device as
possible.
affects the aꢀplifier’s low-frequency response. Use
capacitors whose dielectrics have low-voltage coeffi-
cients, such as tantaluꢀ or aluꢀinuꢀ electrolytic.
Capacitors with high-voltage coefficients, such as
ceraꢀics, ꢀay result in an increased distortion at low
frequencies.
DD
Gain Select
The MAX9760–MAX9763 feature ꢀultiple gain settings
on each channel, ꢀaking available different gain and
Other considerations when designing the input filter
include the constraints of the overall systeꢀ,
the actual frequency band of interest, and click-and-
pop suppression.
feedback configurations. The gain-setting resistor (R )
F
is connected between the aꢀplifier output (OUT_+)
and the gain setpoint (GAIN_). An internal ꢀultiplexer
switches between the different feedback resistors
20 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
GAIN
C
F
R
F2
R
R
F1
IN
R
F1
R
IN
R
F1
R
F2
R
IN
FREQUENCY
V
1
BIAS
2π R
C
F
F2
Figure 10. Bass Boost Response
Figure 9. Bass Boost Circuit
depending on the status of the gain control input. The
stereo MAX9760/MAX9761 feature two gain options per
channel. The ꢀono MAX9762/MAX9763 feature two
gain options per single-ended channel, and a single
gain option for the ꢀono speaker aꢀplifier (see Tables
1a and 1b for the gain-setting options).
Assuꢀing R = R , then R
at low frequencies is
F1
F2
F(EFF)
twice that of R
at high frequencies (Figure 10).
F(EFF)
Thus, the aꢀplifier has ꢀore gain at lower frequencies,
boosting the systeꢀ’s bass response. Set the gain roll-
off frequency based upon the response of the speaker
and enclosure.
The MAX9762 defaults to GAINM in speaker ꢀode and
can switch between GAINA and GAINB in headphone
ꢀode.
Layout and Grounding
Good PC board layout is essential for optiꢀizing perfor-
ꢀance. Use large traces for the power-supply inputs
and aꢀplifier outputs to ꢀiniꢀize losses due to para-
sitic trace resistance, as well as route heat away froꢀ
the device. Good grounding iꢀproves audio perfor-
ꢀance, ꢀiniꢀizes crosstalk between channels, and
prevents any digital switching noise froꢀ coupling into
the audio signal. If digital signal lines ꢀust cross over
or under audio signal lines, ensure that they cross per-
pendicular to each other.
Bass Boost Circuit
Headphones typically have a poor low-frequency
response due to speaker and enclosure size liꢀitations.
A bass boost circuit coꢀpensates the poor low-frequen-
cy response (Figure 9). At low frequencies, the capaci-
tor C is an open circuit, and the effective iꢀpedance in
F
the feedback loop (R
) is R = R .
F(EFF) F(EFF) F1
At the frequency:
The MAX9760–MAX9763 QFN and TSSOP-EP pack-
ages feature exposed therꢀal pads on their under-
sides. This pad lowers the package’s therꢀal
resistance by providing a direct heat conduction path
froꢀ the die to the printed circuit board. Connect the
pad to signal ground by using a large pad, or ꢀultiple
vias to the ground plane.
1
2πR
C
F
F2
where the iꢀpedance, C begins to decrease, and at
F,
high frequencies, the C is a short circuit. Here the
F
iꢀpedance of the feedback loop is:
R
× R
+ R
F1
F2
F2
R
=
F(EFF)
R
F1
______________________________________________________________________________________ 21
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Application Circuit
V
DD
0.1µF
V
PV
DD
DD
0.047µF
BIAS
SV
27.4kΩ
33.2kΩ
15kΩ
DD
1µF
GAINLB
220µF
10kΩ
GAINLA
OUTL+
15kΩ
AUX_IN
BIAS
INL1
INL2
INR1
INR2
OUT
0.68µF
OUTL-
0.68µF
0.68µF
0.68µF
15kΩ
15kΩ
15kΩ
HPF
HPF
MAX4060
CODEC
MAX9760
IN+
IN-
OUTR-
OUTR+
V
DD
220µF
10kΩ
15kΩ
V
GAINRA
GAINRB
DD
33.2kΩ
27.4kΩ
1kΩ
1kΩ
10kΩ
680kΩ
SCL
SDA
ADD
INT
0.047µF
47kΩ
HPS
MICROCONTROLLER
SHDN
22 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Functional Diagrams
V
DD
PV
V
SV
DD
DD
DD
GAINLB
GAINLA
GAIN
SET
MUX
10kΩ
AUDIO
INPUT
AUDIO
INPUT
INL1
INL2
2:1
INPUT
MUX
10kΩ
OUTL+
10kΩ
BIAS
BIAS
10kΩ
OUTL-
GAINRB
GAINRA
GAIN
SET
MUX
10kΩ
AUDIO
INPUT
AUDIO
INPUT
INR1
INR2
2:1
INPUT
MUX
10kΩ
OUTR+
10kΩ
SHDN
SCL
SDA
ADD
INT
10kΩ
OUTR-
HPS
LOGIC
HPS
MAX9760
GND
______________________________________________________________________________________ 23
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Functional Diagrams (continued)
PV
V
SV
DD
DD DD
GAINLB
GAINLA
GAIN
SET
MUX
10kΩ
INL1
INL2
2:1
INPUT
MUX
10kΩ
OUTL+
10kΩ
BIAS
BIAS
10kΩ
OUTL-
GAINRB
GAINRA
GAIN
SET
MUX
10kΩ
INR1
INR2
2:1
INPUT
MUX
10kΩ
OUTR+
10kΩ
SHDN
MUTE
HP_EN
GAINA/B
IN1/IN2
10kΩ
OUTR-
HPS
LOGIC
HPS
MAX9761
GND
24 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Functional Diagrams (continued)
PV
V
SV
DD
DD DD
GAINRB
GAINRA
GAINM
GAIN
SET
MUX
10kΩ
INR1
INR2
2:1
INPUT
MUX
MIXER
10kΩ
OUTR+
10kΩ
BIAS
BIAS
10kΩ
OUTR-
GAINLB
GAINLA
GAIN
SET
MUX
10kΩ
INL1
INL2
2:1
INPUT
MUX
10kΩ
OUTL
HPS
SHDN
SCL
SDA
ADD
INT
LOGIC
HPS
MAX9762
GND
______________________________________________________________________________________ 25
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Functional Diagrams (continued)
PV
V
SV
DD
DD DD
GAINRB
GAINRA
GAINM
GAIN
SET
MUX
10kΩ
INR1
INR2
2:1
INPUT
MUX
MIXER
10kΩ
OUTR+
10kΩ
BIAS
BIAS
10kΩ
OUTR-
GAINLB
GAINLA
GAIN
SET
MUX
10kΩ
INL1
INL2
2:1
INPUT
MUX
10kΩ
OUTL
HPS
SHDN
HP_EN
MUTE
IN1/IN2
GAINA/B
LOGIC
HPS
MAX9763
GND
26 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Pin Configurations
TOP VIEW
TOP VIEW
MUTE
1
2
3
4
5
6
7
21 GAINRA
SDA
INT
1
2
3
4
5
6
7
21 GAINRA
HPS_EN
20
19
INR2
INR1
20
19
INR2
INR1
V
DD
V
DD
SV
18 GND
DD
SV
18 GND
DD
MAX9761
MAX9760
17
16
INL1
INL2
BIAS
HPS
17
16
INL1
INL2
BIAS
HPS
GAINLA
15 GAINA/B
GAINLA
15 ADD
THIN QFN
THIN QFN
SV
1
2
3
4
5
6
7
8
9
28 V
DD
DD
SV
1
2
3
4
5
6
7
8
9
28 V
DD
DD
INL1
INL2
27 HPS_EN
26 MUTE
25 IN/1V2
24 PGND
23 OUTR-
INL1
INL2
27 INT
26 SDA
25 SCL
24 PGND
23 OUTR-
GAINLA
GAINLB
PGND
GAINLA
GAINLB
PGND
MAX9761
MAX9760
OUTL+
22 PV
DD
OUTL+
22 PV
DD
PV
21 OUTR+
20 PGND
19 GAINRB
18 GAINRA
17 INR2
DD
PV
21 OUTR+
20 PGND
19 GAINRB
18 GAINRA
17 INR2
DD
OUTL-
OUTL-
PGND 10
SHDN 11
GAIN/AVB 12
HPS 13
PGND 10
SHDN 11
ADD 12
HPS 13
BIAS 14
16 INR1
16 INR1
BIAS 14
15 GND
15 GND
TSSOP
TSSOP
______________________________________________________________________________________ 27
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Pin Configurations (continued)
TOP VIEW
TOP VIEW
SDA
INT
1
2
3
4
5
6
7
21 GAINRA
MUTE
1
2
3
4
5
6
7
21 GAINRA
20
19
INR2
INR1
HPS_EN
20
19
INR2
INR1
V
V
DD
DD
SV
DD
18 GAINM
SV
DD
18 GAINM
MAX9762
THIN QFN
MAX9762
MAX9763
17
16
INL1
INL2
BIAS
HPS
17
16
INL1
INL2
BIAS
HPS
GAINLA
15 ADD
GAINLA
15 GAINA/B
THIN QFN
SV
1
2
3
4
5
6
7
8
9
28 V
DD
SV
1
2
3
4
5
6
7
8
9
28 V
DD
DD
DD
INL1
INL2
27 HPS_EN
26 MUTE
25 IN1/2
INL1
INL2
27 INT
26 SDA
25 SCL
24 PGND
23 OUTR-
GAINLA
GAINLB
PGND
GAINLA
GAINLB
PGND
24 PGND
23 OUTR-
MAX9763
OUTL+
22 PV
DD
OUTL+
22 PV
DD
PV
DD
21 OUTR+
20 PGND
19 GAINRB
18 GAINRA
17 INR2
PV
DD
21 OUTR+
20 PGND
19 GAINRB
18 GAINRA
17 INR2
N.C.
N.C.
GND 10
SHDN 11
GAINA/B 12
HPS 13
GND 10
SHDN 11
ADD 12
HPS 13
BIAS 14
16 INR1
16 INR1
BIAS 14
15 GAINM
15 GAINM
TSSOP
TSSOP
28 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Ordering Information (continued)
Chip Information
MAX9760 TRANSISTOR COUNT: 5256
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 Thin QFN-EP*
28 TSSOP-EP*
28 Thin QFN-EP*
28 TSSOP-EP*
28 Thin QFN-EP*
28 TSSOP-EP*
MAX9761 TRANSISTOR COUNT: 2715
MAX9762 TRANSISTOR COUNT: 5046
MAX9763 TRANSISTOR COUNT: 2505
PROCESS: BiCMOS
MAX9761ETI
MAX9761EUI
MAX9762ETI
MAX9762EUI
MAX9763ETI
MAX9763EUI
*EP = Exposed paddle.
Selector Guide
PART
MAX9760
MAX9761
MAX9762
MAX9763
CONTROL INTERFACE
SPEAKER AMPLIFIER
HEADPHONE AMPLIFIER
INPUT MUX
Yes
I2C Coꢀpatible
Stereo
Stereo
Mono
Mono
Stereo
Stereo
Stereo
Stereo
Parallel
Yes
I2C Coꢀpatible
Parallel
Yes
Yes
______________________________________________________________________________________ 29
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0140
C
2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0140
C
2
30 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2003 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
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