MAX9778ETI+ [MAXIM]
Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux;
| 型号： | MAX9778ETI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Stereo 3W Audio Power Amplifiers with Headphone Drive and Input Mux |
| 文件： | 总27页 (文件大小：1208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
µ
19-0509; Rev 0; 4/06
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
General Description
Features
♦ Industry-Leading, Ultra-High 100dB PSRR
The MAX9777/MAX9778 combine a stereo 3W bridge-
tied load (BTL) audio power amplifier, stereo single-
ended (SE) headphone amplifier, headphone sensing,
and a 2:1 input multiplexer all in a tiny 28-pin thin QFN
package. These devices operate from a single 4.5V to
5.5V supply and feature an industry-leading 100dB
PSRR, allowing these devices to operate from noisy
supplies without the addition of a linear regulator. An
ultra-low 0.002% THD+N ensures clean, low-distortion
amplification of the audio signal. Click-and-pop sup-
pression minimizes audible transients on power and
shutdown cycles. Power-saving features include low
♦ 3W BTL Stereo Speaker Amplifier
♦ 200mW Stereo Headphone Amplifier
♦ Low 0.002% THD+N
♦ Click-and-Pop Suppression
♦ ESD-Protected Outputs
♦ Low Quiescent Current: 13mA
♦ Low-Power Shutdown Mode: 10µA
♦ MUTE Function
♦ Headphone Sense Input
♦ Stereo 2:1 Input Multiplexer
4mV V
(minimizes DC current drain through the
OS
speakers), low 13mA supply current, and a 10µA shut-
down mode. A MUTE function allows the outputs to be
quickly enabled or disabled.
2
♦ Optional 2-Wire, I C-Compatible or Parallel
Interface
♦ Tiny 28-Pin Thin QFN (5mm x 5mm x 0.8mm)
A headphone sense input detects the presence of a
headphone jack and automatically configures the
amplifiers for either speaker or headphone mode. In
speaker mode, the amplifiers can deliver up to 3W of
continuous average power into a 3Ω load. In head-
phone mode, the amplifier can deliver up to 200mW of
continuous average power into a 16Ω load. The gain of
the amplifiers is externally set, allowing maximum flexi-
bility in optimizing output levels for a given load. The
amplifiers also feature a 2:1 input multiplexer, allowing
multiple audio sources to be selected. The multiplexer
can also be used to compensate for limitations in the
frequency response of the loud speakers by selecting
an external equalizer network. The various functions are
Package
Ordering Information
CONTROL
INTERFACE
PIN-
PACKAGE
PKG
PART
CODE
2
MAX9777ETI+
MAX9778ETI+
I C Compatible 28 Thin QFN-EP* T2855-6
Parallel 28 Thin QFN-EP* T2855-6
Note: All devices are specified over the -40°C to +85°C operat-
ing temperature range.
+Denotes lead-free package.
*EP = Exposed paddle.
Pin Configurations and Functional Diagrams appear at end
of data sheet.
2
controlled by either an I C-compatible (MAX9777) or
simple parallel control interface (MAX9778).
The MAX9777/MAX9778 are available in a thermally
efficient 28-pin thin QFN package (5mm x 5mm x
0.8mm). These devices have thermal-overload protec-
tion (OVP) and are specified over the extended -40°C
to +85°C temperature range.
Simplified Block Diagram
SINGLE SUPPLY
4.5V TO 5.5V
LEFT IN1
LEFT IN2
Applications
SE/
BTL
Notebooks
PC Audio Peripherals
Camcorders
Portable DVD Players
Tablet PCs
RIGHT IN1
RIGHT IN2
Multimedia Monitor
I2C-
CONTROL
COMPATIBLE
MAX9777
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND ...........................................................................+6V
Continuous Power Dissipation (T = +7±°C)
A
PV
to V
.......................................................................±±.ꢀV
ꢁ8-Pin TQFN, Multilayer Board
DD
DD
PGND to GND.....................................................................±±.ꢀV
All Other Pins to GND.................................-±.ꢀV to (V + ±.ꢀV)
Continuous Input Current (into any pin except power-supply
and output pins) ...............................................................±ꢁ±mA
OUT__ Short Circuit to GND, V ..........................................1±s
DD
(derate ꢀ4.5mW/°C above +7±°C)..........................ꢁ758.6mW
Operating Temperature Range ...........................-4±°C to +85°C
Storage Temperature Range.............................-65°C to +15±°C
Junction Temperature......................................................+15±°C
Lead Temperature (soldering, 1±s) .................................+ꢀ±±°C
DD
Short Circuit Between OUT_+ and OUT_- .................Continuous
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= PV
= 5.±V, GND = PGND = ±V, V
= 5V, C
= 1µF, R = R = 15kΩ, R = ∞. T = T
to T
, unless otherwise
MAX
SHDN
DD
DD
BIAS
IN
F
L
A
MIN
noted. Typical values are at T = +ꢁ5°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
Inferred from PSRR test
BTL mode, HPS = ±V, MAX9777/MAX9778
MIN
TYP
MAX
UNITS
/MAX978
Supply Voltage Range
V
/PV
4.5
5.5
V
DD
DD
1ꢀ
ꢀꢁ
18
5±
Quiescent Supply Current
I
mA
DD
(I
+ I
)
VDD
PVDD
Single-ended mode, HPS = V
SHDN = GND
7
1±
DD
Shutdown Current
Switching Time
I
µA
µs
SHDN
t
Gain or input switching
1±
SW
C
C
= 1µF
ꢀ±±
ꢀ±
BIAS
BIAS
Turn-On Time
t
ms
ON
= ±.1µF
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
+16±
15
oC
oC
OUTPUT AMPLIFIERS (SPEAKER MODE, HPS = GND)
Output Offset Voltage
V
OUT_+ - OUT_-, A = 1V/V
4
1±±
8ꢁ
ꢀꢁ
mV
dB
OS
V
V
= 4.5V to 5.5V
75
DD
Power-Supply Rejection Ratio
(Note ꢁ)
PSRR
f = 1kHz, V
= ꢁ±±mV
P-P
RIPPLE
f = ꢁ±kHz, V
= ꢁ±±mV
7±
RIPPLE
P-P
R
R
R
= 8Ω
1.4
ꢁ.6
ꢀ
L
f
= 1kHz,
IN
Output Power
P
THD+N < 1%,
T
= 4Ω
= ꢀΩ
W
%
OUT
L
= +ꢁ5°C
A
L
P
P
= 1W, R = 8Ω
±.±±5
±.±1
95
OUT
OUT
L
Total Harmonic Distortion Plus
Noise
f
= 1kHz, BW =
IN
THD+N
ꢁꢁHz to ꢁꢁkHz
= ꢁW, R = 4Ω
L
Signal-to-Noise Ratio
Slew Rate
SNR
SR
R
= 8Ω, P
= 1W, BW = ꢁꢁHz to ꢁꢁkHz
OUT
dB
V/µs
nF
L
1.6
1
Maximum Capacitive Load Drive
Crosstalk
C
No sustained oscillations
= 1±kHz
L
f
7ꢀ
dB
IN
Peak voltage, A-weighted,
ꢀꢁ samples per second
(Notes ꢁ, 6)
Into shutdown
-5±
-65
Click/Pop Level
K
dBV
CP
Out of shutdown
2
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
ELECTRICAL CHARACTERISTICS (continued)
(V
= PV
= 5.±V, GND = PGND = ±V, V
= 5V, C
= 1µF, R = R = 15kΩ, R = ∞. T = T
to T
, unless otherwise
MAX
SHDN
DD
DD
BIAS
IN
F
L
A
MIN
noted. Typical values are at T = +ꢁ5°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT AMPLIFIERS (HEADPHONE MODE, HPS = V
)
DD
V
= 4.5V to 5.5V
75
1±6
88
DD
Power-Supply Rejection Ratio
(Note ꢁ)
PSRR
f = 1kHz, V
= ꢁ±±mV
dB
RIPPLE
P-P
f = ꢁ±kHz, V
= ꢁ±±mV
76
RIPPLE
P-P
R
= ꢀꢁΩ
= 16Ω
88
L
L
f
= 1kHz, THD+N <
IN
Output Power
P
mW
OUT
1%, T = +ꢁ5°C
A
R
ꢁ±±
P
R
= 6±mW,
= ꢀꢁΩ
OUT
±.±±ꢁ
±.±±ꢁ
9ꢁ
L
Total Harmonic Distortion Plus
Noise
f
= 1kHz,
IN
THD+N
%
BW = ꢁꢁHz to ꢁꢁkHz
P
R
= 1ꢁ5mW,
= 16Ω
OUT
L
R
V
= ꢀꢁΩ, BW = ꢁꢁHz to ꢁꢁkHz,
L
Signal-to-Noise Ratio
SNR
SR
dB
= 1V
OUT
RMS
Slew Rate
1.8
ꢁ
V/µs
nF
Maximum Capacitive Load Drive
Crosstalk
C
No sustained oscillations
= 1±kHz
L
f
78
dB
IN
BIAS VOLTAGE (BIAS)
BIAS Voltage
V
R
ꢁ.ꢀ5
ꢁ
ꢁ.5
5±
ꢁ.65
V
BIAS
Output Resistance
kΩ
BIAS
1
DIGITAL INPUTS (MUTE, SHDN, HPS_EN, GAINA/B, IN /2)
Input-Voltage High
V
V
V
IH
Input-Voltage Low
V
±.8
1
IL
Input Leakage Current
HEADPHONE SENSE INPUT (HPS)
I
µA
IN
±.9 x
Input-Voltage High
V
V
IH
V
DD
±.7 x
Input-Voltage Low
V
V
IL
V
DD
Input Leakage Current
I
1
µA
IN
Peak voltage, A-weighted,
ꢀꢁ samples per second
(Notes ꢁ, 4)
Into shutdown
-7±
-5ꢁ
Click/Pop Level
K
dBV
CP
Out of shutdown
_______________________________________________________________________________________
3
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
ELECTRICAL CHARACTERISTICS (continued)
(V
= PV
= 5.±V, GND = PGND = ±V, V
= 5V, C
= 1µF, R = R = 15kΩ, R = ∞. T = T
to T
, unless otherwise
MAX
SHDN
DD
DD
BIAS
IN
F
L
A
MIN
noted. Typical values are at T = +ꢁ5°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, INT) (MAX9777)
Input-Voltage High
V
ꢁ.6
V
V
IH
Input-Voltage Low
V
±.8
IL
Input Hysteresis
±.ꢁ
1±
V
Input High Leakage Current
Input Low Leakage Current
Input Capacitance
I
V
V
= 5V
= ±V
1
1
µA
µA
pF
V
IH
IN
IN
I
IL
C
IN
OL
OH
Output-Voltage Low
Output Current High
V
I
= ꢀmA
±.4
1
OL
I
V
= 5V
µA
OH
TIMING CHARACTERISTICS (MAX9777)
Serial Clock Frequency
f
4±±
kHz
µs
SCL
/MAX978
Bus Free Time Between STOP
and START Conditions
t
1.ꢀ
BUF
START Condition Hold Time
START Condition Setup Time
Clock Period Low
t
±.6
±.6
1.ꢀ
±.6
1±±
±
µs
µs
µs
µs
ns
µs
HD:STA
t
SU:STA
t
LOW
Clock Period High
t
HIGH
Data Setup Time
t
SU:DAT
HD:DAT
Data Hold Time
t
(Note ꢀ)
(Note 4)
±.9
ꢁ± +
Receive SCL/SDA Rise Time
Receive SCL/SDA Fall Time
Transmit SDA Fall Time
t
r
t
f
t
f
ꢀ±±
ns
ns
ns
ns
±.1C
B
ꢁ± +
±.1C
(Note 4)
(Note 4)
(Note 5)
ꢀ±±
ꢁ5±
B
ꢁ± +
±.1C
B
Pulse Width of Suppressed
Spike
t
5±
SP
Note 1: All devices are 1±±% production tested at +ꢁ5°C. All temperature limits are guaranteed by design.
Note 2: Inputs AC-coupled to GND.
Note 3: A master device must provide a hold time of at least ꢀ±±ns for the SDA signal to bridge the undefined region of SCL’s
falling edge.
Note 4: C = total capacitance of one of the bus lines in picofarads. Device tested with C = 4±±pF. 1kΩ pullup resistors connected
B
B
from SDA/SCL to V
.
DD
Note 5: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 5±ns.
Note 6: Headphone mode testing performed with ꢀꢁΩ resistive load connected to GND. Speaker mode testing performed with 8Ω
resistive load connected to GND. Mode transitions are controlled by SHDN. KCP level is calculated as ꢁ±log[(peak voltage
during mode transition, no input signal)/1V
]. Units are expressed in dBV.
RMS
4
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Typical Operating Characteristics
(V
DD
= PV
= 5V, GND = PGND = ±V, V
= 5V, C
= 1µF, T = +ꢁ5°C, unless otherwise noted.)
BIAS
A
DD
SHDN
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
1
1
1
R = 3Ω
L
R = 4Ω
L
R = 3Ω
L
A
= 4V/V
A = 2V/V
V
V
A
V
= 2V/V
0.1
0.1
0.01
0.1
P
= 500mW
= 1W
P
OUT
P
OUT
P
= 500mW
P
= 1W
OUT
OUT
P
= 250mW
P
OUT
= 500mW
OUT
0.01
0.01
= 2.5W
OUT
P
= 2W
100
OUT
P
= 2W
P
= 2.5W
1k
OUT
OUT
P
= 2W
OUT
P
= 1W
100
OUT
0.001
0.001
0.001
10
1k
FREQUENCY (Hz)
10k
100k
10
1k
FREQUENCY (Hz)
10k
100k
10
100
10k
100k
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (SPEAKER MODE)
1
1
1
R = 8Ω
L
R = 8Ω
L
R = 4Ω
L
A
= 2V/V
A
= 4V/V
A
= 4V/V
V
V
V
0.1
0.1
0.01
0.1
P
= 250mW
P
= 500mW
OUT
OUT
P
= 250mW
P
= 500mW
OUT
OUT
P
= 250mW
OUT
P
= 500mW
= 1.2W
OUT
P
0.01
0.001
0.01
0.001
P
= 2W
OUT
1k
P
= 1W
100
OUT
P
= 1.2W
OUT
1k
P
= 1W
OUT
OUT
P
= 1W
OUT
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
10
10k
100k
10
100
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
100
100
A = 4V/V
V
A
= 2V/V
A
= 2V/V
V
V
R = 3Ω
L
R = 3Ω
L
R = 4Ω
L
10
10
10
1
1
1
f = 10kHz
f = 1kHz
f = 10kHz
f = 10kHz
0.1
0.1
0.1
f = 20Hz
f = 1kHz
1
f = 1kHz
0.01
0.001
0.01
0.001
0.01
0.001
f = 20Hz
f = 20Hz
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT POWER (W)
0
2
3
4
0
1
2
OUTPUT POWER (W)
3
4
OUTPUT POWER (W)
_______________________________________________________________________________________
5
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
DD
= PV
= 5V, GND = PGND = ±V, V
= 5V, C
= 1µF, T = +ꢁ5°C, unless otherwise noted.)
BIAS
A
DD
SHDN
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (SPEAKER MODE)
100
100
100
A
= 4V/V
A
= 2V/V
V
A = 4V/V
V
V
R = 4Ω
L
R = 8Ω
L
R = 8Ω
L
10
1
10
10
f = 10kHz
1
1
f = 10kHz
f = 1kHz
f = 20Hz
f = 10kHz
0.1
0.1
0.1
f = 1kHz
f = 1kHz
0.01
0.001
0.01
0.001
0.01
0.001
f = 20Hz
0.5
f = 20Hz
0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
OUTPUT POWER (W)
0
1.0
1.5
2.0
0
1.0
1.5
2.0
/MAX978
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER vs. AMBIENT TEMPERATURE
OUTPUT POWER vs. AMBIENT TEMPERATURE
OUTPUT POWER vs. AMBIENT TEMPERATURE
(SPEAKER MODE)
(SPEAKER MODE)
(SPEAKER MODE)
4
4
2.0
THD+N = 10%
THD+N = 10%
THD+N = 10%
3
3
1.5
1.0
0.5
0
THD+N = 1%
THD+N = 1%
2
THD+N = 1%
2
1
1
f = 1kHz
R = 4Ω
L
f = 1kHz
R = 3Ω
L
f = 1kHz
R = 8Ω
L
0
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
OUTPUT POWER vs. LOAD RESISTANCE
(SPEAKER MODE)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
f = 1kHz
THD+N = 10%
THD+N = 1%
R = 4Ω
f = 1kHz
L
0
0.5
1.0
1.5
2.0
2.5
1
10
100
1k
10k
100k
OUTPUT POWER (W)
LOAD RESISTANCE (Ω)
6
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Typical Operating Characteristics (continued)
(V
DD
= PV
= 5V, GND = PGND = ±V, V
= 5V, C
= 1µF, T = +ꢁ5°C, unless otherwise noted.)
BIAS
A
DD
SHDN
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPEAKER MODE)
CROSSTALK vs. FREQUENCY
(SPEAKER MODE)
40
50
-40
-50
V
= 200mV
P-P
V
= 200mV
P-P
RIPPLE
IN
L
R = 8Ω
-60
60
-70
RIGHT TO LEFT
70
-80
-90
80
-100
-110
-120
LEFT TO RIGHT
90
100
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
ENTERING SHUTDOWN (SPEAKER MODE)
EXITING SHUTDOWN (SPEAKER MODE)
MAX9777/78 toc20
MAX9777/78 toc21
V
DD
SHDN
2V/div
2V/div
OUT_+ AND OUT_-
1V/div
OUT_+ AND OUT_-
1V/div
OUT_+ - OUT_-
200mV/div
OUT_+ - OUT_-
500mV/div
400ms/div
100ms/div
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
1
1
R = 16Ω
L
R = 16Ω
L
A
= 1V/V
A
= 2V/V
V
V
0.1
0.1
P
= 25mW
OUT
P
= 50mW
OUT
P
= 25mW
OUT
P
= 50mW
OUT
0.01
0.01
P
= 100mW
0.001
0.0001
0.001
0.0001
P
= 150mW
10k
OUT
OUT
P
= 100mW
100
OUT
P
= 150mW
10k
OUT
10
1k
FREQUENCY (Hz)
100k
10
100
1k
FREQUENCY (Hz)
100k
_______________________________________________________________________________________
7
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
DD
= PV
= 5V, GND = PGND = ±V, V
= 5V, C
= 1µF, T = +ꢁ5°C, unless otherwise noted.)
BIAS
A
DD
SHDN
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
1
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (HEADPHONE MODE)
100
1
A
= 1V/V
R = 32Ω
L
V
R = 32Ω
L
R = 16Ω
L
A
= 2V/V
A
= 1V/V
V
V
10
0.1
0.1
0.01
1
P
= 25mW
OUT
P
P
= 50mW
OUT
OUT
f = 20Hz
P
P
= 25mW
OUT
f = 10kHz
P
= 50mW
OUT
0.1
0.01
0.01
0.001
0.0001
0.001
0.001
0.0001
= 100mW
P
= 150mW
100
OUT
= 100mW
100
OUT
P
= 150mW
10k
OUT
f = 1kHz
0.0001
0
50
100
150
200
250
300
10
1k
100k
10
1k
FREQUENCY (Hz)
10k
100k
/MAX978
OUTPUT POWER (mW)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
100
100
100
A
= 1V/V
A = 2V/V
V
R = 32Ω
L
A
= 2V/V
V
L
V
L
R = 32Ω
R = 16Ω
10
10
10
f = 1kHz
1
1
1
f = 10kHz
f = 10kHz
f = 10kHz
f = 20Hz
0.1
0.1
0.1
f = 20Hz
f = 20Hz
0.01
0.001
0.0001
0.01
0.001
0.0001
0.01
0.001
0.0001
f = 1kHz
f = 1kHz
75
OUTPUT POWER (mW)
0
25
50
75
100
125
0
50
100
150
200
250
300
0
25
50
100
125
OUTPUT POWER (mW)
OUTPUT POWER (mW)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(HEADPHONE MODE)
150
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)
OUTPUT POWER vs. AMBIENT TEMPERATURE
(HEADPHONE MODE)
300
600
500
400
300
200
100
0
f = 1kHz
THD+N = 10%
THD+N = 1%
125
100
75
50
25
0
THD+N = 10%
THD+N = 1%
250
200
150
100
50
THD+N = 10%
THD+N = 1%
f = 1kHz
R = 32Ω
L
f = 1kHz
R = 16Ω
L
0
-40
-15
10
35
60
85
1
10
100
1k
10k
-40
-15
10
35
60
85
AMBIENT TEMPERATURE (°C)
LOAD RESISTANCE (Ω)
AMBIENT TEMPERATURE (°C)
8
_______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Typical Operating Characteristics (continued)
(V
DD
= PV
= 5V, GND = PGND = ±V, V
= 5V, C
= 1µF, T = +ꢁ5°C, unless otherwise noted.)
BIAS
A
DD
SHDN
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
70
60
50
40
30
20
10
0
40
50
120
V
= 200mV
P-P
RIPPLE
100
80
60
40
20
0
60
70
80
90
R = 32Ω
f = 1kHz
L
R = 16Ω
f = 1kHz
L
100
0
20
40
60
80
100
10
100
1k
FREQUENCY (Hz)
10k
100k
0
50
100
150
200
OUTPUT POWER (mW)
OUTPUT POWER (mW)
CROSSTALK vs. FREQUENCY
(HEADPHONE MODE)
EXITING SHUTDOWN (HEADPHONE MODE)
MAX9777/78 toc37
-40
-50
V
= 200mV
P-P
IN
L
R = 16Ω
SHDN
2V/div
-60
-70
-80
RIGHT TO LEFT
OUT_+
1V/div
-90
-100
-110
-120
HP JACK
200mV/div
LEFT TO RIGHT
10
100
1k
10k
100k
100ms/div
R = 16Ω
L
FREQUENCY (Hz)
INPUT AC-COUPLED TO GND
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(SPEAKER MODE)
ENTERING SHUTDOWN (HEADPHONE MODE)
MAX9777/78 toc38
25
20
15
10
5
T
= +85°C
A
SHDN
2V/div
T
= +25°C
A
OUT_+
1V/div
T
= -40°C
A
HP JACK
100mV/div
0
4.50
4.75
5.00
5.25
5.50
100ms/div
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Operating Characteristics (continued)
(V
DD
= PV
= 5V, GND = PGND = ±V, V
= 5V, C
= 1µF, T = +ꢁ5°C, unless otherwise noted.)
BIAS
A
DD
SHDN
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(HEADPHONE MODE)
12
12
10
8
10
8
T
= +85°C
T
= +85°C
A
A
6
6
T
= +25°C
T
A
= +25°C
A
4
4
T
= -40°C
T
= -40°C
A
A
2
2
/MAX978
0
0
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
POWER DISSIPATION vs. OUTPUT POWER
(SPEAKER MODE)
EXITING POWER-DOWN
(SPEAKER MODE)
MAX9777/78 toc43
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
DD
2V/div
OUT_+ AND OUT_-
1V/div
R = 8Ω
f = 1kHz
L
OUT_+ - OUT_-
1V/div
0
0.25 0.50 0.75 1.00 1.25 1.50
OUTPUT POWER (W)
100ms/div
10 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Pin Description
PIN
NAME
FUNCTION
MAX9777
MAX9778
1
—
SDA
Serial Data I/O
ꢁ
—
INT
Interrupt Output
ꢀ, 4
ꢀ, 4
V
Power-Supply Input
Left-Channel Input 1
Left-Channel Input ꢁ
Left-Channel Gain Set A
Left-Channel Gain Set B
Power Ground. Connect to GND.
DD
5
5
INL1
INLꢁ
6
6
7
7
GAINLA
GAINLB
PGND
8
8
9, 1ꢀ, ꢁꢀ, ꢁ7
9, 1ꢀ, ꢁꢀ, ꢁ7
Left-Channel Bridged Amplifier Positive Output. OUTL+ also serves as the
left-channel headphone amplifier output.
1±
1±
OUTL+
11, ꢁ5
1ꢁ
11, ꢁ5
1ꢁ
PV
Output Amplifier Power Supply
DD
OUTL-
Left-Channel Bridged Amplifier Negative Output
14
15
14
—
SHDN
Active-Low Shutdown Input. Connect SHDN to V
for normal operation.
DD
Address Select. A logic-high sets the address LSB to 1, a logic-low sets the
address LSB to zero.
ADD
HPS
BIAS
Headphone Sense Input. A logic-high configures the device as a single-
ended headphone amp. A logic-low configures the device as a BTL
speaker amp.
16
16
DC Bias Bypass Terminal. See the BIAS Capacitor section for capacitor
17
17
selection. Connect C
from BIAS to GND.
BIAS
18
19
ꢁ±
ꢁ1
ꢁꢁ
18
19
ꢁ±
ꢁ1
ꢁꢁ
GND
INR1
Ground. Connect to PGND.
Right-Channel Input 1
INRꢁ
Right-Channel Input ꢁ
GAINRA
GAINRB
Right-Channel Gain Set A
Right-Channel Gain Set B
Right-Channel Bridged Amplifier Positive Output. OUTR+ also serves as the
right-channel headphone amplifier output.
ꢁ4
ꢁ6
ꢁ4
ꢁ6
OUTR+
OUTR-
Right-Channel Bridged Amplifier Negative Output
ꢁ8
—
—
1
SCL
Serial Clock Line
MUTE
Active-High Mute Input
Headphone Enable. A logic-high enables HPS. A logic-low disables HPS
and the device is always configured as a BTL speaker amplifier.
—
—
ꢁ
HPS_EN
Gain Select. A logic-low selects the gain set by GAIN_A. A logic-high
selects the gain set by GAIN_B.
15
GAINA/B
Input Select. A logic-low selects amplifier input 1. A logic-high selects
amplifier input ꢁ.
—
ꢁ8
EP
IN1/ꢁ
EP
EP
Exposed Paddle. Connect to GND.
______________________________________________________________________________________ 11
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Input Multiplexer
Detailed Description
Each amplifier features a ꢁ:1 input multiplexer, allowing
input selection between two stereo sources. Both multi-
plexers are controlled by bit 1 in the control register
(MAX9777) or by the IN1/ꢁ pin (MAX9778). A logic-low
selects input IN_1 and a logic-high selects input IN_ꢁ.
The MAX9777/MAX9778 feature ꢀW BTL speaker
amplifiers, ꢁ±±mW headphone amplifiers, input multi-
plexers, headphone sensing, and comprehensive click-
and-pop suppression. The MAX9777/MAX9778 are
stereo BTL/headphone amplifiers. The MAX9777 is
ꢁ
The input multiplexer can also be used to further
expand the number of gain options available from the
MAX9777/MAX9778 family. Connecting the audio
source to the device through two different input resis-
tors (Figure 1) increases the number of gain options
from two to four. Additionally, the input multiplexer
allows a speaker equalization network to be switched
into the speaker signal path. This is typically useful in
optimizing acoustic response from speakers with small
physical dimensions.
controlled through an I C-compatible, ꢁ-wire serial
interface. The MAX9778 is controlled through five logic
inputs: MUTE, SHDN, HPS_EN, GAINA/B, and IN1/ꢁ
(see the Selector Guide). The MAX9777/MAX97778 fea-
ture exceptional PSRR (1±±dB at 1kHz), allowing these
devices to operate from noisy digital supplies without
the need for a linear regulator.
The speaker amplifiers use a BTL configuration. The
signal path is composed of an input amplifier and an
output amplifier. Resistor R sets the input amplifier’s
IN
gain, and resistor R sets the output amplifier’s gain.
F
Headphone Sense Enable
The HPS input is enabled by HPS_EN (MAX9778) or the
HPS_D bit (MAX9777). HPS_D or HPS_EN determines
whether the device is in automatic detection mode or
fixed-mode operation (see Tables 1a and 1b).
The output of these two amplifiers serves as the input to
a slave amplifier configured as an inverting unity-gain
follower. This results in two outputs, identical in magni-
/MAX978
°
tude, but 18± out of phase. The overall gain of the
speaker amplifiers is twice the product of the two
amplifier gains (see the Gain-Setting Resistors section).
A feature of this architecture is that there is no phase
inversion from input to output.
MAX9777
MAX9778
IN_1
15kΩ
30kΩ
When configured as a headphone (single-ended) ampli-
fier, the slave amplifier is disabled, muting the speaker
and the main amplifier drives the headphone. The
MAX9777/MAX9778 can deliver ꢀW of continuous power
into a ꢀΩ load with less than 1% THD+N in speaker
mode, and ꢁ±±mW of continuous average power into a
16Ω load with less than 1% THD+N in headphone mode.
These devices also feature thermal-overload protection.
AUDIO
INPUT
IN_2
Figure 1. Using the Input Multiplexer for Gain Setting
BIAS
These devices operate from a single 5V supply, and fea-
ture an internally generated, power-supply independent,
common-mode bias voltage of ꢁ.5V referenced to GND.
BIAS provides both click-and-pop suppression and sets
the DC bias level for the audio outputs. BIAS is internally
connected to the noninverting input of each speaker
amplifier (see the Typical Application Circuits and
Functional Diagrams). Choose the value of the bypass
capacitor as described in the BIAS Capacitor section.
No external load should be applied to BIAS. Any load
lowers the BIAS voltage, affecting the overall perfor-
mance of the device.
Table 1a. MAX9777 HPS Setting
INPUTS
GAIN
PATH*
MODE
HPS_D
BIT
SPKR/HP
BIT
HPS
±
±
1
1
±
1
X
X
X
X
±
1
BTL
SE
A
B
BTL
SE
A or B
A or B
*Note:
A—GAINA path selected
B—GAINB path selected
A or B—Gain path selected by GAINAB control bit in register
±ꢁh
12 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Table 1b. MAX9778 HPS Setting
V
DD
INPUTS
HPS_EN
R1
680kΩ
MODE
GAIN PATH*
HPS
R3
47kΩ
MAX9777
MAX9778
0
1
1
X
0
1
BTL
BTL
SE
A or B
A or B
A or B
HPS
OUTL+
OUTR+
*Note:
A or B—Gain path selected by external GAINAB
R2
R2
10kΩ 10kΩ
Headphone Sense Input (HPS)
With headphone sense enabled, a voltage on HPS less
than 0.7 x V
sets the device to speaker mode. A volt-
DD
Figure 2. HPS Configuration Circuit
age greater than 0.9 x V
disables the inverting
DD
bridge amplifier (OUT_-), which mutes the speaker
amplifier and sets the device into headphone mode.
device. The digital section of the MAX9777 remains
active when the device is shut down through the inter-
face. All devices feature a logic-low on the SHDN input.
For automatic headphone detection, enable headphone
sense and connect HPS to the control pin of a 3-wire
headphone jack as shown in Figure 2. With no head-
phone present, the resistive voltage-divider created by
R1 and R2 sets the voltage on HPS to be less than 0.7 x
MUTE
The MAX9777/MAX9778 feature a mute mode. When
the device is muted, the input is disconnected from the
amplifiers. MUTE does not shut down the device.
V , setting the device to speaker mode and the gain
DD
setting defaults to GAINA (MAX9777). When a head-
phone plug is inserted into the jack, the control pin is dis-
MAX9777 MUTE
The MAX9777 MUTE mode is selected by writing to the
MUTE register (see the Mute Register section). The left
and right channels can be independently muted.
connected from the tip contact, and HPS is pulled to V
DD
through R1, setting the device into headphone mode and
the gain-setting defaults to GAINB (MAX9777) (see the
Gain Select section). Place a resistor in series with the
control pin and HPS (R3) to prevent any audio signal from
coupling into HPS when the device is in speaker mode.
MAX9778 MUTE
The MAX9778 features an active-high MUTE input that
mutes all channels.
Shutdown
The MAX9777/MAX9778 feature a 10µA, low-power
shutdown mode that reduces quiescent current con-
sumption and extends battery life. The drive amplifiers
and bias circuitry are disabled, the amplifier outputs
(OUT_) go high impedance, and BIAS is driven to
GND. Driving SHDN low places the devices into shut-
down mode, disables the interface, and resets the I2C
registers to a default state. A logic-high on SHDN
enables the devices.
Click-and-Pop Suppression
The MAX9777/MAX9778 feature Maxim’s comprehen-
sive click-and-pop suppression. When entering or exit-
ing shutdown, the common-mode bias voltage of the
amplifiers is slowly ramped to and from the DC bias
point using an S-shaped waveform. In headphone
mode, this waveform shapes the frequency spectrum,
minimizing the amount of audible components present
at the headphone. In speaker mode, the BTL amplifiers
start up in the same fashion as in headphone mode.
When entering shutdown, both amplifier outputs ramp
to GND quickly and simultaneously. To maximize click-
and-pop suppression, drive SHDN to 0V before power-
up or power-down transitions.
MAX9777 Software Shutdown
A logic-high on bit 0 of the SHDN register places the
MAX9777 in shutdown mode. A logic-low enables the
______________________________________________________________________________________ 13
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
devices from high-voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
Digital Interface
ꢁ
The MAX9777 features an I C/SMBus™-compatible ꢁ-
wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX9777 and the master at clock rates up to 4±±kHz.
Figure ꢀ shows the ꢁ-wire interface timing diagram. The
MAX9777 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see the START
and STOP Conditions section). SDA and SCL idle high
ꢁ
when the I C bus is not busy.
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
low transition on SDA with SCL high. A STOP condition
is a low-to-high transition on SDA while SCL is high
(Figure 4). A START condition from the master signals
the beginning of a transmission to the MAX9777. The
master terminates transmission by issuing the STOP
condition; this frees the bus. If a REPEATED START
condition is generated instead of a STOP condition, the
bus remains active.
A master device communicates to the MAX9777 by
transmitting the proper address followed by a com-
mand and/or data words. Each transmit sequence is
framed by a START (S) or REPEATED START (S ) con-
r
dition and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge clock pulse.
/MAX978
SDA and SCL are open-drain outputs requiring a pullup
resistor (5±±Ω or greater) to generate a logic-high volt-
age. Series resistors in line with SDA and SCL are option-
al. These series resistors protect the input stages of the
SMBus is a trademark of Intel Corp.
SDA
t
BUF
t
t
HD, STA
SU, DAT
t
t
SP
HD, STA
t
SU, STO
t
t
HD, DAT
LOW
SCL
t
HIGH
t
HD, STA
t
R
t
F
START
CONDITION
REPEATED
START
STOP
CONDITION
START
CONDITION
CONDITION
Figure ꢀ. ꢁ-Wire Serial-Interface Timing Diagram
S
S
r
P
SCL
SDA
Figure 4. START/STOP Conditions
14 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Early STOP Conditions
The MAX9777 recognizes a STOP condition at any
point during the transmission except if a STOP condi-
tion occurs in the same high pulse as a START condi-
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9777 generates an ACK when
receiving an address or data by pulling SDA low during
the night clock period. When transmitting data, the
MAX9777 waits for the receiving device to generate an
ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
ꢁ
tion (Figure 5). This condition is not a legal I C format;
at least one clock pulse must separate any START and
STOP condition.
REPEATED START Conditions
A REPEATED START (S ) condition may indicate a
r
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. S may also be used when the bus
r
ꢁ
master is writing to several I C devices and does not
want to relinquish control of the bus. The MAX9777 ser-
ial interface supports continuous write operations with
Slave Address
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9777
waits for a START condition followed by its slave
address. The LSB of the address word is the
Read/Write (R/W) bit. R/W indicates whether the master
is writing to or reading from the MAX9777 (R/W = ±
selects the write condition, R/W = 1 selects the read
condition). After receiving the proper address, the
MAX9777 issues an ACK by pulling SDA low for one
clock cycle.
or without an S condition separating them. Continuous
r
read operations require S conditions because of the
r
change in direction of data flow.
SCL
SDA
The MAX9777 has a factory-/user-programmed
address. Address bits A6–Aꢁ are preset, while A± and
A1 is set by ADD. Connect ADD to either V , GND,
DD
SCL, or SDA to change the last ꢁ bits of the slave
address (Table ꢁ).
STOP
START
LEGAL STOP CONDITION
SCL
SDA
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 6. Slave Address Byte Definition
2
Table 2. MAX9777 I C Slave Addresses
I2C ADDRESS
START
ILLEGAL
STOP
ADD CONNECTION
GND
1±± 1±±±
ILLEGAL EARLY STOP CONDITION
V
1±± 1±±1
DD
SDA
SCL
1±± 1±1±
Figure 5. Early STOP Condition
1±± 1±11
______________________________________________________________________________________ 15
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Write Data Format
There are three registers that configure the MAX9777:
the MUTE register, SHDN register, and control register.
In write data mode (R/W = ±), the register address and
data byte follow the device address (Figure 7).
in bit ± of the SHDN register shuts down the device; a
logic-low turns on the device. A logic-high is required in
bits ꢁ to 7 to reset all registers to their default settings.
Control Register
The control register (±ꢀhex) is a read/write register that
determines the device configuration. Bit 1 (IN1/INꢁ) con-
trols the input multiplexer, a logic-high selects input 1; a
logic-low selects input ꢁ. Bit ꢁ (HPS_D) controls the
headphone sensing. A logic-low configures the device in
automatic headphone detection mode. A logic-high dis-
ables the HPS input. Bit ꢀ (GAINA/B) controls the gain-
select multiplexer. A logic-low selects GAINA. A logic-
high selects GAINB. GAINA/B is ignored when HPS_D =
±. Bit 4 (SPKR/HP) selects the amplifier operating mode
when HPS_D = 1. A logic-high selects speaker mode,
and a logic-low selects headphone mode.
MUTE Register
The MUTE register (±1hex) is a read/write register that
sets the MUTE status of the device. Bit ꢀ (MUTEL) of
the MUTE register controls the left channel; bit 4
(MUTER) controls the right channel. A logic-high mutes
the respective channel; a logic-low brings the channel
out of mute.
SHDN Register
The SHDN register (±ꢁhex) is a read/write register that
controls the power-up state of the device. A logic-high
S
ADDRESS
7 BITS
WR ACK
COMMAND
8 BITS
ACK
DATA
ACK
P
1
/MAX978
8 BITS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
REGISTER ADDRESS.
SELECTS REGISTER TO BE
WRITTEN TO.
REGISTER DATA
S
ADDRESS
7 BITS
WR ACK
COMMAND
8 BITS
ACK
S
ADDRESS
WR ACK
DATA
P
1
7 BITS
2
8 BITS
2
I C SLAVE ADDRESS.
SELECTS DEVICE.
REGISTER ADDRESS.
SELECTS REGISTER
TO BE READ.
I C SLAVE ADDRESS.
SELECTS DEVICE.
DATA FROM
SELECTED REGISTER
Figure 7. Write/Read Data Format Example
Table 4. MAX9777 SHDN Register Format
Table 3. MAX9777 MUTE Register Format
REGISTER
0000 0001
ADDRESS
REGISTER ADDRESS
0000 0010
DESCRIPTION
BIT
NAME
VALUE
±*
—
Reset device
—
BIT
7
NAME
VALUE
Don’t Care
Don’t Care
Don’t Care
±*
DESCRIPTION
7
RESET
1
±*
X
X
X
—
6
—
6
5
4
ꢀ
RESET
RESET
RESET
RESET
1
Reset device
—
Reset device
—
5
—
±*
1
Unmute right channel
4
ꢀ
MUTER
MUTEL
1
Mute right channel
±*
±*
Unmute left channel
1
±*
Reset device
—
1
Mute left channel
1
Reset device
—
Reset device
—
ꢁ
1
±
X
X
X
Don’t Care
Don’t Care
Don’t Care
—
—
—
±*
1
ꢁ
1
±
RESET
X
Don’t Care
*Default state.
±*
1
Normal operation
Shutdown
SHDN
*Default state.
16 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Read Data Format
Table 5. MAX9777 Control Register Format
In read mode (R/W = 1), the MAX9777 writes the con-
tents of the selected register to the bus. The direction of
the data flow reverses following the address acknowl-
edge by the MAX9777. The master device reads the
contents of all registers, including the read-only status
register. Table 6 shows the status register format.
REGISTER ADDRESS
0000 0011
BIT
7
NAME
VALUE
Don’t Care
Don’t Care
Don’t Care
±*
DESCRIPTION
X
X
X
—
6
—
5
—
Interrupt Output (INT)
The MAX9777 includes an interrupt output (INT) that
can indicate to a master device that an event has
occurred. INT is triggered when the state of HPS
changes. During normal operation, INT idles high. If a
headphone is inserted/removed from the jack and that
action is detected by HPS, INT pulls the line low. INT
remains low until a read data operation is executed.
Speaker mode selected
4
ꢀ
SPKR/HP
GAINA/B
Headphone mode
selected
1
±*
1
Gain-setting A selected
Gain-setting B selected
Automatic headphone
detection enabled
±*
2
I C Compatibility
ꢁ
1
HPS_D
Automatic headphone
detection disabled
(HPS ignored)
ꢁ
The MAX9777 is compatible with existing I C systems.
1
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The communication protocol supports the
±*
1
Input 1 selected
Input ꢁ selected
—
IN1/INꢁ
X
ꢁ
standard I C 8-bit communications. The general call
address is ignored. The MAX9777 slave addresses are
±
Don’t Care
ꢁ
compatible with the 7-bit I C addressing protocol only.
*Default
Table 6. MAX9777 Status Register Format
REGISTER ADDRESS
0000 0000
BIT
NAME
VALUE
DESCRIPTION
±
Device temperature below thermal limit
Device temperature exceeding thermal limit
OUTR- current below current limit
OUTR- current exceeding current limit
OUTR+ current below current limit
OUTR+ current exceeding current limit
OUTL- current below current limit
OUTL- current exceeding current limit
OUTL+ current below current limit
OUTL+ current exceeding current limit
Device in speaker mode
7
THRM
1
±
6
5
4
ꢀ
ꢁ
AMPR-
AMPR+
AMPL-
AMPL+
HPSTS
1
±
1
±
1
±
1
±
1
Device in headphone mode
—
1
±
X
X
Don’t Care
Don’t Care
—
______________________________________________________________________________________ 17
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Single-Ended Headphone Amplifier
Applications Information
The MAX9777/MAX9778 can be configured as single-
ended headphone amplifiers through software or by
sensing the presence of a headphone plug (HPS). In
headphone mode, the inverting output of the BTL
amplifier is disabled, muting the speaker. The gain is
1/ꢁ that of the device in speaker mode, and the output
power is reduced by a factor of 4.
BTL Speaker Amplifiers
The MAX9777/MAX9778 feature speaker amplifiers
designed to drive a load differentially, a configuration
referred to as bridge-tied load (BTL). The BTL configu-
ration (Figure 8) offers advantages over the single-
ended configuration, where one side of the load is
connected to ground. Driving the load differentially
doubles the output voltage compared to a single-
ended amplifier under similar conditions. Thus, the
devices’ differential gain is twice the closed-loop gain
of the input amplifier. The effective gain is given by:
In headphone mode, the load must be capacitively
coupled to the device, blocking the DC bias voltage
from the load (see the Typical Application Circuits).
Power Dissipation and Heat Sinking
Under normal operating conditions, the MAX9777/
MAX9778 can dissipate a significant amount of power.
The maximum power dissipation for each package is
given in the Absolute Maximum Ratings section under
Continuous Power Dissipation or can be calculated by
the following equation:
R
F
A
= ꢁ×
VD
R
IN
Substituting ꢁ x V
for V
into the follow-
OUT(P-P)
OUT(P-P)
ing equations yields four times the output power due to
doubling of the output voltage:
/MAX978
T
− T
A
J(MAX)
P
=
DISSPKG(MAX)
V
θ
OUT(P−P)
JA
V
=
=
RMS
ꢁ ꢁ
ꢁ
where T
is +15±°C, T is the ambient tempera-
A
J(MAX)
V
ture, and θ is the reciprocal of the derating factor in
JA
RMS
P
OUT
°C/W as specified in the Absolute Maximum Ratings
R
L
section. For example, θ
of the TQFN package is
JA
Since the differential outputs are biased at midsupply,
there is no net DC voltage across the load. This elimi-
nates the need for DC-blocking capacitors required for
single-ended amplifiers. These capacitors can be large
and expensive, consume board space, and degrade
low-frequency performance.
+ꢁ9°C/W.
The increase in power delivered by the BTL configura-
tion directly results in an increase in internal power dis-
sipation over the single-ended configuration. The
maximum power dissipation for a given V
given by the following equation:
and load is
DD
When the MAX9777 is configured to automatically detect
the presence of a headphone jack, the device defaults to
gain setting A when the device is in speaker mode.
ꢁ
ꢁV
DD
P
=
DISS(MAX)
ꢁ
π R
L
If the power dissipation for a given application exceeds
the maximum allowed for a given package, either reduce
V
, increase load impedance, decrease the ambient
DD
V
+1
OUT(P-P)
temperature, or add heatsinking to the device. Large
output, supply, and ground PC board traces improve the
maximum power dissipation in the package.
2 x V
OUT(P-P)
Thermal-overload protection limits total power dissipa-
tion in these devices. When the junction temperature
exceeds +16±°C, the thermal-protection circuitry dis-
ables the amplifier output stage. The amplifiers are
enabled once the junction temperature cools by 15°C.
This results in a pulsing output under continuous ther-
mal-overload conditions as the device heats and cools.
V
-1
OUT(P-P)
Figure 8. Bridge-Tied Load Configuration
18 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
the load impedance form a highpass filter with a -ꢀdB
point determined by:
Component Selection
Gain-Setting Resistors
1
External feedback components set the gain of the
f
=
−ꢀdB
MAX9777/MAX9778. Resistor R sets the gain of the
IN
ꢁπR C
L
OUT
input amplifier (A ), and resistor R sets the gain of
VIN
F
the second stage amplifier (A
):
VOUT
As with the input capacitor, choose C
such that
OUT
f
is well below the lowest frequency of interest.
-ꢀdB
⎛
⎞
1±kΩ
R
F
1±kΩ
⎛
⎞
Setting f
too high affects the amplifier‘s low-fre-
-ꢀdB
A
= −
, A
= −
VOUT
⎜
⎝
⎟
⎠
VIN
⎜
⎟
quency response.
R
⎝
⎠
IN
Load impedance is a concern when choosing C
.
OUT
Combining A
and A
, R and R set the single-
VIN
VOUT IN
F
Load impedance can vary, changing the -ꢀdB point of
the output filter. A lower impedance increases the cor-
ner frequency, degrading low-frequency response.
ended gain of the device as follows:
⎛
⎞
⎛
⎞
1±kΩ
R
1±kΩ
R
F
⎛
⎞
Select C
such that the worst-case load/C
com-
F
OUT
OUT
A
= A
× A = −
VOUT
× −
= +
⎜
⎝
⎟
⎠
V
VIN
⎜
⎟
⎜
⎟
bination yields an adequate response. Select capaci-
tors with low ESR to minimize resistive losses and
optimize power transfer to the load.
R
R
⎝
⎠
⎝
⎠
IN
IN
As shown, the two-stage amplifier architecture results
in a noninverting gain configuration, preserving
absolute phase through the MAX9777/MAX9778. The
gain of the device in BTL mode is twice that of the sin-
If layout constraints require a physically smaller output-
coupling capacitor, decrease the value of C
and add
OUT
series resistance to the output of the MAX9777/MAX9778
(see Figure 9). With the added series resistance at the
output, the cutoff frequency of the highpass filter is:
gle-ended mode. Choose R between 1±kΩ and 15kΩ
IN
and R between 15kΩ and 1±±kΩ.
F
1
Input Filter
The input capacitor (C ), in conjunction with R , forms
a highpass filter that removes the DC bias from an
incoming signal. The AC-coupling capacitor allows the
amplifier to bias the signal to an optimum DC level.
Assuming zero-source impedance, the -ꢀdB point of
the highpass filter is given by:
f−ꢀdB
=
ꢁπ R +R
C
(
)
IN
IN
L
SERIES OUT
Since the cutoff frequency of the output highpass filter
is inversely proportional to the product of the total load
resistance seen by the outputs (R + R
) and
SERIES
L
C
, increase the total resistance seen by the
OUT
MAX9777/MAX9778 outputs by the same amount C
OUT
1
f
=
−ꢀdB
is decreased to maintain low-frequency performance.
Since the added series resistance forms a voltage-
divider with the headphone speaker resistance for fre-
quencies within the passband of the highpass filter,
there is a loss in voltage gain. To compensate for this
loss, increase the voltage gain setting by an amount
equal to the attenuation due to the added series resis-
tance. Use the following equation to approximate the
required voltage gain compensation:
ꢁπR C
IN IN
Choose R according to the Gain-Setting Resistors sec-
IN
tion. Choose the C such that f
lowest frequency of interest. Setting f
is well below the
-ꢀdB
IN
too high affects
-ꢀdB
the amplifier’s low-frequency response. Use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with high-
voltage coefficients, such as ceramics, may result in an
increased distortion at low frequencies.
⎛
⎞
R +R
L
SERIES
A
= ꢁ±log
⎜
Other considerations when designing the input filter
include the constraints of the overall system,
the actual frequency band of interest, and click-and-
pop suppression.
V _COMP
⎟
R
⎝
⎠
L
C
R
OUT
SERIES
OUT_+
Output-Coupling Capacitor
The MAX9777/MAX9778 require output-coupling
capacitors to operate in single-ended (headphone)
mode. The output-coupling capacitor blocks the DC
component of the amplifier output, preventing DC cur-
rent from flowing to the load. The output capacitor and
R
L
Figure 9. Reducing C
by Adding R
SERIES
OUT
______________________________________________________________________________________ 19
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
BIAS Capacitor
where the impedance, C begins to decrease, and at
F,
BIAS is the output of the internally generated ꢁ.5VDC
high frequencies, the C is a short circuit. Here the
F
bias voltage. The BIAS bypass capacitor, C
,
impedance of the feedback loop is:
BIAS
improves PSRR and THD+N by reducing power supply
and other noise sources at the common-mode bias
node, and also generates the clickless/popless, start-
up/shutdown DC bias waveforms for the speaker ampli-
fiers. Bypass BIAS with a 1µF capacitor to GND.
R
× R
+ R
F1
Fꢁ
Fꢁ
R
=
F(EFF)
R
F1
Assuming R = R , then R
at low frequencies is
F1
Fꢁ
F(EFF)
F(EFF)
twice that of R
at high frequencies (Figure 11).
Supply Bypassing
Proper power-supply bypassing ensures low-noise, low-
distortion performance. Place a ±.1µF ceramic capacitor
Thus, the amplifier has more gain at lower frequencies,
boosting the system’s bass response. Set the gain roll-
off frequency based upon the response of the speaker
and enclosure.
from V
to GND. Add additional bulk capacitance as
DD
required by the application, typically 1±±µF. Bypass
PV with a 1±±µF capacitor to GND. Locate bypass
To minimize distortion at low frequencies, use capaci-
tors with low-voltage coefficient dielectrics when select-
ing C . Film or C±G dielectric capacitors are good
choices for C . Capacitors with high-voltage coeffi-
cients, such as ceramics (non-C±G dielectrics), can
result in increased distortion at low frequencies.
DD
capacitors as close to the device as possible.
F
Gain Select
F
The MAX9777/MAX9778 feature multiple gain settings on
each channel, making available different gain and feed-
/MAX978
back configurations. The gain-setting resistor (R ) is con-
F
Layout and Grounding
Good PC board layout is essential for optimizing perfor-
mance. Use large traces for the power-supply inputs
and amplifier outputs to minimize losses due to para-
sitic trace resistance, as well as route heat away from
the device. Good grounding improves audio perfor-
mance, minimizes crosstalk between channels, and
prevents any digital switching noise from coupling into
the audio signal. If digital signal lines must cross over
or under audio signal lines, ensure that they cross per-
pendicular to each other.
nected between the amplifier output (OUT_+) and the
gain set point (GAIN_). An internal multiplexer switches
between the different feedback resistors depending on
the status of the gain control input. The stereo
MAX9777/MAX9778 feature two gain options per chan-
nel. See Tables 1a and 1b for the gain-setting options.
Bass Boost Circuit
Headphones typically have a poor low-frequency
response due to speaker and enclosure size limitations.
A bass boost circuit compensates the poor low-frequen-
cy response (Figure 1±). At low frequencies, the capaci-
The MAX9777/MAX9778 TQFN package features an
exposed thermal pad. This pad lowers the package’s
thermal resistance by providing a direct heat conduc-
tion path from the die to the PC board. Connect the pad
to signal ground (±V) by using a large pad or multiple
vias to the ground plane.
tor C is an open circuit, and the effective impedance in
F
the feedback loop (R
) is R = R .
F(EFF) F(EFF) F1
At the frequency:
1
ꢁπR
C
F
Fꢁ
GAIN
R
R
F1
C
F
R
F2
IN
R
F1
R
IN
R
F1
R
F2
R
IN
FREQUENCY
1
V
BIAS
2π R
C
F
F2
Figure 11. Bass Boost Response
Figure 1±. Bass Boost Circuit
20 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Typical Application Circuits
4.5V TO 5.5V
100µF
0.1µF
3, 4
11, 25
DD
V
PV
DD
17
0.047µF
BIAS
27.4kΩ
1µF
33.2kΩ
15kΩ
8
GAINLB
220µF
10kΩ
7
GAINLA
OUTL+
10
15kΩ
5
6
INL1
INL2
INR1
INR2
0.68µF
12
OUTL-
0.68µF
0.68µF
0.68µF
15kΩ
15kΩ
15kΩ
HPF
CODEC
MAX9777
19
26
24
OUTR-
20
HPF
OUTR+
4.5V TO 5.5V
220µF
15kΩ
21
22
4.5V TO 5.5V
GAINRA
GAINRB
33.2kΩ
27.4kΩ
1kΩ
1kΩ
10kΩ
10kΩ
680kΩ
28
SCL
SDA
ADD
INT
1
15
2
0.047µF
47kΩ
16
HPS
MICROCONTROLLER
14
SHDN
GND
18
PGND
9, 13, 23, 27
______________________________________________________________________________________ 21
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Typical Application Circuits (continued)
4.5V TO 5.5V
100µF
0.1µF
3, 4
11, 25
DD
V
PV
DD
17
0.047µF
BIAS
27.4kΩ
1µF
33.2kΩ
15kΩ
8
GAINLB
220µF
10kΩ
7
GAINLA
OUTL+
10
15kΩ
5
6
INL1
INL2
INR1
INR2
0.68µF
12
/MAX978
OUTL-
0.68µF
0.68µF
0.68µF
15kΩ
15kΩ
15kΩ
HPF
CODEC
MAX9778
19
26
24
OUTR-
20
HPF
OUTR+
220µF
15kΩ
21
22
4.5V TO 5.5V
GAINRA
GAINRB
33.2kΩ
27.4kΩ
10kΩ
680kΩ
28
IN1/2
1
15
2
0.047µF
MUTE
47kΩ
16
HPS
MICROCONTROLLER
GAINA/B
HPS_EN
SHDN
14
GND
18
PGND
9, 13, 23, 27
22 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Functional Diagrams
4.5V TO 5.5V
100µF
0.1µF
11, 25
3, 4
PV
V
DD
DD
8
GAINLB
GAIN
SET
MUX
10kΩ
0.047µF
27.4kΩ
GAINLA 7
0.68µF 15kΩ
0.68µF 15kΩ
1µF
AUDIO
INPUT
AUDIO
INPUT
33.2kΩ
5
6
INL1
INL2
2:1
INPUT
MUX
15kΩ
10kΩ
10kΩ
OUTL+ 10
220µF
10kΩ
17 BIAS
BIAS
10kΩ
OUTL- 12
GAINRB
GAINRA
22
21
GAIN
SET
MUX
10kΩ
0.047µF
27.4kΩ
0.68µF
15kΩ
33.2kΩ
AUDIO
INPUT
AUDIO
INPUT
19 INR1
20 INR2
2:1
INPUT
MUX
10kΩ
15kΩ
10kΩ
OUTR+
24
0.68µF 15kΩ
4.5V TO 5.5V
220µF
10kΩ
1kΩ
1kΩ
10kΩ
10kΩ
14 SHDN
28 SCL
OUTR- 26
TO
1
15
2
SDA
ADD
INT
LOGIC
µCONTROLLER
HPS
16
HPS
MAX9777
GND
18
PGND
9, 13, 23, 27
______________________________________________________________________________________ 23
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Functional Diagrams (continued)
4.5V TO 5.5V
100µF
0.1µF
11, 25
3, 4
PV
V
DD
DD
8
GAINLB
GAIN
SET
MUX
10kΩ
0.047µF
27.4kΩ
GAINLA 7
0.68µF 15kΩ
0.68µF 15kΩ
1µF
AUDIO
INPUT
AUDIO
INPUT
33.2kΩ
5
6
INL1
INL2
2:1
INPUT
MUX
15kΩ
10kΩ
10kΩ
OUTL+ 10
220µF
10kΩ
17 BIAS
BIAS
10kΩ
/MAX978
OUTL- 12
GAINRB
GAINRA
22
21
GAIN
SET
MUX
10kΩ
0.047µF
27.4kΩ
0.68µF
15kΩ
33.2kΩ
AUDIO
INPUT
AUDIO
INPUT
19 INR1
20 INR2
2:1
INPUT
MUX
10kΩ
15kΩ
10kΩ
OUTR+
24
0.68µF 15kΩ
4.5V TO 5.5V
220µF
10kΩ
1kΩ
1kΩ
10kΩ
10kΩ
14
28
1
15
2
OUTR- 26
SHDN
IN1/2
MUTE
GAINA/B
HPS_EN
TO
LOGIC
µCONTROLLER
HPS
16
HPS
MAX9778
GND
18
PGND
9, 13, 23, 27
24 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Pin Configurations
TOP VIEW
TOP VIEW
21 20 19 18 17 16 15
21 20 19 18 17 16 15
14
13
14
13
GAINRB 22
PGND 23
SHDN
PGND
GAINRB 22
PGND 23
SHDN
PGND
12 OUTL-
12 OUTL-
24
25
26
27
28
24
25
26
27
28
OUTR+
PV
OUTR+
PV
PV
PV
DD
11
10
9
11
10
9
DD
DD
DD
MAX9777
MAX9778
OUTR-
PGND
SCL
OUTL+
PGND
OUTR-
PGND
IN1/2
OUTL+
PGND
+
+
8
8
GAINLB
GAINLB
1
2
3
4
5
6
7
1
2
3
4
5
6
7
THIN QFN
THIN QFN
______________________________________________________________________________________ 25
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
/MAX978
26 ______________________________________________________________________________________
Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux
/MAX978
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© ꢁ±±6 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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