MAX9880AEWM [MAXIM]
Low-Power, High-Performance Dual I2S Stereo Audio Codec Comprehensive Headset Detection; 低功耗，高性能的双立体声I2S音频编解码器的综合耳机检测
| 型号： | MAX9880AEWM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Power, High-Performance Dual I2S Stereo Audio Codec Comprehensive Headset Detection |
| 文件： | 总70页 (文件大小：1912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5139; Rev 1; 3/11
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
General Description
Features
o 1.8V Single-Supply Operation
The MAX9880A is a high-performance, stereo audio
codec designed for portable consumer applications
such as smartphones and tablets. Operating from a sin-
gle 1.8V supply to ensure low-power consumption, the
MAX9880A offers a variety of input and output configu-
rations for design flexibility. The MAX9880A can be
combined with an audio subsystem, such as the
MAX9877 or MAX9879, for a complete audio solution
for portable applications.
o 10.6mW Playback Power Consumption
o 8kHz to 96kHz Stereo DAC with 96dB Dynamic
Range
o 8kHz to 48kHz Stereo ADC with 82dB Dynamic
Range
o Support for Any Master Clock Between 10MHz to
60MHz
o Stereo Microphone Inputs Support Digital
The MAX9880A’s stereo differential microphone inputs
can support either analog or digital microphones. A
stereo single-ended line input, with a configurable pre-
amplifier, can either be recorded by the ADC or routed
directly to the headphone or line output amplifiers. The
stereo headphone amplifiers can be configured as dif-
ferential, single ended, or capacitorless. The stereo line
outputs have dedicated level adjustment.
Microphones
o Stereo Headphone Amplifiers: Differential
(30mW), Single-Ended, or Capacitorless (10mW)
o Stereo Line Inputs and Stereo Line Outputs
o Voiceband Filters with Stopband Attenuation
Greater than 70dB
o Battery-Measurement Auxiliary ADC
o Comprehensive Headset Detection
There are two digital audio interfaces. The primary
interface is intended for voiceband applications, while
the secondary interface can be used for high perfor-
mance stereo audio data. Two digital input streams can
be processed simultaneously and both digital inter-
faces support TDM and I2S data formats.
2
o Dual I S- and TDM-Compatible Digital Audio
Interfaces
2
o I C- or SPI-Compatible Control Bus with 3.6V
Tolerant Inputs
Ordering Information
The flexible clocking circuitry utilizes any available
10MHz to 60MHz system clock, eliminating the need for
an external PLL and multiple crystal oscillators. Both
the ADC and DAC can be operated synchronously or
asynchronously in master or slave mode. The ADC can
be operated from 8kHz to 48kHz sample rates, while
the DAC can be operated up to 96kHz.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
MAX9880AEWM+
MAX9880AETM+
48 WLP
48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
The MAX9880A prevents click and pop during volume
changes and during power-up and power-down. Audio
quality is further enhanced with user-configurable digital
filters for voice and audio data. Voiceband filters pro-
vide extra attenuation at the GSM packet frequency and
Simplified Block Diagram
DIGITAL
AUDIO
INTERFACE INTERFACE
DIGITAL
AUDIO
JACK SENSE/
MEASUREMENT
ADC
2
MIC
BIAS
MASTER
CLOCK
I C
greater than 70dB stopband attenuation at f /2. An I2C
INTERFACE
S
1
2
or SPI™ serial interface provides control for volume lev-
els, signal mixing, and general operating modes.
LEFT
DAC
LEFT
The MAX9880A is available in space-saving, 48-bump,
2.7mm x 3.5mm, 0.4mm-pitch WLP and 48-pin, 6mm x
6mm TQFN packages.
DIGITAL
FILTERING
RIGHT
DAC
RIGHT
Applications
Cellular Phones
MAX9880A
Tablet PCs
Portable Gaming Devices
Portable Multimedia Players
Functional Diagram/Typical Operating Circuit appears at
end of data sheet.
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.)
LINL, LINR, MICLP/DIGMICDATA,
DVDD, AVDD, PVDD ................................................-0.3V to +2V
DVDDS1, JACKSNS, MICVDD ..............................-0.3V to +3.6V
DGND, PGND........................................................-0.1V to +0.1V
MICLN/DIGMICCLK, MICRP/SPDMDATA,
MICRN/SPDMCLK...............................-0.3V to (V
+ 0.3V)
AVDD
Continuous Power Dissipation (T = +70°C)
A
PREG, REF, REG....................................-0.3V to (V
MICBIAS .............................................-0.3V to (V
MCLK, LRCLKS1, BCLKS1,
SDINS1, SDOUTS1..........................-0.3V to (V
X1, X2, LRCLKS2, BCLKS2, SDINS2,
+ 0.3V)
+ 0.3V)
48-Bump WLP (derate 12.5mW/°C above +70°C) .....1000mW
48-Pin TQFN (derate 37mW/°C above +70°C) ..........2963mW
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
AVDD
MICVDD
DVDDS1
+ 0.3V)
+ 0.3V)
SDOUTS2, DOUT, MODE ...................-0.3V to (V
DVDD
MX980A
SDA/DIN, SCL/SCLK, CS, IRQ ..............................-0.3V to +3.6V
LOUTP, LOUTN, ROUTP, ROUTN,
LOUTL, LOUTR ....................(V
- 0.3V) to (V
+ 0.3V)
PVDD
PGND
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
WLP
Junction-to-Ambient Thermal Resistance (θ )................42°C/W
Junction-to-Ambient Thermal Resistance (θ )...............27°C/W
Junction-to-Case Thermal Resistance (θ )......................1°C/W
JA
JA
Junction-to-Case Thermal Resistance (θ ).......................5°C/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= 2.2µF, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
REF
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.65
1.65
TYP
1.8
MAX
1.95
3.6
UNITS
PVDD, DVDD, AVDD
DVDDS1, MICVDD
Supply Voltage Range
V
1.8
Analog (AVDD + PVDD +
MICVDD)
5.33
1.4
8
2
Full-duplex 8kHz
mono (Note 3)
Digital (DVDD + DVDDS1)
Analog (AVDD + PVDD +
MICVDD)
DAC playback
48kHz stereo
(Note 3)
3.5
6
Digital (DVDD + DVDDS1)
2.5
4
Total Supply Current
I
mA
VDD
Analog (AVDD + PVDD +
MICVDD)
8.4
12
5
Full-duplex 48kHz
stereo (Note 3)
Digital (DVDD + DVDDS1)
3.0
Analog (AVDD + PVDD +
MICVDD)
Stereo line-in to
line-out only,
4.9
8
T
= +25°C
A
Digital (DVDD + DVDDS1)
0.012
0.3
0.05
2
Analog (AVDD + PVDD +
MICVDD)
Shutdown Supply
Current
T
A
= +25°C
µA
Digital (DVDD + DVDDS1)
2.6
8
Shutdown to Full
Operation
Excludes PLL lock time
10
ms
2
_______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
DAC (Note 4)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Master or slave mode
Slave mode
96
Dynamic Range
(Note 5)
f
T
= 48kHz, AV
= 0dB,
VOL
S
DR
dB
= +25°C
A
88
Differential mode
1
Full-Scale Output
Gain Error
V
RMS
Capacitorless and single-ended modes
0.56
DC accuracy, measured with respect to full-scale
output
1
5
%
1kHz, 0dB input, highpass
f
f
= 8kHz
1.2
0.59
-75
S
S
filter disabled measured from
digital input to analog output;
MODE = 0 (IIR voice)
Voice Path Phase Delay
P
ms
dB
DLY
= 16kHz
Total Harmonic
Distortion
f = 12.288MHz, f = 48kHz, 0dBFS, measured
MCLK S
THD
at headphone outputs
VDACA/SDACA = 0xF to 0x0
VDACG = 00 to 11
DAC Attenuation Range
DAC Gain Adjust
AV
-15
0
0
dB
dB
DAC
AV
+18
GAIN
V
= V
= 1.65V to 1.95V
= 100mV , AV = 0dB
VOL
85
85
80
74
AVDD
PVDD
f = 217Hz, V
Power-Supply Rejection
Ratio
RIPPLE
P-P
PSRR
dB
f = 1kHz, V
= 100mV , AV
= 0dB
VOL
RIPPLE
P-P
f = 10kHz, V
= 100mV , AV
= 0dB
VOL
RIPPLE
P-P
DAC VOICE MODE DIGITAL IIR LOWPASS FILTER (6x Interpolation)
With respect to f within ripple; f = 8kHz to 48kHz
0.448 x f
0.451 x f
±0.1
S
S
S
S
Passband Cutoff
f
Hz
PLP
-3dB cutoff
f < f
Passband Ripple
Stopband Cutoff
dB
Hz
dB
PLP
f
With respect to f ; f = 8kHz to 48kHz
0.476 x f
SLP
S
S
S
Stopband Attenuation
f > f
, f = 20Hz to 20kHz
SLP
75
DAC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
DVFLT = 0x1
0.0161 x
(Elliptical tuned for 16kHz GSM + 217Hz notch)
f
S
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312 x
5th-Order Passband
Cutoff
f
S
DVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0321 x
(-3dB from Peak,
f
Hz
DHPPB
f
S
2
I C Register
DVFLT = 0x4
0.0625 x
Programmable)
(500Hz Butterworth tuned for 8kHz)
f
S
DVFLT = 0x5
0.0042 x
(f /240 Butterworth)
S
f
S
_______________________________________________________________________________________
3
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DVFLT = 0x1
0.0139 x
(Elliptical tuned for 16kHz GSM + 217Hz notch)
f
S
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0156 x
5th-Order Stopband
Cutoff
f
S
MX980A
DVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0279 x
(-30dB from Peak,
f
Hz
DHPSB
f
S
2
I C Register
DVFLT = 0x4
0.0312 x
Programmable)
(500Hz Butterworth tuned for 8kHz)
f
S
DVFLT = 0x5
0.0021 x
(f /240 Butterworth)
S
f
S
DC Attenuation
DC
DVFLT not equal to 000
90
dB
Hz
ATTEN
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 0 for f
< 50kHz)
LRCLK
With respect to f within ripple; f = 8kHz to 48kHz
0.43 x f
0.47 x f
0.50 x f
±0.1
S
S
S
S
S
Passband Cutoff
f
f
-3dB cutoff
PLP
SLP
-6.02dB cutoff
Passband Ripple
Stopband Cutoff
f < f
dB
Hz
dB
PLP
With respect to f ; f = 8kHz to 48kHz; f = 0.58 f
S
S
S
0.58 x f
S
to 7.42 f
S
Stopband Attenuation
f > f
60
SLP
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER (DHF = 1 for f
> 50kHz)
LRCLK
Ripple limit cutoff
0.24 x f
0.33 x f
0.1
S
S
Passband Cutoff
f
Hz
PLP
-3dB cutoff
f < f
Passband Ripple
Stopband Cutoff
dB
Hz
dB
PLP
f
With respect to f ; f = 0.5 f to 3.5 f
0.5 x f
S
SLP
S
S
S
Stopband Attenuation
f > f
60
SLP
DAC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER
Passband Cutoff
0.000625 x
f
DVFLT = 0x1 (DAI1), DCB = 1 (DAI2)
DVFLT = 0x1 (DAI1), DCB = 1 (DAI2)
Hz
dB
DHPPB
(-3dB from Peak)
DC Attenuation
ADC (Note 6)
f
S
DC
90
ATTEN
f
f
= 8kHz, MODE = 0 (IIR voice), T = +25°C
72
82
Dynamic Range
(Note 5)
S
A
DR
dB
= 8kHz to 48kHz, MODE = 1 (FIR audio) (Note 7)
84
S
Differential MIC input or stereo line inputs,
AV = 0dB, AV = 0dB
Full-Scale Input
1
V
P-P
PRE
PGAM
DC accuracy, measured with respect to 80% of full-
scale output
Gain Error (Note 7)
1
5
%
1kHz, 0dB input, highpass
f
f
= 8kHz
1.2
S
S
filter disabled measured from
analog input to digital output;
MODE = 0 (IIR voice)
Voice Path Phase Delay
ms
= 16kHz
0.61
4
_______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
Total Harmonic
Distortion
SYMBOL
CONDITIONS
MIN
TYP
MAX
-70
UNITS
dB
THD
f = 1kHz, f = 8kHz, T = +25°C, -20dB input
-80
S
A
ADC Level Adjust
AV
AVL/AVR = 0xF to 0x0
-12
60
+3
dB
ADC
V
AVDD
= 1.65V to 1.95V, input referred
80
80
f = 217Hz, V
= 100mV , AV
= 0dB,
ADC
RIPPLE
P-P
input referred
Power-Supply Rejection
Ratio
PSRR
dB
f = 1kHz, V
referred
= 100mV , AV
= 0dB, input
ADC
RIPPLE
P-P
78
72
f = 10kHz, V
= 100mV , AV
= 0dB,
ADC
RIPPLE
P-P
input referred
ADC VOICE MODE DIGITAL IIR LOWPASS FILTER
With respect to f within ripple; f = 8kHz to 48kHz
0.445 x f
0.449 x f
0.1
S
S
S
S
Passband Cutoff
f
f
Hz
PLP
SLP
-3dB cutoff
f < f
Passband Ripple
Stopband Cutoff
dB
Hz
dB
PLP
With respect to f ; f = 8kHz to 48kHz
0.469 x f
S
S
S
Stopband Attenuation
f > f
, f = 20Hz to 20kHz
SLP
74
ADC VOICE MODE DIGITAL 5th-ORDER IIR HIGHPASS FILTER
AVFLT = 0x1
0.0161 x
(Elliptical tuned for 16kHz GSM + 217Hz notch)
f
S
AVFLT = 0x2
0.0312 x
(500Hz Butterworth tuned for 16kHz)
f
S
Passband Cutoff
(-3dB from Peak)
f
Hz
AHPPB
AVFLT = 0x3
(Elliptical tuned for 8kHz GSM + 217Hz notch)
0.0321 x
f
S
AVFLT = 0x4
0.0625 x
(500Hz Butterworth tuned for 8kHz)
f
S
AVFLT = 0x5 (f /240 Butterworth)
S
0.0042 x f
0.0139 x
S
S
AVFLT = 0x1 (Elliptical tuned for 16kHz GSM +
217Hz notch)
f
S
AVFLT = 0x2 (500Hz Butterworth tuned for 16kHz)
0.0156 x f
0.0279 x
Stopband Cutoff
(-30dB from Peak)
f
Hz
AHPSB
AVFLT = 0x3 (Elliptical tuned for 8kHz GSM +
217Hz notch)
f
S
AVFLT = 0x4 (500Hz Butterworth tuned for 8kHz)
0.0312 x f
0.0021 x f
90
S
S
AVFLT = 0x5 (f /240 Butterworth)
S
DC Attenuation
DC
AVFLT ꢀ 000
dB
Hz
ATTEN
ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
With respect to f within ripple; f = 8kHz to 48kHz
0.43 x f
0.48 x f
S
S
S
S
Passband Cutoff
f
PLP
-3dB cutoff
-6.02dB cutoff
0.5 x f
S
_______________________________________________________________________________________
5
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
±0.1
MAX
UNITS
dB
Passband Ripple
Stopband Cutoff
f < f
PLP
f
With respect to f ; f = 8kHz to 48kHz
0.58 x f
60
Hz
SLP
S
S
S
Stopband Attenuation
f > f
, f = 20Hz to 20kHz
dB
SLP
ADC STEREO AUDIO MODE DIGITAL DC-BLOCKING HIGHPASS FILTER
MX980A
Passband Cutoff
(-3dB from Peak)
0.000625
x f
f
AVFLT = 0x1
AVFLT = 0x1
Hz
dB
AHPPB
S
DC Attenuation
DC
90
ATTEN
OUTPUT VOLUME CONTROL
VOLL/VOLR = 0x00
8.1
7.6
7.1
6.1
3.1
-5.9
-60
-94
8.6
8.1
7.6
6.6
3.6
-5.4
-55.1
-84
0.5
1
9.2
8.6
8.1
7.2
4.3
-4.9
-52
-81
VOLL/VOLR = 0x01
VOLL/VOLR = 0x02
VOLL/VOLR = 0x04
Output Volume Control
(Note 8)
dB
VOLL/VOLR = 0x08
VOLL/VOLR = 0x10
VOLL/VOLR = 0x20
VOLL/VOLR = 0x27
VOLL/VOLR = 00x00 to 0x06 (+9dB to +6dB)
VOLL/VOLR = 00x06 to 0x0F (+6dB to +3dB)
VOLL/VOLR = 00x0F to 0x17 (-3dB to -19dB)
VOLL/VOLR = 00x17 to 0x27 (-19dB to -81dB)
Output Volume Control
Step Size
dB
dB
2
4
Output Volume Control
Mute Attenuation
f = 1kHz
100
HEADPHONE AMPLIFIER (Note 9)
R = 16ꢀ
25
48
30
17
10
Output Power
(Differential Mode)
f = 1kHz, 0dBFS input,
L
P
P
mW
mW
OUT
OUT
THD < 1%, T = +25°C
A
R = 32ꢀ
L
R = 16ꢀ
L
Output Power
(Capacitorless Mode)
f = 1kHz, 0dBFS input,
THD < 1%, T = +25°C
A
R = 32ꢀ
L
Total Harmonic
Distortion + Noise
(Differential Mode)
R = 16ꢀ
-78
-79
-73
-75
-70
-70
-67
-60
-60
L
THD+N f = 1kHz, -3dBFS input
THD+N f = 1kHz, -3dBFS input
THD+N f = 1kHz, -3dBFS input
dB
dB
R = 32ꢀ
L
Total Harmonic
Distortion + Noise
(Capacitorless Mode)
R = 16ꢀ
L
R = 32ꢀ
L
Total Harmonic
Distortion + Noise
(Single-Ended Mode)
R = 16ꢀ
L
dB
dB
R = 32ꢀ
L
Dynamic Range
(Notes 5, 7)
DR
AV
= +6dB
77
90
VOL
6
_______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
80
MAX
UNITS
V
= V
= 1.65V to 1.95V
= 100mV , AV = 0dB
VOL
60
AVDD
PVDD
f = 217Hz, V
80
Power-Supply Rejection
Ratio (Note 7)
RIPPLE
P-P
PSRR
dB
f = 1kHz, V
= 100mV , AV = 0dB
VOL
78
RIPPLE
P-P
f = 10kHz, V
= 100mV , AV = 0dB
VOL
72
RIPPLE
P-P
AV
= -81dB,
LOUTP to LOUTN, ROUTP to
VOL
±0.2
±0.6
differential mode
ROUTN, T = +25°C
A
Output Offset Voltage
Crosstalk
V
mV
OS
AV = -81dB,
capacitorless mode LOUTN, T = +25°C
LOUTP to LOUTN, ROUTP to
VOL
A
Differential, P
= 5mW, f = 1kHz
90
45
OUT
XTALK
dB
pF
Capacitorless mode, P
= 5mW, f = 1kHz
OUT
R = 32ꢀ
500
100
Capacitive Drive
Capability
L
No sustained oscillations
R =
L
Click-and-Pop Level
(Differential,
Capacitorless Modes)
Into shutdown
-70
-70
Peak voltage, A-weighted,
32 samples per second
dBV
dBV
Out of shutdown
Into shutdown
-70
-70
Click-and-Pop Level
(Single-Ended Mode)
Peak voltage, A-weighted,
32 samples per second
Out of shutdown
LINE OUTPUTS (Note 7)
Full-Scale Output
0.5
-0.1
-2.1
-4.1
V
RMS
LOGL/LOGR = 0x00
LOGL/LOGR = 0x01
LOGL/LOGR = 0x02
-0.7
-2.6
-4.6
+0.6
-1.6
-3.6
Line Output Level
Adjust
AV
dB
LO
LOGL/LOGR = 0x04
LOGL/LOGR = 0x08
LOGL/LOGR = 0x0F
-8.6
-16.6
-31.1
-8.1
-16
-7.6
-15.6
-29.1
-29.9
Line Output Mute
Attenuation
f = 1kHz
90
dB
dB
dB
Total Harmonic
Distortion + Noise
THD+N R = 1kꢀ, f = 1kHz, V
= 1.4V (Note 9)
P-P
-67
-59
L
OUT
20Hz < f < 20kHz
A-weighted
86
90
46
78
80
76
R = 1kꢀ, LINL/LINR =
L
Signal-to-Noise Ratio
1µF to GND
V
AVDD
= V
= 1.65V to 1.95V
PVDD
f = 217Hz, V
= 100mV , AV
= 0dB
VOL
Power-Supply Rejection
Ratio
RIPPLE
P-P
PSRR
dB
pF
f = 1kHz, V
= 100mV , AV
= 0dB
VOL
RIPPLE
P-P
f = 10kHz, V
= 100mV , AV
= 0dB
VOL
RIPPLE
P-P
Capacitive Drive
Capability
R = 10kꢀ, no sustained oscillations
L
100
_______________________________________________________________________________________
7
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MICROPHONE AMPLIFIER
PALEN/PAREN = 01
PALEN/PAREN = 10
PALEN/PAREN = 11
-0.5
19.5
29.3
-0.5
19.3
0
20
30
0
+0.5
20.5
30.5
+0.6
20.4
Preamplifier Gain
AV
dB
dB
PRE
MX980A
PGAML/PGAMR = 0x1F
PGAML/PGAMR = 0x00
MIC PGA Gain
AV
PGAM
19.9
Common-Mode
Rejection Ratio
CMRR
V
= 100mV , f = 217Hz
50
50
dB
IN
P-P
MIC Input Resistance
RIN_MIC All gain settings
AV = 0dB
30
60
kꢀ
PRE
-80
V
= 1V , f = 1kHz, A-weighted
P-P
IN
Total Harmonic
Distortion + Noise
THD+N
dB
dB
V
AV
V
= +30dB
PRE
-65
80
= 32mV , f = 1kHz, A-weighted
P-P
IN
V
AVDD
= 1.65V to 1.95V, input referred
f = 217Hz, V
referred
= 100mV, AV
= 0dB, input
ADC
RIPPLE
80
Power-Supply Rejection
Ratio
PSRR
f = 1kHz, V
referred
= 100mV, AV
= 0dB, input
ADC
RIPPLE
78
72
f = 10kHz, V
referred
= 100mV, AV
= 0dB, input
ADC
RIPPLE
MICROPHONE BIAS
V
V
= 1.8V, MBIAS = 0
= 3V, MBIAS = 0
1.48
2.15
1.52
2.2
1.56
2.25
10
MICVDD
MICBIAS Output Voltage
V
I
= 1mA
MICBIAS LOAD
MICVDD
Load Regulation
Line Regulation
I
= 1mA to 2mA, MBIAS = 0
0.6
V/A
LOAD
V
AVDD
= 1.8V, V
= 1.65V to 1.95V, MBIAS = 0
1.55
100
90
mV/V
MICVDD
f = 217Hz, V
f = 10kHz, V
A-weighted
= 100mV
Power-Supply Rejection
Ratio
RIPPLE
P-P
P-P
PSRR
dB
= 100mV
RIPPLE
Noise Voltage
LINE INPUT
9.5
µV
RMS
P-P
Full-Scale Input
V
AV
= 0dB
LINE
1.0
23.9
21.9
20
V
IN
LIGL/LIGR = 0x00
LIGL/LIGR = 0x01
LIGL/LIGR = 0x02
LIGL/LIGR = 0x04
LIGL/LIGR = 0x08
22.8
20.7
18.9
14.9
6.9
24.9
22.9
20.9
16.9
8.9
Line Input Level Adjust
AV
dB
LINE
16
8
8
_______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
Line Input Mute
Attenuation
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
dB
f = 1kHz
AV = +24dB
100
Input Resistance
R
20
kꢀ
IN_LINE
LINE
Total Harmonic
Distortion + Noise
THD+N
V
= 0.1V , f = 1kHz
-74
dB
IN
P-P
AUXIN INPUT
Input DC Voltage Range
AUXIN Input Resistance
JACK DETECT
AUXEN = 1
0
0.738
0.98 x
V
AUXEN = 1, 0V ꢁ V
ꢁ 0.738V
R
10
40
Mꢀ
AUXIN
IN
0.92 x
0.95 x
SHDN = 1
SHDN = 0
SHDN = 1
SHDN = 0
SHDN = 0
SHDN = 0
V
V
V
MICBIAS MICBIAS MICBIAS
JACKSNS High
Threshold
V
V
V
TH1
TH2
0.95 x
MICVDD
V
0.06 x
0.10 x
0.17 x
V
V
V
MICBIAS MICBIAS MICBIAS
JACKSNS Low
Threshold
V
0.08 x
MICVDD
V
V
JACKSNS Sense
Voltage
V
R
V
kꢀ
ms
ꢀ
SENSE
SENSE
GLITCH
MICVDD
JACKSNS Sense
Resistance
1.9
12
2.3
3.1
JACKSNS Deglitch
Period
t
300
Headphone Sense
Threshold
8
1-BIT SPDM OUTPUT
Dynamic Range
(Note 5)
f = 48kHz, A-weighted, 20Hz to 20kHz,
S
DR
90
dB
%
AV
= 0dB; master or slave mode, T = +25°C
A
VOL
Output Operational
Range
0dB signal 1’s density
25
75
0
DIGITAL SIDETONE (MODE = 1 IIR Voice Mode Only)
Sidetone Gain Adjust
Range
AV
Differential output mode
-60
dB
ms
STGA
MIC input to headphone
output, f = 1kHz, HP filter
disabled
f
f
= 8kHz
2.2
1.1
S
S
Voice Path Phase Delay
P
DLY
= 16kHz
_______________________________________________________________________________________
9
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
MCLK Input Duty Cycle
f
For any LRCLK sample rate
Prescaler = /1 mode
/2 or /4 modes
10
40
30
60
60
70
MHz
%
MCLK
MX980A
Maximum MCLK Input
Jitter
Maximum allowable RMS for performance limits
100
ps
DHF = 0
DHF = 1
8
48
96
LRCLK Sample Rate
(Note 10)
kHz
48
FREQ1 mode = 0x8 to 0xF
0
0
0
0
LRCLK Average
Frequency Error (Master
and Slave Modes)
(Note 11)
%
PCLK = 192x, 256x, 384x, 512x, 768x, and 1024x
FREQ1 mode = Any clock other than above
-0.025
+0.025
Rapid lock mode
2
7
Any allowable LRCLK and
PCLK rate, slave mode
LRCLK PLL Lock Time
ms
Nonrapid lock mode
12
25
LRCLK Acceptable
Jitter for Maintaining
PLL Lock
Allowable LRCLK period change from nominal for
slave PLL mode at any allowable LRCLK and PCLK
rates
±100
ns
Soft-Start/Stop Time
CRYSTAL OSCILLATOR
Frequency
10
ms
Fundamental mode only
12.288
100
MHz
ꢀ
Maximum Crystal ESR
Input Leakage Current
Input Capacitance
I
, I
X1, T = +25°C
-1
+1
µA
pF
IH IL
A
C
, C
4
X1
X2
Maximum Load
Capacitor
C , C
L1 L2
45
pF
DIGITAL INPUT (MCLK)
Input High Voltage
Input Low Voltage
V
1.2
-1
V
V
IH
V
0.6
+1
IL
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
µA
pF
10
DIGITAL INPUTS (SDINS1, BCLKS1, LRCLKS1)
0.7
DVDDS1
Input High Voltage
Input Low Voltage
V
V
V
IH
x V
0.3
DVDDS1
V
IL
x V
Input Hysteresis
200
10
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
-1
+1
10 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SDA, SCL, DIN, SCLK, CS, MODE, SDINS2, BCLKS2, LRCLKS2)
0.7
Input High Voltage
Input Low Voltage
V
V
V
IH
x V
DVDD
0.3
V
IL
x V
DVDD
Input Hysteresis
200
10
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
-1
+1
DIGITAL INPUTS (DIGMICDATA)
0.65
Input High Voltage
Input Low Voltage
V
V
V
IH
x V
DVDD
0.35
V
IL
x V
DVDD
Input Hysteresis
100
10
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T = +25°C
A
-35
+35
CMOS DIGITAL OUTPUTS (BCLKS1, LRCLKS1, SDOUTS1)
Output Low Voltage
V
I
= 3mA
0.4
0.4
0.4
V
V
OL
OL
V
DVDDS1
- 0.4
Output High Voltage
V
I
= 3mA
OH
OH
CMOS DIGITAL OUTPUTS (BCLKS2, LRCLKS2, SDOUTS2)
Output Low Voltage
V
I
= 3mA
V
V
OL
OL
V
DVDD
- 0.4
Output High Voltage
V
I
= 3mA
OH
OH
CMOS DIGITAL OUTPUTS (DOUT)
Output Low Voltage
V
I
I
= 1mA, CS = DVDD
= 1mA, CS = DVDD
V
V
OL
OL
V
DVDD
- 0.4
Output High Voltage
V
OH
OH
Output Low Current
Output High Current
I
MODE = DVDD, DOUT = 0, T = +25°C
-1
-1
+1
+1
µA
µA
OL
A
I
MODE = DVDD, DOUT = DVDD, T = +25°C
A
OH
CMOS DIGITAL OUTPUTS (DIGMICCLK, SPDMDATA, SPDMCLK)
Output Low Voltage
V
I
= 1mA
0.4
V
V
OL
OL
V
DVDD
- 0.4
Output High Voltage
V
I
= 1mA
OH
OH
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Current
I
V
= V
, T = +25°C
-1
+1
µA
V
OH
OUT
DVDD
A
0.2
Output Low Voltage
V
I
= 3mA
OL
OL
x V
DVDD
______________________________________________________________________________________ 11
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL MICROPHONE TIMING CHARACTERISTICS (V
= 1.8V)
DVDD
MICCLK = 00
MICCLK = 01
MICCLK = 10
1.536
2.048
DIGMICCLK Frequency
f
f
= 12.288MHz
MHz
MICCLK
MCLK
64f
S
MX980A
DIGMICDATA to
DIGMICCLK Setup Time
t
t
Either clock edge
Either clock edge
20
0
ns
ns
SU, MIC
DIGMICDATA to
DIGMICCLK Hold Time
HD, MIC
SPDM TIMING CHARACTERISTICS
SPDMCLK = 00
SPDMCLK = 01
SPDMCLK = 10
1.536
2.048
3.072
SPDMCLK Frequency
f
f
= 12.288MHz
MHz
ns
SPDMCLK MCLK
Rising edge SPDMCLK
to right-channel valid
SPDMDATA and falling
edge SPDMCLK to left-
channel valid
Minimum, f
MCLK
= 20MHz
= 10MHz
15
65
SPDMCLK to
SPDMDATA Delay Time
t
DLY,SPDM
Maximum, f
MCLK
SPDMDATA
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 0, V
= 1.8V)
DVDD
BCLK Cycle Time
BCLK High Time
BCLK Low Time
t
75
30
30
ns
ns
ns
BCLKS
BCLKH
t
T
T
= +25°C
= +25°C
A
t
BCLKL
A
BCLK or LRCLK Rise
and Fall Time
t , t
Master operation, C = 15pF
7
ns
ns
ns
ns
R
F
L
SDIN or LRCLK to BCLK
Setup Time
t
t
20
5
SU
SDIN or LRCLK to BCLK
Hold Time
HD
SDOUT Delay Time from
BCLK Rising Edge
t
C = 30pF
L
0
40
DLY
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (TDM = 1, Figure 3, V
= 1.8V)
DVDD
TDM Clock Frequency
TDM Clock Time High
TDM Clock Time Low
1/t
TDM mode (TDM = 1)
TDM mode (TDM = 1), T = +25°C
128
220
220
2048
kHz
ns
CLK
t
CLKH
A
t
TDM mode (TDM = 1), T = +25°C
ns
CLKL
A
Short TDM mode (TDM = 1, FSW = 0), master mode
(MAS = 1)
200
TDM Short-Sync Setup
Time
t
ns
SYNCSET
Short TDM mode (TDM = 1, FSW = 0), slave mode
(MAS = 0)
20
12 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Short TDM mode (TDM = 1, FSW = 0), master mode
(MAS = 1)
200
TDM Short Sync Hold
Time
t
ns
SYNCHOLD
Short TDM mode (TDM = 1, FSW = 0), slave mode
(MAS = 0)
20
TDM Short Sync Tx Data
Delay
t
Short TDM mode (TDM = 1, FSW = 0)
Long TDM mode (TDM = 1, FSW = 1)
Long TDM mode (TDM = 1, FSW = 1)
TDM mode (TDM = 1)
12
3.4
51
ns
ns
ns
ns
ns
SYNCTX
TDM Long Sync Start
Delay
t
CLKSYNC
TDM Long Sync End
Time Setup
t
ENDSYNC
TDM Data Delay from
Clock
t
40
CLKTX
TDM High-Impedance
State Setup from Data
t
TDM mode (TDM = 1)
120
HIZOUT
TDM Rx Data Setup
Time
t
TDM mode (TDM = 1)
TDM mode (TDM = 1)
20
20
ns
ns
SETUP
TDM Rx Data Hold Time
t
HOLD
2
I C TIMING CHARACTERISTICS (V
= 1.65V)
DVDD
Serial-Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between
STOP and START
Conditions
t
1.3
BUF
Hold Time (Repeated)
START Condition
t
t
0.6
µs
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a
Repeated START
Condition
0.6
µs
SU,STA
Data Hold Time
Data Setup Time
t
t
R
= 475ꢀ
PU,SDA
0
900
ns
ns
HD,DAT
SU,DAT
100
SDA and SCL Receiving
Rise Time
20 +
t
(Note 12)
(Note 12)
300
300
250
ns
ns
ns
µs
R
0.1C
B
SDA and SCL Receiving
Fall Time
20 +
0.1C
t
t
F
F
B
SDA Transmitting Fall
Time
20 +
R
= 475ꢀ (Note 12)
PU,SDA
0.1C
B
Setup Time for STOP
Condition
t
0.6
SU,STO
______________________________________________________________________________________ 13
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
REF
= V
= 2.2µF, C
= V
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN, dif-
AVDD
PVDD
MICVDD
DVDD
DVDDS1
L
L
ferential modes, C
= C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB,
MICBIAS
PREG
REG
PRE
PGAM
DAC
LINE
AV
= 0dB, AV = 0dB, f
= 13MHz, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
VOL
LO
MCLK
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bus Capacitance
C
B
400
pF
Pulse Width of
Suppressed Spike
t
0
50
ns
SP
SPI TIMING CHARACTERISTICS
MX980A
Minimum SCLK Clock
Period
t
40
18
18
ns
ns
ns
CP
Minimum SCLK Pulse-
Width Low
t
CL
Minimum SCLK Pulse-
Width High
t
CH
Minimum CS Setup
Time
t
20
20
20
ns
ns
ns
CSS
CSH
CSW
Minimum CS Hold Time
t
Minimum CS Pulse-
Width High
t
Minimum DIN Setup Time
Minimum DIN Hold Time
t
5
5
ns
ns
DS
t
DH
Minimum Output Data
Propagation Delay
t
C = 50pF
L
9
5
5
ns
ns
ns
DO
Minimum Output Data
Enable Time
t
DEN
Minimum Output Data
Disable Time
t
DZ
Note 2: The MAX9880A is 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by
A
design.
Note 3: Clocking all zeros into the DAC. Master mode. Differential headphone mode.
Note 4: DAC performance measured at headphone outputs.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 6: Performance measured using microphone inputs, unless otherwise stated.
Note 7: Performance measured using line inputs.
Note 8: Performance measured using line inputs to line outputs.
Note 9: Performance measured using DAC. f
= 12.288MHz, f
= 48kHz, unless otherwise stated.
MCLK
LRCLK
Note 10: LRCLK can be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios can exhibit some full-
scale performance degradation compared to synchronous integer-related MCLK/LRCLK ratios.
Note 11: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock
rate.
Note 12: C is in pF.
B
14 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Typical Operating Characteristics
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
PRE
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
= 1µF, AV
L
L
C
REF
= C
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
R
= 13MHz
= 8kHz
= 16Ω
f
f
R
= 13MHz
= 8kHz
= 32Ω
f
f
= 12.288MHz
= 48kHz
MCLK
LRCLK
LOAD
MCLK
LRCLK
LOAD
MCLK
LRCLK
1kHz
R
LOAD
= 32Ω
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
3kHz
3kHz
1kHz
1kHz
6kHz
20Hz
20Hz
20Hz
50
0
10
20
30
40
60
0
10
20
30
40
50
0
10
20
30
40
50
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
= 12.288MHz
= 48kHz
f
f
= 12.288MHz
= 96kHz
f
f
= 12.288MHz
= 96kHz
MCLK
LRCLK
MCLK
LRCLK
MCLK
LRCLK
R
LOAD
= 16Ω
R
LOAD
= 16Ω
R
LOAD
= 32Ω
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
1kHz
1kHz
1kHz
6kHz
6kHz
6kHz
20Hz
40
20Hz
20Hz
0
10
20
30
40
50
60
0
10
20
30
40
50
60
0
10
20
30
50
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
-70
-75
-80
-85
-90
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
f
f
R
= 13MHz
= 8kHz
= 32Ω
f
f
R
= 13MHz
= 8kHz
= 16Ω
f
f
= 12.288MHz
= 48kHz
MCLK
LRCLK
LOAD
MCLK
LRCLK
LOAD
MCLK
LRCLK
R = 32Ω
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
5mW
5mW
5mW
20mW
20mW
20mW
10
100
1000
10,000
10
100
1000
10,000
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
______________________________________________________________________________________ 15
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
f
f
= 12.288MHz
= 48kHz
f
f
= 12.288MHz
= 96kHz
f
f
= 12.288MHz
= 96kHz
MCLK
LRCLK
MCLK
LRCLK
MCLK
LRCLK
R
= 16Ω
R
= 32Ω
R = 16Ω
LOAD
LOAD
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
5mW
MX980A
5mW
5mW
20mW
20mW
20mW
10
100
1k
10k
100k
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
R
= 13MHz
= 8kHz
= 32Ω
f
f
= 12.288MHz
= 48kHz
f
f
= 12.288MHz
= 96kHz
MCLK
LRCLK
LOAD
MCLK
LRCLK
MCLK
LRCLK
R
LOAD
= 32Ω
R = 32Ω
LOAD
CAPACITORLESS MODE
CAPACITORLESS MODE
CAPACITORLESS MODE
3kHz
1kHz
6kHz
1kHz
20Hz
1kHz
20Hz
6kHz
20Hz
0
5
10
15
0
5
10
15
0
5
10
15
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
-60
-65
-70
-75
-80
-85
-90
-60
-65
-70
-75
-80
-85
-90
-60
-65
-70
-75
-80
-85
-90
f
f
R
= 13MHz
= 8kHz
= 32Ω
f
f
= 12.288MHz
= 48kHz
f
f
= 12.288MHz
= 96kHz
MCLK
LRCLK
LOAD
MCLK
LRCLK
MCLK
LRCLK
R
= 32Ω
R = 32Ω
LOAD
LOAD
CAPACITORLESS MODE
CAPACITORLESS MODE
CAPACITORLESS MODE
5mW
1mW
1mW
5mW
20mW
5mW
10
100
1000
10,000
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
16 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
R
= 13MHz
= 8kHz
= 32Ω
f
f
= 12.288MHz
= 48kHz
MCLK
LRCLK
LOAD
MCLK
LRCLK
f
f
= 12.288MHz
= 96kHz
MCLK
LRCLK
R
LOAD
= 32Ω
R
LOAD
= 32Ω
SINGLE-ENDED MODE
SINGLE-ENDED MODE
SINGLE-ENDED MODE
1kHz
1kHz
1kHz
6kHz
20Hz
20Hz
3kHz
6kHz
20Hz
12
0
2
4
6
8
10
12
0
2
4
6
8
10
12
0
3
6
9
15
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTON + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
-60
-65
-70
-75
-80
-85
-90
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-60
-65
-70
-75
-80
-85
-90
f
f
R
= 13MHz
= 8kHz
= 32Ω
f
f
= 12.288MHz
= 96kHz
MCLK
LRCLK
LOAD
MCLK
LRCLK
1mW
R
= 32Ω
LOAD
SINGLE-ENDED MODE
SINGLE-ENDED MODE
5mW
1mW
5mW
20mW
5mW
f
f
= 12.288MHz
= 48kHz
MCLK
LRCLK
R
= 32Ω
LOAD
SINGLE-ENDED MODE
10
100
1000
10,000
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE-IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE-IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE-IN TO HEADPHONE)
10
1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
LINE-IN PREAMP = +18dB
LINE-IN PREAMP = 0dB
LINE-IN PREAMP = +18dB
R
= 32Ω
R
= 32Ω
LOAD
LOAD
1kHz
R
= 32I
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
6kHz
5mW
0.1
1kHz
6kHz
20Hz
20Hz
40
0.01
0.001
20mW
10
100
1000
FREQUENCY (Hz)
10,000
100,000
0
10
20
30
40
50
0
10
20
30
50
POWER OUT (mW)
POWER OUT (mW)
______________________________________________________________________________________ 17
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE-IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO LINE-OUT)
POWER OUT vs. HEADPHONE LOAD
10
1
-30
-40
-50
-60
-70
-80
-90
50
45
40
35
30
25
20
15
10
5
f
f
= 13MHz
= 8kHz
f
f
= 12.288MHz
= 48kHz
MCLK
LRCLK
MCLK
LRCLK
LINE-IN PREAMP = 0dB
R
= 32I
LOAD
0dBFS
THD+N ≤ 0.1%
DIFFERENTIAL MODE
DIFFERENTIAL MODE
MX980A
IIR
0.1
5mW
0.01
0.001
FIR
20mW
0
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
1
10
100
1000
FREQUENCY (Hz)
HEADPHONE LOAD (Ω)
OUTPUT POWER vs. LOAD RESISTANCE
(DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
POWER OUT vs. HEADPHONE LOAD
25
20
15
10
5
25
20
15
10
5
10
1
f
f
= 12.288MHz
= 48kHz
f
f
= 12.288MHz
= 48kHz
MCLK
LRCLK
f
f
= 13MHz
= 8kHz
MCLK
LRCLK
MCLK
LRCLK
THD+N ≤ 0.1%
SINGLE-ENDED MODE
THD+N ≤ 0.1%
CAPACITORLESS MODE
MICPRE = 0dB
= 1V
V
IN
P-P
0.1
0.01
0.001
0
0
1
10
100
1000
1
10
100
1000
10
100
1000
10,000
HEADPHONE LOAD (Ω)
HEADPHONE LOAD (Ω)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
10
1
0
-20
100
10
f
f
= 12.288MHz
= 48kHz
f
f
= 13MHz
= 8kHz
MCLK
LRCLK
MCLK
LRCLK
f
f
= 13MHz
= 8kHz
MCLK
LRCLK
V
= 100mV
MICPRE = +20dB
RIPPLE
P-P
MICPRE = +30dB
= 32mV
V
IN
= 100mV
P-P
V
IN
P-P
-40
1
0.1
-60
0.1
-80
0.01
0.001
0.01
0.001
-100
-120
10
100
1000
10,000
1
10
100
1k
10k
100k
10
100
1000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
18 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICROPHONE TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICBIAS)
FFT, DAC TO HEADPHONE,
0dBFS, f
= 13MHz, f
= 8kHz
MCLK
LRCLK
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-20
20
0
V
= 100mV
P-P
= 12.288MHz
= 48kHz
FREQ1 = 0xA
RIPPLE
V
= 100mV
RIPPLE P-P
f
f
MCLK
LRCLK
-20
-40
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
0
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, DAC TO HEADPHONE,
FFT, DAC TO HEADPHONE,
FFT, DAC TO HEADPHONE,
-60dBFS, f
= 13MHz, f
= 8kHz
0dBFS, f
= 12.288MHz, f
= 48kHz
-60dBFS, f
= 12.288MHz, f = 48kHz
MCLK
LRCLK
MCLK
LRCLK
MCLK
LRCLK
20
0
20
20
FREQ1 = 0xA
NI = 0x6000
NI = 0x6000
0
0
-20
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
-140
0
5k
10k
15k
20k
0
5k
10k
15k
20k
0
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, DAC TO HEADPHONE,
FFT, DAC TO HEADPHONE,
FFT, DAC TO HEADPHONE,
0dBFS, f
= 12.288MHz, f
= 96kHz
-60dBFS, f
= 12.288MHz, f
= 96kHz
0dBFS, f
= 13MHz, f
= 48kHz
MCLK
LRCLK
MCLK
LRCLK
MCLK
LRCLK
20
20
20
0
NI = 0x6000
DHF = 1
PLL MODE
NI = 0x6000
DHF = 1
0
0
-20
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
-140
0
5k
10k
15k
20k
0
5k
10k
15k
20k
0
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
______________________________________________________________________________________ 19
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
FFT, DAC TO HEADPHONE,
FFT, DAC TO HEADPHONE,
FFT, DAC TO HEADPHONE,
-60dBFS, f
= 13MHz, f
= 48kHz
0dBFS, f
= 13MHz, f
= 44.1kHz
-60dBFS, f
= 13MHz, f
= 44.1kHz
MCLK
LRCLK
MCLK
LRCLK
MCLK
LRCLK
20
0
20
0
20
PLL MODE
PLL MODE
PLL MODE
0
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
MX980A
0
5k
10k
15k
20k
0
5k
10k
15k
20k
0
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, MICROPHONE TO ADC,
FFT, MICROPHONE TO ADC,
0dBFS, f
= 13MHz, f
= 8kHz
0dBFS, f
= 12.288MHz, f
= 48kHz
MCLK
LRCLK
MCLK
LRCLK
0
0
-20
20
FREQ1 = 0xA
NI = 0x6000
0
-20
-40
-20
-40
-60
-80
-100
-120
-140
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
1000
2000
3000
4000
0
1000
2000
3000
4000
0
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, MICROPHONE TO ADC,
FFT, MICROPHONE TO ADC,
FFT, MICROPHONE TO ADC,
-60dBFS, f
= 12.288MHz, f
= 48kHz
0dBFS, f
= 13MHz, f
= 48kHz
-60dBFS, f
= 13MHz, f
= 48kHz
MCLK
LRCLK
MCLK
LRCLK
MCLK
LRCLK
20
20
0
0
NI = 0x6000
PLL MODE
PLL MODE
0
-20
-20
-40
-20
-40
-60
-80
-100
-120
-140
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5k
10k
15k
20k
0
5k
10k
15k
20k
0
5k
10k
15k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
20 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
WIDEBAND FFT, DAC TO HEADPHONE,
0dBFS, f = 13MHz, f = 8kHz
WIDEBAND FFT, DAC TO HEADPHONE,
-60dBFS, f = 13MHz, f = 8kHz
DAC IIR HIGHPASS FILTER FREQUENCY
RESPONSE, MODE = 0
MCLK
FREQ1 = 0xA
LRCLK
MCLK
LRCLK
20
0
0
-20
20
0
DVFLT = 0
f
= 8kHz
LRCLK
FREQ1 = 0xA
-20
-40
-60
-80
-100
-120
-140
DVFLT = 3
-40
-20
-40
-60
-80
-100
-60
-80
-100
-120
-140
DVFLT = 4
0
20k
40k
60k
80k
100k 120k
0
20k
40k
60k
80k
100k 120k
0
100
200
300
400
500
600
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
ADC IIR HIGHPASS FILTER FREQUENCY
RESPONSE, MODE = 0
DAC IIR/FIR LOWPASS FILTER FREQUENCY
RESPONSE (f = 8kHz)
DAC FIR LOWPASS FILTER FREQUENCY
RESPONSE (f = 96kHz)
LRCLK
MODE = 1
LRCLK
20
20
0
20
0
AVFLT = 0
f
= 8kHz
LRCLK
0
-20
AVFLT = 3
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
MODE = 0
-40
-60
AVFLT = 4
-80
-100
0
100
200
300
400
500
600
3000
3200
3400
3600
3800
4000
20k 24k 28k 32k 36k 40k 44k 48k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
ADC IIR/FIR LOWPASS FILTER FREQUENCY
RESPONSE (f = 8kHz)
SHUTDOWN TO FULL OPERATION
(DIFFERENTIAL)
SHUTDOWN TO FULL OPERATION
(SE CLICKLESS)
LRCLK
MODE = 1
20
0
-20
-40
-60
-80
-100
MODE = 0
3000
3200
3400
3600
3800
4000
TIME (4ms/div)
TIME (40ms/div)
FREQUENCY (Hz)
______________________________________________________________________________________ 21
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= 2.2µF, C
= V
MICBIAS
= V
PREG
= V
REG
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN,
AVDD
PVDD
MICVDD
DVDD
= C
DVDDS1
L
L
C
REF
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
= 0dB,
VOL
PRE
PGAM
DAC
LINE
AV = 0dB, f
= 13MHz, differential output, unless otherwise noted.)
LO
MCLK
SHUTDOWN TO FULL OPERATION
(SE FAST TURN ON)
FULL OPERATION TO SHUTDOWN
SOFT-START ADC
MX980A
TIME (4ms/div)
TIME (400µs/div)
TIME (1ms/div)
TOTAL HARMONIC DISTORTION + NOISE
DYNAMIC RANGE vs. MCLK FREQUENCY
vs. MCLK FREQUENCY, 0dBFS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
120
110
100
90
f
= 48kHz
V
= -60dBFS
= 48kHz
LRCLK
IN
PLL MODE
f
LRCLK
PLL MODE
80
70
60
10
100
10
100
MCLK FREQUENCY (MHz)
MCLK FREQUENCY (MHz)
LINE INPUT RESISTANCE
vs. GAIN SETTING
AUX CODE vs. INPUT VOLTAGE
30,000
25,000
20,000
15,000
10,000
5000
300
250
200
150
100
50
0
-5000
0
-0.4 -0.2
0
0.2 0.4 0.6 0.8 1.0 1.2
INPUT VOLTAGE (V)
-10
-5
0
5
10
15
20
25
GAIN SETTING (dB)
22 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
MAX9880A
1
2
3
4
5
6
7
8
+
DGND
X1
X2
IRQ
MODE
AVDD
PREG
AGND
A
B
C
D
E
DVDD
SDINS2
MCLK
SDA/DIN
LRCLKS2
SDOUTS2
BCLKS1
SCL/SCLK
BCLKS2
SDINS1
PVDD
CS
DOUT
N.C.
REF
REG
MICVDD
MICLN/
MICBIAS
MICRP/
N.C.
DIGMICCLK SPDMDATA
JACKSNS/
AUX
MICLP/
DIGMICDATA SPDMCLK
MICRN/
N.C.
N.C.
LRCLKS1
SDOUTS1
LOUTP
LOUTN
ROUTP
ROUTN
PGND
PGND
LOUTL
LOUTR
LINL
LINR
DVDDS1
PVDD
F
WLP
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
24
23
22
21
20
19
18
17
16
15
14
13
SDOUTS1 37
LINR
38
39
40
41
42
43
44
45
46
47
48
SDINS1
LRCLKS1
BCLKS1
MCLK
LINL
JACKSNS/AUX
MICRN/SPDMCLK
MICRP/SPDMDATA
MICLP/DIGMICDATA
MICLN/DIGMICCLK
MICBIAS
MAX9880A
SDOUTS2
SDINS2
LRCLKS2
BCLKS2
DVDD
MICVDD
AGND
*EP
+
DGND
N.C.
N.C.
REG
2
3
4
5
6
7
8
9
10
1
11
12
THIN QFN
(6mm × 6mm)
*EP = EXPOSED PAD
______________________________________________________________________________________ 23
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Pin Description
PIN
NAME
FUNCTION
TQFN-EP
WLP
2
I C Serial-Data Input/Output (MODE = 0). Connect a pullup resistor to DVDD for
full output swing. SPI compatible serial-data input (MODE = 1).
1
B2
SDA/DIN
SCL/SCLK
X1
2
I C Serial-Clock Input (MODE = 0). Connect a pullup resistor to DVDD for full
output swing. SPI-compatible serial clock input (MODE = 1).
2
3
4
B3
A2
A3
Crystal Oscillator Input. Connect load capacitor and one terminal of the crystal
to this pin. Acceptable input frequency range: 10MHz to 30MHz.
MX980A
Crystal Oscillator Output. Connect load capacitor and second terminal of the
crystal to this pin.
X2
5
6
7
B4
B5
A5
CS
SPI-Compatible, Active-Low Chip-Select Input
SPI-Compatible Serial-Data Output
DOUT
MODE
2
2
I C/SPI Mode Select Input (MODE = 0 for I C mode, MODE = 1 for SPI mode)
Hardware Interrupt Output. IRQ can be programmed to go low when bits in the
status register 0x00 are set. Read status register 0x00 to clear IRQ once set.
Repeat faults have no effect on IRQ until it is cleared by reading the I C status
8
A4
IRQ
2
register 0x00. Connect a 10kꢀ pullup resistor to DVDD for full output swing.
9
A6
B6
AVDD
REF
Analog Power Supply. Bypass to AGND with a 1µF capacitor.
10
Converter Reference. Bypass to AGND with a 2.2µF capacitor (1.23V nominal).
11, 14,
28, 33,
35, 48
C4, D4,
C5, D6
N.C.
No Connection. Connect to GND.
Positive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (1.6V
nominal).
12
13
A7
C6
PREG
REG
PREG/2 Voltage Reference. Bypass to AGND with a 1µF capacitor (0.8V
nominal)
15
16
A8
B7
AGND
Analog Ground
MICVDD
Microphone Bias Power Supply. Bypass to AGND with a 1µF capacitor.
Low-Noise Microphone Bias. Connect a 2.2kꢀ to 470ꢀ resistor to the positive
output of the microphone. Bypass to AGND with a 1µF capacitor.
17
18
B8
C7
MICBIAS
MICLN/
DIGMICCLK
Left Negative Differential Microphone Input. AC-couple a microphone with a series
2
1µF capacitor. Also digital microphone clock output. Selectable through I C.
Left Positive Differential Microphone Input. AC-couple a microphone with a
series 1µF capacitor. Also digital microphone data input. Selectable through
I C.
MICLP/
DIGMICDATA
19
D7
2
MICRP/
SPDMDATA
Right Positive Differential Microphone Input or SPDM Data Output. AC-couple a
microphone with a series 1µF capacitor. Selectable through I C.
20
21
C8
D8
2
MICRN/
SPDMCLK
Right Negative Differential Microphone Input or SPDM Clock Output. AC-couple
2
a microphone with a series 1µF capacitor. Selectable through I C.
Jack Sense. Detects the presence or absence of a jack. See the Headset
Detection section. When used as an auxiliary ADC input, AUX is used to
measure DC voltages.
22
D5
JACKSNS/AUX
24 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN-EP
WLP
E8
23
24
25
26
27
LINL
LINR
Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
F8
Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
F7
LOUTR
LOUTL
PGND
Right-Line Output
E7
Left-Line Output
E6, F6
Headphone Power Ground
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
29
30
31
E5
F5
F4
ROUTP
ROUTN
LOUTN
Negative Right-Channel Headphone Output. Unused in capacitorless and
single-ended mode.
Negative Left-Channel Headphone Output. Common headphone return in
capacitorless mode. Unused in single-ended mode.
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
32
34
36
E4
E3, F3
F2
LOUTP
PVDD
Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1µF
capacitor.
DVDDS1
37
38
F1
SDOUTS1
SDINS1
S1 Digital Audio Serial-Data ADC Output
S1 Digital Audio Serial-Data DAC Input
D3
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample
rate clock and determines whether the audio data on SDINS1 is routed to the left
or right channel. In TDM mode, LRCLKS1 is a frame sync pulse. LRCLKS1 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
39
E1
LRCLKS1
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the
MAX9880A is in slave mode and an output when in master mode.
40
E2
BCLKS1
41
42
43
D1
D2
C1
MCLK
SDOUTS2
SDINS2
Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
S2 Digital Audio Serial-Data ADC Output
S2 Digital Audio Serial-Data DAC Input
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample
rate clock and determines whether the audio data on SDINS2 is routed to the left
or right channel. In TDM mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an
input when the MAX9880A is in slave mode and an output when in master
mode.
44
C2
LRCLKS2
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the
MAX9880A is in slave mode and an output when in master mode.
45
46
C3
B1
BCLKS2
DVDD
2
Digital Power Supply. Supply for the digital core and I C/SPI interface. Bypass to
DGND with a 1.0µF capacitor.
47
—
A1
—
DGND
EP
Digital Ground
Exposed Pad. Connect the exposed thermal pad to AGND.
______________________________________________________________________________________ 25
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
The MAX9880A’s flexible clock circuitry utilizes a pro-
Detailed Description
The MAX9880A is a low-power stereo audio codec
designed for portable applications requiring minimum
power consumption.
grammable clock divider and a digital PLL to allow the
DAC and ADC to operate at maximum dynamic range
for all combinations of master clock (MCLK) and sam-
ple rate (LRCLK) without consuming extra supply cur-
rent. Any master clock between 10MHz and 60MHz is
supported as are all sample rates from 8kHz to 48kHz
for the record path and 8kHz to 96kHz for the playback
path. Master and slave modes are supported for maxi-
mum flexibility.
The stereo playback path accepts digital audio through
2
flexible digital audio interfaces compatible with I S,
TDM, and left-justified audio signals. The MAX9880A
can process two simultaneous digital input streams that
can be mixed digitally. The primary interface is intend-
ed for voiceband applications, while the secondary
interface can be used for stereo audio data. An over-
sampling sigma-delta DAC converts the mixed incom-
ing digital data stream to analog audio and outputs
through the stereo headphone amplifier and stereo-line
outputs. The headphone amplifier can be configured in
differential, single-ended, and capacitorless output
modes.
MX980A
The right analog microphone input can be retasked to
output SPDM data. Integrated digital filtering provides a
range of notch and highpass filters for both the play-
back and record paths to limit undesirable low-frequen-
cy signals and GSM transmission noise. The digital
filtering provides attenuation of out-of-band energy by
over 70dB, eliminating audible aliasing. A digital
sidetone function allows audio from the record path to
be summed into the playback path after digital filtering.
The stereo record path has two differential analog
microphone inputs with selectable gain. The micro-
phones are powered by an integrated microphone bias.
The MAX9880A can retask the left analog microphone
input to accept data from up to two digital micro-
phones. An oversampling sigma-delta ADC converts
the microphone signals and outputs the digital bit
stream over the digital audio interface. An auxiliary
ADC allows accurate measurements of DC voltages by
retasking the right audio ADC. DC voltages can be
read through the registers.
2
I C/SPI Registers
Forty internal registers program and report the status of
the MAX9880A. Table 1 lists all of the registers, their
addresses, and power-on-reset states. Registers
0x00–0x03 are read-only while all of the other registers
are read/write. Write zeros to all unused bits in the regis-
ter table when updating the register, unless otherwise
noted. All bits in the read-only registers are not pro-
grammable. Read operations of unused bits return zero.
The MAX9880A also includes two line inputs. These
inputs allow a stereo single-ended signal to be gain
adjusted and then recorded by the ADCs and output by
the headphone amplifier and line output amplifiers. A
jack detection function allows the detection of head-
phone, microphone, and headset jacks. Insertion and
removal events can be programmed to trigger a hard-
ware interrupt and flag a register bit.
2
I C Slave Address
The MAX9880A is preprogrammed with a slave
address of 0x20 or 0010000. The address is defined as
the 7 most significant bits (MSBs) followed by the
read/write bit. Set the read/write bit to 1 to configure the
MAX9880A to read mode. Set the read/write bit to zero
to configure the MAX9880A to write mode. The address
is the first byte of information sent to the MAX9880A
after the START (S) condition.
Table 1. Register Map
REGISTER
POR
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
R/W
STATE
STATUS
Status
CLD
SLD
ULK
—
—
—
*
—
*
JDET
—
—
—
0x00
0x01
0x02
0x03
0x04
—
—
R
R
Jack Status
JKSNS[1:0]
—
AUX High
AUX[15:8]
AUX[7:0]
0*
—
R
AUX Low
—
R
Interrupt Enable
SYSTEM CLOCK CONTROL
System Clock
ICLD
0
ISLD
0
IULK
0
0*
IJDET
0
0x00
R/W
PSCLK
FREQ1
0x05
0x00
R/W
26 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 1. Register Map (continued)
REGISTER
POR
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
R/W
STATE
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
DAI1 CONFIGURATION
Interface Mode A
PLL1
NI1[14:8]
0x06
0x07
0x00
0x00
R/W
R/W
NI1[7:1]
DLY1
RLK1/NI1[0]
0
MAS1
DL1
WCI1
SEL1
BCI1
HIZOFF1 TDM1
FSW1
BSEL1
0x08
0x09
0x0A
0x00
0x00
0x00
R/W
R/W
R/W
Interface Mode B
SDOEN1 SDIEN1 DMONO1
SLOTR1
Time-Division Multiplex
DAI2 CLOCK CONTROL
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
DAI2 CONFIGURATION
Interface Mode A
SLOTL1
SLOTDLY1[3:0]
PLL2
NI2[14:8]
NI2[7:1]
0x0B
0x0C
0x00
0x00
R/W
R/W
RLK2/NI2[0]
WS2
MAS2
DL2
WCI2
SEL2
BCI2
DLY2
HIZOFF2 TDM2
FSW2
BSEL2
0x0D
0x0E
0x0F
0x00
0x00
0x00
R/W
R/W
R/W
Interface Mode B
SDOEN2 SDIEN2
SLOTR2
DHF
Time-Division Multiplex
DIGITAL MIXERS
SLOTL2
SLOTDLY2[3:0]
DAC-L/R Mixer
MIXDAL
MIXDAR
DVFLT
0x10
0x11
0x00
0x00
R/W
R/W
DIGITAL FILTERING
Codec Filters
MODE
AVFLT
DCB
0
SPDM OUTPUTS
Configuration
SPDMCLK
SPDML SPDMR
0
0
0
0x12
0x13
0x00
0x00
R/W
R/W
Input
MIXSPDML
MIXSPDMR
REVISION ID
Rev ID location (replicated for
SPI mode)
REV
0x14
0x42
R/W
LEVEL CONTROL
Sidetone
DSTS
SDACM
0
0
DVST
SDACA
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stereo DAC Level
Voice DAC Level
Left ADC Level
0
0
0
0
0
0
0
0
0
0
0
0
0
VDACM
0
VDACG
AVLG
VDACA
AVL
Right ADC Level
Left-Line Input Level
Right-Line Input Level
Left Volume Control
Right Volume Control
Left-Line Output Level
Right-Line Output Level
Left Microphone Gain
Right Microphone Gain
CONFIGURATION
Input
0
AVRG
AVR
LILM
LIRM
VOLLM
VOLRM
LOLM
LORM
0
0
0
0
LIGL
LIGR
VOLL
VOLR
0
0
0
0
LOGL
LOGR
PALEN
PAREN
PGAML
PGAMR
MXINL
MXINR
AUXCAP AUXGAIN AUXCAL
AUXEN
MBIAS
0x22
0x23
0x24
0x25
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
Microphone
MICCLK
DIGMICL DIGMICR
0
0
0
0
0
Mode
DSLEW
JDETEN
VSEN
ZDEN
0
0
HPMODE
Jack Detect
0
JDWK
0
JDEB
______________________________________________________________________________________ 27
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 1. Register Map (continued)
REGISTER
ADDRESS
(SEE NOTE)
POR
STATE
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
R/W
POWER MANAGEMENT
Enable
LNLEN LNREN LOLEN LOREN DALEN DAREN ADLEN
SHDN XTEN XTOSC
ADREN
0
0x26
0x27
0x00
0x00
R/W
R/W
System Shutdown
REVISION ID
0
0
0
0
Revision ID
REV
0xFF
0x42
R/W
MX980A
*Reserved.
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
Bits in status register 0x00 are set when an alert condi-
tion exists. All bits in status register 0x00 are automati-
cally cleared upon a read operation of the register and
are set again if the condition remains or occurs follow-
ing the read of this register.
Device Status
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon reading the status
register and are set the next time the event occurs.
Registers 0x02 and 0x03 report the DC level applied to
AUX. See the ADC section for more details.
Table 2. Status Register
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
Status
CLD
SLD
ULK
—
—
—
*
*
JDET
—
—
—
0x00
0x01
0x02
0x03
Jack Status
JKSNS[1:0]
—
—
AUX High
AUX[15:8]
AUX[7:0]
AUX Low
*Reserved.
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
28 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 3. Status Register Bits
BITS
FUNCTION
Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC. To resolve a clip condition in
the signal path, the DAC gain settings and analog input gain settings should be lowered. As the CLD bit does
not indicate where the overload has occurred, identify the source by lowering gains individually.
CLD
SLD
Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through
all intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final
value. SLD is also set when soft start or stop is complete.
Digital PLL Unlock Flag. Indicates that the digital audio PLL has become unlocked and digital signal data is not
reliable.
ULK
Headset Configuration Change Flag. JDET reports changes in JKSNS[1:0]. Changes to JKSNS[1:0] are
debounced before setting JDET. The debounce period is programmable using the JDEB bits.
JDET
JKSNS reports the status of the JACKSNS pin when JDETEN = 1. JKSNS is not debounced and should be
interpreted according to the following information.
JKSNS[1:0]
DESCRIPTION
00
01
10
11
JACKSNS is below V
.
JKSNS[1:0]
TH2
JACKSNS is between V
Invalid.
and V
.
TH1
TH2
JACKSNS is above V
.
TH1
Auxiliary Input Measurement. AUX is a 16-bit signed two’s complement number representing the voltage
measured at JACKSNS/AUX. Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After
reading the value, set AUXCAP to 0.
Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
AUX
ꢁ AUX ꢄ
Voltage = 0.738V ꢀ
ꢃ
ꢆ
ꢂ
ꢅ
k
k = AUX value when AUXGAIN = 1. See AUXGAIN for details on determining the value of k, the calibration
constant.
______________________________________________________________________________________ 29
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
If a flag is set, it is reported as a hardware interrupt only
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00.
Table 4. Interrupt Enable
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
MX980A
Interrupt Enable
ICLD
ISLD
IULK
0
0*
0*
IJDET
0
0x04
*Reserved.
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
flexibility in both the MCLK and LRCLK frequencies
and can be used in either master or slave mode.
Clock Control
The MAX9880A can work with a master clock (MCLK)
supplied from any system clock within the 10MHz to
60MHz range. Internally the MAX9880A requires a
10MHz to 20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9880A.
• Exact integer mode: Common MCLK frequencies
(12MHz, 13MHz, 16MHz, and 19.2MHz) can be pro-
grammed to operate in exact integer mode for both
8kHz and 16kHz sample rates. In these modes, the
MCLK and LRCLK rates are selected by using the
FREQ1 bits instead of the NI high, NI low, and PLL con-
trol bits.
The MAX9880A can support any sample rate from 8kHz
to 48kHz for the digital audio path DAI1 (DAC and
ADC) and 8kHz to 96kHz for the DAI2 (high-fidelity
DAC path), including all common sample rates (8kHz,
16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz). To
accommodate a wide range of system architectures,
the MAX9880A supports three main clocking modes:
• PLL mode: When operating in slave mode, a PLL
can be enabled to lock onto externally generated
LRCLK signals that are not integer related to PCLK.
Prior to enabling the interface, program NI to the
nearest desired ratio and set the NI[0] = 1 to enable
the PLL’s rapid lock mode. If NI[0] = 0, then NI is
ignored and PLL lock time is slower.
• Normal mode: This mode uses a 15-bit clock
divider coefficient to set the sample rate relative to
the prescaled MCLK input (PCLK). This allows high
Table 5. System and Audio Clock Registers
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
SYSTEM CLOCK CONTROL
System Clock
0
0
PSCLK
FREQ1
0x05
DAI1 CLOCK CONTROL
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
DAI2 CLOCK CONTROL
PLL1
NI1[14:8]
NI2[14:8]
0x06
0x07
NI1[7:1]
NI2[7:1]
RLK1/NI1[0]
RLK2/NI2[0]
Stereo Audio Clock Control High
Stereo Audio Clock Control Low
PLL2
0x0B
0x0C
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
30 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 5. System and Audio Clock Registers (continued)
BITS
FUNCTION
MCLK Prescaler. Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
PSCLK
01 = Select if MCLK is between 10MHz and 20MHz. PCLK = MCLK.
10 = Select if MCLK is between 20MHz and 40MHz. PCLK = MCLK/2.
11 = Select if MCLK is greater than 40MHz. PCLK = MCLK/4.
Exact Integer Modes. Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or
16kHz sample rates.
FREQ1[3:0]
PCLK (MHz)
LRCLK (kHz)
PCLK/LRCLK
Normal or PLL mode
0x00
0x1–0x7
Reserved
Reserved
Reserved
0x8
0x9
12
12
8
16
1500
750
FREQ1
0xA
0xB
13
13
8
16
1625
812.5
0xC
0xD
16
16
8
16
2000
1000
0xE
0xF
19.2
19.2
8
16
2400
1200
Modes 0x8 to 0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK
ratio cannot be guaranteed, use PLL mode instead.
PLL Mode Enable
0 = (Valid for slave and master mode) The frequency of LRCLK is set by the NI divider bits. In master mode,
the MAX9880A generates LRCLK using the specified divide ratio. In slave mode, the MAX9880A expects
an LRCLK as specified by the divide ratio.
PLL1/PLL2
1 = (Valid for slave mode only) A digital PLL locks on to any externally supplied LRCLK signal.
Rapid Lock Mode. To enable rapid lock mode set NI_ to the nearest desired ratio and set RLK_ = 1 before
enabling the interface.
RLK1/RLK2
Normal Mode LRCLK Divider. When PLL = 0, the frequency of LRCLK is determined by NI. See Table 6 for
common NI values.
For LRCLK = 8kHz to 48kHz operation (DHF = 0 for DAI2):
NI = (65,536 x 96 x f
)/f
LRCLK PCLK
f
f
= LRCLK frequency
= Prescaled internal MCLK frequency (PCLK)
LRCLK
NI1/NI2
PCLK
For LRCLK > 50kHz operation (DHF = 1 for DAI2):
NI = (65,536 x 48 x f )/f
LRCLK PCLK
f
f
= LRCLK frequency
= Prescaled internal MCLK frequency (PCLK)
LRCLK
PCLK
______________________________________________________________________________________ 31
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 6. Common NI Values
(DAI1, DAI2 for DHF = 0)
(DAI2 for DHF = 1)
64 96
LRCLK (kHz)
8
11.025
1B18
18A2
1800
1694
160D
14D8
135B
1210
10EF
1000
FF0
12
16
22.05
3631
3144
3000
2D29
2C1A
29AF
26B5
2420
21DE
2000
1FE0
1E1B
1D66
1C85
1B18
24
32
44.1
6C61
6287
6000
5A51
5833
535F
4D6A
4841
43BD
4000
3FC1
3C36
48
88.2
6C61
6287
6000
5A51
5833
535F
4D6A
4841
43BD
4000
3FC1
3C36
10
11
13A9
11E0
1D7E
1ACF
1A1F
1893
1800
16AF
1511
13A9
126F
116A
1159
1062
1000
F86
2752
23BF
22D4
20C5
2000
1E3F
1C16
1A37
1893
1738
1721
15D8
1555
14B2
13A9
3AFB
359F
343F
3127
3000
2D5F
2A21
2752
24DD
22D4
22B2
20C5
2000
1F0B
1D7E
4EA5
477E
45A9
4189
4000
3C7F
382C
346E
3127
2E71
2E43
2BB1
75F7
6B3E
687D
624E
6000
5ABE
5443
4EA5
49BA
45A9
4564
4189
4000
3E16
3AFB
4EA5
477E
45A9
4189
4000
3C7F
382C
346E
3127
2E71
2E43
2BB1
75F7
6B3E
687D
624E
6000
5ABE
5443
4EA5
49BA
45A9
4564
4189
4000
3E16
3AFB
11.2896 116A
12
12.288
13
1062
1000
F20
PCLK
(MHz):
MX980A
(Note: Any
PCLK from
10MHz to
20MHz
with any
LRCLK
14
E0B
D1B
C4A
B9C
B91
AEC
AAB
A59
9D5
15
16
7.8kHz to
50kHz
can be
16.9344
17
used.)
18
F0E
18.432
19
EB3
2AAB 3ACD
2AAB 3ACD
E43
2964
2752
390B
3631
2964
2752
390B
3631
20
D8C
EBF
Note: Values in bold and underline are exact integers that provide maximum full-scale performance.
• DAC path connectable to either S1 or S2
• ADC path connectable to either S1 or S2
• 8kHz to 48kHz sample rates
Digital Audio Interface
The MAX9880A’s dual digital audio interface supports a
wide range of operating modes to ensure maximum
compatibility. See Figures 1 to 5 for timing diagrams. In
master mode, the MAX9880A outputs LRCLK and
BCLK, while in slave mode they are inputs. When oper-
ating in master mode, BCLK can be configured in a
number of ways to ensure compatiblity with other audio
devices.
2
• I S and TDM-compatible modes
• Voice filters or audio filter modes
DAI2: Digital Audio Path 2 Operation
• High-fidelity DAC path with DR of 96dB
• DAC path connectable to either S1 or S2
• 8kHz to 96kHz sample rates
The MAX9880A has two sets of digital audio interface
pins, S1 and S2, that can be connected to one of two
digital audio paths, DAI1 or DAI2.
2
• I S and TDM-compatible modes
DAI1: Digital Audio Path 1 Operation
• Audio FIR filters
• DAC path with DR of 90dB and ADC path with DR of
82dB
• No ADC clock control from DAI2 sample clock and
no voice filter modes available in DAI2
32 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 7. Digital Audio Interface Registers
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DAI1 CONFIGURATION
Interface Mode A
MAS1
DL1
WCI1
SEL1
BCI1
DLY1
HIZOFF1
TDM1
FSW1
0
0x08
0x09
0x0A
Interface Mode B
SDOEN1 SDIEN1 DMONO1
SLOTR1
BSEL1
Time-Division Multiplex
DAI2 CONFIGURATION
Interface Mode A
SLOTL1
SLOTDLY1[3:0]
MAS2
DL2
WCI2
SEL2
BCI2
DLY2
HIZOFF2
DHF
TDM2
FSW2
WS2
0x0D
0x0E
0x0F
Interface Mode B
SDOEN2 SDIEN2
SLOTR2
BSEL2
Time-Division Multiplex
SLOTL2
SLOTDLY2[3:0]
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Master Mode
0 = The MAX9880A operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9880A operates in master mode with LRCLK and BCLK configured as outputs.
MAS1/2
LRCLK Invert (TDM1/2 = 0)
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
WCI1/2
BCI1/2
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK. SDOUT transitions immediately after the rising edge
of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK. SDOUT transitions immediately after the falling
edge of BCLK.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
Delay Mode. DLY1/2 have two different functions in TDM and non-TDM mode.
In Non-TDM Mode (TDM1/TDM2 = 0): The functionality is as follows:
1 = The most significant bit of an audio word is latched at the second BCLK edge after the LRCLK transition.
0 = The most significant bit of an audio word is latched at the first BCLK edge after the LRCLK transition.
In TDM Mode (TDM1/TDM2 = 1): The functionality is as follows:
DLY1/2
1 = The HOLD time on the SDOUT output is increased to be greater than 150ns.
0 = The HOLD time on the SDOUT output is the default (greater than 20ns but less than 150ns).
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9880A,
allowing SDOUT to be shared by other devices.
HIZOFF1/2
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9880A.
Note: High-impedance mode is intended for use when TDM = 1.
______________________________________________________________________________________ 33
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 7. Digital Audio Interface Registers (continued)
BITS
FUNCTION
TDM Mode Select
TDM1/2
1 = Enables time-division multiplex mode and configures the audio interface to accept PCM data.
0 = Disables time-division multiplex mode. LRCLK signal polarity indicates left and right audio.
Frame Sync Width
1 = Frame sync pulse extended to the width of the entire 16-bit first slot 0 data word (TDM1/TDM2 = 1 only;
SLOTDLY[0] must be 0 when FSW is set to 1).
0 = Frame sync pulse is 1 bit wide.
FSW1/2
WS2
MX980A
Word Size
0 = The number of bits per input data word sample is 16 bits, and at least 16 BCLKs per input word are required.
1 = The number of bits per input data word sample is 18 bits, and at least 18 BCLKs per input word transfer is
required. These control bits are only recognized when TDM1/TDM2 are cleared to 0.
Data Loop. Enabling of these bits provides a bridge from one DAI interface to the other. Data format looping could
occur in both directions simultaneously.
BIT
DESCRIPTION
DL1 = 0
Normal operation
DL1/2
DL1 = 1, SEL2 = 1
DL2 = 0
Enables SDINS1 to SDOUTS2.
Normal operation
DL2 = 1, SEL1 = 0
Enables SDINS2 to SDOUTS1.
Note: The LRCLKS1 and LRCLKS2 interfaces must be identical.
Set the SEL1/2, SDOEN1/2, and SDIEN1/2 bits as shown in the table below to connect the S1 and S2 pins to the
DAI1 and DAI2 paths in the MAX9880A.
SETTING
SEL1
SEL2
SDIEN1
SDOEN1
SDIEN2
SDOEN2
Connect S1 pins to DAI1 (DAC and ADC)
Connect S2 pins to DAI1 (DAC and ADC)
Connect S1 pins (DAC only) to DAI2
Connect S2 pins (DAC only) to DAI2
0
1
1
X
X
0
0
1
1
1
0
0
1
0
0
0
0
0
1
1
0
1
0
0
SEL1/SEL2
Connect S1 pins (DAC and ADC) to DAI1,
connect S2 to DAI2 (DAC only)
0
1
1
0
1
1
1
0
1
1
0
1
Connect S2 pins (DAC and ADC) to DAI1,
connect S1 to DAI2 (DAC only)
SDOUT Enable
1 = Serial-data output enabled on S1/S2 pins.
0 = Serial-data output disabled on S1/S2 pins.
SDOEN1/2
SDIEN1/2
SDIN Enable
1 = Serial-data input to DAI1/2 audio path enabled.
0 = Serial-data input to DAI1/2 audio path disabled.
Mono Playback Mode
0 = Stereo data input on DAI1 path is processed separately.
DMONO1
1 = Stereo data input on DAI1 path is mixed to a single channel and routed to both the left and right DAC.
When operating in mono voice mode (MODE = 1), stereo data may still be input through DAI1 path and optionally
mixed using DMONO1 = 1.
34 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 7. Digital Audio Interface Registers (continued)
BITS
FUNCTION
BCLK Select. Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL =
010, unless sharing the bus with multiple devices.
BSEL
000
001
010
011
100
101
110
111
DESCRIPTION
Off (BCLK output held low)
64x LRCLK (192x internal clock divided by 3)
BSEL1/2
48x LRCLK (192x internal clock divided by 4)
128x LRCLK (Note: Not a valid BSEL2 choice when DHF = 1.)
PCLK/2
PCLK/4
PCLK/8
PCLK/16
TDM Slot Select. Selects the time slot to use for left/right data according to the following information when
operating in time-division multiplex mode.
SLOT
DESCRIPTION
SLOTL1/2
SLOTR1/2
00
Time slot 1
Time slot 2
Time slot 3
Time slot 4
01
10
11
Slot Data Delay (SLOTDLY1/SLOTDLY2)
In TDM Mode: Configures the data delay for each slot in TDM mode of operation according to the following
information.
In Non-TDM Mode (TDM = 0): SLOTDLY[1:0] does not have any effect.
SLOTDLY1/2[3:0]
0xxx
DESCRIPTION
Data for slot 4 begins immediately.
1xxx
Data for slot 4 delayed 1 BCLK cycle.
Data for slot 3 begins immediately.
SLOTDLY1/2
x0xx
x1xx
Data for slot 3 delayed 1 BCLK cycle.
Data for slot 2 begins immediately.
xx0x
xx1x
Data for slot 2 delayed 1 BCLK cycle.
Data for slot 1 begins immediately.
xxx0
xxx1
Data for slot 1 delayed 1 BCLK cycle (not valid when FSW = 1).
DAC High Sample Rate Mode (DHF) (Valid only for DAI2 audio path)
1 = LRCLK is greater than 50kHz. 4x FIR interpolation filter used.
0 = LRCLK is less than 50kHz. 8x FIR interpolation filter used.
DHF
______________________________________________________________________________________ 35
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
AUDIO MASTER MODES:
LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
LRCLK
RIGHT
LEFT
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D15
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MX980A
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
LEFT
RIGHT
LRCLK
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
LEFT
RIGHT
LRCLK
SDIN
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
BCLK
CONFIGURED BY BSEL
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2
I
S: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
7ns (typ)
7ns (typ)
LEFT
RIGHT
LRCLK
SDIN
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
BCLK
CONFIGURED BY BSEL
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
7ns (typ)
7ns (typ)
RIGHT
LEFT
LRCLK
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED-DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) PERIOD OF MCLK PLUS THE
INTERNAL DELAY. FOR EXAMPLE: IF f = 12.288MHz, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
PCLK
Figure 1. Digital Audio Interface Audio Master Mode
36 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
AUDIO SLAVE MODES:
LEFT JUSTIFIED: TDM = 0, WCI = 0, BCI = 0, DLY = 0, SLOTDLY = 0
LEFT
RIGHT
LRCLK
1/f
S
20ns (min)
0ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
0ns (min)
30ns (min)
75ns (min)
5ns (min)
30ns (min)
20ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
LEFT
RIGHT
LRCLK
1/f
S
0ns (min)
20ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
0ns (min)
30ns (min)
75ns (min)
5ns (min)
30ns (min)
20ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 0
LEFT
RIGHT
LRCLK
SDIN
1/f
S
0ns (min)
20ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
BCLK
75ns (min)
5ns (min)
30ns (min)
20ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2
I S: TDM = 0, WCI = 0, BCI = 0, DLY = 1, SLOTDLY = 0
LEFT
RIGHT
LRCLK
SDIN
1/f
S
0ns (min)
20ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
BCLK
75ns (min)
30ns (min)
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: TDM = 0, WCI = 1, BCI = 0, DLY = 0, SLOTDLY = 1
RIGHT
LEFT
LRCLK
1/f
S
20ns (min)
0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
0ns (min)
30ns (min)
30ns (min)
75ns (min)
20ns (min)
5ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. Digital Audio Interface Audio Slave Mode
______________________________________________________________________________________ 37
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
VOICE (TDM/PCM) MASTER MODES:
TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
200ns
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
MX980A
CONFIGURED BY BSEL
20ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00
7ns (typ)
7ns (typ)
LRCLK
SDOUT
BCLK
1/f
S
200ns
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
20ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0
7ns (typ)
7ns (typ)
LRCLK
SDOUT
BCLK
1/f
S
200ns
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
20ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
Figure 3. Digital Audio Interface Voice Master Mode
38 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
VOICE (TDM/PCM) SLAVE MODES:
TDM = 1, BCI = 0, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
LRCLK
SDOUT
BCLK
1/f
S
20ns
0ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
7ns (typ)
75ns (min)
30ns (min)
20ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 1, HIZOFF = 0, SLOTDLY = 0, SLOT = 00, DLY = 0
SDIN
LRCLK
SDOUT
BCLK
1/f
S
20ns
0ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
7ns (typ)
75ns (min)
30ns (min)
20ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
TDM = 1, BCI = 0, HIZOFF = 1, SLOTDLY = 0, SLOT = 00, DLY = 0
SDIN
LRCLK
SDOUT
BCLK
1/f
S
20ns
0ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
30ns (min)
20ns (min)
0ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
Figure 4. Digital Audio Interface Voice Slave Mode
Table 8. Digital Mixers
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DIGITAL MIXERS
DAC-L/R Mixer
MIXDAL
MIXDAR
0x10
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Digital Mixers (MIXDAL/MIXDAR). Selects and mixes the audio source(s) for the DACs according to the
information below.
MIXDAL/MIXDAR
SOURCE
DAI1 left-channel data
MIXDAL/
MIXDAR
1xxx
x1xx
xx1x
xxx1
DAI1 right-channel data
DAI2 left-channel data
DAI2 right-channel data
______________________________________________________________________________________ 39
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Digital Filtering
The MAX9880A incorporates both IIR (voice) and FIR
(audio) digital filters to accomodate a wide range of
audio sources. The IIR fiilters provide over 70dB of
stopband attenuation as well as selectable highpass fil-
ters. The FIR filters provide low power consumption and
are linear phase to maintain stereo imaging.
Table 9. Digital Filtering Register
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
DIGITAL FILTERING
MX980A
Codec Filters
MODE
AVFLT
DCB
DVFLT
0x11
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Digital Audio Filter Mode. Selects the filtering mode for the DAI1 DAC and ADC signal paths.
0 = IIR voice filters
1 = FIR audio filters
MODE
ADC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
AVFLT
DCB
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
1 = DC-blocking filter for DAI2 enabled.
0 = DC-blocking filter for DAI2 disabled.
DAC Digital Audio Filter. Configures the highpass filters for the DAI1 signal path.
MODE = 0
Select the desired digital filter response from Table 10. See the frequency response graphs in the Typical
DVFLT
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter disabled.
0x1 = DC-blocking filter enabled.
Table 10. IIR Highpass Digital Filters
VALID SAMPLE
RATE (kHz)
CODE
FILTER TYPE
HIGHPASS CORNER FREQUENCY
217Hz NOTCH
0x0
0x1
Disabled
256Hz
500Hz
256Hz
500Hz
Elliptical
Butterworth
Elliptical
16
Yes
No
0x2
16
0x3
8
8
Yes
No
0x4
Butterworth
Butterworth
0x5
8 to 24
f /240
S
No
0x6 to 0x7
Reserved
40 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 11. SPDM Output Registers
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
Configuration
Input
SPDMCLK
SPDML
SPDMR
0
0
0
0
0x12
0x13
MIXSPDML
MIXSPDMR
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
The MAX9880A supports stereo PDM outputs. The PDM
signals consist of PDM data outputs (SPDMDATA) and a
clock output (SPDMCLK). The mixer at the input to the
PDM modulators allows a mix/mux of the audio digital data
stream from the digital audio ports SDINS1 and SDINS2.
Figure 5 shows the SPDM interface timing diagram.
SPDMCLK
t
DLY, DSD
t
DLY, DSD
SPDMDATA
LEFT CH
RIGHT CH
LEFT CH
RIGHT CH
Figure 5. SPDM Timing Diagram
BITS
FUNCTION
SPDM Clock Rate (SPDMCLK)
00 = SPDMCLK is set to PCLK/8.
01 = SPDMCLK is set to PCLK6.
10 = SPDMCLK is set to PCLK/4.
11 = Reserved
SPDMCLK
0 = Disables SPDM data.
1 = Enables SPDM data.
SPDML/SPDMR
SPDM Input Mixers. Selects and mixes the audio source(s) for the SPDM output according to following
information.
MIXSPDML/MIXSPDMR
SOURCE
MIXSPDML/
MIXSPDMR
1xxx
x1xx
xx1x
xxx1
DAI1 left-channel data
DAI1 right-channel data
DAI2 left-channel data
DAI2 right-channel data
______________________________________________________________________________________ 41
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Digital Gain Control
The MAX9880A includes gain adjustment for the play-
back and record paths. Independent gain adjustment is
provided for the two record channels. Sidetone gain
adjustment is also provided to set the sidetone level rel-
ative to the playback level.
Table 12. Digital Gain Registers
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
LEVEL CONTROL
Sidetone
DSTS
0
0
DVST
0x15
0x16
0x17
0x18
0x19
MX980A
Stereo DAC Level
Voice DAC Level
Left ADC Level
0
0
0
0
SDACM
0
SDACA
VDACM
VDACG
AVLG
VDACA
AVL
0
0
Right ADC Level
Grayed boxes = Not used.
AVRG
AVR
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Digital Sidetone Source Mixer
00 = No sidetone selected.
01 = Left ADC
DSTS
10 = Right ADC
11 = Left and right ADC
Digital Sidetone Level Control. All gain settings are relative to the ADC input voltage.
Differential Headphone Output Mode
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
SETTING
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
GAIN (dB)
-20
SETTING
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
—
GAIN (dB)
-42
Off
0
-2
-4
-6
-22
-24
-26
-28
-30
-32
-34
-36
-44
-46
-48
-50
-52
-54
-56
-58
-8
-10
-12
-14
-16
-18
-38
-40
-60
—
DVST
Capacitorless and Single-Ended Headphone Output Mode
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
Off
SETTING
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
GAIN (dB)
-25
SETTING
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
—
GAIN (dB)
-47
-5
-7
-9
-11
-13
-15
-17
-19
-21
-23
-27
-29
-31
-33
-35
-37
-39
-41
-49
-51
-53
-55
-57
-59
-61
-63
-43
-45
-65
—
42 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 12. Digital Gain Registers (continued)
BITS
FUNCTION
DAC Mute Enable
0 = No mute
1 = Mute
SDACM/
VDACM
DAC Gain
00 = 0dB
01 = +6dB
10 = +12dB
11 = +18dB
VDACG
Note: VDACG is only used when MODE = 0. If MODE = 1, then the DAC gain is always 0dB.
DAC Level Control. VDACA/SDACA works in all modes.
SETTING
0x0
GAIN (dB)
SETTING
0x8
GAIN (dB)
-8
0
0x1
-1
-2
-3
-4
-5
-6
-7
0x9
-9
0x2
0xA
-10
VDACA/SDACA
0x3
0xB
-11
0x4
0xC
-12
0x5
0xD
-13
0x6
0xE
-14
0x7
0xF
-15
ADC Gain Control. Applies the specified gain to the digital ADC paths according to the following
information.
SETTING
GAIN (dB)
AVLG/AVRG
0x0
0
0x1
+6
0x2
+12
+18
0x3
ADC Left/Right Level Control
SETTING
0x0
GAIN (dB)
SETTING
0x8
GAIN (dB)
+3
+2
+1
0
-5
-6
0x1
0x9
0x2
0xA
-7
AVL/AVR
0x3
0xB
-8
0x4
-1
-2
-3
-4
0xC
-9
0x5
0xD
-10
-11
-12
0x6
0xE
0x7
0xF
______________________________________________________________________________________ 43
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Line Inputs
Playback Volume
The MAX9880A include one pair of single-ended line
inputs. When enabled the line inputs connect directly to
the headphone amplifier and line outputs and can be
optionally connected to the ADC for recording.
The MAX9880A incorporates volume and mute control to
allow level control for the playback audio path. Program
registers 0x1C and 0x1D to set the desired volume.
Line Output Level
The MAX9880A incorporates gain and mute control to
allow level control for the line outputs.
Table 13. Line Input Registers
REGISTER
MX980A
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
Left-Line Input Level
Right-Line Input Level
Grayed boxes = Not used.
0
0
LILM
LIRM
0
0
0
0
LIGL
LIGR
0x1A
0x1B
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Line Input Left/Right Playback Mute
0 = Line input is connected to the headphone amplifiers.
1 = Line input is disconnected from the headphone amplifiers.
LILM/LIRM
Line Input Left/Right Gain
SETTING
0x0
GAIN (dB)
+24
SETTING
0x8
GAIN (dB)
+8
+6
+4
+2
0
0x1
+22
0x9
0x2
+20
0xA
LIGL/LIGR
0x3
+18
0xB
0x4
+16
0xC
0x5
+14
0xD
-2
0x6
+12
0xE
-4
0x7
+10
0xF
-6
Table 14. Playback Volume Registers
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
Left Volume Control
0
0
VOLLM
VOLRM
VOLL
VOLR
0x1C
0x1D
Right Volume Control
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Left/Right Playback Mute. VOLLM and VOLRM mute both the DAC and line input audio signals.
0 = Audio playback is unmuted.
1 = Audio playback is muted.
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
VOLLM/
VOLRM
44 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 14. Playback Volume Registers (continued)
BITS
FUNCTION
Left/Right Playback Volume. VOLL and VOLR control the playback volume for both the DAC and line input
audio signals.
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
GAIN (dB)
+9
SETTING
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
GAIN (dB)
-2
SETTING
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
GAIN (dB)
-39
+8.5
+8
+7.5
+7
+6.5
+6
+5
+4
+3
+2
+1
-3
-5
-7
-9
-11
-13
-15
-17
-19
-23
-27
-31
-35
-43
-47
-51
-55
-59
-63
-67
-71
VOLL/VOLR
-75
-79
-81
0
-1
0x28 to 0x3F
MUTE
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-
ended and capacitorless modes, the actual gain is 5dB lower. Assuming LOGL/LOGR = 0dB, line output
gain is 6dB lower.
Table 15. Output Line-Level Registers
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
0
0
Left-Line Output Level
Right-Line Output Level
Grayed boxes = Not used.
0
0
LOLM
LORM
0
0
LOGL
LOGR
0x1E
0x1F
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Left/Right Line Output Mute. LOLM and LORM mute both the DAC and line input audio signals.
0 = Line output is unmuted.
LOLM/LORM
1 = Line output is muted.
Note: VSEN has no effect on the mute function. When LOLM or LORM is set the output is muted immediately
(ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Left/Right Line Output Gain. LOGL and LOGR set the line output gain according to the following information.
SETTING
0x00
GAIN (dB)
SETTING
0x08
GAIN (dB)
-16
0
0x01
-2
0x09
-18
0x02
0x03
0x04
0x05
0x06
0x07
-4
-6
-8
-10
-12
-14
0x0A
0x0B
0x0C
0x0D
0x0E
-20
-22
-24
-26
-28
-30
LOGL/LOGR
0x0F
______________________________________________________________________________________ 45
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
microphone signals are amplified by two stages of gain
Microphone Inputs
Two differential microphone inputs and a low noise 1.5V
microphone bias for powering the microphones are
provided by the MAX9880A. In typical applications, the
left microphone records a voice signal and the right
microphone records a background noise signal. In
applications that require only one microphone, use the
left microphone input and disable the right ADC. The
and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable gain amplifier (PGA)
adjustable from 0dB to 20dB in 1dB steps. Zero-cross-
ing detection is included on the PGA to minimize zipper
noise while making gain changes. See Figure 6 for a
detailed diagram of the microphone input structure.
MX980A
MAX9880A
1.5V
MICBIAS
0/20/30dB
V
REG
MICLP
MICLN
ADC
L
PREAMP
-
PGA
0dB TO +20dB
0/20/30dB
V
REG
MICRP
MICRN
ADC
R
PREAMP
PGA
0dB TO +20dB
Figure 6. Microphone Input Block Diagram
Table 16. Microphone Input Registers
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Left Microphone Gain
Right Microphone Gain
Grayed boxes = Not used.
0
0
PALEN
PAREN
PGAML
PGAMR
0x20
0x21
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Left/Right Microphone Preamplifier Gain. Enables the microphone circuitry and sets the preamplifier gain.
00 = Disabled
01 = 0dB
10 = +20dB
11 = +30dB
PALEN/
PAREN
46 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 16. Microphone Input Registers (continued)
BITS
FUNCTION
Left/Right Microphone Programmable Gain Amplifier
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
SETTING
0x0B
GAIN (dB)
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
+19
0x0C
+18
0x0D
+17
0x0E
PGAML/
PGAMR
+16
0x0F
+15
0x10
+14
0x11
+13
0x12
+12
0x13
+11
0x14 to 0x1F
+10
Setup Procedure
1) Ensure a valid MCLK signal is provided and config-
ure PSCLK appropriately.
ADC
The MAX9880A includes two 18-bit ADCs. The first
ADC is used to record left-channel microphone and
line-input audio signals. The second ADC can be used
to record right-channel microphone and line-input sig-
nals or it can be configured to accurately measure DC
voltages.
2) Choose a clocking mode. The following options are
possible:
a. Slave mode with LRCLK and BCLK signals
provided. The measurement sample rate is
determined by the external clocks.
When measuring DC voltages both the left and right ADC
must be enabled by setting ADLEN and ADREN in regis-
ter 0x26. The input to the second ADC is JACKSNS/
AUX and the output is reported in AUX (registers 0x02
and 0x03). Since the audio ADC is used to perform the
measurement, the digital audio interface must be prop-
erly configured. If the left ADC is being used to convert
audio, then the DC measurement is performed at the
same sample rate. When not using the left ADC, config-
ure the digital interface for a 48kHz sample rate to
ensure the fastest possible settling time.
b. Slave mode with no LRCLK and BCLK signals
provided. Configure the device for normal clock
mode using the NI ratio. Select f = 48kHz to
S
allow for the fastest settling times.
c. Master mode with audio. Configure the device
in normal mode using the NI ratio or exact inte-
ger mode using FREQ1 as required by the audio
signal.
d. Master mode without audio. Configure the
device in normal mode using the NI ratio. Select
To ensure accurate results, the MAX9880A includes
two calibration routines. Calibrate the ADC each time
the MAX9880A is powered on. Calibration settings are
not lost if the MAX9880A is placed in shutdown. When
making a measurement, set AUXCAP to 1 to prevent
AUX from changing while reading the registers.
f = 48kHz to allow for the fastest settling times.
S
3) Ensure jack sense is disabled.
4) Enable the left and right ADC; take the MAX9880A
out of shutdown.
______________________________________________________________________________________ 47
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Offset Calibration Procedure
Perform before the first DC measurement is taken after
applying power to the MAX9880A.
Complete DC Measurement Example
= 13MHz, slave mode, BCLK, and LRCLK are
f
MCLK
not externally supplied.
1) Enable the AUX input (AUXEN = 1).
2) Enable the offset calibration (AUXCAL = 1).
3) Wait the appropriate time (see Table 17).
4) Complete calibration (AUXCAL = 0).
1) Configure the digital audio interface for f = 48kHz
s
(PSCLK = 01, FREQ1 = 0x0, PLL = 0, NI = 0x5ABE,
MAS = 0).
2) Disable jack sense (JDETEN = 0).
3) Enable the left and right ADC; take the MAX9880A
out of shutdown (ADLEN = ADREN = SHDN = 1).
Gain Calibration Procedure
Perform the first time a DC measurement is taken after
applying power to the MAX9880A or if the temperature
changes significantly.
MX980A
4) Calibrate the offset:
a. Enable the AUX input (AUXEN = 1).
b. Enable the offset calibration (AUXCAL = 1).
c. Wait 40ms.
1) Enable the AUX input (AUXEN = 1).
2) Start gain calibration (AUXGAIN = 1).
3) Wait the appropriate time (see Table 17).
4) Freeze the measurement results (AUXCAP = 1).
d. Complete calibration (AUXCAL = 0).
5) Calibrate the gain:
a. Start gain calibration (AUXGAIN = 1).
b. Wait 40ms.
5) Read AUX and store the value in memory to correct
all future measurements (k = AUX[15:0], k is typical-
ly 19,500).
c. Freeze the measurement results (AUXCAP = 1).
6) Complete calibration (AUXGAIN = AUXCAP = 0).
d. Read AUX and store the value in memory to cor-
rect all future measurements (k = AUX[15:0]).
DC Measurement Procedure
Perform after offset and gain calibration are complete.
e. Complete calibration (AUXGAIN = AUXCAP =
AUXEN = 0).
1) Enable the AUX input (AUXEN = 1).
6) Measure the voltage on JACKSNS/AUX.
a. Enable the AUX input (AUXEN = 1).
b. Wait 40ms.
2) Wait the appropriate time (see Table 17).
3) Freeze the measurement results (AUXCAP = 1).
4) Read AUX and correct with the gain calibration value
c. Freeze the measurement results (AUXCAP = 1).
⎛
⎞
⎟
A UX[15:0]
k
⎛
⎞
V
= 0.738
.
d. Read AUX and correct with the gain calibration
value.
AUX
⎜
⎝
⎟
⎠
⎜
⎝
⎠
e. Complete measurement (AUXCAP = 0).
7) DC measurement is complete.
5) Complete measurement (AUXCAP = 0).
Table 17. AUX ADC Wait Times
LRCLK (kHz)
WAIT TIME (ms)
48
44.1
32
40
44
60
24
80
22.05
16
90
120
160
175
240
12
11.025
8
48 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 18. ADC Input Register
REGISTER
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS
(SEE NOTE)
Input
MXINL
MXINR
AUXCAP AUXGAIN AUXCAL AUXEN
0x22
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Left/Right ADC Audio Input Mixer
00 = No input selected
01 = Left/right analog microphone
10 = Left/right line input
11 = Left/right analog microphone + line input
MXINL/MXINR
Note: If the right line input is disabled, then the left line input is connected to both mixers. Enabling the left
and right digital microphones disables the left and right audio mixer, respectively. See the DIGMICL/
DIGMICR bit description for more details.
Auxiliary Input Capture
0 = Update AUX with the voltage at JACKSNS/AUX.
1 = Hold AUX for reading.
AUXCAP
Auxiliary Input Gain Calibration
0 = Normal operation
1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference.
While in this mode, read the AUX register and store the value. Use the stored value as a gain
calibration factor, k, on subsequent readings. AUXCAL must remain set for time indicated in Table 17 to
guarantee an accurate offset calibration.
AUXGAIN
Auxiliary Input Offset Calibration
0 = Normal operation
AUXCAL
AUXEN
1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal
offsets. AUXCAL must remain set for time indicated in Table 17 to guarantee an accurate offset
calibration.
Auxiliary Input Enable
0 = Use JACKSNS/AUX for jack detection.
1 = Use JACKSNS/AUX for DC measurements.
Note: Set MXINR = 00, ADLEN = 1, and ADREN = 1 when AUXEN = 1.
______________________________________________________________________________________ 49
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
microphone input. The right analog microphone input is
Digital Microphone Input
The MAX9880A can accept audio from up to two digi-
tal microphones. When using digital microphones, the
left analog microphone input is retasked as a digital
still available to allow a combination of analog and digi-
tal microphones to be used. Figure 7 shows the digital
microphone interface timing diagram.
1/f
MICCLK
MX980A
DIGMICCLK
t
t
t
t
SU, MIC
HD, MIC
SU, MIC
HD, MIC
DIGMICDATA
LEFT
RIGHT
LEFT
RIGHT
Figure 7. Digital Microphone Timing Diagram
Table 19. Digital Microphone Input Register
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Microphone
Grayed boxes = Not used.
MICCLK
DIGMICL DIGMICR
0
0
0
MBIAS
0x23
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Digital Microphone Clock
00 = PCLK/8
MICCLK
01 = PCLK/6
10 = 64f (high jitter clock)
S
11 = Reserved
Digital Left/Right Microphone Enable
DIGMICL
DIGMICR
LEFT ADC INPUT
RIGHT ADC INPUT
0
0
ADC input mixer
ADC input mixer
DIGMICL/
DIGMICR
Line input (left analog
microphone unavailable)
0
1
Right digital microphone
1
1
0
1
Left digital microphone
Left digital microphone
ADC input mixer
Right digital microphone
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.
Microphone Bias Output Voltage
Set MBIAS = 0 for nominal output of 1.52V (V
= 1.8V)
MICVDD
MBIAS
Set MBIAS = 1 for nominal output of 2.2V (V
= 3V)
MICVDD
50 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
and providing information to assist the system controller
in determining the configuration of an inserted plug. If
programmed to do so, upon insertion or removal of a
plug, the IRQ output is asserted (pulled low).
Mode Configuration
The MAX9880A includes circuitry to minimize click-and-
pop during volume changes, detect headsets, and con-
figure the headphone amplifier mode. Both volume
slewing and zero-crossing detection are included to
ensure click-and-pop free volume transitions.
Table 20 shows the registers associated with the jack
detect function in MAX9880A.
Headset Detection Overview
The MAX9880A contains headset detect circuitry that is
capable of detecting the insertion or removal of a plug
Table 20. Jack-Detect Registers
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
POR STATE
R/W
Status
CLD
SLD
ULK
—
—
—
0
*
*
JDET
—
—
—
0
0x00
0x01
0x04
0x25
—
—
R
Jack Status
JKSNS[1:0]
—
0*
0
—
0*
0
R
Interrupt Enable
Jack Detect
ICLD
ISLD
0
IULK
JDWK
IJDET
0x00
0x00
R/W
R/W
JDETEN
0
JDEB
Grayed boxes = Not used.
Jack Configuration Change Flag (JDET)
1 = Jack configuration has changed.
Jack-Detect Enable (JDETEN)
Enables the jack-detect circuitry.
Jack-Sense Weak Pullup (JDWK)
0 = No change in jack configuration.
JDET reports changes in JKSNS[1:0]. Changes to
JKSNS[1:0] are debounced before setting JDET. The
debounce period is programmable using the JDEB bits.
Jack status register 0x01 is a read-only register that reports
the status of the jack-detect circuitry when enabled.
Enables a weak internal pullup current for reduced
power loss when the chip is in shutdown or the
MICBIAS is disabled.
JDWK = 0 enables a 2.2kΩ pullup to obtain full jack-
detect operation. This mode can be used to detect
insertion and removal of a plug as well as distinguish
between headphone and headset accessories.
Jack Sense (JKSNS)
JKSNS[1:0] reports the status of the JACKSNS pin
when JDETEN = 1. JKSNS[1:0] should be interpreted
according to Table 21.
JDWK = 1 enables a 4µA pullup current source when
SHDN = 0 or MICBIAS disabled. In this power-saving
configuration, the circuit can detect insertion and
removal of a plug but cannot distinguish between head-
phone and headset accessories.
Jack-Detect Interrupt Enable (IJDET)
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. So IJDET must be set to
enable interrupts for jack detect.
The recommended usage follows: Set JDWK = 0 (or set
any bit in the microphone preamplifier gain registers
PALEN[1:0] or PAREN[1:0]). This enables the 2.2kΩ
pullup. Once the jack has been inserted and the type of
accessory determined, set JDWK = 1 to save power.
Once the plug is removed, set JDWK = 0.
Table 21. Jack Sense (JKSNS)
JKSNS[1:0]
DESCRIPTION
00
01
10
11
JACKSNS is below V
(low).
TH2
JACKSNS is between V
Invalid.
and V
(mid).
TH1
TH2
JACKSNS is above V
(high).
TH1
______________________________________________________________________________________ 51
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
LOUTP
MICBIAS
MIC
GND
HPR
HPL
JACKSNS/AUX
ROUTP
MICLP
MX980A
Figure 8. Typical Configuration for Headset Detection
(> 95% x MICBIAS), mid, or low (< 10% x MICBIAS).
When connected to the microphone pin of the headset
jack, this window comparator allows detection of:
Table 22. Debounce Time
JDEB
00
DEBOUNCE (ms)
25
50
• No headset (high)
01
• Cellular headset with microphone (high → mid)
• Stereo headset without microphone (high → low)
• Cellular headset button press (mid → low → mid)
• Headset removal (low or mid → high)
10
100
200
11
Debounce (JDEB)
Jack removal: A jack is present. All output poles
(headphones/line outs) are assumed driven by a low
impedance amplifier. All input poles (microphones) are
assumed to be biased with a voltage above ground but
below 95% of the MICBIAS voltage. For the MAX9880A
to sense when a jack is removed, the JACKSNS pin
must be connected to the jack in such a way as to
ensure either the JACKSNS pin gets pulled above 95%
of MICBIAS (as would happen if JACKSNS is hooked to
a microphone pole) or it changes state from low to high
or vice versa (as would happen if JACKSNS is hooked
to a ground pole which goes high impedance when the
jack is removed, or is hooked to a regular jack insertion
tab that shorts to ground when the jack is removed).
Subsequently, IRQ is pulled low.
Configures the JDET debounce time for changes to
JKSNS[1:0] according to Table 22.
For jack plug insertion/removal, the sequence of events
is as follows:
Jack insertion: No jack is present. The MAX9880A has
a power supply and is in low-power sleep mode
(LOUTP/ROUTP are high impedance). When the
2
JDETEN I C bit is set, the JACKSNS pin has weak
pullups to MICVDD. When a jack is subsequently insert-
2
ed, JACKSNS should change state (indicated by I C
bits JKSNS[1:0]), and this causes the IRQ pin to be
pulled low, which can trigger a system wakeup.
Jack present: After an interrupt has been sent to the
2
system controller, the I C must indicate unambiguously
Jack absent: After an interrupt has been sent to the
2
that a jack is present when the I C registers are read.
2
system controller, the I C must indicate unambiguously
2
This is done with the JDET I C bit, which goes high
2
that a jack is not present when the I C registers are
when there is a change of state of the JKSNS[1:0] bits.
The MAX9880A jack-detect system monitors the
JACKSNS pin and reports the voltage level as high
read. This is indicated by reading the status of the
2
JKSNS[1:0] I C read bits.
52 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 23. Headset Detect Configuration
JACK ACTION
JKSNS
IRQ TOGGLES?
SHDN
MICBIAS
JDWK
FROM
TO
Headset
Headphone
None
FROM
11
11
01
00
11
11
00
00
11
11
01
00
11
11
00
00
11
11
01
00
TO
01
00
11
11
00
00
11
11
01
00
11
11
00
00
11
11
01
00
11
11
IJDET = 1 IJDET = 0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
—
—
—
—
—
—
—
—
0
0
0
None
None
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
0
Headset
Headphone
None
0
None
1
Headset
Headphone
None
1
None
1
Headset
Headphone
None
1
None
0
Headset
Headphone
None
0
0
None
0
0
Headset
Headphone
None
0
0
None
0
1
Headset
Headphone
None
0
1
None
0
1
Headset
Headphone
None
0
1
None
1
—
—
—
—
Headset
Headphone
None
1
None
1
Headset
Headphone
1
None
Note: JDETEN = 1; MICBIAS enable; any bit of PALEN/PAREN set.
______________________________________________________________________________________ 53
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Headphone Modes
The MAX9880A’s headphone amplifier supports differen-
tial, single-ended, and capacitorless output modes, as
shown in Figure 9. In each mode, the amplifier can be
configured for stereo or mono operation. The single-
ended mode optionally includes click-and-pop reduc-
tion to eliminate the click-and-pop that would normally
be caused by the output coupling capacitor. When
click-and-pop reduction is not required leave LOUTN
and ROUTN unconnected.
DIFFERENTIAL
CAPACITORLESS
SINGLE-ENDED
220µF
LOUTP
LOUTP
LOUTN
LOUTP
MX980A
LOUTN
LOUTN
1µF
220µF
ROUTP
ROUTN
ROUTP
ROUTN
ROUTP
ROUTN
1µF
OPTIONAL COMPONENTS REQUIRED FOR CLICK-AND-POP SUPPRESSION ONLY.
Figure 9. Headphone Amplifier Modes
Table 24. Mode Configuration Register
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Mode
DSLEW
VSEN
ZDEN
0
0
0
0
HPMODE
0x24
0x25
Jack Detect
JDETEN
0
JDWK
0
JDEB
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
BITS
FUNCTION
Digital Volume Slew Speed
0 = Digital volume changes are slewed over 10ms.
1 = Digital volume changes are slewed over 80ms.
DSLEW
Volume Change Smoothing
0 = Volume changes slew through all intermediate values.
1 = Volume changes occur in one step.
VSEN
ZDEN
Line Input Zero-Crossing Detection
0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero
crossing occurs.
1 = Line input volume changes occur immediately.
54 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 24. Mode Configuration Register (continued)
BITS
FUNCTION
Headphone Amplifier Mode
HPMODE
MODE
000
Stereo differential
001
Mono (left) differential
Stereo capacitorless
010
HPMODE
011
Mono (left) capacitorless
100
Stereo single-ended (clickless)
Mono (left) single-ended (clickless)
Stereo single-ended (fast turn-on)
Mono (left) single-ended (fast turn-on)
101
110
111
Note: In mono operation, the right amplifier is disabled.
Jack-Detection Enable
SHDN = 0: Sleep Mode. Enables pullups on JACKSNS/AUX to detect jack insertion.
SHDN = 1: Normal Mode. Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes.
Note: AUXEN must be set to 0 for jack detection to function.
JDETEN
JDWK
Jack-Sense Weak Pullup. Enables an internal pullup. Set JDWK = 1 to enable an internal 4µA current
source. Set JDWK = 0 for external pullup.
Jack Detect Debounce. Configures the JDET debounce time for changes to JKSNS[1:0] according to
information below.
JDEB
00
DEBOUNCE TIME (ms)
JDEB
25
50
01
10
100
200
11
Power Management
Revision Code
The MAX9880A includes complete power management
control to minimize power usage. The DAC and both
ADCs can be independently enabled so that only the
required circuitry is active.
The MAX9880A includes a revision code to allow easy
identification of the device revision. Revision code at
register address 0xFF is not accessible through the SPI
interface and so the revision code is accessible
through SPI at an additional address of 0x214. The cur-
rent revision code is 0x42.
______________________________________________________________________________________ 55
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 25. Power Management Register
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Enable
LNLEN
LNREN
0
LOLEN
0
LOREN
0
DALEN
XTEN
DAREN
ADLEN
0
ADREN
0
0x26
0x27
System Shutdown
SHDN
XTOSC
Grayed boxes = Not used.
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
MX980A
BITS
FUNCTION
Left-Line Input Enable. Enables the left-line input preamp and automatically enables the left and right
headphone amplifiers. If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and
right headphone amplifier.
LNLEN
Note: Control of the right headphone amplifier can be overridden by HPMODE.
Right-Line Input Enable. Enables the right-line input preamp and automatically enables the right headphone
amplifiers.
LNREN
Note: Control of the right headphone amplifier can be overridden by HPMODE.
LOLEN
LOREN
Left-Line Output Enable. Enables the left-line output.
Right-Line Output Enable. Enables the right-line output.
Left DAC Enable. Enables the left DAC and automatically enables the left and right headphone amplifiers. If
DAREN = 0, the left DAC signal is also routed to the right headphone amplifier.
DALEN
Note: Control of the right headphone amplifier can be overridden by HPMODE.
DAREN
ADLEN
Right DAC Enable. Enables the right DAC. Right DAC operation requires DALEN = 1.
Left ADC Enable.
2
Right ADC Enable. Enabling the right ADC must be done in the same I C write operation that enables the left
ADREN
SHDN
XTEN
ADC. The right ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must
be toggled to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
Shutdown. Places the device in low power shutdown mode.
Crystal Clock Enable
1 = Output of crystal oscillator and buffer routed to the clock prescaler. MCLK input disabled.
0 = MCLK input routed to the clock prescaler. Crystal oscillator and buffer disabled.
Crystal Clock Source
1 = Disables the internal crystal oscillator. Provide an external clock on X1.
0 = Enables the internal crystal oscillator. Attach a crystal between X1 and X2. XTOSC is ignored if XTEN = 0.
XTOSC
Table 26. Revision Code Register
REGISTER
ADDRESS
(SEE NOTE)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Revision ID
Revision ID
REV
REV
0x14
0xFF
2
Note: Register addresses listed are for I C. To get the SPI address, add 0x200 with the following exception: Register 0xFF is not
accessible through SPI.
56 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
t
t
CSH
CSS
t
CP
CS
SCLK
DIN
t
CSW
t
CL
t
CH
t
DZ
t
t
t
DO
DH
DS
t
DEN
DOUT
Figure 10. SPI Interface Timing Diagram
CS
SCLK
DIN
R/W
ADDR9
ADDR0
UNUSED4
UNUSED0
D7
D0
1 DATA BYTE
HIGH-Z
DOUT
Figure 11. Writing 1 Byte of Data to the MAX9880A
Serial-Data In (DIN) and Serial-Data Out (DOUT)
The SPI frame is organized into 24 bits. The first 16 bits
consist of the R/W enable bit, followed by the 10 regis-
ter address bits and 5 unused bits. The next 8 bits are
data bits, sent most significant bit first.
Serial Peripheral Interface (SPI)
Chip Select (CS)
The MAX9880A SPI interface is active only when CS is
low. When CS is high, the MAX9880A configures the
DOUT output for high impedance and resets the inter-
nal SPI logic. If CS goes high in the middle of an SPI
transfer, all the data is discarded. When CS is low,
unless the register address is correctly decoded by the
MAX9880A, the DOUT output is high impedance.
For an SPI write transfer, write a 1 to the R/W bit, fol-
lowed by the 10 register address bits, 5 unused bits,
then the 8 data bits.
Figure 11 illustrates the proper frame format for writing
one byte of data to the MAX9880A. Additional 24-bit
frames can be sent while CS remains low. The DOUT
output is high impedance during a write operation.
Serial Clock (SCLK)
The SPI master provides the SCLK signal to clock the
SPI interface. SCLK has an upper frequency limit of
25MHz. The MAX9880A samples the DIN input data on
the falling edge of SCLK and changes the output data
on the rising edge of SCLK. The MAX9880A ignores
SCLK transitions when CS is high.
For an SPI read transfer, write a zero to the R/W bit, fol-
lowed by the 10 register address bits and 5 unused
bits. Any data sent after the register address bits are
ignored. The internal contents of the register being read
______________________________________________________________________________________ 57
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
CS
SCLK
DIN
R/W
ADDR9
ADDR0
UNUSED4
UNUSED0
HIGH-Z
DOUT
D7
D0
1 DATA BYTE
MX980A
Figure 12. Reading 1 Byte of Data from the MAX9880A
CS
SCLK
DIN
R/W
ADDR9
ADDR0
UNUSED4
UNUSED0
HIGH-Z
DOUT
D7
D0
D7
D0
1 DATA BYTE
1 DATA BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Reading n Bytes of Data from the MAX9880A
2
do not change until the transfer is complete. The DOUT
output is high impedance when writing the register
address bits. If the correct register address is decod-
ed, DOUT is driven low at the first rising clock edge
after the first unused bit.
I C Serial Interface
2
The MAX9880A features an I C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9880A and
the master at clock rates up to 400kHz. Figure 14
shows the 2-wire interface timing diagram. The master
generates SCL and initiates data transfer on the bus.
The master device writes data to the MAX9880A by
transmitting the proper slave address followed by the
register address and then the data word. Each transmit
sequence is framed by a START (S) or repeated
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the MAX9880A is 8 bits long and is
followed by an acknowledge clock pulse. A master
reading data from the MAX9880A transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX9880A transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read
Figure 12 illustrates the proper frame format for reading
1 byte of data from the MAX9880A.
When reading data from the MAX9880A, the address
pointer autoincrements by one register address if CS is
held low after reading the first 8 data bits. For each
subsequent eight clock cycles, a byte of data is read.
This autoincrement feature allows a master to read
sequential registers within one continuous SPI register
address range from 0x200 to 0x227. The register
address does not autoincrement if a read is initiated at
a register address lower than 0x200. If the register
address increments beyond 0x227, the DOUT output is
high impedance. Figure 13 illustrates the proper format
for reading multiple bytes of data.
SMBus is a trademark of Intel Corp.
58 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
SP
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
t
HIGH
HD,STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 14. 2-Wire Interface Timing Diagram
S
Sr
P
SCL
SDA
Figure 15. START, STOP, and Repeated START Conditions
sequence is framed by a START or repeated START
condition, a not acknowledge, and a STOP condition.
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically greater than 500Ω, is
required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX9880A
from high voltage spikes on the bus lines and minimize
crosstalk and undershoot of the bus signals.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 15). A
START condition from the master signals the beginning
of a transmission to the MAX9880A. The master termi-
nates transmission and frees the bus by issuing a STOP
condition. The bus remains active if a repeated START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX9880A recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
______________________________________________________________________________________ 59
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
9
NOT ACKNOWLEDGE
SDA
MX980A
ACKNOWLEDGE
Figure 16. Acknowledge
ACKNOWLEDGE FROM MAX9880A
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 17. Writing 1 Byte of Data
Slave Address
The master pulls down SDA during the 9th clock cycle
to acknowledge receipt of data when the MAX9880A is
in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue.
A not acknowledge is sent when the master reads the
final byte of data from the MAX9880A, followed by a
STOP condition.
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
MAX9880A, the seven most significant bits are
0010000. Setting the read/write bit to 1 (slave address
= 0x21) configures the MAX9880A for read mode.
Setting the read/write bit to 0 (slave address = 0x20)
configures the MAX9880A for write mode. The address
is the first byte of information sent to the MAX9880A
after the START condition.
Write Data Format
A write to the MAX9880A includes transmission of a
START condition, the slave address with the R/W bit set
to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
condition. Figure 17 illustrates the proper frame format
for writing 1 byte of data to the MAX9880A. Figure 18
illustrates the frame format for writing n bytes of data to
the MAX9880A.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9880A uses to handshake receipt each byte of
data when in write mode (see Figure 16). The
MAX9880A pulls down SDA during the entire master-
generated 9th clock pulse if the previous byte is suc-
cessfully received. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master retries communication.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9880A.
The MAX9880A acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
60 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
The second byte transmitted from the master config-
the rising edge of SCL. The address pointer autoincre-
ments after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from register 0x00.
ures the MAX9880A’s internal register address pointer.
The pointer tells the MAX9880A where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9880A upon receipt of the address pointer data.
The third byte sent to the MAX9880A contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9880A signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This
autoincrement feature allows a master to write to
sequential registers within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x17
are reserved. Do not write to these addresses.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9880A’s
slave address with the R/W bit set to 0 followed by the
register address. A repeated START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX9880A then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX9880A acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START command followed
by a read command resets the address pointer to reg-
ister 0x00.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figure 19 illustrates the frame format for reading 1
byte from the MAX9880A. Figure 20 illustrates the frame
format for reading multiple bytes from the MAX9880A.
The first byte transmitted from the MAX9880A is the
contents of register 0x00. Transmitted data is valid on
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9880A
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9880A
REGISTER ADDRESS
S
0
A
A
A
DATA BYTE 1
1 BYTE
DATA BYTE n
1 BYTE
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 18. Writing n Bytes of Data
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
ACKNOWLEDGE FROM MAX9880A
Sr SLAVE ADDRESS
A
P
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
A
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 19. Reading 1 Byte of Data
______________________________________________________________________________________ 61
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
ACKNOWLEDGE FROM MAX9880A
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9880A
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9880A
Sr SLAVE ADDRESS
NOT ACKNOWLEDGE FROM MASTER
A
S
0
A
A
1
A
DATA BYTE
1 BYTE
P
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 20. Reading n Bytes of Data
MX980A
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD and
DVDDS1 directly to DGND.
Applications Information
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the
MAX9880A, partition the circuitry so that the analog
sections of the MAX9880A are separated from the digi-
tal sections. This ensures that the analog audio traces
are not routed near digital traces.
Route microphone signals from the microphone to the
MAX9880A as a differential pair, ensuring that the posi-
tive and negative signals follow the same path as
closely as possible with equal trace length. When using
single-ended microphones or other single-ended audio
sources, ground the negative microphone input as
close to the audio source as possible and then treat the
positive and negative traces as differential pairs.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect
AGND and DGND directly to the ground plane using
the shortest trace length possible. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any digital noise from
coupling into the analog audio signals.
The MAX9880A TQFN package features an exposed
thermal pad on its underside. Connect the exposed
thermal pad to AGND.
An evaluation kit (EV kit) is available to provide an
example layout for the MAX9880A. The EV kit allows
quick setup of the MAX9880A and includes easy-to-use
software allowing all internal registers to be controlled.
Ground the bypass capacitors on MICBIAS, REG,
PREG, and REF directly to the ground plane with mini-
mum trace length. Also be sure to minimize the path
length to AGND. Bypass AVDD directly to AGND.
Startup Sequences
Table 27. Clock Initialization (Perform Before Any Playback or Record Setup)
SEQUENCE
DESCRIPTION
REGISTERS
0x27
1
2
3
SHDN = 0
Configure clocks
0x05, 0x06, 0x07, 0x0B, 0x0C
0x08, 0x09, 0x0A, 0x0D, 0x0E, 0x0F
Configure digital audio interface
Table 28. Music Playback
SEQUENCE
DESCRIPTION
REGISTERS
0x10
1
2
3
4
5
6
7
8
9
Select DAC audio source
Select music filters
Set output volume
0x11
0x1C, 0x1D
0x1E, 0x1F
0x24
Set line output volume
Select headphone mode
Enable line outputs and DAC as required
Enable LRCLK and BCLK (if operating in slave mode)
Enable MAX9880A
0x26
N/A
0x27
Enable external amplifier (if using)
N/A
62 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Table 29. Line Input Playback
SEQUENCE
DESCRIPTION
REGISTERS
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x24
1
2
3
4
5
6
7
Set line input gain
Set volume
Set line output volume (if using)
Select headphone mode
Enable line outputs and line inputs as required
Enable MAX9880A
0x26
0x27
Enable external amplifier (if using)
N/A
Table 30. Line Input Playback with Record
SEQUENCE
DESCRIPTION
REGISTERS
0x11
1
2
Select music filters
Set line input gain
Set volume
0x1A, 0x1B
0x1C, 0x1D
0x1E, 0x1F
0x22
3
4
Set line output volume (if using)
Configure ADC input mixer
5
6
Select headphone mode
0x24
7
Enable line outputs, line inputs, and ADC as required
Enable LRCLK and BCLK (if operating in slave mode)
Enable MAX9880A
0x26
8
N/A
9
0x27
10
Enable external amplifier (if using)
N/A
Table 31. Voice Playback
SEQUENCE
DESCRIPTION
REGISTERS
0x10
1
2
3
4
5
6
7
8
9
Select DAC audio source
Select voice filters
Set volume
0x11
0x1C, 0x1D
0x1E, 0x1F
0x24
Set line output volume (if using)
Select headphone mode
Enable line outputs and DAC as required
Enable LRCLK and BCLK (if operating in slave mode)
Enable MAX9880A
0x26
N/A
0x27
Enable external amplifier (if using)
N/A
______________________________________________________________________________________ 63
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Table 32. Voice Microphone Record
SEQUENCE
DESCRIPTION
REGISTERS
0x11
1
2
3
4
5
6
7
8
9
Select voice filters
Set ADC level to 0dB
0x18, 0x19
0x20, 0x21
0x1E, 0x1F
0x22
Configure microphone gain
Set line output volume (if using)
Configure ADC input mixer
Configure MICBIAS voltage
Enable ADC
0x23
MX980A
0x26
Enable LRCLK and BCLK (if operating in slave mode)
Enable MAX9880A
N/A
0x27
Table 33. Voice Playback with Record
SEQUENCE
DESCRIPTION
REGISTERS
0x11
1
2
3
4
5
6
7
8
9
Select voice filters
Set ADC level to 0dB
0x18, 0x19
0x20, 0x21
0x1E, 0x1F
0x22
Configure microphone gain
Set line output volume (if using)
Configure ADC input mixer
Configure MICBIAS voltage
Enable ADCs and DACs as required
Enable LRCLK and BCLK (if operating in slave mode)
Enable MAX9880A
0x23
0x26
N/A
0x27
64 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
mode, music source connected through S2 pins to
DAI2 audio path, and output on headphone amplifiers
(output capacitorless mode).
Example of Register Settings for Music
Playback and Voice Duplex Senarios
Music Playback
f
f
= 12.288MHz (master clock supplied to codec),
LRCLK
MCLK
2
= 48kHz, standard I S format, codec in slave
Table 34. Music Playback
SEQUENCE
DESCRIPTION
REGISTER ADDRESS
REGISTER VALUE
1
2
SHDN = 0
0x27
0x05
04h
10h
60h
00h
11h
50h
21h
80h
09h
40h
02h
0Ch
84h
Configure system clock
3
Configure DAI2 clock
0x0B
4
Configure DAI2 clock
0x0C
5
Configure DAI2 audio path
Configure DAI2 audio path
Select DAC audio source
Select music filters
0x0D
6
0x0E
7
0x10
8
0x11
9
Set output volume (0dB)
0x1C, 0x1D
0x1E, 0x1F
0x24
10
11
12
13
Set line output volume (muted)
Select headphone mode (output capacitorless mode)
Enable line outputs and DAC as required
Enable MAX9880A
0x26
0x27
Voice Duplex
= 13MHz (master clock supplied to codec),
= 8kHz, TDM/PCM format, codec in slave
mode, voice signals on S1 pins to DAI1 audio path and
output on headphone amplifier left (differential mode).
f
f
MCLK
LRCLK
Table 35. Voice Duplex
SEQUENCE
DESCRIPTION
REGISTER ADDRESS
0x27
REGISTER VALUE
1
2
SHDN = 0
04h
10h
0Fh
1Fh
04h
30h
21h
33h
03h
54h
09h
40h
50h
01h
01h
0Bh
84h
Configure system clock
0x05
3
Configure DAI1 clock
0x0B
4
Configure DAI1 clock
0x0C
5
Configure DAI1 audio path
Configure DAI2 audio path
Select DAC audio source
Select voice GSM filters
0x0D
6
0x0E
7
0x10
8
0x11
9
Set ADC level to 0dB
0x18, 0x19
0x20, 0x21
0x1C, 0x1D
0x1E, 0x1F
0x22
10
11
12
13
14
15
16
17
Configure microphone gain (20dB preamp gain)
Set headphone volume
Set line output volume (if using)
Configure ADC input mixer
Configure MICBIAS voltage (2.2V)
Select headphone mode
0x23
0x24
Enable line outputs, ADC and DAC as required
Enable MAX9880A
0x26
0x27
______________________________________________________________________________________ 65
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Functional Diagram/Typical Operating Circuit
MX980A
P V D D
M I X
M I X
M I X
M I X
P R E G
A V D D
D V D D
M I X / M U X
S D O U T S 2
S D I N S 2
L R C L K S 2
B C L K S 2
S D O U T S 1
S D I N S 1
M I X / M U X
M I X / M U X
L R C L K S 1
B C L K S 1
F R E Q 1
P S C L K
M C L K
S P D M C L K
D O U T
S D A / D I N
C S
S C L / S C L K
M O D E
I R Q
XM890A
M I X
M I X
M I C V D D
D V D D S 1
R E C E I V E R
F M
66 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
90-0057
48 TQFN-EP
48 WLP
T4866+1
21-0141
21-0230
Refer to Application Note 1891
W482A3+1
______________________________________________________________________________________ 67
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MX980A
68 ______________________________________________________________________________________
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
MX980A
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
______________________________________________________________________________________ 69
Low-Power, High-Performance
Dual I2S Stereo Audio Codec
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
7/10
Initial release
—
15–22, 24, 29, 31,
47, 49, 51, 52,
55–58, 60, 61,
62, 66
1
3/11
Various data sheet errors
MX980A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
70 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX9880A_11
Low-Power, High-Performance Dual I2S Stereo Audio Codec Comprehensive Headset Detection
MAXIM
MAX988ESA-T
Comparator, 1 Func, 7000uV Offset-Max, 210ns Response Time, CMOS, PDSO8, 0.150 INCH, SOIC-8
MAXIM
©2020 ICPDF网 联系我们和版权申明