MAX9949FCCB+ [MAXIM]
Dual Per-Pin Parametric Measurement Units; 双每个引脚参数测量单元
| 型号： | MAX9949FCCB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Per-Pin Parametric Measurement Units |
| 文件： | 总23页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3014; Rev 2; 3/09
Dual Per-Pin Parametric Measurement Units
4/MAX950
General Description
Features
The MAX9949/MAX9950 dual parametric measurement
units (PMUs) feature a small package size, wide force
and measurement range, and high accuracy, making the
devices ideal for automatic test equipment (ATE) and
other instrumentation that requires a PMU per pin or per
site.
o Force Voltage/Measure Current (FVMI)
o Force Current/Measure Voltage (FIMV)
o Force Voltage/Measure Voltage (FVMV)
o Force Current/Measure Current (FIMI)
o Force Nothing/Measure Voltage (FNMV)
The MAX9949/MAX9950 force or measure voltages in
the -2V to +7V through -7V to +13V ranges, dependent
o Five Programmable Current Ranges
upon the supply voltage (V
and V ). The devices
EE
CC
±±2µ
handle supply voltages of up to +30V (V
to V ) and
EE
CC
±±ꢀ2µ
±±ꢀꢀ2µ
±±mµ
a 20V device under test (DUT) voltage swing at full cur-
rent. The MAX9949/MAX9950 also force or measure
currents up to 25mA with a lowest full-scale range of
2ꢀA. ꢁntegrated support circuitry facilitates use of an
external buffer amplifier for current ranges greater than
25mA.
±±ꢁmµ
o -±V to +7V Through -7V to +13V Input Voltage
Range and Higher (Up to ±ꢀV Voltage Swing at
Full Current)
A voltage proportional to the measured output voltage
or current is provided at the MSR_ output. ꢁntegrated
comparators, with externally set voltage thresholds, pro-
vide detection for both voltage and current levels. The
MSR_ and comparator outputs can be placed in a high-
Z state. ꢁntegrated voltage clamps limit the force output
to levels set externally. The force-current or the mea-
sure-current voltage can be offset -0.2V to +4.4V (ꢁOS).
This feature allows for the centering of the control or
measured signal within the external DAC or ADC range.
o Force-Current/Measure-Current Voltage Offset
(IOS)
o Programmable Voltage Clamps for the Force
Output
o Low-Leakage, High-Z Measure State
o 3-Wire Serial Interface
o Low Power, 8mµ (max) per PMU
The MAX9949D/MAX9950D feature an integrated 10kΩ
force-sense resistor between FORCE_ and SENSE_.
The MAX9949F/MAX9950F have no internal force-sense
resistor. These devices are available in a 64-pin 10mm x
10mm, 0.5mm pitch TQFP package with an exposed
8mm x 8mm die pad on the top (MAX9949) or the bottom
(MAX9950) of the package for efficient heat removal. The
Ordering Information
PµRT
TEMP RµNGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PµCKµGE
64 TQFP-EPR*
64 TQFP-EPR*
64 TQFP-EP**
64 TQFP-EP**
MµX9949DCCB+
MAX9949FCCB+
MµX99ꢁꢀDCCB+
MAX9950FCCB+
exposed paddle is internally connected to V . The
EE
MAX9949/MAX9950 are specified over the commercial
(0°C to +70°C) temperature range.
+Denotes a lead(Pb)-free/RoHs-compliant part.
*EPR = Exposed pad on top.
**EP = Exposed pad on bottom.
Note: Exposed pad is internally connected to VEE.
Applications
Memory Testers
Selector Guide
VLSꢁ Testers
System-on-a-Chip Testers
Structural Testers
PµRT
DESCRIPTION
MAX9949DCCB+
MAX9949FCCB+
MAX9950DCCB+
MAX9950FCCB+
ꢁnternal 10kΩ force-sense resistor
No internal force-sense resistor
ꢁnternal 10kΩ force-sense resistor
No internal force-sense resistor
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-6±9-464±, or visit Maxim’s website at www.maxim-ic.com.
Dual Per-Pin Parametric Measurement Units
µBSOLUTE MµXIMUM RµTINGS
V
V
V
to AGND.......................................................................+20V
to AGND.........................................................................-15V
Continuous Power Dissipation (T = +70°C)
A
CC
EE
CC
64-Pin TQFP-EP (derate 43.5mW/°C above +70°C)....3478mW
to V ...........................................................................+32V
θ
θ
(Note 1) ................................................................+23.0°C/W
(Note 1) .....................................................................+8°C/W
EE
JA
JC
V to AGND............................................................................+6V
L
AGND to DGND.....................................................-0.5V to +0.5V
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Operating Temperature (commercial) Range ........0°C to +70°C
Lead Temperature (soldering 10s) ..................................+300°C
All Other Pins ...................................(V - 0.3V) to (V
+ 0.3V)
EE
CC
L
Digital ꢁnputs/Outputs ...................................-0.3V to (V + 0.3V)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICµL CHµRµCTERISTICS
(V = +12V, V = -7V, V = +3.3V, T = T
to T
, unless otherwise noted. T < +25°C guaranteed by design and characterization.
CC
EE
L
A
MꢁN
MAX A
Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
4/MAX950
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
FORCE VOLTµGE (Note 3)
V
V
_
V
3.5V
+
V
3.5V
-
CC
ꢁN0 ,
EE
Force ꢁnput Voltage Range
Forced Voltage
V
_
ꢁN1
V
V
= +12V, V = -7V
EE
-2
-7
+7
CC
CC
DUT current at full
scale
= +18V, V = -
EE
+13
V
DUT
V
V
3.5V
+
V
3.5V
-
CC
EE
DUT current = 0
ꢁnput Bias Current
1
ꢀA
Forced-Voltage Offset Error
V
V
T
T
T
= +25°C
-25
-1
+25
+1
mV
FOS
FGE
A
A
A
Forced-Voltage Offset
Temperature Coefficient
100
0.005
10
ꢀV/°C
%
Forced-Voltage Gain Error
= +25°C, nominal gain of +1
Forced-Voltage Gain
Temperature Coefficient
ppm/°C
= +25°C, gain and offset errors
Forced-Voltage Linearity Error
V
-0.02
-1
+0.02
+1
%FSR
FLER
calibrated out (Notes 4, 5)
MEµSURE CURRENT (Note 3)
Measure-Current Offset
ꢁ
T
T
= +25°C (Note 4)
= +25°C (Note 7)
%FSR
ppm/°C
%
MOS
A
A
Measure-Current Offset
Temperature Coefficient
20
20
Measure-Current Gain Error
ꢁ
-1
+1
MGE
Measure-Current Gain
Temperature Coefficient
ppm/°C
T
= +25°C, gain, offset, and
A
Ranges A–D -0.02
+0.02
+1
%FSR
nA
Linearity Error
ꢁ
common-mode errors
calibrated out (Notes 4, 5, 6)
MLER
Range E
-1
V
V
= V
-4
0
+4
8
ꢁOS
ꢁOS
DUTGND
Measure Output Voltage Range
over Full Current Range (Note 8)
V
V
MSR
= 4V + V
DUTGND
±
_______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
DC ELECTRICµL CHµRµCTERISTICS (continued)
(V = +12V, V = -7V, V = +3.3V, T = T
to T , unless otherwise noted. T < +25°C guaranteed by design and characterization.
MAX A
CC
EE
L
A
MꢁN
Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
Current-Sense Amp Offset
Voltage ꢁnput
V
Relative to V
-0.2
+4.4
V
ꢁOS
DUTGND
Rejection of Output Measure
Error Due to Common-Mode
Sense Voltage
Specified as the percent of full-scale range
change at the measure output per volt
change in the DUT voltage
CMVR
0.001
0.007 %FSR/V
+2
LER
Range E, R_E = 1MΩ
Range D, R_D = 100kΩ
Range C, R_C = 10kΩ
Range B, R_B = 1kΩ
Range A, R_A = 80Ω
-2
-20
-200
-2
ꢀA
+20
+200
+2
Measure Current Range
mA
-25
+25
FORCE CURRENT (Note 3)
V
V
= V
-4
0
+4
+8
ꢁOS
ꢁOS
DUTGND
ꢁnput Voltage Range for Setting
Forced Current Over Full Range
V
V
V
ꢁNꢁ
= 4V + V
DUTGND
Current-Sense Amp Offset
Voltage ꢁnput
V
Relative to V
-0.2
+4.4
ꢁOS
DUTGND
VꢁOS ꢁnput Bias Current
Forced-Current Offset
1
ꢀA
ꢁ
ꢁ
T
= +25°C (Note 4)
= +25°C (Note 7)
-1
+1
%FSR
FOS
A
A
Forced-Current Offset
Temperature Coefficient
20
ppm/°C
%
Forced-Current Gain Error
T
-1
+1
FGE
Forced-Current Gain
Temperature Coefficient
20
ppm/°C
T
= +25°C, gain, offset, and
A
Ranges A–D -0.02
+0.02
+1
%FSR
nA
Forced-Current Linearity Error
ꢁ
FLER
common-mode errors
calibrated out (Notes 4, 5, 6)
Range E
-1
Specified as the percent of full-scale range
change of the forced current per volt
change in the DUT voltage
Rejection of Output Error Due to
Common-Mode Load Voltage
CMRꢁ
+0.001 +0.007 %FSR/V
+2
OER
Range E, R_E = 1MΩ
Range D, R_D = 100kΩ
Range C, R_C = 10kΩ
Range B, R_B = 1kΩ
Range A, R_A = 80Ω
-2
-20
-200
-2
+20
+200
+2
ꢀA
Forced-Current Range
mA
-25
+25
MEµSURE VOLTµGE (Note 3)
Measure-Voltage Offset
V
T
= +25°C
-25
-1
+25
+1
mV
ꢀV/°C
%
MOS
A
A
Measure-Voltage Offset
Temperature Coefficient
100
0.005
10
Gain Error
V
T
= +25°C, nominal gain of +1
MGER
Measure-Voltage Gain
Temperature Coefficient
ppm/°C
_______________________________________________________________________________________
3
Dual Per-Pin Parametric Measurement Units
DC ELECTRICµL CHµRµCTERISTICS (continued)
(V = +12V, V = -7V, V = +3.3V, T = T
to T , unless otherwise noted. T < +25°C guaranteed by design and characterization.
MAX A
CC
EE
L
A
MꢁN
Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
T
= +25°C, gain and offset errors
A
Measure-Voltage Linearity Error
V
-0.02
+0.02
%FSR
MLER
calibrated out (Notes 4, 5, 6)
V
V
= +12V, V = -7V
EE
-2
-7
+7
CC
CC
DUT current at
full scale
= +18V, V = -12V
EE
+13
Measure Output Voltage Range
V
V
MSR
over Full DUT Voltage (V
)
DUT
V
+
V
-
CC
3.5V
EE
3.5V
DUT current = 0V
FORCE OUTPUT
Off-State Leakage Current
T
= +25°C
-5
+5
-28
nA
mA
kΩ
A
ꢁ
-45
+28
7.8
LꢁM-
Short-Circuit Current Limit
ꢁ
+45
13.3
LꢁM+
Force-to-Sense Resistor
R
D option only
10
FS
4/MAX950
SENSE INPUT
V
3.5V
+
V
3.5V
-
CC
EE
ꢁnput Voltage Range
V
Leakage Current
-5
+5
nA
COMPµRµTOR INPUTS
V
3.5V
+
V
3.5V
-
CC
EE
ꢁnput Voltage Range
V
Offset Voltage
T
= +25°C
-25
+25
mV
ꢀA
A
ꢁnput Bias Current
VOLTµGE CLµMPS
1
V
V
_,
_
V
3.4V
+
V
3.4V
-
CC
CLLO
EE
ꢁnput Control Voltage
Clamp Voltage Range
V
CLHꢁ
V
3.5V
+
V
3.5V
-
CC
EE
V
Clamp Voltage Accuracy
-100
+100
mV
DIGITµL INPUTS
5V logic
+3.5
+2.0
+1.7
ꢁnput High Voltage (Note 9)
ꢁnput Low Voltage (Note 9)
V
V
V
3.3V logic
2.7V logic
ꢁH
5V and 3.3V logic
2.5V logic
+0.8
+0.7
V
ꢁL
ꢁnput Current
ꢁ
1
ꢀA
pF
ꢁN
ꢁnput Capacitance
C
3.0
ꢁN
COMPµRµTOR OUTPUTS (Note 9)
Output High Voltage
V
V = +2.375V to +5.5V, R
= 1kΩ
= 1kΩ
V - 0.2
L
V
V
OH
L
PUP
Output Low Voltage
V
V = +2.375V to +5.5V, R
+0.4
OL
L
PUP
High-Z State Leakage Current
High-Z State Output Capacitance
1
ꢀA
pF
6.0
4
_______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
DC ELECTRICµL CHµRµCTERISTICS (continued)
(V = +12V, V = -7V, V = +3.3V, T = T
to T , unless otherwise noted. T < +25°C guaranteed by design and characterization.
MAX A
CC
EE
L
A
MꢁN
Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
DIGITµL OUTPUTS (Note 9)
ꢁ
= 1mA, V = +2.375V to +5.5V, relative
V -
L
0.25
OUT
L
Output High Voltage
Output Low Voltage
V
V
V
OH
to DGND
ꢁ
= -1mA, V = +2.375V to +5.5V,
OUT
L
V
0.2
OL
relative to DGND
POWER SUPPLY
Positive Supply
V
(Note 2)
(Note 2)
+10
-15
+12
-7
+18
-5
CC
V
Negative Supply
V
EE
Total Supply Voltage
Logic Supply
V
- V
+30
+5.5
16.0
16.0
1.2
V
CC
EE
V
+2.375
V
L
Positive Supply Current
Negative Supply Current
Logic Supply Current
Analog Ground Current
Digital Ground Current
ꢁ
No load, clamps enabled
mA
mA
mA
mA
mA
CC
ꢁ
No load, clamps enabled
EE
ꢁ
No load, all digital inputs at rails
No load, clamps enabled
L
ꢁ
0.9
AGND
DGND
ꢁ
No load, all digital inputs at rails
1MHz, measured at force output
60Hz, measured at force output
1.4
20
85
Power-Supply Rejection Ratio
PSRR
dB
µC ELECTRICµL CHµRµCTERISTICS
(V
= +12V, V = -7V, V = +3.3V, C
= 120pF, C = 100pF, T = T
to T , unless otherwise noted. T < +25°C guaranteed
MAX A
CC
EE
L
CM
L
A
MꢁN
by design and characterization. Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
FORCE VOLTµGE (Notes 1ꢀ, 11)
Range E, R_E = 1MΩ
160
35
25
20
25
Range D, R_D = 100kΩ
Range C, R_C = 10kΩ
Range B, R_B = 1kΩ
Range A, R_A = 80Ω
Settling Time
30
ꢀs
Maximum Stable Load
Capacitance
2500
pF
FORCE VOLTµGE/MEµSURE CURRENT (Notes 1ꢀ, 11)
Range E, R_E = 1MΩ
480
50
35
20
25
Range D, R_D = 100kΩ
Range C, R_C = 10kΩ
Range B, R_B = 1kΩ
Range A, R_A = 80Ω
Settling Time
45
ꢀs
ꢀs
ꢁn addition to force-voltage and measure-
current settling times, range A to range B,
R_A = 80Ω, R_B = 1kΩ
Range Change Switching
10
_______________________________________________________________________________________
ꢁ
Dual Per-Pin Parametric Measurement Units
µC ELECTRICµL CHµRµCTERISTICS (continued)
(V
= +12V, V = -7V, V = +3.3V, C
= 120pF, C = 100pF, T = T
to T , unless otherwise noted. T < +25°C guaranteed
MAX A
CC
EE
L
CM
L
A
MꢁN
by design and characterization. Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
FORCE CURRENT (Notes 1ꢀ, 11)
Range E, R_E = 1MΩ
300
100
40
Range D, R_D = 100kΩ
Range C, R_C = 10kΩ
Range B, R_B = 1kΩ
Range A, R_A = 80Ω
Settling Time
45
ꢀs
25
25
FORCE CURRENT/MEµSURE VOLTµGE (Notes 1ꢀ, 11, 1±)
Range E, R_E = 1MΩ
1600
170
40
Range D, R_D = 100kΩ
Range C, R_C = 10kΩ
Range B, R_B = 1kΩ
Range A, R_A = 80Ω
Settling Time
50
ꢀs
25
4/MAX950
25
ꢁn addition to force-voltage and measure-
current settling times, range A to range B,
R_A = 80Ω, R_B = 1kΩ
Range Change Switching
12
ꢀs
ꢀs
ns
SENSE INPUT TO MEµSURE OUTPUT PµTH (Note 1±)
Settling Time
C
= 100pF
0.2
LMSR
MEµSURE OUTPUT
C
= 100pF, measured from 50% of
LMSR
HIZ_ or HIZMSR True (0) to
High-Z
digital input voltage to 10% of output
voltage
250
5
C
= 100pF, measured from 50% of
LMSR
HIZ_ or HIZMSR False (1) to
Active
digital input voltage to 90% of output
voltage
ꢀs
Maximum Stable Load
Capacitance
1000
pF
FORCE OUTPUT
Measured from 50% of digital input voltage
to 10% of output voltage
HIZFORCE True (0) to High-Z
2
2
ꢀs
ꢀs
Measured from 50% of digital input voltage
to 90% of output voltage
HIZFORCE False (1) to Active
COMPµRµTORS
50mV overdrive, 1V , C
= 20pF,
P-P LCOMP
R
= 1kΩ measured from input-threshold
PUP
Propagation Delay
75
ns
zero crossing to 50% of output voltage
(Note 13)
C
= 20pF, R
= 1kΩ measured
PUP
LCOMP
from input-threshold zero crossing to 50%
of output voltage
Rise Time
Fall Time
60
5
ns
ns
C
= 20pF, R
= 1kΩ, 20% to 80%
PUP
LCOMP
6
_______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
µC ELECTRICµL CHµRµCTERISTICS (continued)
(V
= +12V, V = -7V, V = +3.3V, C
= 120pF, C = 100pF, T = T
to T , unless otherwise noted. T < +25°C guaranteed
MAX A
CC
EE
L
CM
L
A
MꢁN
by design and characterization. Typical values are at T = +25°C, unless otherwise specified.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
C
= 20pF, measured from 50% of
LCOMP
DISABLE True (0) to High-Z
digital input voltage to 10% of output
voltage
300
ns
C
= 20pF, measured from 50% of
LCOMP
DISABLE False (1) to Active
digital input voltage to 90% of output
voltage
100
ns
SERIµL PORT (V = +3.ꢀV, C
L
= 1ꢀpF)
DOUT
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to DOUT Valid
CS Low to SCLK High Setup
SCLK High to CS High Hold
SCLK High to CS Low Hold
CS High to SCLK High Setup
DꢁN to SCLK High Setup
DꢁN to SCLK High Hold
CS Pulse-Width High
f
20
22
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ꢀs
SCLK
t
12
12
CH
t
CL
t
DO
t
10
22
0
CSS0
CSH1
CSH0
t
t
t
5
CSS1
t
10
0
DS
t
(Note 14)
(Note 14)
DH
t
10
10
20
CSWH
CS Pulse-Width Low
t
CSWL
LOAD Pulse-Width Low
t
LDW
V
High to CS Low (Power-Up)
500
DD
Note ±: The device operates properly with different supply voltages with equally different voltage swings.
Note 3: Tested at V = +18V and V = -12V.
CC
EE
Note 4: ꢁnterpret errors expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point to end-point
range, i.e., for the 25mA range, the full-scale range = 50mA and a 1% error = 500ꢀA.
Note ꢁ: Case must be maintained 5°C for linearity specifications.
Note 6: Current linearity specifications are maintained to within 700mV of the clamp voltages when the clamps are enabled.
Note 7: Tested in range C.
Note 8: Linearity of the measured output is only guaranteed within the specified current range.
Note 9: The digital interface accepts +5V, +3.3V, and +2.5V CMOS logic levels. The voltage at V adjusts the threshold.
L
Note 1ꢀ: Settling times are to 0.1% of FSR. Cx = 47pF.
Note 11: All settling times are specified using a single compensation capacitor (Cx) across all current-sense resistors. Use an indi-
vidual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges.
Note 1±: The actual settling time of the measured voltage path (SENSE_ input to MSR_ output) is less than 1ꢀs. However, the R-C
time constant of the sense resistor and the load capacitance causes a longer overall settling time of the DUT voltage. This
settling time is a function of the current-range resistor used.
Note 13: The propagation delay time is only guaranteed over the force-voltage output range. Propagation delay is measured by
holding the SENSE_ input voltage steady and transitioning THMAX_ or THMꢁN_.
Note 14: Guaranteed by design.
_______________________________________________________________________________________
7
Dual Per-Pin Parametric Measurement Units
Typical Operating Characteristics
(V = +12V, V = -7V, C = 100pF, R to +2.5V, range A: R_A = 80Ω, R = 180Ω; range B: R_B = 1kΩ, R = 2.25kΩ; range C: R_C =
CC
EE
L
L
L
L
10kΩ, R = 22.5kΩ; range D: R_D = 100kΩ, R = 225kΩ; range E: R_E = 1MΩ, R = 2.25MΩ, T = +25°C.
L
L
L
A
TRANSIENT RESPONSE FVMI MODE
TRANSIENT RESPONSE FVMI MODE
RANGE D
TRANSIENT RESPONSE FVMI MODE
RANGES A, B, C
RANGE E
MAX9949/50 toc01
MAX9949/50 toc03
MAX9949/50 toc02
IN_
5V/div
IN_
5V/div
IN_
5V/div
0
0
0
0
0
FORCE_
5V/div
FORCE_
5V/div
FORCE_
5V/div
0
4/MAX950
20µs/div
1.0ms/div
100µs/div
TRANSIENT RESPONSE FVMV MODE
TRANSIENT RESPONSE FIMI MODE
TRANSIENT RESPONSE FIMI MODE
RANGE C
RANGES A, B, C
RANGE D
MAX9949/50 toc04
MAX9949/50 toc05
MAX9949/50 toc06
IN_
5V/div
IN_
5V/div
IN_
5V/div
0
0
0
0
0
0
MSR_
5V/div
FORCE_
5V/div
FORCE_
5V/div
20µs/div
20µs/div
100µs/div
TRANSIENT RESPONSE FIMI MODE
RANGE E
IOS vs. POWER SUPPLIES
MAX9949/50 toc08
MAX9949/50 toc07
20
15
10
5
V
CC
11.2
4.4
IN_
5V/div
0
0
IOS (MAX)
IOS (MIN)
3.2
1.8
FORCE_
5V/div
0
-0.2
-7
-5
V
EE
-10
-15
1.0ms/div
8
_______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
Pin Description
PIN
NµME
FUNCTION
MµX99ꢁꢀ
MµX9949
1, 16,
33, 48
1, 16,
33, 48
V
Negative Analog Supply ꢁnput
Positive Analog Supply ꢁnput
EE
2, 15,
34, 47
2, 15,
34, 47
V
CC
PMU-B Range-Setting-Resistor Common Connection. Connect to one end of all the range-
3
14
RBCOM setting resistors (RB_) for PMU-B. Also serves as the input to an external current-range buffer
for PMU-B.
4
5
6
7
8
9
13
12
11
10
9
RBE
RBD
RBC
RBB
RBA
PMU-B Range E Resistor Connection
PMU-B Range D Resistor Connection
PMU-B Range C Resistor Connection
PMU-B Range B Resistor Connection
PMU-B Range A Resistor Connection
8
FORCEB PMU-B Driver Output. Forces a current or voltage to the DUT for PMU-B.
PMU-B Sense ꢁnput. A Kelvin connection to the DUT. Provides the feedback signal in FVMꢁ
mode and the measured signal in FꢁMV mode for PMU-B.
10
11
12
13
7
6
5
4
SENSEB
PMU-B Compensation Capacitor Connection 1. Provides compensation for the PMU-B main
amplifier.
CC1B
PMU-B Compensation Capacitor Connection 2. Provides compensation for the PMU-B main
amplifier.
CC2B
PMU-B Current-Range Sense-Resistor Connection. Connects to the external current-range
sense resistor on the DUT side for PMU-B. See Figure 5.
RXDB
PMU-B Current-Range Sense-Resistor Connection. Connects to the external current-range
sense resistor on the amplifier side for PMU-B. See Figure 5.
14
17
18
3
RXAB
64
63
CS
Chip-Select ꢁnput. Force CS low to enable communication with the serial port.
Serial Port Load ꢁnput. A logic low asynchronously loads data from the input registers into the
PMU registers.
LOAD
19
20
62
61
SCLK
DꢁN
Serial Clock ꢁnput
Serial Data ꢁnput. Data loads into DꢁN MSB first.
PMU-B Window-Comparator High-Comparator Output. A sense-B voltage above the V
level forces the DUTHB output low. DUTHB is an open-drain output.
THMAXB
21
22
60
59
DUTHB
DUTLB
PMU-B Window-Comparator Low-Comparator Output. A sense-B voltage below the V
THMꢁNB
level forces the DUTLB output low. DUTLB is an open-drain output.
23
58
EXTBSEL PMU-B External Current-Range Selector. Selects the external current range for PMU-B.
DGND Digital Ground
24, 27
54, 57
Serial Data Output. Provides data out from the shift register. Facilitates daisy-chaining to DꢁN
of a downstream PMU. DOUT clocks out data MSB first.
25
56
DOUT
26
28
55
53
V
Logic Supply Voltage ꢁnput. The voltage applied at VL sets the upper logic-voltage level.
L
EXTASEL PMU-A External Current-Range Selector. Selects the external current range for PMU-A.
PMU-A Window-Comparator Low-Comparator Output. A sense-A voltage below the V
level forces the DUTLA output low. DUTLA is an open-drain output.
THMꢁNA
29
52
DUTLA
_______________________________________________________________________________________
9
Dual Per-Pin Parametric Measurement Units
Pin Description (continued)
PIN
NµME
DUTHA
HI-ZB
FUNCTION
MµX99ꢁꢀ
MµX9949
PMU-A Window-Comparator High-Comparator Output. A sense-A voltage above the V
level forces the DUTHA output low. DUTHA is an open-drain output.
THMAXA
30
51
PMU-B MSRB Output State Control. A logic low places the MSRB output in a high-impedance
state.
31
32
35
36
37
38
39
50
49
46
45
44
43
42
PMU-A MSRA Output State Control. A logic low places the MSRA output in a high-impedance
state.
HI-ZA
PMU-A Current-Range Sense-Resistor Connection. Connects to the external current-range
sense resistor on the amplifier side for PMU-A. See Figure 5.
RXAA
PMU-A Current-Range Sense-Resistor Connection. Connects to the external current-range
sense resistor on the DUT side for PMU-A. See Figure 5.
RXDA
PMU-A Compensation Capacitor Connection 2. Provides compensation for the PMU-A main
amplifier.
CC2A
4/MAX950
PMU-A Compensation Capacitor Connection 1. Provides compensation for the PMU-A main
amplifier.
CC1A
PMU-A Sense ꢁnput. A Kelvin connection to the DUT. Provides the feedback signal in FVMꢁ
mode and the measured signal in FꢁMV mode for PMU-A.
SENSEA
40
41
42
43
44
45
41
40
39
38
37
36
FORCEA PMU-A Driver Output. Forces a current or voltage to the DUT for PMU-A.
RAA
RAB
RAC
RAD
RAE
PMU-A Range A Resistor Connection
PMU-A Range B Resistor Connection
PMU-A Range C Resistor Connection
PMU-A Range D Resistor Connection
PMU-A Range E Resistor Connection
PMU-A Range-Setting-Resistor Common Connection. Connect to one end of all range-setting
resistors (RA_) for PMU-A. Also serves as the input to an external current range buffer for
PMU-A.
46
35
RACOM
PMU-A Window-Comparator Upper Threshold Voltage ꢁnput. Sets the upper voltage threshold
for the PMU-A window comparator.
49
50
32
31
THMAXA
THMꢁNA
PMU-A Window-Comparator Lower Threshold Voltage ꢁnput. Sets the lower voltage threshold
for the PMU-A window comparator.
51
52
30
29
CLHꢁA PMU-A Upper Clamp Voltage ꢁnput. Sets the upper clamp voltage level for PMU-A.
CLLOA PMU-A Lower Clamp Voltage ꢁnput. Sets the lower clamp voltage level for PMU-A.
ꢁnput Voltage 0 for PMU-A. Sets the forced current in Fꢁ mode or the forced voltage in FV
mode for PMU-A.
53
54
28
27
ꢁN0A
ꢁnput Voltage 1 for PMU-A. Sets the forced voltage in FV mode or the forced current in Fꢁ
mode for PMU-A.
ꢁN1A
PMU-A Measurement Output. Provides a voltage equal to the SENSE voltage in FꢁMV mode
MSRA and provides a voltage proportional to the DUT current in FVMꢁ mode for PMU-A. Force HI-ZA
low to place MSRA in a high-impedance state.
55
56
26
25
Offset Voltage ꢁnput. Sets an offset voltage for the internal current-sense amplifier for both
ꢁOS
PMU-A and -B.
1ꢀ ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
Pin Description (continued)
PIN
NµME
FUNCTION
MµX99ꢁꢀ
MµX9949
57
24
AGND Analog Ground
PMU-B Measurement Output. Provides a voltage equal to the SENSE voltage in FꢁMV mode
MSRB and provides a voltage proportional to the DUT current in FVMꢁ mode for PMU-B. Force HI-ZB
low to place MSRB in a high-impedance state.
58
23
ꢁnput Voltage 1 for PMU-B. Sets the forced voltage in FV mode or the forced current in Fꢁ
mode for PMU-B.
59
60
22
21
ꢁN1B
ꢁnput Voltage 0 for PMU-B. Sets the forced current in Fꢁ mode or the forced voltage in Fꢁ mode
for PMU-B.
ꢁN0B
61
62
20
19
CLLOB PMU-B Lower-Clamp Voltage ꢁnput. Sets the lower clamp voltage level for PMU-B.
CLHꢁB PMU-B Upper-Clamp Voltage ꢁnput. Sets the upper clamp voltage level for PMU-B.
PMU-B Window-Comparator Lower Threshold Voltage ꢁnput. Sets the lower voltage threshold
for the PMU-B window comparator.
63
64
18
17
THMꢁNB
PMU-B Window-Comparator Upper Threshold Voltage ꢁnput. Sets the upper voltage threshold
for the PMU-B window comparator.
THMAXB
Once the input data register fills, the data becomes avail-
Detailed Description
able at DOUT MSB first. This data output allows for
The MAX9949/MAX9950 force or measure voltages in
the -2V to +7V through -7V to +13V ranges, dependent
daisy-chaining multiple devices. Figures 1, 2, and 3
show the serial interface timing diagrams.
upon the supply voltage range (V
and V ).
EE
CC
However, the devices can handle supply voltages up to
+30V (V to V ) and a 20V DUT voltage swing at full
current. The MAX9949/MAX9950 PMU also force or
measure currents up to 25mA, with a lowest full-scale
range of 2ꢀA. Use an external buffer amplifier for cur-
rent ranges greater than 25mA.
Serial Port Speed
CC
EE
The serial port timing specifications are measured at a
logic supply voltage (V ) of +3.0V, ensuring operation
L
of the serial port at rated speed for V from +3.0V to
L
+5.5V.
The serial interface has two ranks. Each PMU has an
input register that loads from the serial port shift register.
Each PMU also has a PMU register that loads from the
input register. Data does not affect the PMU until it reach-
es the PMU register. This register configuration permits
loading of the PMU data into the input register at one time
and then latching the input register data into the PMU
register later, at which time the PMU function changes
accordingly. The register configuration also provides the
ability to change the state of the PMU asynchronously
with respect to the loading of that PMU’s data into the ser-
ial port. Thus, the PMU easily updates simultaneously with
other PMUs or other devices.
The MSR_ output presents a voltage proportional to the
measured voltage or current. Place MSR_ in a low-leak-
age, high-impedance state by pulling HI-Z_ low.
ꢁntegrated comparators with externally programmable
voltage thresholds provide “too low” (DUTL_) and “too
high” (DUTH_) voltage-monitoring outputs. Each com-
parator output features a selectable high-impedance
state. The devices feature separate FORCE_ and
SENSE_ connections and are fully protected against
short circuits. The FORCE_ output has two voltage
clamps, negative (CLLO_) and positive (CLHꢁ_), to limit
the voltage to externally provided levels. Two control
voltage inputs, selected independently of the PMU
mode, allow for greater flexibility.
Use the LOAD input to asynchronously load all input
registers into the PMU registers. ꢁf LOAD remains low
when data latches into an input register, the data also
transfers to the PMU register.
Serial Interface
The MAX9949/MAX9950 use a standard 3-wire
SPꢁ™/QSPꢁ™/MꢁCROWꢁRE™-compatible serial port.
SPꢁ and QSPꢁ are trademarks of Motorola, ꢁnc.
MꢁCROWꢁRE is a trademark of National Semiconductor, Corp.
______________________________________________________________________________________ 11
Dual Per-Pin Parametric Measurement Units
Functional Diagram
TO EXTERNAL CURRENT BOOSTER
FOR HIGHEST RANGE
RXA_
RXD_
C
RE
X
RD
EXTSEL_
RC
RB
C
CM
RA
V
CC
V
1
EE
R_COM
R_A R_B R_C R_D R_E
IN1_
IN0_
RANGE RESISTOR SELECT
FORCE_
4/MAX950
0
CL
ENABLE_
IN
MODE_
IOS
RS0_
RS1_
RS2_
CS
SCLK
LOAD
DIN
1
0
SERIAL
INTERFACE
10
TO OTHER PMU CHANNEL
F
MODE_
MODE_
DOUT
V
L
M
R
FS*
HI-Z_
HI-ZMEAS_
0
MSR_
1
SENSE_
THMAX_
DISABLE_
DUTH_
MAX9949
MAX9950
DUTL_
THMIN_
AGND
*RFS INTERNAL TO MAX9949D/MAX9950D ONLY
DGND
1± ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
CS
INPUT
REGISTER(S)
UPDATED
SCLK
DIN
D15
D14
Q15
D13
Q14
D12
Q13
D11
Q12
D10
Q11
D9
D8
Q9
D7
Q8
D6
Q7
D5
Q6
D4
Q5
D3
Q4
D2
Q3
D1
Q2
D0
Q1
DOUT
Q10
Q0
LAST BIT FROM
PREVIOUS WRITE
FIRST BIT FROM
PREVIOUS WRITE
LOAD
PMU REGISTERS
UPDATED
Figure 1. Serial Port Timing with Asynchronous Load
CS
INPUT AND PMU
REGISTER(S)
UPDATED
SCLK
DIN
D15
D14
Q15
D13
Q14
D12
Q13
D11
Q12
D10
Q11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Q1
DOUT
LOAD
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q0
LAST BIT FROM
PREVIOUS WRITE
FIRST BIT FROM
PREVIOUS WRITE
LOAD = 0
Figure 2. Serial Port Timing with Synchronous Load
______________________________________________________________________________________ 13
Dual Per-Pin Parametric Measurement Units
t
CH
SCLK
t
CL
t
CSSO
t
CSS1
t
CSH1
t
CSHO
CS
t
t
CSWH
DH
t
DS
4/MAX950
D15
D14
D13
D12
D11
D10
D1
D0
DIN
DOUT
D15last
D14last
D13last
D12last
D11last
DO
D10last
D1last
D0last
t
t
LDW
LOAD
Figure 3. Detailed Serial Port Timing Diagram
CS
SCLK
DIN
SHIFT REGISTER /16
INPUT REGISTER A
DOUT
6
10
CONTROL
DECODE
INPUT REGISTER B
10
10
PMU REGISTER A
PMU REGISTER B
LOAD
TO PMUA
TO PMUB
Figure 4. Dual PMU Serial Port Block Diagram
14 ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
Table 1. Bit Order
Table ±. µddress Bit
BIT
BIT NµME
(BIT 3) (BIT ±)
OPERµTION
µ±
µ1
15 (MSB)
ꢁN
MODE
14
F
0
0
1
0
1
0
Do not update any input register (NOP).
Only update input register A.
MODE
13
M
MODE
12
RS2
Only update input register B.
11
RS1
Update both input registers with the same
data.
1
1
10
RS0
9
CL
ENABLE
Table 3. Control Bit
8
HI-ZFORCE
HI-ZMSR
DISABLE
Don’t care
Don’t care
A2
7
(BIT 1) (BIT ꢀ)
OPERµTION
C±
C1
6
0
0
Data stays in input register.
5
Transfer PMU-A input register to PMU
register.
4
0
1
1
1
0
1
3
Transfer PMU-B input register to PMU
register.
2
1
A1
C2
Transfer both input registers to the PMU
registers.
0 (LSB)
C1
Bit Order
mits the latching of data into the PMU register at a later
The MAX9949/MAX9950 use the bit order, MSB first in
and first out, as shown in Table 1.
time by the LOAD input or subsequent command.
Table 4 summarizes the possible control and address
bit combinations.
PMU Control
Programming both PMUs with the same data requires a
16-bit word. Programming each PMU with separate
data requires two 16-bit words.
When asynchronously latching only one PMU’s data,
the input register of the other PMU maintains the same
data. Therefore, loading both PMU registers would
update the one PMU with new data while the other PMU
remains in its current state.
The address bits specify which input registers the shift
register loads. Table 2 describes the function of the
address bits.
Mode Selection
Four bits from the control word select between the vari-
ous modes of operation. ꢁNMODE selects between the
two input analog control voltages. FMODE selects
whether the PMU forces a voltage or a current. MMODE
selects whether the DUT current or DUT voltage is
directed to the MSR_ output. HI-ZFORCE places the
driver amplifier in a high-output impedance state. Table
5 describes the various force and measure modes of
operation.
Bits (C2, C1) specify how the data loads into the second
rank PMU registers. These two control bits serve a similar
function as the LOAD input. The specified actions occur
when CS goes high, whereas the LOAD input loads the
PMU register anytime. When either C2 or C1 is low, the
corresponding PMU register is transparent. Table 3
describes the function of the two control bits.
The NOP operation requires A1 = A2 = C1 = C2 = 0. ꢁn
this case, the data transfers through the shift register
without changing the state of the MAX9949/MAX9950.
Current-Range Selection
Three bits from the control word, RS0, RS1, RS2, con-
trol the full-scale current range for either Fꢁ (force cur-
C1 = C2 = 0 allows for data transfer from the shift regis-
ter to the input register without transferring data to the
PMU register (unless the LOAD input is low). This per-
______________________________________________________________________________________ 1ꢁ
Dual Per-Pin Parametric Measurement Units
Table 4. PMU Operation Using Control and µddress Bits
BIT (3:±)
BIT (1:ꢀ)
PMU-B OPERµTION
PMU-µ OPERµTION
µ±
µ1
0
C±
C1
0
0
0
0
0
0
0
0
1
1
0
NOP: data just passes through.
0
1
NOP.
Load PMU register A from input register A.
NOP.
0
0
Load PMU register B from input register B.
Load PMU register B from input register B.
NOP.
0
1
Load PMU register A from input register A.
Load input register A from shift register.
1
0
Load input register A and PMU register A
from shift register.
0
0
0
1
1
1
0
1
1
1
0
1
NOP.
Load PMU register B from input register B.
Load PMU register B from input register B.
Load input register A from shift register.
Load input register A and PMU register A
from shift register.
1
1
0
0
0
0
0
1
Load input register B from shift register.
Load input register B from shift register.
NOP.
Load PMU register A from input register A.
4/MAX950
Load input register B and PMU register B
from shift register.
1
0
1
0
NOP.
Load input register B and PMU register B
from shift register.
1
1
1
0
1
1
1
0
0
1
0
1
Load PMU register A from input register A.
Load input register A from shift register.
Load input register B from shift register.
Load input register A and PMU register A
from shift register.
Load input register B from shift register.
Load input register B and PMU register B
from shift register.
1
1
1
1
1
1
0
1
Load input register A from shift register.
Load input register B and PMU register B
from shift register.
Load input register A and PMU register A
from shift register.
Table ꢁ. PMU Force/Measure Mode Selection
(BIT 1ꢁ)
IN MODE
(BIT 14)
F MODE
(BIT 13)
M MODE
(BIT 8)
HI-ZFORCE
FORCE
OUTPUT
MEµSURE
OUTPUT
µCTIVE
INPUT
PMU MODE
0
1
0
1
0
1
0
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
0
0
FVMꢁ
FVMꢁ
FVMV
FVMV
FꢁMꢁ
Voltage
Voltage
Voltage
Voltage
Current
Current
Current
Current
ꢁ
ꢁ
V
V
V
V
V
V
V
V
DUT
DUT
ꢁN0
ꢁN1
ꢁN0
ꢁN1
ꢁN0
ꢁN1
ꢁN0
ꢁN1
V
V
DUT
DUT
DUT
DUT
ꢁ
ꢁ
FꢁMꢁ
FꢁMV
FꢁMV
V
V
DUT
DUT
FNMꢁ—Meaningless mode
Hꢁ-Z
X
X
FNMV
V
X
DUT
16 ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
Table 6. Current Range Selection
(BIT 1±) RS±
(BIT 11) RS1
(BIT 1ꢀ) RSꢀ
RµNGE
2ꢀA
NOMINµL RESISTOR VµLUE
R_E = 1MΩ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2ꢀA
R_E = 1MΩ
20ꢀA
R_D = 100kΩ
R_C = 10kΩ
R_B = 1kΩ
200ꢀA
2mA
25mA
External
25mA
R_A = 80Ω
—
R_A = 80Ω
Table 7. Clamp Enable
Table 8. MSR_ Output Truth Table
CL
MODE
ENµBLE
(BIT 7) HI-ZMSR
HI-Z_
MSR_ STµTE
Measure output enabled
High-Z
1
0
Clamps enabled
Clamps disabled
1
0
1
0
1
1
0
0
High-Z
rent) or Mꢁ (measure current). Table 6 describes the
full-scale current-range control.
High-Z
serial data word 16.5 clock cycles later. This allows for
daisy-chaining an additional device using DOUT and
the same clock.
Clamp Enable
The CL
bit enables the force-output voltage
ENABLE
clamps when high and disables the clamps when low.
Table 7 depicts the various clamp mode options.
“Quick Load” Using Chip Select
ꢁf CS goes low and then returns high without any clock
activity, the data from the input registers latch into the
PMU registers. This extra function is not standard for
SPꢁ/QSPꢁ/MꢁCROWꢁRE interfaces. The quick load mim-
ics the function of LOAD without forcing LOAD low.
Measure Output High-Impedance Control
The MSR_ output attains a low-leakage, high-imped-
ance state by using the HI-ZMSR control bit or the HI-Z_
input. The 2 bits are logically ORed together to control
the MSR_ output. The HI-Z_ input allows external multi-
plexing among several PMU MSR_ outputs without
using the serial interface. Table 8 explains the various
output modes for the MSR_ output.
Comparators
Two comparators configured as a window comparator
monitor the MSR_ output. THMAX_ and THMꢁN_ set the
high and low thresholds that determine the window.
Both outputs are open drain and share a single disable
control that places the outputs in a high-Z, low-leakage
state. Table 9 describes the comparator output states
of the MAX9949/MAX9950.
Digital Output (DOUT)
The digital output follows the last output of the serial
shift register and clocks out on the falling edge of the
input clock. DOUT provides the first bit of the incoming
Table 9. Comparator Truth Table
(BIT 6) DISABLE
CONDITION
DUTH_
DUTL_
0
1
1
1
1
X
High-Z
High-Z
V
V
V
V
> V
and V
0
1
1
0
1
1
0
0
MSR
THMAX
THMꢁN
> V
THMꢁN
> V
THMAX
THMAX
THMꢁN
MSR
and V
> V
THMꢁN
MSR
> V
> V
*
MSR
THMAX
*V
THMAX
> V
constitutes normal operation. This condition, however, has V
> V and does not cause any problems with
THMAX
THMꢁN
THMꢁN
the operation of the comparators.
______________________________________________________________________________________ 17
Dual Per-Pin Parametric Measurement Units
ing +4V to ꢁOS forces the voltage range that corre-
sponds to full-scale current from 0 to +8V.
Applications Information
The following equations determine the minimum and
ꢁn force-voltage (FV) mode, the output FORCE_ voltage
maximum currents for each current range correspond-
is directly proportional to the input control voltage. ꢁn
ing to the input voltage or measure voltage:
force-current (Fꢁ) mode, the current flowing out of the
FORCE_ output is proportional to the input control volt-
age. Positive current flows out of the PMU.
V
= V
= V
+ 4V
- 4V
MAXCURRENT
ꢁOS
ꢁOS
V
MꢁNCURRENT
Choose ꢁOS so the limits of the MSR_ output do not go
closer than 2.8V to either V or V . For example, with
ꢁn force-nothing (FN) mode, the FORCE_ output is high
impedance.
EE
CC
supplies of +10V and -5V, limit the MSR_ output to -2.2V
and +7.2V. Therefore, set ꢁOS between +1.8V and +3.2V.
The MSR_ output could clip if ꢁOS is not within this range.
Use these general equations for the limits on ꢁOS:
ꢁn measure-current (Mꢁ) mode, the voltage at the MSR_
output is directly proportional to the current exiting the
FORCE_ output. Positive current flows out of the PMU.
ꢁn measure-voltage (MV) mode, the voltage at the
MSR_ output is directly proportional to the voltage at
the SENSE_ input.
Minimum V
= V + 6.8V
EE
ꢁOS
Maximum V
= V
- 6.8V
ꢁOS
CC
Current Booster for Highest Current Range
An external buffer amplifier can be used to provide a
current range greater than the MAX9949/MAX9950
maximum output current (Figure 5). This function oper-
ates as follows.
Current-Sense-Amplifier Offset
Voltage Input
4/MAX950
ꢁOS is a buffered input to the current-sense amplifier.
The current-sense amplifier converts the input control
voltage (ꢁN0_ or ꢁN1_) to the forced DUT current (Fꢁ)
AND converts the sensed DUT current to the MSR_ out-
put voltage (Mꢁ). When ꢁOS equals zero relative to DUT-
GND (the GND voltage at the DUT, which the
level-setting DACs and the ADC are presumed to use
as a ground reference), the nominal voltage range that
corresponds to full-scale current is -4V to +4V. Any
voltage applied to the ꢁOS input adds directly to this
control input/measure output voltage range, i.e., apply-
A digital output decoded from the range select bits,
EXTSEL_, indicates when to activate the booster. The
R_COM output serves as an input to an external buffer
through a 50Ω current-limit series resistor. Each side of
the external current-sense resistor feeds back to RXA_
and RXD_. Ensure that the buffer circuit enters a high-Z
output state when not selected. Any leakage in the
buffer adds to the leakage of the PMU.
Voltage Clamps
The voltage clamps limit the FORCE_ output and oper-
ate over the entire specified current range. Set the
clamp voltages externally at CLHꢁ_ and CLLO_. The
voltage at the FORCE_ output triggers the clamps inde-
pendent of the voltage at the SENSE_ input. When
enabled, the clamps function in both Fꢁ and FV modes.
50Ω
R
EXTBOOST
FORCE_
Current Limit
The current-limiting circuitry on the FORCE_ output
ensures a well-behaved MSR_ output for currents
between the full current range and the current limits, i.e.,
for currents greater than the full-scale current, the MSR_
voltage is greater than +4V and for currents less than the
full-scale current, the MSR_ voltage is less than -4V.
R_COM
EXTSEL_
RXA_
RXD_
A
= +2
V
Independent Control of the Feedback
Switch and the Measure Switch
Two single-pole-double-throw (SPDT) switches deter-
mine the mode of operation of the PMU. One switch
INTERNAL TO MAX9949/MAX9950
Figure 5. External Current Boost
18 ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
IN1_
IN1_
R
R
SENSE
SENSE
FORCE_
SENSE_
FORCE_
DUT
DUT
A
= +2
A = +2
V
V
SENSE_
DUTGND
DUTGND
MSR_
MSR_
Figure 6. Force-Voltage/Measure-Current Functional Diagram
Figure 7. Force-Current/Measure-Voltage Functional Diagram
determines whether the sensed DUT current or DUT
voltage feeds back to the input (sensing), and thus
determines whether the MAX9949/MAX9950 force cur-
rent or voltage. The other switch determines whether the
MSR_ output senses the DUT current or DUT voltage.
input samples the voltage at the DUT and provides a
buffered result at the MSR_ output.
High-Z States
The FORCE_, MSR_, and comparator outputs feature
individual high-Z control that places them into a high-
impedance, low-leakage state. The high-Z state allows
busing of MSR_ and comparator outputs with other
PMU measure and comparator outputs. The FORCE_
output high-Z state allows for additional modes of oper-
ation as described in Table 5 and can eliminate the
need for a series relay in some applications.
ꢁndependent control of these switches and the
HI-ZFORCE state permits flexible modes of operation
beyond the traditional force-voltage/measure-current
(FVMꢁ) and force-current/measure-voltage (FꢁMV)
modes. The MAX9949/MAX9950 support the following
five modes:
• FVMꢁ
• FꢁMV
• FVMV
• FꢁMꢁ
The FORCE_, MSR_, and comparator outputs power up
in the high-Z state.
Input Source Selection and Gating
Either one of two input signals, ꢁN0_ or ꢁN1_, can control
both the forced voltage and the forced current. ꢁn this
case, the two input signals represent alternate forcing
values that can be selected with the serial interface.
Alternatively, each input signal can be dedicated to con-
trol a single forcing function (i.e., voltage or current).
• FNMV
Figure 6 shows the internal path structure for force-volt-
age/measure-current mode. ꢁn force-voltage/measure-
current mode, the current across the appropriate
external sense resistor (R_A to R_E) provides a voltage
to the MSR_ output. The SENSE_ input samples the
voltage at the DUT and feeds the buffered result back
to the negative input of the voltage amplifier. The volt-
age at MSR_ is proportional to the FORCE_ current in
accordance with the following formula:
Ground, DUT Ground, IOS
The MAX9949/MAX9950 utilize two local grounds,
AGND (analog ground) and DGND (digital ground).
Connect AGND and DGND together on the PC board.
ꢁn a typical ATE system, the PMU force voltage is rela-
tive to the DUT ground. ꢁn this case, reference the input
voltages ꢁN0_ and ꢁN1_ to the DUT ground. Similarly,
reference ꢁOS to the DUT ground. ꢁf it is not desired to
offset the current control and measure voltages, con-
nect ꢁOS to the DUT ground potential.
V _ = ꢁ
MSR
x R
x 2
SENSE
FORCE_
Figure 7 shows the internal path structure for the force-
current/measure-voltage mode. ꢁn force-current/mea-
sure-voltage mode, the appropriate external sense
resistor (R_A to R_E) provides a feedback voltage to
the inverting input of the voltage amplifier. The SENSE_
Reference the MSR_ output to the DUT ground.
______________________________________________________________________________________ 19
Dual Per-Pin Parametric Measurement Units
3) Variations in the power supplies—system implemen-
V
DUT
tation determines the variance
V
V
- 3.5V
- 5V
EE
EE
4) Variation of DUT ground vs. PMU ground—system
implementation determines the variance
Neglecting the effects of the third and fourth items,
Figure 8 demonstrates the force output capabilities
of the PMU.
I
DUT
Figure 8 indicates that, for zero DUT current, the
DUT voltage swings from (V
+ 3.5V) to (V
-
CC
EE
3.5V). For larger positive DUT currents, the positive
swing drops off linearly until it reaches (V - 5V) at
full current. Similarly, for larger negative DUT cur-
rents, the negative voltage swing drops off linearly
until it reaches (V + 5V) at full current.
EE
CC
V
+ 5V
EE
V
+ 3.5V
EE
I
I
MIN
MIN
Settling Times and Compensation
Capacitors
Figure 8. PMU Force Output Capability
The data in the Electrical Characteristics table reflects
the circuit shown in the block diagram that includes a
single compensation capacitor (Cx) effectively across all
4/MAX950
Short-Circuit Protection
The FORCE_ output and SENSE_ input can withstand a
short to any voltage between the supply rails.
the sense resistors. Placing individual capacitors, C
,
RA
C
, C , C , and C
directly across the sense
RB
RC
RD
RE
resistors, R_A, R_B, R_C, R_D, and R_E, independently
optimizes each range.
Mode and Range Change Transients
The MAX9949/MAX9950 feature make-before-break
switching to minimize glitches. The integrated voltage
clamps also reduce glitching on the output.
The combination of the capacitance across the sense
resistors (Cx or C , C , C , C , and C ) and the
RA
RB
RC
RD
RE
main amplifier compensation comparator, C , ensures
CM
DUT Voltage Swing vs. DUT Current and
Power-Supply Voltages
Several factors limit the actual DUT voltage that the
PMU delivers:
stability into the maximum expected load capacitance
while optimizing settling time.
Digital Inputs (SCLK, DIN, CS, LOAD)
The digital inputs incorporate hysteresis to mitigate
issues with noise, as well as provide for compatibility
with opto-isolators that can have slow edges.
1) The overhead required by the amplifiers and other
integrated circuitry—this is typically 3.5V from each
rail for no load current and 5V under full load
2) The voltage drop across the current-range select
resistor and internal circuitry in series with the sense
resistor—at full current, the combined voltage drop is
typically 2.75V
Chip Information
PROCESS: BiCMOS
±ꢀ ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
MAX9949 Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
+
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
V
V
EE
EE
V
CC
CC
3
RXAA
RXDA
CC2A
CC1A
SENSEA
FORCEA
RAA
RXAB
RXDB
CC2B
CC1B
SENSEB
FORCEB
RBA
4
5
6
7
8
MAX9949
9
10
11
12
13
RAB
RBB
RAC
RBC
RAD
RBD
RAE
RBE
RACOM
RBCOM 14
V
V
15
16
CC
CC
V
V
EE
EE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
______________________________________________________________________________________ ±1
Dual Per-Pin Parametric Measurement Units
MAX9950 Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
+
1
2
48
47
V
V
V
EE
EE
V
CC
CC
3
46 RACOM
RBCOM
RBE
4
45
44
43
42
41
40
39
38
37
36
35
34
33
RAE
5
RAD
RBD
6
RAC
RBC
7
RAB
RBB
4/MAX950
8
RAA
RBA
MAX9950
9
FORCEA
SENSEA
CC1A
CC2A
RXDA
RXAA
FORCEB
SENSEB
CC1B
CC2B
RXDB
RXAB
10
11
12
13
14
15
16
V
V
CC
CC
V
V
EE
EE
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PµCKµGE TYPE PµCKµGE CODE DOCUMENT NO.
64 TQFP-EPR
64 TQFP-EP
C64E-9R
C64E-6
±1-ꢀ16±
±1-ꢀꢀ84
±± ______________________________________________________________________________________
Dual Per-Pin Parametric Measurement Units
4/MAX950
Revision History
REVISION
NUMBER
REVISION
DµTE
PµGES
CHµNGED
DESCRIPTION
2
3/09
Corrected timing diagrams and changed to lead-free package.
1, 13, 14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ ±3
© 2009 Maxim ꢁntegrated Products
Maxim is a registered trademark of Maxim ꢁntegrated Products, ꢁnc.
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