MAX9951DCCB+TD [MAXIM]
Dual Per-Pin Parametric Measurement Units; 双每个引脚参数测量单元
| 型号： | MAX9951DCCB+TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Per-Pin Parametric Measurement Units |
| 文件： | 总24页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3267; Rev 6; 11/09
Dual Per-Pin Parametric
Measurement Units
1/MAX952
General Description
Features
o Force Voltage/Measure Current (FVMI)
o Force Current/Measure Voltage (FIMV)
o Force Voltage/Measure Voltage (FVMV)
o Force Current/Measure Current (FIMI)
o Force Nothing/Measure Voltage (FNMV)
The MAX9951/MAX9952 dual parametric measurement
units (PMUs) feature a small package size, wide force and
measurement range, and high accuracy, making the
devices ideal for automatic test equipment (ATE) and other
instrumentation that requires a PMU per pin or per site.
The MAX9951/MAX9952 force or measure voltages in the
-2V to +7V through -7V to +13V ranges, dependent upon
o Force Nothing/Measure Current (FNMI,
Range E Only)
the supply voltage (V
and V ). The devices handle
EE
CC
o Termination/Measure Current
o Termination/Measure Voltage
o Five Programmable Current Ranges
supply voltages of up to +30V (V
to V ) and a 20V
EE
CC
device-under-test (DUT) voltage swing at full current. The
MAX9951/MAX9952 also force or measure currents up to
±±6mA with a lowest full-scale range of ±2ꢀA. ꢁntegrated
support circuitry facilitates use of an external buffer ampli-
fier for current ranges greater than ±±6mA.
±±20µ
±±20µ
±±220µ
±±mµ
A voltage proportional to the measured output voltage
or current is provided at the MSR_ output. ꢁntegrated
comparators, with externally set voltage thresholds,
provide detection for both voltage and current levels.
The MSR_ and comparator outputs can be placed in a
high-impedance state. Separate FORCE and SENSE
connections are short-circuit protected for voltages
±ꢀ6mµ
o -±V to +7V Through -7V to +13V Input-Voltage
Range
o Force-Current/Measure-Current µdjustable-
Voltage Offset (IOS)
o Programmable Voltage Clamps at Force Output
from (V - 0.3V) to (V
+ 0.3V). The FORCE output
CC
also features a low-leakage, high-impedance state.
o Low-Leakage, High-Impedance Measure, and
EE
Force States
o 3-Wire Serial Interface
o Low ꢀmµ (max) Quiescent Current per PMU
ꢁntegrated voltage clamps limit the force output to lev-
els set externally. The force-current or the measure-cur-
rent voltage can be offset -0.2V to +6.6V (ꢁOS). This
feature allows for the centering of the control or mea-
sured signal within the external DAC or ADC range.
Ordering Information
PµRT
TEMP RµNGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PµCKµGE
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EPR*
±6 TQFP-EP**
±6 TQFP-EP**
±6 TQFP-EP**
±6 TQFP-EP**
±6 TQFP-EP**
±6 TQFP-EP**
±6 TQFP-EP**
±6 TQFP-EP**
MµX9951DCCB+D
MAX9951DCCB+TD
MAX9951DCCB-D
MAX9951DCCB-TD
MAX9951FCCB+
MAX9951FCCB+T
MAX9951FCCB-D
MAX9951FCCB-TD
MµX995±DCCB+
MAX9952DCCB+T
MAX9952DCCB-D
MAX9952DCCB-TD
MAX9952FCCB+
MAX9952FCCB+T
MAX9952FCCB-D
MAX9952FCCB-TD
The MAX9951D/MAX9952D feature an integrated 10kΩ
force-sense resistor between FORCE_ and SENSE_.
The MAX9951F/MAX9952F have no internal force-sense
resistor. These devices are available in a ±6-pin, 10mm
x 10mm, 0.5mm pitch TQFP package with an exposed
8mm x 8mm die pad on the top (MAX9951) or the bot-
tom (MAX9952) of the package for efficient heat
removal. The exposed pad is internally connected to
V
. The MAX9951/MAX9952 are specified over the
EE
commercial 0°C to +70°C temperature range.
Applications
Memory Testers
VLSꢁ Testers
System-on-a-Chip Testers
Structural Testers
+Denotes a lead(Pb)-free/RoHS-compliant package.
-Denotes a package containing lead(Pb).
Pin Configurations and Selector Guide appear at end of
data sheet.
D = Dry pack.
*EPR = Top side exposed pad.
**EP = Exposed pad.
T = Tape and reel.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-ꢀ±9-6ꢀ6±,
or visit Maxim’s website at www.maxim-ic.com.
Dual Per-Pin Parametric
Measurement Units
µBSOLUTE MµXIMUM RµTINGS
V
V
V
to AGND.......................................................................+20V
to AGND.........................................................................-15V
θ
θ
θ
θ
MAX9951_CCB (Note 1) ...........................................+8°C/W
MAX9951_CCB (Note 1) ...........................................+2°C/W
MAX9952_CCB (Note 1) .........................................+23°C/W
MAX9952_CCB (Note 1) ...........................................+2°C/W
JA
JC
JA
JC
CC
EE
CC
to V ...........................................................................+32V
EE
V to AGND............................................................................+±V
L
AGND to DGND.....................................................-0.5V to +0.5V
Digital ꢁnputs/Outputs ..................................-0.3V to (V + 0.3V)
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-±5°C to +150°C
Operating Temperature Range (commercial) ........0°C to +70°C
Lead Temperature (soldering 10s) ..................................+300°C
L
CC
All Other Pins to AGND....................(V - 0.3V) to (V
+ 0.3V)
EE
Continuous Power Dissipation (T = +70°C)
A
MAX9951_CCB (derate 125mW/°C above +70°C)...10,000mW
MAX9952_CCB (derate 63.5mW/°C above +70°C).....3678mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICµL CHµRµCTERISTICS
(V
= +12V, V = -7V, V = +3.3V, T = +25°C, unless otherwise noted. Specifications at T = T
and T = T
are guaranteed
MAX
CC
EE
L
A
A
MꢁN
A
1/MAX952
by design and characterization. Typical values are at T = +25°C, unless otherwise noted.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
FORCE VOLTµGE
Force ꢁnput Voltage
Range
V
V
,
ꢁN0_
ꢁN1_
V
V
+ 2.5
V
V
- 2.5
CC
V
V
EE
V
V
= +12V, V = -7V
-2
-7
+7
+13
- 2.5
CC
CC
EE
DUT current at full scale
DUT current = 0
Forced Voltage
V
= +18V, V = -12V
EE
DUT
+ 2.5
EE
CC
ꢁnput Bias Current
±1
ꢀA
Forced-Voltage Offset
V
V
-25
-1
+25
mV
FOS
Forced-Voltage-Offset
Temperature Coefficient
±100
0.005
±10
ꢀV/°C
%
Forced-Voltage Gain
Error
Nominal gain of +1
+1
FGE
Forced-Voltage-Gain
Temperature Coefficient
ppm/°C
%FSR
Forced-Voltage Linearity
Error
V
Gain and offset errors calibrated out (Notes 3, 6)
(Note 3)
-0.02
-1
+0.02
+1
FLER
MEµSURE CURRENT
Measure-Current Offset
ꢁ
ꢁ
%FSR
MOS
Measure-Current-Offset
Temperature Coefficient
±20
±20
ppm/°C
Measure-Current Gain
Error
(Note 5)
-1
+1
%
MGE
Measure-Current-Gain
Temperature Coefficient
ppm/°C
%FSR
Gain and offset errors calibrated out
(Notes 3, 6, ±)
Linearity Error
ꢁ
-0.02
+0.02
MLER
±
_______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
DC ELECTRICµL CHµRµCTERISTICS (continued)
(V
= +12V, V = -7V, V = +3.3V, T = +25°C, unless otherwise noted. Specifications at T = T
and T = T
are guaranteed
MAX
CC
EE
L
A
A
MꢁN
A
by design and characterization. Typical values are at T = +25°C, unless otherwise noted.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
+6
UNITS
Measure-Output-Voltage
Range Over Full-Current
Range
V
V
= V
-6
ꢁOS_
ꢁOS_
DUTGND
V
V
MSR
= 6V + V
0
+8
DUTGND
Current-Sense Amp
Offset-Voltage ꢁnput
V
Relative to V
-0.2
+6.6
V
ꢁOS
DUTGND
Rejection of Output-
Measure Error Due to
Common-Mode Sense
Voltage
CMVR
(Notes 5 and 7)
+0.001
+0.007 %FSR/V
+2
LER
Range E, R_E = 500kΩ
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
Range A, R_A = 15.±Ω
-2
-20
-200
-2
ꢀA
+20
+200
+2
Measure-Current Range
mA
-±6
+±6
FORCE CURRENT
ꢁnput Voltage Range for
Setting Forced Current
Over Full Range
V
V
= V
-6
0
+6
+8
ꢁOS_
ꢁOS_
DUTGND
V
V
ꢁN0_,
V
V
ꢁN1_
= 6V + V
DUTGND
Current-Sense Amp
Offset-Voltage ꢁnput
V
Relative to V
(Note 3)
-0.2
-1
+6.6
+1
ꢁOS
DUTGND
ꢁOS_ ꢁnput Bias Current
Forced-Current Offset
±1
ꢀA
%FSR
Forced-Current-Offset
Temperature Coefficient
±20
ppm/°C
%
Forced-Current Gain
Error
(Note 5)
-1
+1
Forced-Current-Gain
Temperature Coefficient
±20
ppm/°C
%FSR
Forced-Current Linearity
Error
Gain and offset errors calibrated out
(Notes 3, 6, ±)
ꢁ
-0.02
+0.02
FLER
Rejection of Output Error
Due to Common-Mode
Load Voltage
CMRꢁ
(Notes 5 and 7)
+0.001
+0.007 %FSR/V
+2
OER
Range E, R_E = 500kΩ
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
Range A, R_A = 15.±Ω
-2
-20
-200
-2
ꢀA
+20
+200
+2
Forced-Current Range
mA
-±6
+±6
_______________________________________________________________________________________
3
Dual Per-Pin Parametric
Measurement Units
DC ELECTRICµL CHµRµCTERISTICS (continued)
(V
= +12V, V = -7V, V = +3.3V, T = +25°C, unless otherwise noted. Specifications at T = T
and T = T
are guaranteed
MAX
CC
EE
L
A
A
MꢁN
A
by design and characterization. Typical values are at T = +25°C, unless otherwise noted.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
MEµSURE VOLTµGE
Measure-Voltage-Offset
V
-25
+25
mV
ꢀV/°C
%
MOS
Measure-Voltage-Offset
Temperature Coefficient
±100
±0.005
±10
Gain Error
V
Nominal gain of +1
-1
+1
MGER
Measure-Voltage-Gain
Temperature Coefficient
ppm/°C
Measure-Voltage
Linearity Error
Gain and offset errors calibrated out
(Notes 3, 6, ±)
V
-0.02
+0.02
%FSR
V
MLER
V
V
= +12V, V = -7V
EE
-2
-7
+7
CC
CC
Measure-Output-Voltage
Range Over Full DUT
Voltage
DUT current at full scale
DUT current = 0
V
= +18V, V = -12V
EE
+13
MSR
1/MAX952
V
+ 2.5
V
- 2.5
CC
EE
FORCE OUTPUT
Off-State Leakage
Current
-1
+1
nA
ꢁ
-92
+±5
8
-±5
+92
12
LꢁM-
Short-Circuit Current
Limit
mA
ꢁ
LꢁM+
Force-to-Sense Resistor
SENSE INPUT
R
D option only
F option only
10
kΩ
FS
ꢁnput Voltage Range
Leakage Current
V
V
+ 2.5
V
V
- 2.5
CC
V
EE
-1
+1
nA
COMPµRµTOR INPUTS
ꢁnput Voltage Range
Offset Voltage
+ 2.5
- 2.5
CC
V
EE
-25
+25
mV
ꢀA
ꢁnput Bias Current
VOLTµGE CLµMPS
±1
V
V
,
CLLO_
ꢁnput Control Voltage
V
+ 2.6
V
- 2.6
CC
V
EE
CLHꢁ_
Clamp Voltage
Accuracy
(Note 8)
-100
+100
mV
DIGITµL INPUTS
V = 5V
L
+3.5
+2.0
+1.7
ꢁnput High Voltage
(Note 9)
V
V
V
V = 3.3V
L
ꢁH
V = 2.5V
L
V = 5V or 3.3V
+0.8
+0.7
L
ꢁnput Low Voltage
(Note 9)
V
ꢁL
V = 2.5V
L
ꢁnput Current
ꢁ
±1
ꢀA
pF
ꢁN
ꢁnput Capacitance
C
3.0
ꢁN
6
_______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
DC ELECTRICµL CHµRµCTERISTICS (continued)
(V
= +12V, V = -7V, V = +3.3V, T = +25°C, unless otherwise noted. Specifications at T = T
and T = T
are guaranteed
MAX
CC
EE
L
A
A
MꢁN
A
by design and characterization. Typical values are at T = +25°C, unless otherwise noted.) (Note 2)
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
COMPµRµTOR OUTPUTS
Output High Voltage
V
V = +2.375V to +5.5V, R
= 1kΩ
V - 0.2
L
V
V
OH
L
PUP
Output Low Voltage
V
V = +2.375V to +5.5V, R
= 1kΩ
+0.6
OL
L
PUP
High-ꢁmpedance-State
Leakage Current
±1
ꢀA
pF
High-ꢁmpedance-State
Output Capacitance
±.0
DIGITµL OUTPUTS
ꢁ
= 1mA, V = +2.375V to +5.5V,
L
OUT
Output High Voltage
V
V - 0.25
L
V
V
OH
relative to DGND
ꢁ
= -1mA, V = +2.375V to +5.5V,
OUT
L
Output Low Voltage
V
+0.2
OL
relative to DGND
POWER SUPPLY
Positive Supply
Negative Supply
V
(Note 2)
(Note 2)
(Note 10)
+10
-15
+12
-7
+18
-5
V
CC
V
V
EE
Total Supply Voltage
Logic Supply
V
- V
+30
+5.5
10.0
10.0
1.2
V
CC
EE
V
+2.375
V
L
Positive Supply Current
Negative Supply Current
Logic Supply Current
Analog Ground Current
Digital Ground Current
ꢁ
No load, clamps enabled
mA
mA
mA
mA
mA
CC
ꢁ
No load, clamps enabled
EE
ꢁ
No load, all digital inputs at rails
No load, clamps enabled
L
ꢁ
0.9
1.6
20
AGND
DGND
ꢁ
No load, all digital inputs at rails
1MHz, measured at force output
±0Hz, measured at force output
Power-Supply Rejection
Ratio
PSRR
dB
85
_______________________________________________________________________________________
5
Dual Per-Pin Parametric
Measurement Units
µC ELECTRICµL CHµRµCTERISTICS
(V
= +12V, V = -7V, V = +3.3V, C
= 120pF, C = 100pF, T = +25°C, unless otherwise noted. Specifications at T = T
CC
EE
L
CM L A A MꢁN
and T = T
are guaranteed by design and characterization. Typical values are at T = +25°C, unless otherwise noted.) (Note 2)
A
MAX
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
FORCE VOLTµGE (Notes 10, 11)
Range E, R_E = 500kΩ
150
50
20
20
25
Range D, R_D = 50kΩ
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
Range A, R_A = 15.±Ω
Settling Time
30
ꢀs
FORCE VOLTµGE/MEµSURE CURRENT (Notes 11, 12)
Range E, R_E = 500kΩ
500
100
30
Range D, R_D = 50kΩ
Settling Time
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
Range A, R_A = 15.±Ω
55
ꢀs
ꢀs
25
1/MAX952
25
ꢁn addition to force-voltage and measure-current
settling times, range A to range B, R_A = 15.±Ω,
R_B = 500Ω
Range Change
Switching
12
FORCE CURRENT/MEµSURE VOLTµGE (Notes 11, 12)
Range E, R_E = 500kΩ
2500
350
30
Range D, R_D = 50kΩ
Settling Time
Range C, R_C = 5kΩ
Range B, R_B = 500Ω
Range A, R_A = 15.±Ω
±0
ꢀs
ꢀs
25
25
ꢁn addition to force-current and measure-voltage
settling times, range A to range B, R_A = 15.±Ω,
R_B = 500Ω
Range Change
Switching
12
SENSE INPUT TO MEµSURE OUTPUT PµTH
Propagation Delay
C
= 100pF
0.2
ꢀs
LMSR
MEµSURE OUTPUT
Maximum Stable Load
Capacitance
1000
pF
COMPµRµTORS (C
= 20pF, R
= 1kΩ)
PUP
LCOMP
50mV overdrive, 1V , measured from input-
P-P
threshold zero crossing to 50% of output voltage
(Note 13)
Propagation Delay
75
ns
Rise Time
Fall Time
20% to 80%
80% to 20%
±0
5
ns
ns
SERIµL PORT (V = +3.3V, C
= 10pF)
L
DOUT
Serial Clock Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
f
(Note 16)
20
MHz
ns
SCLK
t
12
12
CH
t
ns
CL
ꢀ
_______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
µC ELECTRICµL CHµRµCTERISTICS (continued)
(V
= +12V, V = -7V, V = +3.3V, C
= 120pF, C = 100pF, T = +25°C, unless otherwise noted. Specifications at T = T
CC
EE
L
CM L A A MꢁN
and T = T
are guaranteed by design and characterization. Typical values are at T = +25°C, unless otherwise noted.) (Note 2)
A
MAX
A
PµRµMETER
SYMBOL
CONDITIONS
MIN
TYP
MµX
UNITS
SCLK Fall to DOUT Valid
t
22
ns
DO
CS Low to SCLK High
Setup
t
10
22
0
ns
CSS0
CSH1
CSH0
SCLK High to CS High
Hold
t
t
ns
ns
ns
SCLK High to CS Low
Hold
CS High to SCLK High
Setup
t
5
CSS1
DꢁN to SCLK High Setup
DꢁN to SCLK High Hold
CS Pulse-Width High
CS Pulse-Width Low
t
10
0
ns
ns
ns
ns
ns
DS
t
(Note 13)
(Note 13)
DH
t
10
10
20
CSWH
t
CSWL
LOAD Pulse-Width Low
t
LDW
V
High to CS Low
DD
500
ns
(Power-Up)
Note ±: The device operates properly with different supply voltages with equally different voltage swings.
Note 3: ꢁnterpret errors expressed in terms of %FSR (percent of full-scale range) as a percentage of the end-point-to-end-point
range, i.e., for the ±±6mA range, the full-scale range = 128mA, and a 1% error = 1.28mA.
Note 6: Case must be maintained ±5°C for linearity specifications.
Note 5: Tested in range C.
Note ꢀ: Current linearity specifications are maintained to within 700mV of the clamp voltages when the clamps are enabled.
Note 7: Specified as the percent of full-scale range change at the output per volt change in the DUT voltage.
Note 8:
V
and V
should differ by at least 700mV.
CLLO_
CLHꢁ_
Note 9: The digital interface accepts +5V, +3.3V, and +2.5V CMOS logic levels. The voltage at V adjusts the threshold.
L
Note 12: Guaranteed by design.
Note 11: Settling times are to 0.1% of FSR. Cx_ = ±0pF.
Note 1±: All settling times are specified using a single compensation capacitor (Cx_) across all current-sense resistors. Use an indi-
vidual capacitor across each sense resistor for better performance across all current ranges, particularly the lower ranges.
Note 13: The propagation delay time is only guaranteed over the force-voltage output range. Propagation delay is measured by
holding V
steady and transitioning THMAX_ or THMꢁN_.
SENSE_
Note 16: Maximum serial clock frequency may diminish at V < +3.3V.
L
_______________________________________________________________________________________
7
Dual Per-Pin Parametric
Measurement Units
Typical Operating Characteristics
(V
= +12V, V = -7V, C = 100pF, C
= 120pF, C
L
= ±0pF, R to +2.5V, range A: R_A = 15.±Ω, R = 70.3Ω; range B: R_B =
CC
EE
L
CM_
CX_ L L
500Ω, R = 2.25kΩ; range C: R_C = 5kΩ, R = 22.5kΩ; range D: R_D = 50kΩ, R = 225kΩ; range E: R_E = 500kΩ, R = 2.25MΩ, T
L
L
L
A
= +25°C.)
TRANSIENT RESPONSE
FVMI MODE, RANGES A, B, C
TRANSIENT RESPONSE
FVMI MODE, RANGE D
TRANSIENT RESPONSE
FVMI MODE, RANGE E
MAX9551 toc01
MAX9551 toc02
MAX9551 toc03
IN_
IN_
IN_
5V/div
5V/div
5V/div
0
0
0
FORCE_
5V/div
FORCE_
5V/div
FORCE_
5V/div
0
0
0
1/MAX952
20μs/div
100μs/div
1ms/div
TRANSIENT RESPONSE
FVMV MODE, RANGE C
TRANSIENT RESPONSE
FIMI MODE, RANGES A, B, C
TRANSIENT RESPONSE
FIMI MODE, RANGE D
MAX9551 toc04
MAX9551 toc05
MAX9551 toc06
IN_
5V/div
IN_
5V/div
IN_
5V/div
0
0
0
FORCE_
5V/div
FORCE_
5V/div
FORCE_
5V/div
0
0
0
20μs/div
20μs/div
100μs/div
TRANSIENT RESPONSE
FIMI MODE, RANGE E
TRANSIENT RESPONSE
FIMI MODE, RANGE C
IOS vs. POWER SUPPLIES
MAX9551 toc07
MAX9551 toc08
MAX9951 toc09
20
15
10
5
IN_
5V/div
IN_
5V/div
V
CC
11.2
4.4
0
0
IOS (MAX)
IOS (MIN)
FORCE_
5V/div
FORCE_
5V/div
3.2
1.8
0
0
0
-0.2
-7
-5
V
EE
-10
-15
2ms/div
40μs/div
8
_______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Pin Description
PIN
NµME
FUNCTION
MµX9951 MµX995±
PMU-A Sense ꢁnput. A Kelvin connection to the DUT. Provides the feedback signal in FVMꢁ
mode and the measured signal in FꢁMV mode for PMU-A.
1
2
3
68
67
6±
SENSEA
FORCEA PMU-A Driver Output. Forces a current or voltage to the DUT for PMU-A.
PMU-A Compensation Capacitor Connection. Provides compensation for the PMU-A main
amplifier. Connect a 120pF capacitor from CCA to CCOMA.
CCA
5, 15,
36, 66
5, 15,
36, 66
V
Negative Analog-Supply ꢁnput
Positive Analog-Supply ꢁnput
EE
6, 16,
35, 65
6, 16,
35, 65
V
CC
±
7
63
62
61
60
39
38
37
CCOMA Common Connection of CMA and CXA for PMU-A
RAAS
RAA
RAB
RAC
RAD
RAE
PMU-A Range Setting Resistor-Sense Connection
PMU-A Range A Setting Resistor Connection
PMU-A Range B Setting Resistor Connection
PMU-A Range C Setting Resistor Connection
PMU-A Range D Setting Resistor Connection
PMU-A Range E Setting Resistor Connection
8
9
10
11
12
PMU-A Current-Range Sense-Resistor Connection. Connects to the external current range
sense resistor for PMU-A.
13
1±
17
3±
33
32
RAX
EXTSELA PMU-A External Current-Range Selector. Selects the external current range for PMU-A.
PMU-A Window Comparator Lower Comparator Output. A high output indicates that the sensed
DUTLA
voltage at the window comparator is above V
. DUTLA is an open-drain output.
THMꢁNA
PMU-A Window Comparator Higher Comparator Output. A high output indicates that the
sensed voltage at the window comparator is below V . DUTHA is an open-drain output.
18
19
20
31
30
29
DUTHA
HI-ZA
THMAXA
MSRA Tri-State Control ꢁnput. A logic-low places MSRA in a high-impedance state.
ꢁnput Select PMU-A. ꢁNSELA is a logic input that selects between ꢁN0A and ꢁN1A. Force
ꢁNSELA low to select ꢁN0A. ꢁNSELA is OR’ed with control register bit ꢁNMODEA.
ꢁNSELA
21
22
23
26
25
28
27
2±
25
26
TEMP
Temperature Output. V
Digital Ground
= 10mV/°C. T (°C) = (100)V
- 273.
TEMP
DꢁE
TEMP
DGND
V
Logic-Supply Voltage ꢁnput. The voltage applied at V sets the upper logic-voltage level.
L
L
DOUT
DꢁN
Serial-Data Output. A standard SPꢁ™-compatible output. Data appears at DOUT MSB first.
Serial-Data ꢁnput. Load data into DꢁN MSB first.
Serial-Port Load ꢁnput. A logic-low asynchronously loads data from the input registers into the
PMU registers.
2±
23
LOAD
SPꢁ is a trademark of Motorola, ꢁnc.
_______________________________________________________________________________________
9
Dual Per-Pin Parametric
Measurement Units
Pin Description (continued)
PIN
NµME
FUNCTION
MµX9951 MµX995±
27
28
22
21
SCLK
Serial-Clock ꢁnput. SCLK accepts external clock frequencies up to 20MHz.
CS
Chip-Select ꢁnput. Force CS low to enable the serial interface.
ꢁnput Select PMU-B. ꢁNSELB is a logic input that selects between ꢁN0B and ꢁN1B. Force
ꢁNSELB low to select ꢁN0B. ꢁNSELB is OR’ed with control register bit ꢁNMODEB.
29
30
31
20
19
18
ꢁNSELB
HI-ZB
MSRB Tri-State Control ꢁnput. A logic-low places MSRB in a high-impedance state.
PMU-B Window Comparator Higher Comparator Output. A high output indicates that the
DUTHB
sensed voltage at the window comparator is below V
. DUTHB is an open-drain output.
THMAXB
PMU-B Window Comparator Lower Comparator Output. A high output indicates that the sensed
voltage at the window comparator is above V . DUTLB is an open-drain output.
32
33
3±
17
1±
13
DUTLB
THMꢁNB
EXTSELB PMU-B External Current-Range Selector. Selects the external current range for PMU-B.
PMU-B Current-Range Sense-Resistor Connection. Connects to the external current-range
sense resistor for PMU-B.
RBX
1/MAX952
37
38
39
60
61
62
63
12
11
10
9
RBE
RBD
RBC
RBB
RBA
RBAS
PMU-B Range E Setting Resistor Connection
PMU-B Range D Setting Resistor Connection
PMU-B Range C Setting Resistor Connection
PMU-B Range B Setting Resistor Connection
PMU-B Range A Setting Resistor Connection
PMU-B Range A Setting Resistor-Sense Connection
8
7
±
CCOMB Common Connection of CMB and CXB for PMU-B
PMU-B Compensation Capacitor Connection. Provides compensation for the PMU-B main
amplifier. Connect a 120pF capacitor from CCB to CCOMB.
6±
67
68
3
2
1
CCB
FORCEB PMU-B Driver Output. Forces a current or voltage to the DUT for PMU-B.
PMU-B Sense ꢁnput. A Kelvin connection to the DUT. Provides the feedback signal in FVMꢁ
mode and the measured signal in FꢁMV mode for PMU-B.
SENSEB
PMU-B Window Comparator Upper Threshold Voltage ꢁnput. Sets the upper voltage threshold
for the PMU-B window comparator.
69
50
±6
±3
THMAXB
PMU-B Window Comparator Lower Threshold Voltage ꢁnput. Sets the lower voltage threshold for
the PMU-B window comparator.
THMꢁNB
51
52
±2
±1
CLHꢁB
PMU-B Upper-Clamp Voltage ꢁnput. Sets the upper-clamp voltage level.
PMU-B Lower-Clamp Voltage ꢁnput. Sets the lower-clamp voltage level.
CLLOB
Force-Threshold Current ꢁnput for PMU-B. Sets the forced voltage in FV mode or the forced
current in Fꢁ mode.
53
56
±0
59
ꢁN0B
ꢁN1B
Force-Threshold Voltage ꢁnput for PMU-B. Sets the forced voltage in FV mode or the forced
current in Fꢁ mode
12 ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Pin Description (continued)
PIN
NµME
FUNCTION
MµX9951 MµX995±
PMU-B Measurement Output. Provides a voltage equal to the SENSE voltage in FꢁMV mode,
and provides a voltage proportional to the DUT current in FVMꢁ mode for PMU-B. Force HI-ZB
low to place MSRB in a high-impedance state.
55
58
MSRB
5±
57
57
5±
AGND
ꢁOS
Analog Ground
Offset-Voltage ꢁnput. Sets an offset voltage for the internal current-sense amplifiers of both
channels.
PMU-A Measurement Output. Provides a voltage equal to the SENSE voltage in FꢁMV mode,
and provides a voltage proportional to the DUT current in FVMꢁ mode for PMU-A. Force HI-ZA
low to place MSRA in a high-impedance state.
58
55
MSRA
Force-Threshold Voltage ꢁnput for PMU-A. Sets the forced voltage in FV mode or the forced
current in Fꢁ mode.
59
±0
56
53
ꢁN1A
ꢁN0A
Force-Threshold Current ꢁnput for PMU-A. Sets the forced voltage in FV mode or the forced
current in Fꢁ mode.
±1
±2
52
51
CLLOA
CLHꢁA
PMU-A Lower-Clamp Voltage ꢁnput. Sets the lower-clamp voltage level.
PMU-A Upper-Clamp Voltage ꢁnput. Sets the upper-clamp voltage level.
PMU-A Window Comparator Lower Threshold Voltage ꢁnput. Sets the lower voltage threshold for
the PMU-A window comparator.
±3
±6
—
50
69
—
THMꢁNA
THMAXA
EP
PMU-A Window Comparator Upper Threshold Voltage ꢁnput. Sets the upper voltage threshold
for the PMU-A window comparator.
Exposed Pad. ꢁnternally biased to V . Connect to a large ground plane or heatsink to
EE
maximize thermal performance. Not intended as an electrical connection point.
______________________________________________________________________________________ 11
Dual Per-Pin Parametric
Measurement Units
Functional Diagram
TO EXTERNAL CURRENT BOOSTER
FOR HIGHEST RANGE
C
X_
RE
RD
RC
RB
RA
CM_
V
CC
V
EE
V
L
CC_
CCOM_
EXTSEL_
R_X
R_E R_D R_C R_B R_A
R_AS**
1
IN1_
IN0_
0
RANGE RESISTOR SELECT
FORCE_
1/MAX952
OR
GATE
INSEL_
1.5MΩ
DGND
CLLO_
CLHI_
IOS
1
0
CS
SCLK
LOAD
DIN
SERIAL
INTERFACE
F
MODE_
M
MODE_
DOUT
R
FS*
V
L
10
TO OTHER PMU CHANNEL
1.5MΩ
1
0
HI-Z_
MSR_
SENSE_
THMAX_
DUTH_
DUTL_
MAX9951
MAX9952
THMIN_
AGND
DGND
*R INTERNAL TO MAX9951D/MAX9952D ONLY
FS
**CONNECT R_AS AS CLOSE TO RESISTOR “RA” AS POSSIBLE
1± ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Detailed Description
Serial Interface
The MAX9951/MAX9952 force or measure voltages in
the -2V to +7V through -7V to +13V ranges, dependent
The MAX9951/MAX9952 use a standard 3-wire
SPꢁ/QSPꢁ™/MꢁCROWꢁRE™-compatible serial port.
Once the input data register fills, the data becomes
available at DOUT MSB first. This data output allows for
daisy-chaining multiple devices. Figures 1, 2, and 3
show the serial interface timing diagrams.
upon the supply voltage range (V
and V ). These
EE
CC
devices also force or measure currents up to ±±6mA,
with a lowest full-scale range of ±2ꢀA. Use an external
buffer amplifier for current ranges greater than ±±6mA.
MSR_ presents a voltage proportional to the measured
voltage or current. Place MSR_ in a low-leakage, high-
impedance state by forcing HI-Z_ low. ꢁntegrated com-
parators with externally programmable voltage
thresholds provide “too low” (DUTL_) and “too high”
(DUTH_) voltage-monitoring outputs. Each comparator
output features a selectable high-impedance state. The
devices feature separate FORCE_ and SENSE_ con-
nections and are fully protected against short circuits.
The FORCE_ output has two voltage clamps, negative
(CLLO_) and positive (CLHꢁ_), to limit the voltage to
externally provided levels. Two control-voltage inputs,
selected independently of the PMU mode, allow for
greater flexibility.
Serial Port Operation
The serial interface has two ranks (Figure 6). Each PMU
has an input register that loads from the serial port shift
register. Each PMU also has a PMU register that loads
from the input register. Data does not affect the PMU
until it reaches the PMU register. This register configura-
tion permits loading of the PMU data into the input regis-
ter at one time and then latching the input register data
into the PMU register later, at which time the PMU func-
tion changes accordingly. The register configuration also
provides the ability to change the state of the PMU asyn-
chronously, with respect to the loading of that PMU’s
data into the serial port. Thus, the PMU easily updates
simultaneously with other PMUs or other devices.
CS
INPUT
REGISTER(S)
UPDATED
SCLK
DIN
D15
D14
Q15
D13
Q14
D12
Q13
D11
Q12
D10
Q11
D9
D8
Q9
D7
Q8
D6
Q7
D5
Q6
D4
Q5
D3
Q4
D2
Q3
D1
Q2
D0
Q1
DOUT
Q10
Q0
LAST BIT FROM
PREVIOUS WRITE
FIRST BIT FROM
PREVIOUS WRITE
LOAD
PMU REGISTERS
UPDATED
Figure 1. Serial Port Timing with Asynchronous Load
QSPꢁ is a trademark of Motorola, ꢁnc.
MꢁCROWꢁRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________ 13
Dual Per-Pin Parametric
Measurement Units
CS
INPUT AND PMU
REGISTER(S)
UPDATED
SCLK
DIN
D15
D14
Q15
D13
Q14
D12
Q13
D11
Q12
D10
Q11
D9
D8
Q9
D7
Q8
D6
Q7
D5
Q6
D4
Q5
D3
Q4
D2
Q3
D1
Q2
D0
Q1
DOUT
Q10
Q0
LAST BIT FROM
PREVIOUS WRITE
FIRST BIT FROM
PREVIOUS WRITE
1/MAX952
LOAD
LOAD = 0
Figure 2. Serial Port Timing with Synchronous Load
t
CH
SCLK
t
CL
t
CSSO
t
CSS1
t
CSH1
t
CSHO
CS
t
t
CSWH
DH
t
DS
D15
D14
D13
D12
D11
D10
D1
D0
DIN
DOUT
D15last
D14last
D13last
D12last
D11last
DO
D10last
D1last
D0last
t
t
LDW
LOAD
Figure 3. Detailed Serial Port Timing Diagram
16 ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Table 1. Bit µssignments
BIT
BIT NµME
ꢁNMODE
FMODE
MMODE
RS2
0 (LSB)
CS
SCLK
DIN
SHIFT REGISTER /16
INPUT REGISTER A
DOUT
1
2
4
12
3
6
RS1
CONTROL
DECODE
5
RS0
INPUT REGISTER B
12
±
CLENABLE
HI-ZFORCE
HI-ZMSR
DISABLE
B2
12
7
8
PMU REGISTER A
PMU REGISTER B
LOAD
9
10
12
12
11
B1
TO PMUA
TO PMUB
12
A2
13
A1
16
C2
Figure 6. Dual PMU Serial Port Block Diagram
15 (MSB)
C1
Use LOAD to asynchronously load all input registers
into the PMU registers. ꢁf LOAD remains low when data
latches into an input register, the data also transfers to
the PMU register.
Table ±. µddress Bit
(BIT 1±) (BIT 13)
OPERµTION
Bit Order
µ±
µ1
The MAX9951/MAX9952 use the bit order, MSB first in
and first out. Table 1 shows bit asignments.
0
0
1
0
1
0
Do not update any input register (NOP).
Only update input register A.
Only update input register B.
PMU Control
Programming both PMUs with the same data requires a
1±-bit word. Programming each PMU with separate
data requires two 1±-bit words.
Update both input registers with the same
data.
1
1
The address bits specify which input registers the shift-
register loads. Table 2 describes the function of the
address bits.
Table 3. Control Bit
(BIT 16) (BIT 15)
Bits C1 and C2 specify how the data loads into the sec-
ond rank PMU registers. These 2 control bits serve a
similar function as the LOAD input. The specified
actions occur when CS goes high, whereas the LOAD
input loads the PMU register at anytime. When either
C1 or C2 is low, the corresponding PMU register is
transparent. Table 3 describes the function of the 2
control bits.
OPERµTION
C±
C1
0
0
Data stays in input register.
Transfer PMU-A input register to PMU
register.
0
1
1
1
0
1
Transfer PMU-B input register to PMU
register.
The NOP operation requires A1 = A2 = C1 = C2 = 0. ꢁn
this case, the data transfers through the shift register
without changing the state of the device.
Transfer both input registers to the PMU
registers.
______________________________________________________________________________________ 15
Dual Per-Pin Parametric
Measurement Units
C1 = C2 = 0 allows for data transfer from the shift regis-
ter to the input register without transferring data to the
PMU register (unless LOAD is low). This permits the
latching of data into the PMU register at a later time by
LOAD or subsequent command. Table 6 summarizes
the possible control and address bit combinations.
When asynchronously latching only one PMU’s data,
the input register of the other PMU maintains the same
data. Therefore, loading both PMU registers would
update the one PMU with new data while the other PMU
remains in its current state.
Mode Selection
Four bits from the control word select between the vari-
ous force-measure modes of operation. ꢁNMODE
selects between the two input analog control voltages.
FMODE selects whether the PMU forces a voltage or a
current. MMODE selects whether the DUT current or
DUT voltage is directed to MSR_. HI-ZFORCE places
the driver amplifier in a high-output-impedance state.
Table 5 describes the various force and measure
modes of operation.
Table 6. PMU Operation Using Control and µddress Bits
BIT (1±:13)
BIT (16:15)
PMU-µ OPERµTION
PMU-B OPERµTION
µ±
0
µ1
0
C±
0
C1
0
NOP: data just passes through
1/MAX952
0
0
0
1
Transfer PMU register A from input register A.
NOP.
NOP.
0
0
1
0
Transfer PMU register B from input register B.
Transfer PMU register B from input register B.
NOP.
0
0
1
1
Transfer PMU register A from input register A.
Transfer input register A from shift register.
0
1
0
0
Transfer input register A and PMU register A
from shift register.
0
0
0
1
1
1
0
1
1
1
0
1
NOP.
Transfer input register A from shift register.
Transfer PMU register B from input register B.
Transfer PMU register B from input register B.
Transfer input register A and PMU register A
from shift register.
1
1
0
0
0
0
0
1
NOP.
Transfer input register B from shift register.
Transfer input register B from shift register.
Transfer PMU register A from input register A.
Transfer input register B and PMU register B
from shift register.
1
0
1
0
NOP.
Transfer input register B and PMU register B
from shift register.
1
1
1
0
1
1
1
0
0
1
0
1
Transfer PMU register A from input register A.
Transfer input register A from shift register.
Transfer input register B from shift register.
Transfer input register A and PMU register A
from shift register.
Transfer input register B from shift register.
Transfer input register B and PMU register B
from shift register.
1
1
1
1
1
1
0
1
Transfer input register A from shift register.
Transfer input register A and PMU register A
from shift register.
Transfer input register B and PMU register B
from shift register.
1ꢀ ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Table 5. PMU Force-Measure Mode Selection
(BIT 2)
IN MODE*
(BIT 1)
F MODE
(BIT ±)
M MODE
(BIT 7)
HI-ZFORCE
FORCE
OUTPUT
MEµSURE
OUTPUT
µCTIVE
INPUT
PMU MODE
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
FVMꢁ
FVMꢁ
FVMV
FVMV
FꢁMꢁ
Voltage
Voltage
Voltage
Voltage
Current
Current
Current
Current
ꢁ
ꢁ
V
V
V
V
V
V
V
V
DUT
DUT
ꢁN0
ꢁN1
ꢁN0
ꢁN1
ꢁN0
ꢁN1
ꢁN0
ꢁN1
V
V
DUT
DUT
DUT
DUT
ꢁ
ꢁ
FꢁMꢁ
FꢁMV
FꢁMV
V
V
DUT
DUT
FNMꢁ
(range E only)
High-
ꢁmpedance
X
X
0
0
1
0
0
0
ꢁ
X
X
DUT
High-
ꢁmpedance
FNMV
V
DUT
0
1
0
1
1
1
1
1
0
0
1
1
0
0
0
0
Termination
Termination
Termination
Termination
Voltage
Voltage
Voltage
Voltage
V
V
V
V
V
V
DUT
DUT
DUT
DUT
ꢁN0
ꢁN1
ꢁN0
ꢁN1
ꢁ
ꢁ
*ꢁNSEL = 0
Table ꢀ. Current-Range Selection
Clamp Enable
The CLENABLE bit enables the force-output-voltage
clamps when high and disables the clamps when low.
There is hysteresis equal to approximately 5% of the
current range for clamp when serial bit 11 is 1. For bit
11 = 0, no hysteresis, but clamp voltage is less accurate.
NOMINµL
RµNGE RESISTOR VµLUE
(Ω)
(BIT 3)
RS±
(BIT 6)
RS1
(BIT 5)
RS2
0
0
0
1
1
1
0
1
1
0
X
1
X
0
1
0
1
0
±2ꢀA
±20ꢀA
±200ꢀA
±2mA
R_E = 500k
R_D = 50k
R_C = 5k
R_B = 500
R_A = 15.±
—
Measure Output High-Impedance Control
MSR_ attains a low-leakage, high-impedance state by
using the HI-ZMSR control bit, or the HI-Z_ input. HI-Z_ is
internally pulled up to V with a 1.5MΩ resistor. The 2
L
±±6mA
External
bits are logically ANDed together to control the MSR_
output. HI-Z_ allows external multiplexing among several
PMU MSR_ outputs without using the serial interface.
Table 7 explains the various output modes for the MSR_
output.
Table 7. MSR_ Output Truth Table
(BIT 8) HI-ZMSR
HI-Z_
MSR_
Digital Output (DOUT)
The digital output follows the last output of the serial-
shift register and clocks out on the falling edge of
SCLK. DOUT serially shifts the first bit of the incoming
serial data word 1±.5 clock cycles later. This allows for
daisy-chaining additional devices using DOUT and the
same clock.
1
0
1
0
1
1
0
0
Measure output enabled
High impedance
High impedance
High impedance
Current-Range Selection
Three bits from the control word, RS0, RS1, and RS2,
control the full-scale current range for either Fꢁ (force
current) or Mꢁ (measure current). Table ± describes the
full-scale current-range control.
______________________________________________________________________________________ 17
Dual Per-Pin Parametric
Measurement Units
and convert the sensed DUT current to the MSR_ out-
put voltage (Mꢁ). When ꢁOS equals zero relative to
DUTGND (the GND voltage at the DUT, which the level-
setting DACs and the ADC are presumed to use as a
ground reference), the nominal voltage range that cor-
responds to ±full-scale current is -6V to +6V. Any volt-
age applied to ꢁOS adds directly to this control
input/measure output voltage range, i.e., applying +6V
to ꢁOS forces the voltage range that corresponds to
±full-scale current from 0 to +8V.
“Quick Load” Using Chip Select
ꢁf CS goes low and then returns high without any clock
activity, the data from the input registers latch into the
PMU registers. This extra function is not standard for
SPꢁ/QSPꢁ/MꢁCROWꢁRE interfaces. The quick load mim-
ics the function of LOAD without forcing LOAD low.
Comparators
Two comparators configured as a window comparator
monitor MSR_. THMAX_ and THMꢁN_ set the high and
low thresholds that determine the window. Both out-
puts are open drain and share a single disable control
that places the outputs in a high-impedance, low-leak-
age state. Table 8 describes the comparator output
states of the MAX9951/MAX9952.
The following equations determine the minimum and
maximum currents for each current range correspond-
ing to the input voltage or measure voltage:
V
= V
= V
+ 6V
- 6V
MAXCURRENT
ꢁOS
ꢁOS
V
MꢁNCURRENT
Applications Information
Choose ꢁOS so the limits of MSR_ do not go closer than
2.8V to either V or V . For example, with supplies of
ꢁn force-voltage (FV) mode, the voltage at FORCE_ is
directly proportional to the input control voltage. ꢁn
force-current (Fꢁ) mode, the current flowing out of
FORCE_ is proportional to the input control voltage.
Positive current flows out of the PMU.
EE
CC
5
+10V and -5V, limit the MSR_ output to -2.2V and
+7.2V. Therefore, set ꢁOS between +1.8V and +3.2V.
MSR_ could clip if ꢁOS is not within this range. Use
these general equations for the limits on ꢁOS:
ꢁn force-nothing (FN) mode, FORCE_ is high impedance.
Minimum V
= V + ±.8V
EE
ꢁOS
ꢁn measure-current (Mꢁ) mode, the voltage at MSR_ is
directly proportional to the current exiting FORCE_.
Positive current flows out of the PMU.
Maximum V
= V
- ±.8V
ꢁOS
CC
Current Booster for Highest Current Range
An external buffer amplifier can be used to provide a
current range greater than the MAX9951/MAX9952
maximum ±±6mA output current (Figure 5). This func-
tion operates as follows:
ꢁn measure-voltage (MV) mode, the voltage at MSR_ is
directly proportional to the voltage at SENSE_.
Current-Sense-Amplifier
Offset-Voltage Input
ꢁOS is a buffered input to the current-sense amplifiers.
The current-sense amplifiers convert the input control
voltage (ꢁN0_ or ꢁN1_) to the forced DUT current (Fꢁ),
R
EXT
RA
RE
Table 8. Comparator Truth Table
CCOM_
EXTSEL_
(BIT 9)
DISABLE
CONDITION
DUTH
DUTL
50Ω
VIN_
A
E
0
1
1
1
1
X
High-Z
High-Z
DUT
FORCE_
V
> V
and V
0
1
1
0
1
1
0
0
MSR
THMAX
THMꢁN
> V
MSR THMꢁN
MAIN AMP
V
> V
THMAX
X
A
E
V
and V
> V
> V
THMAX
THMꢁN
> V
MSR
*
V
MAX9951
MAX9952
THMꢁN
MSR
THMAX
x4
CURRENT-
SENSE AMP
*V
> V
constitutes normal operation. This condition,
THMAX
however, has V
THMꢁN
> V
and does not cause any prob-
THMꢁN
THMAX
lems with the operation of the comparators.
MSR_
SENSE_
PMU
Figure 5. External Current Boost
18 ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
A digital output decoded from the range select bits,
EXTSEL_, indicates when to activate the booster.
CCOM_ serves as an input to an external buffer through
an internal 50Ω current-limit series resistor. Connect the
external buffer output to the external current-sense resis-
ꢁndependent control of these switches and the Hꢁ-
ZFORCE state permits flexible modes of operation
beyond the traditional force-voltage/measure-current
(FVMꢁ) and force-current/measure-voltage (FꢁMV)
modes. The MAX9951/MAX9952 support the following
eight modes:
tor, R
, and to R_X. Connect the other side of R_X to
EXT
FORCE_. Ensure that the external switch is low leakage.
• FVMꢁ
• FꢁMV
Voltage Clamps
The voltage clamps limit FORCE_ and operate over the
entire specified current range. Set the clamp voltages
externally at CLHꢁ_ and CLLO_. The voltage at FORCE_
triggers the clamps independent of the voltage at
SENSE_. When enabled, the clamps function in Fꢁ
mode only. Use clamp voltages of 0.7V above and
below the FORCE_ voltage range to ensure proper
operation of the PMU.
• FVMV
• FꢁMꢁ
• FNMV
• FNMꢁ (range E only)
• Terminate/Measure V
• Terminate/Measure ꢁ
Figure ± shows the internal path structure for force-volt-
age/measure-current mode. ꢁn force-voltage/measure-
current mode, the current across the appropriate
external sense resistor (R_A to R_E) provides a voltage
at MSR_. SENSE_ samples the voltage at the DUT and
feeds the buffered result back to the negative input of
the voltage amplifier. The voltage at MSR_ is propor-
tional to the FORCE_ current in accordance with the fol-
lowing formula:
Current Limit
The FORCE_ current-limiting circuitry, 92mA (maximum),
ensures a well-behaved MSR_ output for currents
between the full current range and the current limits. For
currents greater than the full-scale current, the MSR_
voltage is greater than +6V, and for currents less than
the full-scale current, the MSR_ voltage is less than -6V.
Additionally, serial interface bit B2 enables a range-sen-
sitive current limit of 2.5 times the nominal current range.
Table 9 shows the current-limit operation.
V
MSR_
= ꢁ
x R
x 6
SENSE
FORCE_
Figure 7 shows the internal path structure for the force-
current/measure-voltage mode. ꢁn force-current/mea-
sure-voltage mode, the appropriate external sense
resistor (R_A to R_E) provides a feedback voltage to
Independent Control of the Feedback
Switch and the Measure Switch
Two single-pole-double-throw (SPDT) switches deter-
mine the mode of operation of the PMU. One switch
determines whether the sensed DUT current or DUT
voltage feeds back to the input, and thus determines
whether the MAX9951/MAX9952 force current or volt-
age. The other switch determines whether MSR_ sens-
es the DUT current or DUT voltage.
IN1_
R
SENSE
FORCE_
SENSE_
DUT
Table 9. Current Limit
A = +4
V
B±
(BIT 12)
FMODE
RµNGE
CURRENT LIMIT
DUTGND
X
0
0
0
0
0
Any
A
0
1
1
1
1
1
±5mA to 92mA
±5mA to 92mA
5mA
MSR_
B
C
500ꢀA
D
50ꢀA
E
5ꢀA
Figure ±. Force-Voltage/Measure-Current Functional Diagram
______________________________________________________________________________________ 19
Dual Per-Pin Parametric
Measurement Units
V
DUT_
IN1_
R
SENSE
V
V
- 2.5V
- 5V
CC
FORCE_
CC
DUT
A = +4
V
I
DUT_
SENSE_
DUTGND
V
V
+ 5V
EE
MSR_
+ 2.5V
EE
I
I
MAX
MIN
1/MAX952
Figure 7. Force-Current/Measure-Voltage Functional Diagram
Figure 8. PMU Force-Output Capability
the inverting input of the voltage amplifier. SENSE_
samples the voltage at the DUT and provides a
buffered result at MSR_.
Mode and Range Change Transients
The MAX9951/MAX9952 feature make-before-break
switching to minimize glitches. The integrated voltage
clamps also reduce glitching at the output.
High-Impedance States
The FORCE_, MSR_, and comparator outputs feature
individual high-impedance control that places them into
a high-impedance, low-leakage state. The high-imped-
ance state allows busing of MSR_ and comparator out-
puts with other PMU measure and comparator outputs.
The FORCE_ output high-impedance state allows for
additional modes of operation as described in Table 5
and can eliminate the need for a series relay in some
applications.
DUT Voltage Swing vs. DUT Current
and Power-Supply Voltages
Several factors limit the actual DUT voltage that the
PMU delivers:
• The overhead required by the device amplifiers and
other integrated circuitry; this is typically 2.5V from
each rail independent of load.
• The voltage drop across the current-range select
resistor and internal circuitry in series with the sense
resistor. At full current, the combined voltage drop is
typically 2.5V.
The FORCE_, MSR_, and comparator outputs power up
in the high-impedance state.
Input Source Selection
Either one of two input signals, ꢁN0_ or ꢁN1_, can con-
trol both the forced voltage and the forced current. ꢁn
this case, the two input signals represent alternate forc-
ing values that can be selected either with the serial
interface or ꢁNSEL_. Alternatively, each input signal can
be dedicated to control a single forcing function (i.e.,
voltage or current).
• Variations in the power supplies.
• Variation of DUT ground vs. PMU ground.
Neglecting the effects of the third and fourth items,
Figure 8 demonstrates the force-output capabilities of
the PMU. For zero DUT current, the DUT voltage swings
from (V + 2.5V) to (V
- 2.5V). For larger positive DUT
EE
CC
currents, the positive swing drops off linearly until it
reaches (V - 5V) at full current. Similarly, for larger
CC
Short-Circuit Protection
FORCE_ and SENSE_ input can withstand a short to
any voltage between the supply rails.
negative DUT currents, the negative voltage swing drops
off linearly until it reaches (V + 5V) at full current.
EE
±2 ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Ground, DUT Ground, and IOS
The MAX9951/MAX9952 utilize two local grounds,
AGND (analog ground) and DGND (digital ground).
Connect AGND and DGND together on the PC board.
ꢁn a typical ATE system, the PMU force voltage is rela-
tive to DUT ground. ꢁn this case, reference the input
voltages ꢁN0_ and ꢁN1_ to DUT ground. Similarly, refer-
ence ꢁOS to DUT ground. ꢁf it is not desired to offset the
current control and measure voltages, connect ꢁOS to
DUT ground potential.
Temperature Monitor
Each device supplies a single temperature output signal,
TEMP, that asserts a nominal output voltage of 2.98V at a
die temperature of +25°C (298K). The output voltage
increases proportionately with temperature at a rate of
10mV/°C. The temperature sensor output impedance is
15kΩ (typ). Determine the die temperature using:
T
DꢁE
= (100) x V
- 273 [°C]
TEMP
Exposed Pad
The exposed pad is internally biased to V . Connect
EE
Reference the MSR_ output to DUT ground.
to a large ground plane or heatsink to maximize thermal
performance. Not intended as an electrical connection
point. Leave EP electrically unconnected, or connect to
Settling Times and
Compensation Capacitors
V
EE
. Do not connect EP to ground.
The data in the Electrical Characteristics table reflects
the circuit shown in the Functional Diagram that
includes a single compensation capacitor (CX_) effec-
tively across all the sense resistors. Placing individual
capacitors, CRA, CRB, CRC, CRD, and CRE directly
across the sense resistors, R_A, R_B, R_C, R_D, and
R_E, independently optimizes each range.
Selector Guide
PµRT
DESCRIPTION
ꢁnternal 10kΩ force-sense resistor
External force-sense resistor
ꢁnternal 10kΩ force-sense resistor
External force-sense resistor
MAX9951DCCB
MAX9951FCCB
MAX9952DCCB
MAX9952FCCB
The combination of the capacitance across the sense
resistors, along with the main amplifier compensation
comparator, CM_, ensures stability into the maximum
expected load capacitance while optimizing settling
time for a given load.
Digital Inputs (SCLK, DIN, CS, and LOAD)
The digital inputs incorporate hysteresis to mitigate
issues with noise, as well as provide for compatibility
with opto-isolators that can have slow edges.
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ ±1
Dual Per-Pin Parametric
Measurement Units
Pin Configurations
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48 SENSEB
47 FORCEB
46 CCB
SENSEA
FORCEA
CCA
3
4
45
44
43
42
41
40
39
38
37
36
35
34
33
V
V
V
CC
EE
CC
5
V
EE
6
CCOMB
RBAS
RBA
CCOMA
RAAS
RAA
1/MAX952
7
8
MAX9951
9
RBB
RAB
10
11
12
13
14
15
RBC
RAC
RBD
RAD
RBE
RAE
RBX
RAX
*EP
V
CC
V
CC
V
EE
V
EE
EXTSELB
EXTSELA 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP-EPR
*EP = EXPOSED PAD.
±± ______________________________________________________________________________________
Dual Per-Pin Parametric
Measurement Units
1/MAX952
Pin Configurations (continued)
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48 SENSEA
47 FORCEA
46 CCA
SENSEB
FORCEB
CCB
3
4
45
44
43
42
41
40
39
38
37
36
35
34
33
V
V
V
CC
EE
CC
5
V
EE
6
CCOMA
RAAS
RAA
CCOMB
RBAS
RBA
7
8
MAX9952
9
RAB
RBB
10
11
12
13
14
15
RAC
RBC
RAD
RBD
RAE
RBE
RAX
*EP
RBX
V
CC
V
CC
V
EE
V
EE
EXTSELA
EXTSELB 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP-EP
*EP = EXPOSED PAD.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PµCKµGE TYPE
±6 TQFP-EPR
±6 TQFP-EP
PµCKµGE CODE
C±6E-±
DOCUMENT NO.
±1-2286
C±6E-9R
±1-21ꢀ±
______________________________________________________________________________________ ±3
Dual Per-Pin Parametric
Measurement Units
Revision History
REVISION REVISION
PµGES
CHµNGED
DESCRIPTION
NUMBER
DµTE
Corrected bit ordering in Figures 1, 2, and 3; updated Ordering Information;
added exposed pad information
1, 11, 13, 16,
21, 22, 23
6
10/09
1/MAX952
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
±6 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim ꢁntegrated Products
Maxim is a registered trademark of Maxim ꢁntegrated Products, ꢁnc.
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