MAX9963BHCCQ [MAXIM]
Quad, Low-Power, 500Mbps ATE Driver/Comparator; 四，低功耗， 500Mbps的ATE驱动器/比较器
| 型号： | MAX9963BHCCQ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad, Low-Power, 500Mbps ATE Driver/Comparator |
| 文件： | 总25页 (文件大小：744K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2977; Rev 1; 1/04
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
General Description
Features
The MAX9963/MAX9964 four-channel, low-power, high-
speed pin electronics driver and comparator ICs
include, for each channel, a three-level pin driver, a dual
comparator, and variable clamps. The driver features a
wide voltage range and high-speed operation, includes
high-Z and active-termination (3rd-level drive) modes,
and is highly linear even at low-voltage swings. The dual
comparator provides low dispersion (timing variation)
over a wide variety of input conditions. The clamps pro-
vide damping of high-speed DUT waveforms when the
device is configured as a high-impedance receiver.
High-speed, differential control inputs compatible with
ECL, LVPECL, LVDS, and GTL levels are provided for
each channel. ECL/LVPECL or flexible open-collector
outputs are available for the comparators.
♦ Small Footprint—Four Channels in 0.4in2
♦ Low Power Dissipation: 825mW/Channel (typ)
♦ High Speed: 500Mbps at 3VP-P
♦ Low Timing Dispersion
♦ Wide -1.5V to +6.5V Operating Range
♦ Active Termination (3rd-Level Drive)
♦ Low-Leakage Mode: 15nA (max)
♦ Integrated Clamps
♦ Interface Easily with Most Logic Families
♦ Digitally Programmable Slew Rate
♦ Internal Logic Termination Resistors
♦ Low Gain and Offset Error
The A-grade version provides tight matching of gain
and offset for the drivers and comparators, allowing ref-
erence levels to be shared across multiple channels in
cost-sensitive systems. For system designs that incor-
porate independent reference levels for each channel,
the B-grade version is available at reduced cost.
Ordering Information
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
MAX9963ADCCQ*
MAX9963AKCCQ*
MAX9963AGCCQ*
MAX9963AHCCQ*
MAX9963AJCCQ
MAX9963BDCCQ*
MAX9963BKCCQ*
MAX9963BGCCQ
MAX9963BHCCQ*
MAX9963BJCCQ*
MAX9964ADCCQ*
MAX9964AKCCQ*
MAX9964AGCCQ*
MAX9964AHCCQ*
MAX9964AJCCQ*
MAX9964BDCCQ*
MAX9964BKCCQ*
MAX9964BGCCQ
MAX9964BHCCQ*
MAX9964BJCCQ*
Optional internal resistors at the high-speed inputs pro-
vide differential termination of LVDS inputs, while
optional internal resistors provide the pullup voltage
and source termination for open-collector comparator
outputs. These features significantly reduce the dis-
crete component count on the circuit board.
Low-leakage, slew rate, and tri-state/terminate controls
are operational configurations that are programmed
through a 3-wire, low-voltage, CMOS-compatible serial
interface.
The MAX9963/MAX9964 operating range is -1.5V to
+6.5V, with power dissipation of only 825mW per channel.
These devices are available in a 100-pin, 14mm x
14mm body, 0.5mm pitch TQFP with an exposed 8mm
x 8mm die pad on the top (MAX9963) or bottom
(MAX9964) of the package for efficient heat removal.
The MAX9963/MAX9964 are specified to operate with
an internal die temperature of +70°C to +100°C, and
feature a die temperature monitor output.
Applications
Flash Memory Testers
*Future product—contact factory for availability.
**EP = Exposed pad.
Commodity DRAM Testers
Low-Cost Mixed-Signal/System-on-Chip Testers
Active Burn-In Systems
Pin Configurations appear at end of data sheet.
Selector Guide appears at end of data sheet.
Structural Testers
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ABSOLUTE MAXIMUM RATINGS
V
V
to GND .........................................................-0.3V to +11.5V
to GND............................................................-7.0V to +0.3V
DLV_ to DTV_....................................................................... 10V
CHV_ or CLV_ to DUT_........................................................ 10V
CH_, NCH_, CL_, NCL_ to GND...............................-2.5V to +5V
Current into DHV_, DLV_, DTV_, CHV_,
CC
EE
All Other Pins....................................(V - 0.3V) to (V + 0.3V)
V
EE
CC
- V ................................................................-0.3V to +18V
CC
EE
DUT_ to GND.........................................................-2.5V to +7.5V
DATA_, NDATA_, RCV_, NRCV_ to GND..............-2.5V to +5.0V
DATA_ to NDATA_.............................................................. 1.5V
RCV_ to NRCV_ .................................................................. 1.5V
CLV_, CPHV_, CPLV_................................................... 10mA
Current into TEMP............................................-0.5mA to +20mA
DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous
Power Dissipation (T = +70°C)
A
V
to GND ........................................................-0.3V to +5V
MAX9963_ _CCQ (derate 167mW/°C above
CCO_ _
SCLK, DIN, CS, RST to GND ...................................-1.0V to +5V
DHV_, DLV_, DTV_, CHV_, CLV_ to GND .............-2.5V to +7.5V
CPHV_ to GND ......................................................-2.5V to +8.5V
CPLV_ to GND.......................................................-3.5V to +7.5V
DHV_ to DLV_ ...................................................................... 10V
DHV_ to DTV_ ...................................................................... 10V
T = +70°C)..................................................................13.3W*
A
MAX9964_ _CCQ (derate 47.6mW/°C above
T = +70°C)....................................................................3.8W*
A
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+125°C
Lead Temperature (soldering, 10s) .................................+300°C
*Dissipation wattage values are based on still air with no heat sink for the MAX9963 and slug soldered to board copper for the
MAX9964. Actual maximum power dissipation is a function of the user’s heat-extraction technique and will vary.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
POWER SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply
Negative Supply
Positive Supply
Negative Supply
V
9.5
9.75
-5.25
165
10.5
-4.5
200
V
CC
V
-6.5
V
EE
I
(Note 2)
(Note 2)
mA
mA
CC
I
-320
-380
EE
Calculated at typical V
(Notes 2, 3)
and V
EE
CC
Power Dissipation
P
3.3
4.0
W
D
DUT_ CHARACTERISTICS
Operating Voltage Range
Maximum
V
(Note 4)
-1.5
+6.5
V
DUT
LLEAK = 0, 0V ≤ V
≤ 3V
1.5
3
DUT_
Leakage Current in High-Z Mode
I
µA
DUT
LLEAK = 0, V
= -1.5V, 6.5V
DUT_
LLEAK = 1, 0 ≤ V
≤ 3V, T < +90°C
10
15
DUT_
J
LLEAK = 1, V
= -1.5V,T < +90°C
J
DUT_
Leakage Current in Low-Leakage
Mode
nA
pF
LLEAK = 1, V
= 6.5V, V
= V
=
CLV_
DUT_
CHV_
15
-1.5V, T < +90°C
J
Driver in term mode (DUT_ = DTV_)
Driver in high-Z mode
3
5
Combined Capacitance
C
DUT
2
_______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
Low-Leakage Enable Time
Low-Leakage Disable Time
SYMBOL
CONDITIONS
MIN
TYP
20
MAX
UNITS
µs
(Notes 5, 7)
(Notes 6, 7)
20
µs
Time to return to the specified maximum
leakage after a 3V, 4V/ns step at DUT_
(Note 7)
Low-Leakage Recovery
10
1
µs
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_)
Input Bias Current
Settling Time
I
25
µA
µs
BIAS
To 5mV
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_)
Input High Voltage
Input Low Voltage
V
-1.6
-2.0
0.15
+3.5
+3.1
1.00
25
V
V
IH
V
IL
Differential Input Voltage
Input Bias Current
V
DIFF
BIAS
V
I
MAX996_ _DCCQ, MAX996_ _HCCQ
µA
MAX996_ _KCCQ, MAX996_ _GCCQ,
and MAX996_ _JCCQ, between signal and
complement
Input Termination Resistor
96
104
Ω
SINGLE-ENDED CONTROL INPUTS (CS, RST, SCLK, DIN)
Input High
Input Low
V
1.6
3.5
V
V
IH
V
-0.1
+0.9
IL
SERIAL INTERFACE TIMING (Figure 5)
SCLK Frequency
f
50
MHz
ns
SCLK
SCLK Pulse Width High
SCLK Pulse Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
CS Pulse Width High
t
8
CH
t
8
ns
CL
t
t
3.5
3.5
3.5
3.5
3.5
20
ns
CSS0
CSS1
CSH1
ns
t
ns
t
ns
DS
DH
t
ns
t
ns
CSWH
TEMPERATURE MONITOR (TEMP)
Nominal Voltage
T = +70°C, R ≥ 10MΩ
3.43
+10
15
V
J
L
Temperature Coefficient
Output Resistance
mV/°C
kΩ
_______________________________________________________________________________________
3
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
DRIVERS (Note 8)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC OUTPUT CHARACTERISTICS (R ≥ 10MΩ )
L
At DUT_ with V
,
DHV_
MAX996_A
MAX996_B
15
DHV_, DLV_, DTV_, Output Offset
Voltage
V
V
DLV_, DTV_
V
mV
OS
independently
tested at +1.5V
100
DHV_, DLV_, DTV_, Output Offset
Temperature Coefficient
65
µV/°C
Measured with
MAX996_A
MAX996_B
0.999
0.960
1.00
1.001
1.001
DHV_, DLV_, DTV_, Gain
A
V/V
V
, V
V
V
DHV_ DLV_, DTV_
at 0 and 4.5V
DHV_, DLV_, DTV_, Gain
Temperature Coefficient
-35
ppm/°C
0 ≤ V
≤ 3V (Note 9)
5
15
7
DUT_
Linearity Error
mV
Full range (Notes 9, 10)
DHV_ to DLV_ Crosstalk
DLV_ to DHV_ Crosstalk
V
V
= 0, V
= 200mV, 6.5V
mV
mV
DLV_
DHV_
DHV_
= 5V, V
= -1.5V, 4.8V
= 0,
8
DLV_
DLV_
DTV_ to DLV_ and DHV_
Crosstalk
V
V
= 3V, V
DHV_
DTV_
2
mV
= -1.5V, 6.5V
DHV_ to DTV_ Crosstalk
DLV_ to DTV_ Crosstalk
V
V
V
= 1.5V, V
= 1.5V, V
= 0, V
DHV_
= 1.6V, 3V
= 0, 1.4V
3
3
mV
mV
DTV_
DTV_
DLV_
DHV
= 3V, V
DLV_
DHV_, DLV_, DTV_ DC Power-
Supply Rejection Ratio
and V independently set to their
EE
CC
PSRR
40
dB
minimum and maximum values
Maximum DC Drive Current
DC Output Resistance
DC Output Resistance Variation
I
R
∆R
_
60
49
120
51
mA
Ω
Ω
DUT
_
DUT
I
I
=
=
30mA (Note 11)
1mA to 40mA
50
1
DUT
_
DUT
DUT
DYNAMIC OUTPUT CHARACTERISTICS (Z = 50Ω )
L
V
V
V
= 0V, V
= 0V, V
= 0V, V
= 0.1V
= 1V
30
40
50
0
DLV_
DLV_
DLV_
DHV_
DHV_
DHV_
Drive Mode Overshoot
mV
= 3V
Term Mode Overshoot
(Note 12)
mV
ns
Settling Time to Within 25mV
Settling Time to Within 5mV
3V step (Note 13)
3V step (Note 13)
10
20
ns
4
_______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Note 14) (Z = 50Ω )
L_
PDD
Prop Delay, Data to Output
Prop Delay Match, t vs. t
t
2
ns
ps
3V
P-P
50
LH
HL
Prop Delay Match, Drivers Within
Package
(Note 15)
40
+3
60
85
ps
ps/°C
ps
Prop Delay Temperature
Coefficient
Prop Delay Change vs. Pulse
Width
3V , 40MHz, 2.5ns to 22.5ns pulse width,
P-P
relative to 12.5ns pulse width
Prop Delay Change vs. Common-
Mode Voltage
V
- V
= 1V, V = 0 to 6V
DHV_
ps
DHV_
DLV_
Prop Delay, Drive to High-Z
Prop Delay, High-Z to Drive
Prop Delay, Drive to Term
Prop Delay, Term to Drive
t
t
V
V
V
V
= 1.0V, V
= 1.0V, V
= -1.0V, V
= -1.0V, V
= 0
= 0
2.9
2.9
2.2
1.8
ns
ns
ns
ns
PDDZ
PDZD
DHV_
DHV_
DHV_
DHV_
DLV_
DLV_
DTV_
DTV_
t
t
= 3V, V
= 3V, V
= 0, V
= 1.5V
= 1.5V
PDDT
PDTD
DLV_
DLV_
DTV_
DTV_
= 0, V
DYNAMIC PERFORMANCE (Z = 50Ω)
L
0.2V
20% to 80%
330
670
1.3
2.0
P-P,
ps
ns
%
1V
3V
5V
10% to 90%
10% to 90%
10% to 90%
P-P,
P-P,
P-P,
Rise and Fall Time
t , t
R F
1.1
1.6
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
SC1 = 0, SC0 = 1 Slew Rate
SC1 = 1, SC0 = 0 Slew Rate
SC1 = 1, SC0 = 1 Slew Rate
75
50
25
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
%
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
%
0.2V
650
1.0
ps
P-P
1V
3V
5V
P-P
Minimum Pulse Width (Note 16)
Data Rate (Note 17)
2.0
ns
P-P
P-P
2.9
0.2V
1700
1000
500
350
20
P-P
1V
3V
5V
P-P
Mbps
P-P
P-P
Dynamic Crosstalk
(Note 18)
mV
P-P
V
= 3V, V
= 0, V
= 0, V
= 1.5V, 10%
= 1.5V, 10%
DHV_
DLV_
DTV_
Rise and Fall Time, Drive to Term
t
t
, t
1.6
0.7
ns
DTR DTF
to 90% (Note 19)
V
= 3V, V
DHV_
DLV_
DTV_
Rise and Fall Time, Term to Drive
, t
ns
TDR TDF
to 90% (Note 19)
_______________________________________________________________________________________
5
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
COMPARATORS (Note 20)
DC CHARACTERISTICS
Input Voltage Range
Differential Input Voltage
Hysteresis
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(Note 4)
-1.5
8
+6.5
V
V
IN
V
DIFF
V
0
mV
HYST
MAX996_A
MAX996_B
15
Input Offset Voltage
V
V
= 1.5V
mV
OS
DUT_
100
Input Offset Voltage Temperature
Coefficient
50
µV/°C
V
V
V
V
V
V
= 0, 3V
47
54
44
78
78
61
3
DUT_
DUT_
DUT_
DUT_
DUT_
DUT_
Common-Mode Rejection Ratio
(Note 21)
CMRR
dB
= 0, 6.5V
= -1.5V, 6.5V
= 0 to 3V
= 6.5V
Linearity Error (Note 9)
15
25
mV
= -1.5V
V
Ratio
Power-Supply Rejection
CC
PSRR
PSRR
V
= -1.5V, 6.5V (Note 22)
57
82
dB
dB
DUT_
V
V
= 0, 6.5V
= -1.5V
44
33
70
45
DUT_
DUT_
V
Power-Supply Rejection
EE
Ratio (Note 22)
AC CHARACTERISTICS (Note 23)
MAX996_ _GCCQ
0.75
1.3
2.2
+6
Minimum Pulse Width
t
(min) (Note 24)
PDL
ns
PW
MAX996_ _HCCQ,
MAX996_ _JCCQ
Prop Delay
t
ns
Prop Delay Temperature
Coefficient
ps/°C
Prop Delay Match, High/Low vs.
Low/High
25
35
ps
ps
Prop Delay Match, Comparators
Within Package
(Note 15)
V
V
V
= 0, 6.4V
= -1.4V
75
CHV_ = CLV_
Prop Delay Dispersion vs.
Common-Mode Input (Note 25)
ps
ps
V
175
CHV_ = CLV_
Prop Delay Dispersion vs.
Overdrive
100mV to 2V
200
35
MAX996_ _GCCQ
2.5ns to 22.5ns pulse
width, relative to 12.5ns
pulse width
Prop Delay Dispersion vs. Pulse
Width
ps
ps
MAX996_ _HCCQ,
MAX996_ _JCCQ
70
Prop Delay Dispersion vs. Slew
Rate
0.5V/ns to 2V/ns slew rate
100
6
_______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
250
500
MAX
UNITS
V
= 1.0V , t
t = 1.0ns 10% to 90%,
F
=
P-P R
DUT_
Term mode
Waveform Tracking 10% to 90%
ps
relative to timing at
50% point
High-Z mode
OPEN-COLLECTOR LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX996_ _DCCQ, MAX996_ _KCCQ, and MAX996_ _GCCQ )
V
Voltage Range
V
0
3.5
V
V
CCO_ _
VCCO_ _
Output Low-Voltage Compliance
Set by I
, R
, and V
-0.5
OUT TERM
CCO_ _
I
= I
= I
= I
= 0mA,
V
V
CCO_
- 0.04
CH_
NCH_
CL_
NCL_
CCO_
Output High Voltage
V
V
OH
MAX996_ _GCCQ
- 0.10
I
= I = I
= I
= 0mA,
V
CCO_
- 0.38
CH_
NCH_
CL_
NCL_
Output Low Voltage
Output Voltage Swing
Termination Resistor
V
V
V
OL
MAX996_ _GCCQ
0.30
47.5
0.33
0.40
Single-ended measurement from V
CH_, NCH_, CL_, NCL_, MAX996_ _GCCQ
to
CCO_ _
R
52.5
+3.5
Ω
TERM
Differential Rise Time
Differential Fall Time
t
20% to 80%
20% to 80%
350
350
ps
ps
R
t
F
OPEN-EMITTER LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX996_ _HCCQ and MAX996_ _JCCQ)
V
V
Voltage Range
Supply Current
V
-0.1
V
CCO_ _
CCO_ _
VCCO_ _
VCCO_ _
I
All outputs 50 Ω to (V
- 2V)
330
mA
VCCO_ _
V
CCO_ _
- 0.9
Output High Voltage
Output Low Voltage
V
50Ω to (V
- 2V)
V
V
OH
VCCO_ _
V
CCO_ _
- 1.7
V
50Ω to (V
50Ω to (V
- 2V)
- 2V)
OL
VCCO_ _
Output Voltage Swing
Differential Rise Time
Differential Fall Time
750
850
600
600
950
mV
ps
ps
VCCO_ _
t
20% to 80%
20% to 80%
R
t
F
CLAMPS
High Clamp Input Voltage Range
Low Clamp Input Voltage Range
V
-0.3
-2.5
+7.5
+5.3
100
V
V
CPH_
V
CPL_
At DUT_ with I
At DUT_ with I
= 1mA, V
= 0
= 0
DUT_
CPHV_
Clamp Offset Voltage
V
mV
OS
= -1mA, V
100
DUT_
CPLV_
Offset Voltage Temperature
Coefficient
0.5
mV/°C
V
and V independently varied full
EE
CC
40
40
range, I
= 1mA, V
= 0
CPHV_
DUT_
Clamp Power-Supply Rejection
PSRR
dB
V
and V independently varied full
EE
CC
range, I
= -1mA, V
= 0
DUT_
CPLV_
_______________________________________________________________________________________
7
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
Voltage Gain
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
A
0.96
1.00
V/V
V
Voltage-Gain Temperature
Coefficient
-100
10
ppm/°C
I
= 1mA, V
= -1.5V, V
= -0.3
= -1.5
DUT
CPLV_
CPHV_
CPLV_
to 6.5V
Clamp Linearity
mV
I
= -1mA, V
= 6.5V, V
CPHV_
DUT
10
to 5.3V
V
V
= 0, V
= 6.0V
= -1.5V,
CPHV_
CPLV_
50
-95
50
95
-50
55
DUT_
Short-Circuit Output Current
Clamp DC Impedance
mA
V
V
= 5V, V
= -1.0V
= 6.5V,
= 0,
CPLV_
CPHV_
CPLV_
DUT_
V
= 3V, V
= -5mA and -15mA
CPHV_
I
DUT
Ω
V
= 3V, V
= 5mA and 15mA
= 0,
CPLV_
CPHV_
50
55
I
DUT
Note 1: All MIN and MAX limits are 100% tested in production.
Note 2: Total for quad device at worst-case setting. R ≥ 10MΩ. The applicable supply currents are measured with typical supply
L_
voltages.
Note 3: Does not include internal dissipation of the comparator outputs. With output loads of 50Ω to (V
- 2V), this adds
VCCO_ _
240mW (typ) to the total chip power (MAX996_ _HCCQ, MAX996_ _JCCQ).
Note 4: Externally forced voltages may exceed this range provided that the absolute maximum ratings are not exceeded.
Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 6: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 7: Based on simulation results only.
Note 8: With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 9: Relative to straight line between 0 and 3V.
Note 10: Full ranges are -1.3V ≤ V
≤ 6.5V, -1.5V ≤ V
≤ 6.5V, -1.5V ≤ V
≤ 6.3V.
DHV_
DTV_
DLV_
Note 11: Nominal target value is 50Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range.
Note 12: V
= 1.5V, R = 50Ω. External signal driven into T-line is a 0 to 3V edge with 1.2ns rise time (10% to 90%).
DTV_
S
Measurement is made using the comparator.
Note 13: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
Note 14: Prop delays are measured from the crossing point of the differential input signals to the 50% point of expected output
swing. Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%).
8
_______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V = -2.2V, T = +85°C, unless otherwise noted. All tem-
CPLV_ J
CC
EE
CCO_ _
CPHV_
perature coefficients are measured at T = +70°C to +100°C, unless otherwise noted.) (Note 1)
J
Note 15: Rising edge to rising edge or falling edge to falling edge.
Note 16: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude.
The pulse width is measured at DATA_.
Note 17: Specified amplitude is programmed. Maximum data rate specified in transitions per second. A square wave that reaches
at least 95% of its programmed amplitude may be generated at one-half this frequency.
Note 18: Crosstalk from any driver to the other three channels. Aggressor channel is driving 3V
into a 50Ω load. Victim channels
P-P
are in term mode with V
= 1.5V.
DTV_
Note 19: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when V
< V
< V
. If
DHV_
DLV_
DTV_
V
< V
or V
> V
, switching speed is degraded by approximately a factor of 3.
DHV_
DTV_
DLV_
DTV_
Note 20: Both high and low comparators are tested.
Note 21: Change in offset voltage over input range.
Note 22: Change in offset voltage with power supplies independently set to their minimum and maximum values.
Note 23: Unless otherwise noted, all prop delays are measured at 40MHz, V = 0 to 2V, V = V = 1V, slew rate = 2V/ns,
DUT_
CHV_
CLV_
Z
V
= 50Ω, driver in term mode with V
CCO_ _
= 0V. Comparator outputs are terminated with 50Ω to GND at scope input with
S
DTV_
=2V. Open-collector outputs are also terminated (internally or externally) with R
= 50Ω to V
Measured
CCO_ _.
TERM
from V
crossing calibrated CHV_/CLV_ threshold to the crossing point of differential outputs.
DUT_
Note 24: V
= 0 to 1V, V
= V
= 0.5V. At this pulse width, the output reaches at least 90% of its DC voltage swing. The
DUT_
CHV_
CLV_
pulse width is measured at the crossing points of the differential outputs.
Note 25: Relative to propagation delay at V
= V
= 1.5V. V
= 200mV . Overdrive = 100mV.
DUT_ P-P
CHV_
CLV_
Typical Operating Characteristics
DRIVE TO TERM TRANSITION
DRIVER SMALL-SIGNAL RESPONSE
DRIVER LARGE-SIGNAL RESPONSE
DLV_ = 0V
R = 50Ω
L
DLV_ = 0V
R = 50Ω
L
DHV_ =
500mV
DHV_ = 5V
DHV_ TO DTV_
DHV_ = 3V
DHV_ =
200mV
DHV_ =
100mV
DHV_ = 1V
DLV_ TO DTV_
0
0
0
R = 50Ω
L
t = 5.0ns/div
t = 2.50ns/div
t = 2.50ns/div
_______________________________________________________________________________________
9
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE, MAX996_ _JCCQ
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
DRIVER TRAILING-EDGE TIMING ERROR
vs. PULSE WIDTH
40
20
70
60
50
40
30
20
10
0
RISING EDGE
0
-20
-40
-60
-80
-100
0
FALLING EDGE
LOW PULSE
HIGH PULSE
-10
-20
-30
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns, DHV_ = 3V, DLV_ = 0
NORMALIZED TO V = 1.5V
CM
t = 2.50ns/div
0
5
10
15
20
25
-1
0
1
2
3
4
5
6
PULSE WIDTH (ns)
COMMON-MODE VOLTAGE (V)
V
= 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V
DUT
EXTERNAL LOAD = 50Ω
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
HIGH-Z TO DRIVE TRANSITION
HIGH-Z TO DHV_
10
8
10
8
DUT_ = DHV_
DUT_ = DLV_
6
6
4
4
0
2
2
0
0
HIGH-Z TO DLV_
R = 50Ω
L
-2
-2
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
t = 5.0ns/div
V
V
OUT_
DUT_
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
CROSSTALK TO DUT_ FROM DLV_
WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM DTV_
WITH DUT_ = DHV_
10
8
9
8
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
DHV_ = 5V
DTV_ = 1.5V
DUT_ = DTV_
DHV_ = 3V
DLV_ = 0
7
6
6
5
4
4
3
2
2
1
0
0
-1
-2
-0.02
-0.04
NORMALIZED AT DLV_ = 0
NORMALIZED AT DTV_ = 1.5V
-2
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
-1.5
0
1.5
3.0
4.5
6.0
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DTV_ VOLTAGE (V)
V
(V)
DLV_ VOLTAGE (V)
DUT_
10 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
CROSSTALK TO DUT_ FROM DHV_
WITH DUT_ = DLV_
CROSSTALK TO DUT_ FROM DTV_
WITH DUT_ = DLV_
CROSSTALK TO DUT_ FROM DLV_
WITH DUT_ = DTV_
3
2
6
4
0.06
0.04
0.02
0
DLV_ = 0
DTV_ = 1.5V
DTV_ = 1.5V
DHV_ = 3V
DLV_ = 0
DHV_ = 3V
1
0
2
-1
-2
-3
-4
-5
-6
-7
-8
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
0
-2
-4
-6
NORMALIZED AT DLV_ = 0
NORMALIZED AT DTV_ = 1.5V
NORMALIZED AT DHV_ = 5V
-0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DHV_ VOLTAGE (V)
-1.5
0
1.5
3.0
4.5
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DTV_VOLTAGE (V)
DLV_ VOLTAGE (V)
CROSSTALK TO DUT_ FROM DHV_
WITH DUT_ = DTV_
DRIVER OFFSET vs. TEMPERATURE
DRIVER GAIN vs. TEMPERATURE
1.0020
1.0015
1.0010
1.0005
1.0000
0.9995
0.9990
1.0
0.5
2
1
DTV_ = 1.5V
DLV_ = 0
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
NORMALIZED AT +85°C
NORMALIZED AT T = +85°C
J
NORMALIZED AT DHV_ = 3V
25
40
55
70
85
100
25
40
55
70
85
100
-0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DHV_ VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
COMPARATOR RISING-EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
COMPARATOR FALLING-EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
0.6
0.4
150
100
50
150
100
50
V
= -4.5V
EE
0.2
V
= -4.5V
= -5.5V
0
EE
V
= -5.5V
EE
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
V
= -4.5V
EE
V
EE
V
= -5.5V
EE
0
0
-50
-100
-150
-50
-100
-150
V
= -6.5V
EE
V
= -6.5V
EE
V
= -6.5V
EE
NORMALIZED AT
= 1.5V AND V = -5.25V
NORMALIZED AT
= 1.5V AND V = -5.25V
NORMALIZED AT
V = 1.5V AND V = -5.25V
CM
V
V
CM
EE
CM
EE
EE
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
______________________________________________________________________________________ 11
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
COMPARATOR TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH, MAX996_ _GCCQ
COMPARATOR TIMING VARIATION
vs. OVERDRIVE
COMPARATOR TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH, MAX996_ _JCCQ
30
100
450
400
350
300
250
200
150
100
50
20
10
50
0
HIGH PULSE
0
-10
-20
-30
-40
-50
-60
-50
HIGH PULSE
LOW PULSE
LOW PULSE
-100
-150
-200
NORMALIZED TO
OVERDRIVE = 0.5V
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns
0
0
5
10
15
20
25
0
5
10
15
20
25
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OVERDRIVE (V)
PULSE WIDTH (ns)
PULSE WIDTH (ns)
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE, DUT_ FALLING
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE, DUT_ RISING
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE, MAX996_ _GCCQ
50
40
50
40
30
30
20
20
10
10
0
0
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
-40
-50
-60
-70
0
NORMALIZED TO SR = 0.84V/ns
NORMALIZED TO SR = 0.824V/ns
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SLEW RATE (V/ns)
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
SLEW RATE (V/ns)
t = 2.50ns/div
V
= 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V
DUT
EXTERNAL LOAD = 50Ω
COMPARATOR RESPONSE
vs. HIGH SLEW RATE OVERDRIVE
COMPARATOR OFFSET
vs. TEMPERATURE
CLAMP RESPONSE
0.8
0.6
HIGH-Z MODE
0.4
RISING EDGE
0.2
DIGITIZED
OUTPUT
INPUT
0.0
-0.2
-0.4
-0.6
FALLING EDGE
0
0
INPUT SLEW RATE = 6V/ns
t = 2.50ns/div
NORMALIZED TO T = +85°C
J
t = 5.0ns/div
65 70 75 80 85 90 95 100 105
TEMPERATURE (°C)
V
R
= 0 TO 3V SQUARE WAVE
DUT
= 25Ω
S
CPLV_ = -0.1V, CPHV_ = +3.1V
12 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
HIGH-Z LEAKAGE CURRENT
vs. DUT_ VOLTAGE
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
0.8
0.6
0.4
0.2
0
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
100
0
V
= 3V
DUT_
CPLV_ = 0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1100
-1200
-0.2
-0.4
-0.6
-0.8
V
= 0
DUT_
-100
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DUT_ VOLTAGE (V)
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
CPHV_ VOLTAGE (V)
-1.50 -1.25 -1.00 -0.75 -0.50 -0.25
0
CPLV_ VOLTAGE (V)
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
DRIVER REFERENCE INPUT CURRENT
vs. INPUT VOLTAGE
9
8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
DTV_
7
DLV_
6
CHV_ = CLV_ = 6.5V
5
4
3
DHV_
CHV_ = CLV_ = 5V
CHV_ = CLV_ < 3V
2
1
0
-1
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DUT_ VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
INPUT VOLTAGE (V)
INPUT CURRENT
vs. INPUT VOLTAGE, CPHV_
COMPARATOR REFERENCE INPUT CURRENT
vs. INPUT VOLTAGE
700
600
500
400
300
200
300
CPLV_ = -2.2V
CHV
250
200
150
100
50
CLV
0
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
CPHV_ VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
INPUT VOLTAGE (V)
______________________________________________________________________________________ 13
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
INPUT CURRENT
vs. INPUT VOLTAGE, CPLV_
SUPPLY CURRENT
vs. V
SUPPLY CURRENT
vs. V
I
I
CC
CC
EE
EE
0
185
170
155
140
125
110
95
-220
-240
-260
-280
-300
-320
-340
-360
-380
-400
A
B
C
-1
-2
-3
-4
-5
B
A
C
80
A: DUT_ = DTV_ = 1.5V, DHV_ = 3V,
A:: DLV_ = 0, CHV_ = CLV_ = 0,
A:: CPHV_ = 7.2V, CPLV_ = -2.2V.
B: SAME AS A EXCEPT DUT_ = HIGH-Z.
C: SAME AS B EXCEPT DUT_ = LOW LEAK.
A: DUT_ = DTV_ = 1.5V, DHV_ = 3V,
A:: DLV_ = 0, CHV_ = CLV_ = 0,
A:: CPHV_ = 7.2V, CPLV_ = -2.2V.
B: SAME AS A EXCEPT DUT_ = HIGH-Z.
C: SAME AS B EXCEPT DUT_ = LOW LEAK.
65
50
CPHV_ = 7.2V
35
20
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
CPLV_ VOLTAGE (V)
9.50
9.75
10.00
(V)
10.25
10.50
-6.50 -6.25 -6.00 -5.75 -5.50 -5.25 -5.00 -4.75 -4.50
V
V
(V)
CC
EE
I
CC
vs. TEMPERATURE
I
EE
vs. TEMPERATURE
166.0
165.5
165.0
164.5
164.0
163.5
163.0
162.5
-313.0
-313.2
-313.4
-313.6
-313.8
-314.0
-314.2
DUT_ = DTV_ = 1.5V, DHV_ = 3V,
DLV_ = 0, CHV_ = CLV_ = 0,
CPHV_ = 7.2V, CPLV_ = -2.2V,
DUT_ = DTV_ = 1.5V, DHV_ = 3V,
DLV_ = 0, CHV_ = CLV_ = 0,
CPHV_ = 7.2V, CPLV_ = -2.2V,
V
= 9.75V, V = -5.25V
V
= 9.75V, V = -5.25V
CC
EE
CC
EE
60
70
80
90
100
110
60
70
80
90
100
110
TEMPERATURE (°C)
TEMPERATURE (°C)
14 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Pin Description
PIN
NAME
FUNCTION
MAX9963
MAX9964
Collector Voltage Input, Channels 3 and 4. For open-collector outputs, this is the
pullup voltage for the internal termination resistors. For open-emitter outputs, this is
1
25
V
34 the collector voltage of the output transistors. Not internally connected on open-
CCO
collector versions without internal termination resistors. V 34 services both
CCO
channel 3 and channel 4.
Channel 4 Multiplexer Control Inputs. Differential controls DATA4 and NDATA4
select driver 4’s input from DHV4 or DLV4. Drive DATA4 above NDATA4 to select
DHV4. Drive NDATA4 above DATA4 to select DLV4.
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
DATA4
NDATA4
RCV4
Channel 4 Multiplexer Control Inputs. Differential controls RCV4 and NRCV4 place
channel 4 into receive mode. Drive RCV4 above NRCV4 to place channel 4 into
receive mode. Drive NRCV4 above RCV4 to place channel 4 into drive mode.
NRCV4
DATA3
NDATA3
RCV3
Channel 3 Multiplexer Control Inputs. Differential controls DATA3 and NDATA3
select driver 3’s input from DHV3 or DLV3. Drive DATA3 above NDATA3 to select
DHV3. Drive NDATA3 above DATA3 to select DLV3.
Channel 3 Multiplexer Control Inputs. Differential controls RCV3 and NRCV3 place
channel 3 into receive mode. Drive RCV3 above NRCV3 to place channel 3 into
receive mode. Drive NRCV3 above RCV3 to place channel 3 into drive mode.
NRCV3
10, 27, 54, 55,
60, 61, 65, 66,
71, 72, 99
16, 27, 54, 55,
60, 61, 65, 66,
71, 72, 99
V
Negative Power-Supply Input
EE
11, 28, 51, 56,
62, 64, 70,
75, 98
15, 28, 51, 56,
62, 64, 70,
75, 98
GND
Ground Connection
Reset Input. Asynchronous reset input for the serial register. RST is active low and
12
14
RST
asserts low-leakage mode. At power-up, hold RST low until V and V have
CC EE
stabilized.
13
14
15
13
12
11
CS
SCLK
DIN
Chip-Select Input. Serial-port activation input. CS is active low.
Serial Clock Input. Clock for serial port.
Data Input. Serial port data input.
16, 26, 52, 58,
68, 74, 100
10, 26, 52, 58,
68, 74, 100
V
Positive Power-Supply Input
CC
Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place
channel 2 into receive mode. Drive RCV2 above NRCV2 to place channel 2 into
receive mode. Drive NRCV2 above RCV2 to place channel 2 into drive mode.
17
18
19
20
9
8
7
6
NRCV2
RCV2
Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2
select driver 2’s input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select
DHV2. Drive NDATA2 above DATA2 to select DLV2.
NDATA2
DATA2
______________________________________________________________________________________ 15
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9963
MAX9964
Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place
channel 1 into receive mode. Drive RCV1 above NRCV1 to place channel 1 into
receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode.
21
5
NRCV1
RCV1
22
23
24
4
3
2
Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1
select driver 1’s input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select
DHV1. Drive NDATA1 above DATA1 to select DLV1.
NDATA1
DATA1
Collector Voltage Input, Channels 1 and 2. For open-collector outputs, this is the
pullup voltage for the internal termination resistors. For open-emitter outputs, this is
25
1
V
12 the collector voltage of the output transistors. Not internally connected on open-
CCO
collector versions without internal termination resistors. V 12 services both
CCO
channel 1 and channel 2.
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NCL2
CL2
Channel 2 Low-Comparator Output. Differential output of channel 2 low comparator.
NCH2
CH2
Channel 2 High-Comparator Output. Differential output of channel 2 high
comparator.
NCL1
CL1
Channel 1 Low-Comparator Output. Differential output of channel 1 low comparator.
NCH1
CH1
Channel 1 High-Comparator Output. Differential output of channel 1 high
comparator.
CPHV2 Channel 2 High-Clamp Reference Input
CPLV2 Channel 2 Low-Clamp Reference Input
DHV2
DLV2
DTV2
CHV2
CLV2
Channel 2 Driver-High Reference Input
Channel 2 Driver-Low Reference Input
Channel 2 Driver-Termination Reference Input
Channel 2 High-Comparator Reference Input
Channel 2 Low-Comparator Reference Input
CPHV1 Channel 1 High-Clamp Reference Input
CPLV1 Channel 1 Low-Clamp Reference Input
DHV1
DLV1
DTV1
CHV1
CLV1
Channel 1 Driver-High Reference Input
Channel 1 Driver-Low Reference Input
Channel 1 Driver-Termination Reference Input
Channel 1 High-Comparator Reference Input
Channel 1 Low-Comparator Reference Input
Channel 1 Device Under Test Input/Output. Combined I/O for driver, comparator,
and clamp.
53
73
DUT1
57, 69
59
57, 69
67
N.C.
DUT2
TEMP
No Connection. Leave open.
Channel 2 Device Under Test Input/Output. Combined I/O for driver, comparator,
and clamp.
63
63
Temperature Monitor Output
16 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9963
MAX9964
Channel 3 Device Under Test Input/Output. Combined I/O for driver, comparator,
and clamp.
67
59
DUT3
Channel 4 Device Under Test Input/Output. Combined I/O for driver, comparator,
and clamp.
73
53
DUT4
CLV4
76
77
78
79
80
81
82
83
84
85
86
87
88
50
49
48
47
46
45
44
43
42
41
40
39
38
Channel 4 Low-Comparator Reference Input
CHV4 Channel 4 High-Comparator Reference Input
DTV4
DLV4
Channel 4 Driver-Termination Reference Input
Channel 4 Driver-Low Reference Input
DHV4 Channel 4 Driver-High Reference Input
CPLV4 Channel 4 Low-Clamp Reference Input
CPHV4 Channel 4 High-Clamp Reference Input
CLV3
Channel 3 Low-Comparator Reference Input
CHV3 Channel 3 High-Comparator Reference Input
DTV3
DLV3
Channel 3 Driver-Termination Reference Input
Channel 3 Driver-Low Reference Input
DHV3 Channel 3 Driver-High Reference Input
CPLV3 Channel 3 Low-Clamp Reference Input
CPHV3 Channel 3 High-Clamp Reference Input
89
90
91
92
93
94
95
96
97
37
36
35
34
33
32
31
30
29
CH4
NCH4
CL4
NCL4
CH3
Channel 4 High-Comparator Output. Differential output of channel 4 high
comparator.
Channel 4 Low-Comparator Output. Differential output of channel 4 low
comparator.
Channel 3 High-Comparator Output. Differential output of channel 3 high
comparator.
NCH3
CL3
Channel 3 Low-Comparator Output. Differential output of channel 3 low
comparator.
NCL3
signal levels, with optional 100Ω differential input termi-
Detailed Description
nations. Optional internal resistors at DATA_ and RCV_
provide differential termination of LVDS inputs. Optional
internal resistors at CH_ and CL_ provide the pullup
voltage and source termination for open-collector com-
parator outputs. These options significantly reduce the
discrete component count on the circuit board.
The MAX9963/MAX9964 four-channel, high-speed pin
electronics driver and comparator ICs for automatic
test equipment include, for each channel, a three-level
pin driver, a dual comparator, and variable clamps
(Figure 1). The driver features a -1.5V to +6.5V operat-
ing range and high-speed operation, including high-Z
and active termination (3rd-level drive) modes, which is
highly linear even at low-voltage swings. The comparator
provides low timing dispersion regardless of changes in
input slew rate and pulse width. The clamps provide
damping of high-speed DUT_ waveforms when the
device is configured as a high-impedance receiver.
The MAX9963/MAX9964 are available in two grade
options. An A-grade version provides tighter matching
of gain and offset of the drivers, and tighter offset
matching of the comparators. This allows reference lev-
els to be shared across multiple channels in cost-sensi-
tive systems. A B-grade version provides lower cost for
system designs that incorporate independent reference
levels for each channel.
Each of the four channels has high-speed, differential
inputs compatible with ECL, LVPECL, LVDS, and GTL
______________________________________________________________________________________ 17
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
ONE OF FOUR IDENTICAL CHANNELS SHOWN
MAX9963
MAX9964
SLEW-
RATE
CONTROL
DLV_
DHV_
DTV_
MULTIPLEXER
BUFFER
50Ω
DUT_
OPTIONAL
SC0 SC1
LLEAK
100Ω
DATA_
NDATA_
RCV_
HIGH-Z
NRCV_
100Ω
TMSEL
OPTIONAL
CPHV_
CLAMPS
CPLV_
CHV_
CH_
NCH_
7Ω
7Ω
COMPARATORS
4 x 43Ω
OPTIONAL
V
CCO
_ _
CL_
NCL_
CLV_
TEMP
CH_ MODE BITS
SERIAL INTERFACE IS COMMON TO ALL FOUR CHANNELS.
MODE BITS ARE INDEPENDENTLY
V
V
CC
LLEAK
SC0
LATCHED FOR EACH CHANNEL.
CS
SCLK
DIN
SERIAL
INTERFACE
EE
SC1
GND
RST
TMSEL
Figure 1. MAX9963/MAX9964 Block Diagram
18 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
HIGH-
SPEED
INPUTS
REFERENCE
INPUTS
0
1
DLV_
0
1
0
SLEW RATE
BUFFER
DHV_
DTV_
0
50Ω
DUT_
1
DATA_
RCV_
CPHV_
CPLV_
CLAMPS
4
MODE
COMPARATORS
Figure 2. Simplified Driver Channel
Table 1. Slew Rate Logic
The MAX9963/MAX9964 modal operation is pro-
grammed through a 3-wire, low-voltage CMOS-compat-
ible serial interface.
SC1
SC0
DRIVER SLEW RATE (%)
0
0
1
1
0
1
0
1
100
75
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs, DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_
and RCV_, and mode control bit TMSEL. A slew rate
circuit controls the slew rate of the buffer input. One of
four possible slew rates can be selected (Table 1). The
slew rate of the internal multiplexer sets the 100% dri-
ver slew rate (see the Driver Large-Signal Response
graph in the Typical Operating Characteristics).
50
25
Table 2. Driver Logic
INTERNAL
CONTROL
REGISTER
EXTERNAL
CONNECTIONS
DRIVER OUTPUT
DATA_ RCV_ TMSEL LLEAK
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
in low-leakage mode (Figure 2, Table 2). In high-imped-
ance mode, the clamps are connected. This switching
is controlled by high-speed input RCV_ and mode con-
trol bits TMSEL and LLEAK. In high-impedance mode,
the bias current at DUT_ is less than 3µA, while the
node maintains its ability to track high-speed signals. In
1
0
0
0
X
X
0
0
Drive to DHV_
Drive to DLV_
Drive to DTV_
(term mode)
X
1
1
0
High-impedance
(high-z) mode
X
X
1
X
0
X
0
1
Low-leakage mode
______________________________________________________________________________________ 19
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
low-leakage mode, the bias current at DUT_ is further
reduced to less than 15nA, and signal tracking slows.
DUT_ voltage range; overvoltage protection remains
active without loading DUT_.
The nominal driver output resistance is 50Ω. Contact
the factory for different resistance values within the
45Ω to 51Ω range.
Comparators
The MAX9963/MAX9964 have two independent high-
speed comparators for each channel. Each comparator
has one input connected internally to DUT_ and the
other input connected to either CHV_ or CLV_
(Figure 1). Comparator outputs are a logical result of
the input conditions, as indicated in Table 3.
Clamps
A pair of voltage clamps (high and low) can be config-
ured to limit the voltage at DUT_, and to suppress
reflections when the channel is configured as a high-
impedance receiver. The clamps behave as diodes
connected to the outputs of high-current buffers.
Internal circuitry compensates for the diode drop at
1mA clamp current. Set the clamp voltages using exter-
nal connections CPHV_ and CPLV_. The clamps are
enabled only when the driver is in the high-impedance
mode (Figure 2). For transient suppression, set the
clamp voltages to approximately the minimum and
maximum expected DUT_ voltage range. The optimal
clamp voltages are application specific and must be
empirically determined. If clamping is not desired, set
the clamp voltages at least 0.7V outside the expected
Three configurations are available for the comparator
differential outputs to ease interfacing with a wide vari-
ety of logic families. An open-collector configuration
switches an 8mA current source between the two out-
puts. This configuration is available with and without
internal termination resistors connected to V
CCO_ _
(Figure 3). For versions without internal termination
resistors, leave V unconnected and add the
CCO_ _
required external resistors. These resistors are typically
50Ω to the pullup voltage at the receiving end of the
output trace. Alternate configurations can be used, pro-
vided that the Absolute Maximum Ratings are not
exceeded. For versions with internal terminations, con-
nect V
to the desired V
provides a nominal 400mV
termination.
voltage. Each output
OH
swing and 50Ω source
CCO_ _
Table 3. Comparator Logic
P-P
DUT_ > CHV_
DUT_ > CLV_
CH_
CL_
0
0
0
1
1
0
1
0
1
0
0
1
1
1
0
CH_
1
100Ω
100Ω
DUT_
CHV_
CH_
8mA
DUT_
CHV_
NCH_
V
EE
NCH_
V
_ _
CCO
7Ω
7Ω
CL_
4 x 43Ω
OPTIONAL
V
_ _
CCO
100Ω
100Ω
CL_
8mA
CLV_
CLV_
NCL_
V
EE
NCL_
Figure 3. Open-Collector Comparator Outputs
Figure 4. Open-Emitter Comparator Outputs
20 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
An open-emitter configuration is also available (Figure
Table 4. Shift Register Functions
4). Connect an external collector voltage to V
CCO_ _
and add external pulldown resistors. These resistors
- 2V at the receiving end
of the output trace. Alternate configurations can be
used, provided that the Absolute Maximum Ratings are
not exceeded.
BIT
NAME
DESCRIPTION
are typically 50Ω to V
CCO_ _
Channel 1 Write Enable. Set to 1 to
update the control byte for channel 1. Set
to zero to make no changes to channel 1.
D7
1E
Channel 2 Write Enable. Set to 1 to
update the control byte for channel 2. Set
to zero to make no changes to channel 2.
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST
places the MAX9963/MAX9964 into a very-low-leakage
state in which the DUT_ input current is less than 10nA
over the 0 to 3V range. In this mode, the comparators
still function at full speed but the driver and clamps are
disabled. This mode is convenient for making IDDQ
and PMU measurements without the need for an output
disconnect relay. LLEAK is programmed independently
for each channel.
D6
D5
D4
2E
3E
4E
Channel 3 Write Enable. Set to 1 to
update the control byte for channel 3. Set
to zero to make no changes to channel 3.
Channel 4 Write Enable. Set to 1 to
update the control byte for channel 4. Set
to zero to make no changes to channel 4.
If DUT_ is driven with a high-speed signal while LLEAK
is asserted, leakage current momentarily increases
beyond the limits specified for normal operation. The
low-leakage recovery specification in the Electrical
Characteristics table indicates device behavior under
this condition.
Low-Leakage Select. Set to 1 to put driver
and clamps into a low-leakage mode.
LLEAK Comparators remain active in low-
leakage mode. Set to zero for normal
operation.
D3
D2
D1
SC1
SC0
Driver Slew-Rate Select. SC1 and SC0 set
the driver slew rate. See Table 1.
Temperature Monitor
Each device supplies a single temperature output sig-
nal, TEMP, that asserts a nominal output voltage of
3.43V at a die temperature of +70°C (343K). The output
voltage increases proportionately with temperature at a
rate of 10mV/°C. The temperature sensor output imped-
ance is 15kΩ (typ).
Driver Termination Select. Set to 1 to
force the driver output to the DTV_
voltage (term mode) when RCV_ = 1. Set
to zero to place the driver into a high-
impedance state (high-Z mode) when
RCV_ = 1. See Table 2.
D0
TMSEL
t
CH
SCLK
t
t
t
CSS0
CSS1
CL
t
CSH1
CS
t
CSWH
t
DH
t
DS
DIN
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Serial Interface Timing
______________________________________________________________________________________ 21
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Serial Interface and Device Control
Heat Removal
A CMOS-compatible serial interface controls the
These devices require heat removal under normal cir-
cumstances through the exposed pad, either by solder-
ing to circuit board copper (MAX9964) or by use of an
external heat sink (MAX9963). The exposed pad is
electrically at VEE potential for both package types, and
must be either connected to VEE or isolated.
MAX9963/MAX9964 modes (Figure 6). Control data flow
into an 8-bit shift register (MSB first) and are latched
when CS is taken high, as shown in Figure 5. Data from
the shift register are then loaded into any or all of a
group of four quad latches, determined by bits D4
through D7, as indicated in Figure 6 and Table 4. The
quad latches contain the 4 mode bits for each channel
of the quad pin driver. The mode bits, in conjunction
with external inputs DATA_ and RCV_, manage the fea-
tures of each channel, as shown in Tables 1 and 2. RST
sets LLEAK=1 for all channels, forcing them into low-
leakage mode. All other bits are unaffected. At power-
Chip Information
TRANSISTOR COUNT: 6499
PROCESS: Bipolar
Package Information
up, hold RST low until V
and V have stabilized.
EE
CC
For the latest package outline information, go to
www.maxim-ic.com/packages.
SHIFT REGISTER
SCLK
DIN
CS
0
1
2
3
4
5
6
7
ENABLE
F/F
F/F
F/F
F/F
3
7
3
6
3
5
3
4
D
Q
D
Q
D
Q
D
Q
ENABLE
RST
ENABLE
RST
ENABLE
RST
ENABLE
RST
RST
F/F
D
F/F
D
F/F
D
F/F
D
0-2
7
0-2
6
0-2
5
0-2
4
Q
Q
Q
Q
3
1
3
1
3
1
3
1
ENABLE
ENABLE
ENABLE
ENABLE
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 1
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 2
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 3
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 4
Figure 6. Serial Interface
22 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Selector Guide
COMPARATOR
OUTPUT
TERMINATION
HIGH-SPEED
DIGITAL INPUT
TERMINATION
ACCURACY
GRADE
COMPARATOR
OUTPUT TYPE
HEAT
EXTRACTION
PART
PIN-PACKAGE
MAX9963ADCCQ*
MAX9963AKCCQ*
MAX9963AGCCQ*
MAX9963AHCCQ*
MAX9963AJCCQ
MAX9963BDCCQ*
MAX9963BKCCQ*
MAX9963BGCCQ
MAX9963BHCCQ*
MAX9963BJCCQ*
MAX9964ADCCQ*
MAX9964AKCCQ*
MAX9964AGCCQ*
MAX9964AHCCQ*
MAX9964AJCCQ*
MAX9964BDCCQ*
MAX9964BKCCQ*
MAX9964BGCCQ
MAX9964BHCCQ*
MAX9964BJCCQ*
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
Open collector
Open collector
Open collector
Open emitter
Open emitter
Open collector
Open collector
Open collector
Open emitter
Open emitter
Open collector
Open collector
Open collector
Open emitter
Open emitter
Open collector
Open collector
Open collector
Open emitter
Open emitter
None
None
None
Top
Top
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100Ω LVDS
100Ω LVDS
None
50Ω to V
Top
CCO_ _
None
Top
None
None
None
100Ω LVDS
None
Top
Top
100Ω LVDS
100Ω LVDS
None
Top
50Ω to V
Top
CCO_ _
None
None
None
None
Top
100Ω LVDS
None
Top
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
100Ω LVDS
100Ω LVDS
None
50Ω to V
CCO_ _
None
None
None
None
100Ω LVDS
None
100Ω LVDS
100Ω LVDS
None
50Ω to V
CCO_ _
None
None
100Ω LVDS
*Future product—contact factory for availability.
______________________________________________________________________________________ 23
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Pin Configurations
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
75
74
V
34
1
2
CCO
V
CC
DATA4
NDATA4
RCV4
73 DUT4
3
72
71
V
EE
V
EE
4
NRCV4
DATA3
NDATA3
RCV3
5
70 GND
69 N.C.
6
7
68
V
CC
8
67 DUT3
NRCV3
9
V
V
66
65
EE
V
10
EE
GND 11
RST 12
CS 13
EE
64 GND
63
TEMP
MAX9963
62 GND
SCLK 14
DIN 15
61
60
V
V
EE
EE
V
CC
16
59 DUT2
58
NRCV2 17
RCV2 18
V
CC
57 N.C.
56 GND
NDATA2 19
DATA2 20
NRCV1 21
RCV1 22
55
54
V
EE
V
EE
53 DUT1
NDATA1 23
DATA1 24
52
51
V
CC
GND
V
CCO
12 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TQFP-EPR
24 ______________________________________________________________________________________
Quad, Low-Power, 500Mbps
ATE Driver/Comparator
Pin Configurations (continued)
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
75
74
V
12
1
2
CCO
V
CC
DATA1
NDATA1
RCV1
73 DUT1
3
72
71
V
EE
V
EE
4
NRCV1
DATA2
NDATA2
RCV2
5
70 GND
69 N.C.
6
7
68
V
CC
8
67 DUT2
NRCV2
9
V
V
66
65
EE
V
10
CC
DIN 11
EE
SCLK
64 GND
12
63
CS 13
TEMP
MAX9964
62 GND
14
GND 15
16
RST
61
60
V
V
EE
EE
V
EE
59 DUT3
58
NRCV3 17
RCV3 18
V
CC
57 N.C.
56 GND
NDATA3 19
DATA3 20
NRCV4 21
RCV4 22
55
54
V
EE
V
EE
53 DUT4
NDATA4 23
DATA4 24
52
51
V
CC
GND
V
CCO
34 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TQFP-EP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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