MAX9977AKCCQ-D [MAXIM]
PWM Based Peripheral Driver, CMOS, PQCC100, PLASTIC, QFN-100;
| 型号： | MAX9977AKCCQ-D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PWM Based Peripheral Driver, CMOS, PQCC100, PLASTIC, QFN-100 驱动器 |
| 文件： | 总17页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0383; Rev 0; 7/05
Quad, Low-Power, 1200Mbps
ATE Driver
General Description
Features
ꢀ Low Power Dissipation: 0.8W/Channel
ꢀ High Speed: 1200Mbps at 3V and 1800Mbps
The MAX9977 quad, low-power, high-speed, pin-elec-
tronics driver includes, for each channel, a three-level
pin driver. The driver features a wide voltage range and
high-speed operation, includes high-impedance and
active-termination (3rd-level drive) modes, and is highly
linear even at low voltage swings.
P-P
at 1V
P-P
ꢀ Low Timing Dispersion
ꢀ Wide -1.5V to +6.5V Operating Range
ꢀ Interfaces Easily with Most Logic Families
ꢀ Active Termination (3rd-Level Drive)
The MAX9977 provides high-speed, differential control
inputs with internal 50Ω (100Ω LVDS) termination resistors
that allow compatibility with 1.8V and 3.5V terminated
CML, reducing the discrete component count
required on the circuit board. The MAX9977AD has no
internal termination.
ꢀ Internal 50Ω Termination Resistors on Control
Inputs
0.4V
P-P
ꢀ Low Gain and Offset Errors
ꢀ Pin Compatible with the MAX9963 and MAX9965
Quad Drivers
A 3-wire, low-voltage, CMOS-compatible serial interface
programs the low-leakage and tri-state/terminate opera-
tional configurations of the MAX9977.
Ordering Information
EXPOSED
The MAX9977’s operating range is -1.5V to +6.5V (con-
sult factory for other operating ranges), and features a
maximum power dissipation of only 0.8W per channel.
The device is available in a 100-pin, 14mm x 14mm
x 0.1mm body, and 0.5mm pitch TQFP. An exposed
8mm x 8mm die pad on the top of the package facili-
tates efficient heat removal. The device is specified to
operate with an internal die temperature of +60°C to
+100°C, and features a die temperature monitor output.
TEMP
RANGE
PIN-
PACKAGE
PAD
VARIATION
CODE
PART
MAX9977AKCCQ
0°C to +70°C 100 TQFP-IDP** C100E-8R
MAX9977AKCCQ+ 0°C to +70°C 100 TQFP-IDP** C100E-8R
100 TQFP-IDP**
100 TQFP-IDP**
MAX9977ADCCQ* 0°C to +70°C
MAX9977ADCCQ+* 0°C to +70°C
C100E-8R
C100E-8R
*Future product—contact factory for availability.
**IDP = Inverted die pad.
Applications
Medium-Performance System-on-Chip ATE and
Memory Applications
+Denotes lead-free package.
Pin Configuration and Selector Guide appear at end of
data sheet.
Functional Diagram
CH_ MODE BITS
V
V
CC
CS
EE
SERIAL INTERFACE IS COMMON
TO ALL FOUR CHANNELS.
MODE BITS INDEPENDENTLY
LATCHED FOR EACH CHANNEL.
SCLK
DIN
TMSEL
LLEAK
SERIAL INTERFACE
TEMP
GND
RST
THR
DLV_
DHV_
47Ω
MULTIPLEXER
BUFFER
0
DUT_
DTV_
GS
LLEAK
OPTIONAL R
OPTIONAL R
DATA
2 x 50Ω
RCV
2 x 50Ω
V _ _
T
MAX9977
DATA_
NDATA_
RCV_
HIGH IMPEDANCE
NRCV_
TMSEL
ONE OF FOUR IDENTICAL CHANNELS SHOWN.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad, Low-Power, 1200Mbps
ATE Driver
ABSOLUTE MAXIMUM RATINGS
V
V
V
to GND............................................................-0.3V to +11V
to GND..........................................................-5.75V to +0.3V
DHV_ to DTV_ ...................................................................... 10V
DLV_ to DTV_....................................................................... 10V
GS to GND............................................................................. 1V
CC
EE
CC
- V ...........................................................-0.3V to +16.75V
EE
DUT_ to GND.......................................................-2.75V to +7.5V
DATA_, NDATA_, RCV_, NRCV_ to GND.................-2.5V to +5V
DATA_ to NDATA_, RCV_ to NRCV_ .................................. 1.5V
All Other Pins to GND ......................(V - 0.3V) to (V
TEMP Current...................................................-0.5mA to +20mA
DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous
+ 0.3V)
EE
CC
V 12, V 34 to GND...................................................-2.5V to +5V
Continuous Power Dissipation (T = +70°C)
T
T
A
DATA_, NDATA_, RCV_, NRCV_ to V 12 or V 34 ................. 2V
100-Pin TQFP (derate 167mW/°C above +70°C) .........13.3W*
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
T
T
SCLK, DIN, CS, RST to GND ......................................-1V to +5V
DHV_, DLV_, DTV_ to GND ...................................-2.5V to +7.5V
DHV_ to DLV_ ...................................................................... 10V
*Dissipation wattage values are based on still air with no heat sink. Actual maximum power dissipation is a function of heat extraction
technique and may be substantially higher.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +9.75V, V = -4.75V, V = 0, V 12 = V 34 = 1.8V, T = +85°C, unless otherwise noted. All temperature coefficients are measured
CC
EE
GS
T
T
J
at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
POWER SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply
Negative Supply
V
9.5
9.75
-4.75
192
175
-224
-207
3.0
10.5
-4.50
215
196
-251
-232
3.3
V
V
CC
V
-5.25
EE
Drivers active
Positive Supply Current (Note 2)
Negative Supply Current (Note 2)
Power Dissipation (Note 2)
I
mA
mA
W
CC
Drivers in high impedance
Drivers active
I
EE
Drivers in high impedance
Drivers active
P
D
Drivers in high impedance
2.7
3.1
DUT_ CHARACTERISTICS
Operating Voltage Range
V
(Note 3)
-1.5
+6.5
3
V
DUT
Leakage Current in
High-Impedance Mode
I
LLEAK = 0; V
LLEAK = 1; V
_ = -1.5V, 0, +3V, +6.5V
_ = -1.5V, 0, +3V, +6.5V
µA
DUT
DUT
Leakage Current in
Low-Leakage Mode
5
50
nA
pF
DUT
Driver in term mode (DUT_ = DTV_)
Driver in high-impedance mode
(Notes 4, 5)
2
4
5
6
Combined Capacitance
C
DUT
Low-Leakage Enable Time
Low-Leakage Disable Time
20
0.1
µs
µs
(Notes 5, 6)
Time to return to the specified maximum
leakage after a 3V, 4V/ns step at DUT_
(Notes 5, 6)
Low-Leakage Recovery
5
µs
2
_______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -4.75V, V = 0, V 12 = V 34 = 1.8V, T = +85°C, unless otherwise noted. All temperature coefficients are measured
CC
EE
GS
T
T
J
at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONTROL AND LEVELS INPUTS
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_)
Input Bias Current
Settling Time
I
25
µA
µs
BIAS
To 0.1% of full-scale change
1
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_)
Input High Voltage
Input Low Voltage
V
0
3.5
V
V
IHD
V
-0.2
0.15
+3.2
1.00
ILD
Between differential inputs
Differential Input Voltage
V
V
DIFF
Between a differential input and its
termination voltage
1.9
+3.5
52.5
Input Termination Voltage
Input Termination Resistor
V
0
V
T_ _
Between signal and corresponding
termination voltage input
47.5
50
Ω
SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST)
Internal Threshold Reference
V
1.05
1.25
20
1.45
V
kΩ
V
THRINT
Internal Reference Output
Resistance
R
O
External Threshold Reference
V
0.43
1.73
3.5
THR
V
+
THR
0.2
Input High Voltage
V
V
IH
V
-
THR
0.2
Input Low Voltage
Input Bias Current
V
-0.1
V
IL
I
25
µA
B
SERIAL INTERFACE TIMING (Figure 4)
SCLK Frequency
f
50
MHz
ns
SCLK
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
CS Pulse-Width High
t
8
CH
t
8
ns
CL
t
t
3.5
3.5
3.5
3.5
3.5
20
ns
CSS0
CSS1
CSH1
ns
t
ns
t
ns
DS
DH
t
ns
t
ns
CSWH
TEMPERATURE MONITOR (TEMP)
Nominal Voltage
T = +70°C, R ≥ 10MΩ
3.33
+10
20
V
J
L
Temperature Coefficient
Output Resistance
mV/°C
kΩ
_______________________________________________________________________________________
3
Quad, Low-Power, 1200Mbps
ATE Driver
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -4.75V, V = 0, V 12 = V 34 = 1.8V, T = +85°C, unless otherwise noted. All temperature coefficients are measured
CC
EE
GS
T
T
J
at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
DRIVERS (Note 7)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC OUTPUT CHARACTERISTICS (R ≥ 10MΩ)
L
DHV_, DLV_, DTV_
Output Offset Voltage
At DUT_ with V
independently tested at +1.5V
_, V
_, V
_
DHV
DTV
DLV
V
15
mV
mV
OS
V
V
= +100mV, V
_ = 6.5V + 100mV
DHV
2
2
GS
GS
Output Offset Voltage Due to
Ground Sense
V
GSOS
= -100mV, V
_ = -1.5V - 100mV
DLV
DHV_, DLV_, DTV_ Output Offset
Temperature Coefficient
+200
1.00
-50
µV/°C
V/V
Measured with V
and V
_, V
_,
DHV
DLV
DHV_, DLV_, DTV_ Gain
A
V
0.997
1.003
_ at 0 and 4.5V
DTV
DHV_, DLV_, DTV_ Gain
Temperature Coefficient
ppm/°C
mV
V
_ = 1.5V, 3V (Note 8)
DUT
5
15
2
Linearity Error
Full range (Notes 8, 9)
DHV_ to DLV_ Crosstalk
DLV_ to DHV_ Crosstalk
V
V
_ = 0; V
_ = 200mV, 6.5V
DHV
mV
mV
DLV
DHV
_ = 5V; V
_ = -1.5V, +4.8V
2
DLV
DTV_ to DLV_ and DHV_
Crosstalk
V
V
_ = 3V; V
_ = -1.5V, +6.5V
_ = 0;
DHV
DLV
2
mV
DTV
DHV_ to DTV_ Crosstalk
DLV_ to DTV_ Crosstalk
V
V
_ = 1.5V; V
_ = 1.5V; V
_ = 0; V _ = 1.6V, 3V
DHV
2
2
mV
mV
DTV
DLV
_ = 3V; V _ = 0, 1.4V
DHV DLV
DTV
DHV_, DTV_, DLV_ DC
Power-Supply Rejection Ratio
PSRR
(Note 10)
18
mV/V
Maximum DC Drive Current
DC Output Resistance
I
_
40
46
80
48
1
mA
DUT
R
_
DUT
I
I
I
_ = 30mA (Note 11)
_ = 1mA, 8mA
47
0.5
Ω
DUT
DUT
DUT
DC Output Resistance Variation
∆R
_
Ω
DUT
_ = 1mA, 8mA, 15mA, 40mA
0.75
1.5
DYNAMIC OUTPUT CHARACTERISTICS (Z = 50Ω)
L
AC Drive Current
80
mA
mV
V
V
V
V
V
V
V
V
V
V
_ = 0, V
_ = 0, V
_ = 0, V
_ = 0, V
_ = 0, V
_ = 0, V
_ = 0.1V
_ = 1V
_ = 3V
_ = 0.1V
_ = 1V
_ = 3V
15
110
210
4
22
130
370
11
DLV
DLV
DLV
DLV
DLV
DLV
DHV
DHV
DHV
DHV
DHV
DHV
DHV
Drive-Mode Overshoot
Drive-Mode Undershoot
20
65
mV
30
185
250
250
_ = V
_ = 1V, V
_ = 0
180
180
100
100
DTV
DLV
Term-Mode Spike
mV
mV
_ = V
_ = 0, V
_ = 1V
DHV
DLV
DLV
DLV
DTV
_ = -1.0V, V
_ = 0
DHV
High-Impedance-Mode Spike
_ = 0, V
_ = 1V
DHV
4
_______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -4.75V, V = 0, V 12 = V 34 = 1.8V, T = +85°C, unless otherwise noted. All temperature coefficients are measured
CC
EE
GS
T
T
J
at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
Settling Time to within 25mV
Settling Time to within 5mV
SYMBOL
CONDITIONS
MIN
TYP
4
MAX
UNITS
ns
3V step (Note 12)
3V step (Note 12)
40
ns
TIMING CHARACTERISTICS (Z = 50Ω) (Note 13)
L
Prop Delay, Data to Output
Prop Delay Match, t vs. t
t
1.2
1.5
40
1.9
ns
ps
PDD
3V
P-P
100
LH
HL
Prop Delay Match, Drivers within
Package
(Note 14)
40
+1.6
25
ps
Prop-Delay Temperature
Coefficient
ps/°C
0.2V , 40MHz, 0.6ns to 24.4ns pulse
P-P
width, relative to 12.5ns pulse width
50
50
55
60
1V , 40MHz, 0.6ns to 24.4ns pulse width,
P-P
relative to 12.5ns pulse width
25
2V , 40MHz, 0.75ns to 24.25ns pulse
P-P
width, relative to 12.5ns pulse width
Prop Delay Change vs.
Pulse Width
30
ps
3V , 40MHz, 0.9ns to 24.1ns pulse width,
P-P
relative to 12.5ns pulse width
35
5V , Z = 500Ω, 40MHz, 1.4ns to 23.6ns
pulse width, relative to 12.5ns pulse width
P-P
L
100
50
Prop Delay Change vs.
Common-Mode Voltage
V
V
V
_ - V
_ = 1V, V _ = 0 to 6V
DHV
75
2.6
3.9
-0.7
ps
ns
ns
ns
DHV
DHV
DHV
DLV
Prop Delay, Drive to
High Impedance
t
t
_ = 1.0V, V
_ = -1.0V, V
_ = -1.0V, V
_ = 0
_ = 0
1.6
2.6
2.1
3.2
-1.1
PDDZ
PDZD
DLV
DLV
DTV
Prop Delay, High
Impedance to Drive
_ = 1.0V, V
DTV
Prop Delay Match,
-1.5
t
vs. t
PDZD
PDDZ
Prop Delay Match, t
vs. t
0.2
1.3
0.6
1.8
1.0
2.3
ns
ns
ns
ns
ns
PDDZ
LH
Prop Delay, Drive to Term
Prop Delay, Term to Drive
t
t
V
V
_ = 3V, V
_ = 3V, V
_ = 0, V
_ = 0, V
_ = 1.5V
_ = 1.5V
PDDT
PDTD
DHV
DLV
DTV
1.6
2.1
2.7
DHV
DLV
DTV
Prop Delay Match, t
vs. t
-0.7
-0.1
-0.3
+0.3
-0.1
+0.7
PDDT
PDTD
Prop Delay Match, t
vs. t
LH
PDDT
DYNAMIC PERFORMANCE (Z = 50Ω)
L
0.2V , 10% to 90%
260
330
430
500
800
310
390
500
650
1000
50
360
450
570
750
1200
P-P
1V , 10% to 90%
P-P
2V , 10% to 90%
P-P
Rise and Fall Time
t , t
ps
ps
R
F
3V , 10% to 90%
P-P
5V , Z = 500Ω, 10% to 90%
P-P
L
Rise and Fall Time Match
t
vs. t
3V , 10% to 90%
P-P
R
F
_______________________________________________________________________________________
5
Quad, Low-Power, 1200Mbps
ATE Driver
ELECTRICAL CHARACTERISTICS (continued)
(V = +9.75V, V = -4.75V, V = 0, V 12 = V 34 = 1.8V, T = +85°C, unless otherwise noted. All temperature coefficients are measured
CC
EE
GS
T
T
J
at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
550
MAX
UNITS
0.2V
P-P
1V
2V
3V
550
630
750
P-P
Minimum Pulse Width
(Note 15)
650
ps
P-P
P-P
850
1000
5V , Z = 500Ω
1300
1800
1800
1500
1200
800
P-P
L
0.2V
P-P
1V
2V
3V
P-P
Data Rate
(Note 16)
Mbps
P-P
P-P
5V , Z = 500Ω
P-P
L
Dynamic Crosstalk
(Note 17)
15
mV
P-P
V
_ = 3V, V
_ = 0, V
_ = 1.5V,
DTV
DHV
DLV
Rise and Fall Time, Drive to Term
t
t
, t
0.6
0.6
1.0
1.0
1.3
1.3
ns
DTR DTF
10% to 90%, Figure 1a (Note 18)
V
_ = 3V, V _ = 0, V _ = 1.5V,
DHV
DLV
DTV
Rise and Fall Time, Term to Drive
, t
ns
TDR TDF
10% to 90%, Figure 1b (Note 18)
GROUND SENSE
GS Voltage Range
GS Input Bias Current
V
250
mV
µA
GS
V
= 0
25
GS
Note 1: Unless otherwise specified, all minimum and maximum DC and AC driver 3V rise and fall time test limits are 100% tested at
production. All other test limits are guaranteed by design. All tests are performed at nominal supply voltages, unless other-
wise noted.
Note 2: Total is for a quad device and is specified at the worst-case setting. The supply currents are measured with typical supply
voltages.
Note 3: Externally forced voltages may exceed this range provided that the Absolute Maximum Ratings are not exceeded.
Note 4: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 5: Based on simulation results only.
Note 6: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 7: With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 8: Specifications measured at the end points of the full range. Full range is -1.3V ≤ V
≤ +6.5V, -1.5V ≤ V
≤ +6.3V,
DLV_
DHV_
-1.5V ≤ V
≤ +6.5V.
DTV_
Note 9: Relative to straight line between 0 and 4.5V.
Note 10: Change in offset voltage with power supplies independently set to their minimum and maximum values.
Note 11: Nominal target value is 47Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range.
Note 12: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
Note 13: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output
swing. Rise time of the differential inputs DATA_ and RCV_ are 250ps (10% to 90%).
Note 14: Rising edge to rising edge or falling edge to falling edge.
Note 15: Specified amplitude is programmed. At this pulse width, the output reaches at least 90% of its nominal (DC) amplitude. The
pulse width is measured at DATA_.
Note 16: Specified amplitude is programmed. Maximum data rate is specified in transitions per second. A square wave that reaches
at least 90% of its programmed amplitude may be generated at one-half of this frequency.
Note 17: Crosstalk from one driver to any other. Aggressor channel is driving 3V
into a 50Ω load. Victim channel is in term mode
P-P
with V
= +1.5V.
DTV_
Note 18: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when V
< V
< V
. If
DHV_
DLV_
DTV_
V
< V
or V
> V
, switching speed is degraded by a factor of approximately 3.
DHV_
DTV_
DLV_
DTV_
6
_______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
t
DTF
90%
DHV_
DLV_
10%
90%
DTV_
10%
t
DTR
(a) DRIVE-TO-TERM RISE AND FALL TIME
t
TDR
90%
DHV_
10%
90%
DTV_
DLV_
TDF
10%
t
(b) TERM-TO-DRIVE RISE AND FALL TIME
Figure 1. Drive-to-Term and Term-to-Drive Rise and Fall Times
Typical Operating Characteristics
(V = +9.75V, V = -4.75V, V = 0, T = +85°C, unless otherwise noted.)
CC
EE
GS
J
DRIVER LARGE-SIGNAL RESPONSE
INTO 500Ω
DRIVER SMALL-SIGNAL RESPONSE
DRIVER LARGE-SIGNAL RESPONSE
V
= 0
V
= 0
V
= 0
DLV_
R = 500Ω
L
DLV_
R = 50Ω
L
DLV_
R = 50Ω
L
V
= 5V
= 3V
= 1V
DHV_
V
= 5V
= 3V
= 1V
V
= 500mV
DHV_
DHV_
V
V
DHV_
DHV_
DHV_
V
= 200mV
= 100mV
DHV_
DHV_
V
V
DHV_
V
0
0
0
t = 2.0ns/div
t = 2.0ns/div
t = 2.0ns/div
_______________________________________________________________________________________
7
Quad, Low-Power, 1200Mbps
ATE Driver
Typical Operating Characteristics (continued)
(V = +9.75V, V = -4.75V, V = 0, T = +85°C, unless otherwise noted.)
CC
EE
GS
J
DRIVER 1V, 600Mbps
SIGNAL RESPONSE
DRIVER 1V, 1800Mbps
SIGNAL RESPONSE
DRIVER 3V, 400Mbps
SIGNAL RESPONSE
V
V
= 0
V
= 0, V
= 1V, R = 50Ω
V
= 0, V
= 1V, R = 50Ω
DLV_
DHV_
L
DLV_
DHV_
L
DLV_
DHV_
L
= 3V
R = 50Ω
0
0
0
t = 1ns/div
t = 500ps/div
t = 1ns/div
DRIVER 3V, 1200Mbps
SIGNAL RESPONSE
DRIVER DYNAMIC
CURRENT-LIMIT RESPONSE
DRIVER 3V TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH
40
V
V
= 0
= 3V
R = 50Ω
DLV_
DHV_
L
20
0
DRIVER SOURCING
DRIVER SINKING
-20
-40
-60
-80
0
0
NORMALIZED AT PW = 12.5ns
-100
-120
PERIOD = 25ns, V
= +3V, V
= 0
R = 10Ω
L
DHV_
DLV_
t = 500ps/div
t = 50ns/div
0
5
10
15
20
25
PULSE WIDTH (ns)
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
DRIVER 1V TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH
DRIVE TO TERM TRANSITION
20
15
60
50
40
30
20
10
0
NORMALIZED AT PW = 12.5ns
PERIOD = 25ns, V
= +1V, V
= 0
DHV_
DLV_
10
DHV_ TO DTV_
5
0
-5
-10
-15
-20
-25
-30
DLV_ TO DTV_
-10
-20
0
R = 50Ω
L
NORMALIZED AT V = 1.5V
CM
0
5
10
15
20
25
-1
0
1
2
3
4
5
6
t = 2.0ns/div
PULSE WIDTH (ns)
COMMON-MODE VOLTAGE (V)
8
_______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
Typical Operating Characteristics (continued)
(V = +9.75V, V = -4.75V, V = 0, T = +85°C, unless otherwise noted.)
CC
EE
GS
J
DRIVE TO
HIGH-IMPEDANCE TRANSITION
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
12
10
8
8
6
DUT_ = DHV_
DUT_ = DLV_
DHV_ TO HIGH IMPEDANCE
V
V
= -1.5V
= 0
V
V
= +6.5V
= 0
DLV_
DTV_
DHV_
DTV_
4
6
2
0
4
0
2
-2
-4
-6
-8
0
-2
-4
DLV_ TO HIGH IMPEDANCE
R = 50Ω
L
t = 2.0ns/div
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
DUT_
DUT_
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
CROSSTALK TO DUT_ FROM
DLV_ WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM
DHV_ WITH DUT_ = DLV_
7
6
1.0
0.8
1.0
0.8
V
V
= 5V
DHV_
DTV_
V
V
= 0
= 1.5V
DUT_ = DTV_
DLV_
DTV_
= 1.5V
V
V
= -1.5V
= +6.5V
DLV_
DHV_
0.6
0.6
5
0.4
4
0.4
3
0.2
0.2
2
0
0
1
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
-1
-2
-3
NORMALIZED AT V
= 5V
NORMALIZED AT V
= 0
DHV_
DLV_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
V
DHV_
DUT_
DLV_
CROSSTALK TO DUT_ FROM
DTV_ WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM
DTV_ WITH DUT_ = DLV_
CROSSTALK TO DUT_ FROM
DLV_ WITH DUT_ = DTV_
1.0
0.8
1.0
0.8
1.0
0.8
V
V
= 6.5V
= 0
V
V
= 6.5V
DHV_
DTV_
V
V
= 3V
= 0
DHV_
DLV_
DHV_
DLV_
= 1.5V
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
NORMALIZED AT V
= 1.5V
NORMALIZED AT V
= 1.5V
NORMALIZED AT V
= 0
DTV_
DTV_
DLV_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
V
DLV_
DTV_
DTV_
_______________________________________________________________________________________
9
Quad, Low-Power, 1200Mbps
ATE Driver
Typical Operating Characteristics (continued)
(V = +9.75V, V = -4.75V, V = 0, T = +85°C, unless otherwise noted.)
CC
EE
GS
J
CROSSTALK TO DUT_ FROM
DHV_ WITH DUT_ = DTV_
DRIVER GAIN vs. TEMPERATURE
DRIVER OFFSET vs. TEMPERATURE
1.0
1.0012
1.0010
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.9992
4
3
V
V
= 1.5V
= -1.5V
DTV_
DLV_
0.8
0.6
2
0.4
1
0.2
0
0
-1
-2
-3
-4
-5
-0.2
-0.4
-0.6
-0.8
-1.0
NORMALIZED AT V
= 3V
NORMALIZED AT T = +85°C
DHV_
J
NORMALIZED AT T = +85°C
J
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
60 65 70 75 80 85 90 95 100
60 65 70 75 80 85 90 95 100
V
DIE TEMPERATURE (°C)
DIE TEMPERATURE (°C)
DHV_
HIGH-IMPEDANCE CURRENT
vs. DUT_ VOLTAGE
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
DRIVE 1V TO
LOW-LEAKAGE TRANSITION
2
1
-0.50
-0.55
-0.60
-0.65
-0.70
-0.75
-0.80
-0.85
-0.90
-0.95
-1.00
-1.05
-1.10
R = 50Ω
L
L
C = 10pF
0
-1
-2
-3
-4
-5
0
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
0
t = 1ns/div
V
(V)
V
(V)
DUT_
DUT_
LOW-LEAKAGE TO
DRIVE 1V TRANSITION
DRIVER REFERENCE CURRENT
vs. DRIVER REFERENCE VOLTAGE
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
R = 50Ω
L
L
C = 10pF
DHV_
DLV_
DTV_
0
0
t = 1ns/div
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
REFERENCE VOLTAGE (V)
10 ______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
Typical Operating Characteristics (continued)
(V = +9.75V, V = -4.75V, V = 0, T = +85°C, unless otherwise noted.)
CC
EE
GS
J
SUPPLY CURRENT I vs.
EE
SUPPLY CURRENT I
vs. VOLTAGE CURRENT V
CC
VOLTAGE CURRENT V
EE
CC
200
195
190
185
180
175
170
165
160
-190
-195
-200
-205
-210
-215
-220
-225
-230
A
B
A
B
9.5
9.7
= V
9.9
10.1
10.3
10.5
-5.25
-5.10
-4.95
-4.80
DHV_
-4.65
-4.50
V
(V)
V
(V)
CC
EE
A: V
= 1.5V, V
= 3V, V
= 0,
A: V
= V
= 1.5V, V
= 3V, V
= 0,
DUT_
L
DTV_
DHV_
DLV_
DUT_
DTV_
DLV_
R = 10kΩ, V = -4.75V
B: SAME AS A EXCEPT DRIVER IN HIGH-IMPEDANCE
R = 10kΩ, V = 9.75V
EE
L CC
B: SAME AS A EXCEPT DRIVER IN HIGH-IMPEDANCE
MODE
MODE
DRIVER OUTPUT-VOLTAGE ERROR
vs. GROUND-SENSE VOLTAGE
SUPPLY CURRENT I vs. TEMPERATURE
SUPPLY CURRENT I vs. TEMPERATURE
CC
EE
8
6
210
-200
-205
-210
-215
-220
-225
-230
-235
-240
V
= V
= 1.5V, V
CC
= 3V, V
= 0,
V
= V
= 1.5V, V
= 3V, V
= 0,
DUT_
DTV_
DHV_
EE
DLV_
DUT_
DTV_
DHV_
DLV_
205
200
195
190
185
180
175
170
165
160
R = 10kΩ, V = 9.75V, V = -4.75V
L
R = 10kΩ, V = 9.75V, V = -4.75V
L CC EE
V
= V
= 3V
DUT_
DHV_
4
2
0
-2
-4
-6
-8
-10
-12
V
= V
= -1.5V
DUT_
DLV_
V
= 1.5V, R = 10kΩ,
L
DTV_
NORMALIZED AT V = 0
GS
-250
-150
-50
V
50
150
250
80
85
90
TEMPERATURE (°C)
95
100
80
85
90
TEMPERATURE (°C)
95
100
(mV)
GS
______________________________________________________________________________________ 11
Quad, Low-Power, 1200Mbps
ATE Driver
Pin Description
PIN
NAME
FUNCTION
Channel 3/4 Termination Voltage Input Differential Inputs, DATA3, NDATA3, RCV3, NRCV3, DATA4,
NDATA4, RCV4, and NRCV4. See the Functional Diagram.
1
V 34
T
Channel 4 Multiplexer Control Inputs. Differential controls DATA4 and NDATA4 select driver 4’s input
from DHV4 or DLV4. Drive DATA4 above NDATA4 to select DHV4. Drive NDATA4 above DATA4 to
select DLV4. See Table 1.
2
3
DATA4
NDATA4
Channel 4 Multiplexer Control Inputs. Differential controls RCV4 and NRCV4 place channel 4 into
receive mode. Drive RCV4 above NRCV4 to place channel 4 into receive mode. Drive NRCV4 above
RCV4 to place channel 4 into drive mode. See Table 1.
Channel 3 Multiplexer Control Inputs. Differential controls DATA3 and NDATA3 select driver 3’s input
from DHV3 or DLV3. Drive DATA3 above NDATA3 to select DHV3. Drive NDATA3 above DATA3 to
select DLV3. See Table 1.
Channel 3 Multiplexer Control Inputs. Differential controls RCV3 and NRCV3 place channel 3 into
receive mode. Drive RCV3 above NRCV3 to place channel 3 into receive mode. Drive NRCV3 above
RCV3 to place channel 3 into drive mode. See Table 1.
4
5
6
7
8
9
RCV4
NRCV4
DATA3
NDATA3
RCV3
NRCV3
10, 27, 54, 55,
60, 61, 65, 66,
71, 72, 99
V
Negative Power-Supply Input
Ground Connection
EE
11, 28, 51, 56,
62, 64, 70, 75,
98
GND
12
13
RST
CS
Reset Input. Asynchronous reset input for the serial register. RST is active low. See Figure 3.
Chip-Select Input. Serial-port activation input. CS is active low.
Serial-Clock Input. Clock for serial port.
14
15
SCLK
DIN
Data Input. Serial-port data input.
16, 26, 52, 58,
68, 74, 100
V
Positive Power-Supply Input
CC
Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 into
receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2 above
RCV2 to place channel 2 into drive mode. See Table 1.
Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2’s input
from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above DATA2 to
select DLV2. See Table 1.
Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 into
receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1 above
RCV1 to place channel 1 into drive mode. See Table 1.
17
18
19
20
21
22
NRCV2
RCV2
NDATA2
DATA2
NRCV1
RCV1
Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1’s input
from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above DATA1 to
select DLV1. See Table 1.
23
24
NDATA1
DATA1
Channel 1/2 Termination Voltage Input Differential Inputs, DATA1, NDATA1, RCV1, NRCV1, DATA2,
NDATA2, RCV2, and NRCV2. See the Functional Diagram.
25
V 12
T
29–38, 43, 44,
45, 49, 50, 57,
69, 76, 77, 81,
82, 83, 88–97
N.C.
No Connection. Leave unconnected.
12 ______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
Pin Description (continued)
PIN
39
40
41
42
46
47
48
53
59
63
67
73
78
79
80
84
85
86
87
NAME
DHV2
DLV2
DTV2
GS
FUNCTION
Channel 2 Driver High Voltage Input
Channel 2 Driver Low Voltage Input
Channel 2 Driver Termination Voltage Input
Ground-Sense Voltage Input for All Channels
Channel 1 Driver High Voltage Input
DHV1
DLV1
DTV1
DUT1
DUT2
TEMP
DUT3
DUT4
DTV4
DLV4
DHV4
THR
Channel 1 Driver Low Voltage Input
Channel 1 Driver Termination Voltage Input
Channel 1 Device-Under-Test Input/Output
Channel 2 Device-Under-Test Input/Output
Temperature Monitor Output, One per Device
Channel 3 Device-Under-Test Input/Output
Channel 4 Device-Under-Test Input/Output
Channel 4 Driver Termination Voltage Input
Channel 4 Driver Low Voltage Input
Channel 4 Driver High Voltage Input
Single-Ended Logic Threshold Reference for All Channels
Channel 3 Driver Termination Voltage Input
Channel 3 Driver Low Voltage Input
DTV3
DLV3
DHV3
Channel 3 Driver High Voltage Input
2) THR on the MAX9977 is in the position of CHV3 on
Detailed Description
the MAX9963/MAX9965. If CHV3 is being controlled
by a DAC that is referenced to ground sense, reas-
sign this input to a reference that is not affected by
changes in ground sense.
The MAX9977 low-power, high-speed, pin-electronics
IC includes four three-level pin drivers. The drivers fea-
ture a -1.5V to +6.5V operating range and high-speed
operation, include high-impedance and active-termina-
tion (3rd-level drive) modes, and are highly linear even
at low voltage swings.
3) MAX9977AK DRV_ and RCV_ inputs have center
taps V 12 and V 34 for the internal termination
T
T
resistors in the positions of V
and V
of
CCO34
CCO12
Optional internal resistors at the high-speed inputs pro-
vide compatibility with CML interfaces and reduce the
discrete component count on the circuit board. Connect
the MAX9963/MAX9965, the comparator-output
resistor termination points. Bias these termination
points accordingly.
the termination voltage inputs, V 12 and V 34, to a volt-
T
T
age appropriate for the drive circuits to terminate the
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_
and RCV_ and mode-control bit TMSEL (Table 1).
multiplexer control inputs (see the Functional Diagram).
A 3-wire, low-voltage CMOS-compatible serial interface
programs the low-leakage and tri-state/terminate opera-
tional configurations of the MAX9977.
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
into low-leakage mode (Figure 2, Table 1). High-speed
input RCV_ and mode-control bits TMSEL and LLEAK
control the switching. In high-impedance mode, the
bias current at DUT_ is less than 3µA over the -1.5V to
+6.5V range, while the node maintains its ability to track
Compatibility with the MAX9963
and MAX9965
To upgrade from the MAX9963 or MAX9965 to the
MAX9977 take these steps:
1) GS on the MAX9977 is in the position of CHV2 on the
MAX9963/MAX9965. Program CHV2 to zero volts.
______________________________________________________________________________________ 13
Quad, Low-Power, 1200Mbps
ATE Driver
HIGH-SPEED REFERENCE
INPUTS
INPUTS
0
1
DLV_
0
1
47Ω
BUFFER
DUT_
DHV_
DTV_
0
DATA_
RCV_
2
SERIAL
INTERFACE
MAX9977
Figure 2. Simplified Driver Channel
Serial Interface and
Device Control
Table 1. Driver Logic
INTERNAL
EXTERNAL
A CMOS-compatible serial interface controls the
MAX9977 modes (Figure 3 and Table 2). Control data
flow into an 8-bit shift register (MSB first) and are
latched when CS is taken high, as shown in Figure 4.
Latches contain 2 control bits for each channel of the
MAX9977. Data from the shift register are then loaded
to any or all of a group of four quad latches as deter-
mined by bits D4 and D7. The control bits, in conjunc-
tion with external inputs DATA_ and RCV_, manage the
features of each channel. RST sets LLEAK = 1 for all
channels, forcing them into low-leakage mode. All other
bits are unaffected. At power-up, hold RST low until
CONTROL
DRIVER
OUTPUT
CONNECTIONS
REGISTER
DATA
RCV
TMSEL LLEAK
1
0
0
0
X
X
0
0
Drive to DHV_
Drive to DLV_
Drive to DTV_
(term mode)
X
1
1
0
High-impedance mode
(high-Z)
X
X
1
X
0
X
0
1
Low-leakage mode
V
and V have stabilized.
EE
CC
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5V to 3.3V logic.
high-speed signals. In low-leakage mode, the bias cur-
rent at DUT_ is further reduced to less than 50nA, and
signal tracking slows. See the Low-Leakage Mode,
LLEAK section for more details.
The nominal driver output resistance is 47Ω. Contact
the factory for custom resistance values within the 45Ω
to 51Ω range.
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST
places the MAX9977 into a low-leakage state (see the
Electrical Characteristics table). This mode is convenient
14 ______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
SCLK
DIN
CS
SHIFT REGISTER
0
1
2
3
4
5
6
7
MAX9977
ENABLE
F/F
F/F
F/F
F/F
3
7
3
6
3
5
3
4
Q
D
D
Q
D
D
ENABLE
SET
ENABLE
SET
ENABLE
SET
ENABLE
SET
RST
F/F
D
F/F
D
F/F
D
F/F
D
0
6
0
7
0
5
0
4
Q
Q
Q
Q
ENABLE
ENABLE
ENABLE
ENABLE
20kΩ
V
= 1.25V
THR
THRINT
TMSEL
TMSEL
TMSEL
TMSEL
LLEAK
LLEAK
LLEAK
LLEAK
CHANNEL 1 MODE BITS
CHANNEL 2 MODE BITS
CHANNEL 3 MODE BITS
CHANNEL 4 MODE BITS
Figure 3. Serial Interface
Table 2. Serial Interface Bit Description
BIT STATE AFTER
RESET AND AT
POWER-UP
BIT
NAME
DESCRIPTION
Channel 1 Write Enable. Set to 1 to update the control byte for channel 1. Set to 0 to make
no changes to channel 1.
D7
D6
D5
CH1
CH2
CH3
CH4
0
0
0
0
Channel 2 Write Enable. Set to 1 to update the control byte for channel 2. Set to 0 to make
no changes to channel 2.
Channel 3 Write Enable. Set to 1 to update the control byte for channel 3. Set to 0 to make
no changes to channel 3.
Channel 4 Write Enable. Set to 1 to update the control byte for channel 4. Set to 0 to make
no changes to channel 4.
D4
D3
LLEAK Low-Leakage Select. Set to 1 to put driver in low-leakage mode. Set to 0 for normal operation.
1
X
X
0
D2 UNUSED
D1 UNUSED
These bits are not used. Their logic state has no effect.
D0
TMSEL Termination Select. Driver termination select bit.
______________________________________________________________________________________ 15
Quad, Low-Power, 1200Mbps
ATE Driver
t
CH
SCLK
t
t
CSS0
t
CL
CSS1
t
CSH1
CS
t
t
CSWH
DH
t
DS
DIN
D7
D6
D5
D4
D3
D2
D1
D0
Figure 4. Serial-Interface Timing
for making IDDQ and PMU measurements without the
need for an output disconnect relay. LLEAK is pro-
grammed independently for each channel.
Heat Removal
Under normal circumstances, the MAX9977 requires
heat removal through the exposed pad by use of an
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behav-
ior under this condition.
external heat sink. The exposed pad is electrically at V
EE
potential, and must be either connected to V or isolat-
EE
ed.
θJC of the exposed-pad package is approximately
1°C/W to 2°C/W. Die temperature is thus highly depen-
dent upon the heat removal techniques used in the
application. Maximum total power dissipation occurs
under the following conditions:
GS Input
The ground-sense input, GS, provides a ground refer-
ence for the mux inputs. Connect GS to the ground of
the DAC circuits driving DHV_, DTV_, and DLV_.
• V
= +10.5V
CC
• V = -5.25V
EE
To maintain an 8V range in the presence of GS variations,
GS offsets DHV_, DLV_, and DTV_ ranges. Adequate
supply headroom must be maintained in the presence of
GS variations. Ensure:
• V
= 6.5V, DATA = HIGH
DHV_
• Short-circuit current = 60mA
Under these extreme conditions, the total power dissi-
pation is 5.8W. If the die temperature cannot be main-
tained at an acceptable level under these conditions,
use software clamping to limit the load output currents
to lower values and/or reduce the supply voltages.
V
≥ 9.5V + Max (V
)
CC
GS
V
EE
≤ -4.5V + Min (V
)
GS
Temperature Monitor
Power-Supply Considerations
The MAX9977 supplies a temperature output signal,
TEMP, that asserts a 3.33V nominal output voltage at a
+70°C (343K) die temperature. The output voltage
changes proportionally with temperature at 10mV/°C.
Bypass all V
and V power input pins with 0.01µF
EE
CC
capacitors, and use bulk bypassing of at least 10µF on
each supply.
16 ______________________________________________________________________________________
Quad, Low-Power, 1200Mbps
ATE Driver
Pin Configuration
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
V 34
T
1
2
75 GND
74
73 DUT4
DATA4
NDATA4
RCV4
V
CC
3
4
72
71
V
V
EE
EE
MAX9977
NRCV4
DATA3
NDATA3
RCV3
5
6
70 GND
69 N.C.
7
8
68
V
CC
NRCV3
9
67 DUT3
V
10
66
65
V
V
EE
EE
EE
GND 11
RST 12
CS 13
64 GND
63 TEMP
62 GND
SCLK 14
DIN 15
61
60
V
V
EE
EE
V
CC
16
NRCV2 17
RCV2 18
59 DUT2
58
V
CC
NDATA2 19
DATA2 20
NRCV1 21
RCV1 22
57 N.C.
56 GND
55
54
V
V
EE
EE
NDATA1 23
DATA1 24
53 DUT1
52
51 GND
V
CC
V 12 25
T
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TQFP-IDP
Selector Guide
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
INTERNAL DATA_ AND
HEAT
PART
RCV_ TERMINATIONS EXTRACTION
MAX9977AKCCQ
MAX9977ADCCQ*
100Ω with center tap
Top
Top
None
*Future product—contact factory for availability.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX9979KCTK+TD
D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFN-68
MAXIM
MAX997ESA+
Comparator, 1 Func, 2000uV Offset-Max, 4.5ns Response Time, CMOS, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8
MAXIM
MAX997ESA-T
Comparator, 1 Func, 2000uV Offset-Max, 4.5ns Response Time, CMOS, PDSO8, 0.150 INCH, MS-012AA, SOIC-8
MAXIM
MAX997EUA+T
Comparator, 1 Func, 4500uV Offset-Max, 4.5ns Response Time, CMOS, PDSO8, LEAD FREE, UMAX-8
MAXIM
©2020 ICPDF网 联系我们和版权申明