MAXQ1061ETP+ [MAXIM]

DeepCover Cryptographic Controller for Embedded Devices;


型号：	MAXQ1061ETP+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	DeepCover Cryptographic Controller for Embedded Devices
文件：	总4页 (文件大小：262K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ABRIDGED DATA SHEET

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MAXQ1061/MAXQ1062

DeepCover Cryptographic Controller

for Embedded Devices

General Description

DeepCover embedded security solutions cloak sensitive

data under multiple layers of advanced physical security

to provide the most secure key storage possible.

Beneﬁts and Features

● Advanced Cryptographic Tool Box Seamlessly

Supports Highly Secure Key Storage

• Certiﬁcates Chain Management

The MAXQ1061/MAXQ1062 cryptographic controller

makes it fast and easy to implement full security for embed-

ded, connected products without requiring firmware devel-

opment. The MAXQ1061/MAXQ1062 coprocessor can be

designed-in from the start or added to an existing design to

guarantee confidentiality, authenticity, and integrity of the

device. It is ideal for connected embedded devices, indus-

trial networking, PLC, and network appliances.

The embedded, comprehensive cryptographic toolbox

provides key generation and storage up to full SSL/

TLS/DTLS support by offering a high level of abstraction

including TLS/DTLS key negotiation, ECDSA-based TLS/

DTLS authentication, digital signature generation and

verification, SSL/TLS/DTLS packet encryption, and MAC

algorithms. It can also serve as a secure bootloader for an

external generic microcontroller.

• Secure 32KB or 8KB File System Based on

Nonvolatile EEPROM (500K Cycles) for Extensive

Key and Certiﬁcate Storage for MAXQ1061 and

MAXQ1061, Respectively

• Symmetric-key: AES-128/-256 (ECB, CBC, CCM)

• Asymmetric-key: ECC NIST P-256, -521, -384 and

Brainpool BP-256, -384, -512

• Secure Hash: SHA-256, -384, -512

• MAC Digest: CBC-MAC, HMAC-SHA256, HMAC-

SHA384, HMAC-SHA512, ECIES

• Signature Schemes: ECDSA (FIPS 186-4)

• Key Exchange: EC Difﬁe-Hellman (TLS)

• 128-Bit AES Stream Encryption Engine Over SPI

(up to 20Mb/s) Supporting AES-GCM and AES-

ECB Modes

• On-Chip Key Generation: ECC, AES

• Random Number Generation: True RNG

32KB of user-programmable EEPROM of MAXQ1061

or 8KB of MAXQ1062 securely store certificates, public

keys, private and secret keys, monotonic counters, and

arbitrary data. A flexible file system manages access

rights for the objects. The device is controlled over a SPI

or I C interface. Life cycle management and a secure key

loading protocols are provided.

● No Firmware Development Required Significantly

Reduces Time to Market

● High-Level Functions Simplify SSL/TLS/DTLS

Implementations

• TLS/DTLS Key Negotiation (PSK, ECDH, ECDHE)

• ECDSA Based TLS/DTLS Authentication, Digital

Signature Generation and Veriﬁcation

• SSL/TLS/DTLS Packet Encryption (AES)

• MAC Algorithm (HMAC-SHA256)

Cryptographic algorithms supported by the device include

AES, ECC, ECDSA signature scheme, SHA, and MAC

digest algorithms. The true random number generator can

be used for on-chip key generation. A separate hardware

AES engine over SPI allows the MAXQ1061/MAXQ1062

to function as a coprocessor for stream encryption.

● Extensive Host/System Services Increase Flexibility

and Reduce System Cost

The advanced physical, environmental and logical protec-

tions, are designed to meet the stringent requirements of

FIPS and Common Criteria EAL4+ certifications.

• Watchdog Timer

• Power-On Reset/Brownout Reset

• Secure Boot Function

Applications

● Internet of Things (IoT)

● Portable Medical Devices

● Building and Home Automation

● Smart Metering

● Certiﬁcate Distribution and Management

● Secure Access Control

● Electronic Signature Generation

● Cybersecurity for Critical Infrastructures

• Gateways and Routers

• Tamper Detection

• Life Cycle Management and Key Loading Protocol

• Flexible File System With User-Programmable

Access Conditions for Each Object Software Reset

• Software Reset, Shutdown, and Wake-Up Functions

● Multiple Communication Interface Options for Simpler

Connection to a Host Processor

• I C Slave Controller

• SPI Slave Controller with a Dedicated DMA Channel

and 128-Bit AES Stream Encryption Engine

Supporting AES-GCM and AES-ECB Modes

• Programmable Logic Controllers

• SCADA

• Smartgrid Monitoring Equipment

• Smart Meters

Ordering Information appears at end of data sheet.

19-8718; Rev 5; 12/19

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MAXQ1061/MAXQ1062

DeepCover Cryptographic Controller

for Embedded Devices

administrator authentication only. TLS handshake

cannot be performed with an unverified certificate.

Detailed Description

The DeepCover cryptographic controller (MAXQ1061/

MAXQ1062) is an effective and easy to implement solu-

tion for strengthening security in embedded systems.

● The exposure of private keys used for authenticating

the equipment embedding the MAXQ1061/MAXQ1062.

Hardware resistance prevents the disclosure of such

private keys.

A comprehensive cryptographic toolbox supports an array of

security needs. Simpler systems may require as little as the

provided key generation and storage. For high levels of securi-

ty, full SSL/TLS/DTLS support offers a high level of abstraction.

● The exposure of the TLS sensitive data (shared

secret or session keys). These data remain inside the

security module.

Cryptographic algorithms supported by the device include

AES-128/-256 with support for ECB, CBC, and CCM

modes, ECC (up to NIST P-521), ECDSA signature

scheme, SHA-2 (up to SHA-512) secure hash algorithms,

MAC digest algorithms such as CBC-MAC or HMAC-SHA.

AES-SPI Engine

The 128-bit AES engine supports AES-GCM (SP 800-38D

compliant) and AES-ECB (SP 800-A compliant) modes. A

dedicated register enables key transfer from the TLS tool-

box to the AES SPI engine. The block is tightly connected

to the SPI slave controller through a dedicated DMA

controller providing high-speed encryption/decryption of a

data stream coming over the SPI interface.

It also has provision for on-chip key generation based

upon a random number generator. The device also pro-

vides a separate hardware AES engine over SPI, sup-

porting AES-GCM and AES-ECB modes, and that can be

used to off-load a host processor for stream encryption.

The SPI controller provides a dedicated command inter-

preter that can only be used when in AES-SPI mode. The

command interpreter includes the following command set:

Communication Interface Selection

The devices communicate through the I C or SPI bus,

●

Authentication only mode

Encryption only mode

determined by the application (TLS toolbox or AES-SPI).

TLS/DTLS Cryptographic Toolbox

Encryption with authentication mode

AES operation mode selection

Keys and initialization vector (IV) loading protocol

Secure storage and handling of block cipher key

(EK) and authentication key (AK)

Software reset

The comprehensive cryptographic toolbox simplifies and

increases the security and resistance of SSL/TLS/DTLS

based applications It offers a high level of abstraction for

the following functions:

●

● Offloads the TLS key exchange

Shutdown

● Securely stores certificates (makes them immutable)

● Securely stores private keys

SSL/TLS/DTLS Functions

• TLS/DTLS key negotiation (ECDH, ECDHE)

• ECDSA-based TLS/DTLS authentication, digital

signature generation and veriﬁcation

● Helps securely verifying certificates and certificate

revocation lists

• SSL/TLS/DTLS packet encryption (AES)

• MAC algorithm (HMAC-SHA256)

• SSL/TLS/DTLS host stack for most CPU architectures

● Securely authenticates to the other peer

● Performs the key exchange securely

● Can encrypt/decrypt and sign/verify data during

execution of the TLS record protocol using the keys

negotiated during the TLS handshake

TLS/DTLS Cipher Suites

• RFC 5487 preshared key (TLS)

TLS_PSK_WITH_AES_128_GCM_SHA256

TLS_PSK_WITH_AES_256_GCM_SHA384

TLS_PSK_WITH_AES_128_CBC_SHA

TLS_PSK_WITH_AES_128_CBC_SHA256

TLS_PSK_WITH_AES_256_CBC_SHA

TLS_PSK_WITH_AES_256_CBC_SHA384

● TLS key exchange and TLS record encryption/

decryption are performed internally and never

exposed. The master secret can be exported to

perform the TLS record processing externally.

The above security features prevent:

● The use of rogue certificates. Certificates are inter-

nally verified and are managed using a dedicated

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MAXQ1061/MAXQ1062

DeepCover Cryptographic Controller

for Embedded Devices

• RFC 6655 AES-CCM (TLS)

System Services

TLS_PSK_WITH_AES_128_CCM

• Life cycle management and key loading protocol

• Software reset

• Shutdown command

TLS_PSK_WITH_AES_256_CCM

TLS_PSK_WITH_AES_128_CCM_8

TLS_PSK_WITH_AES_256_CCM_8

Secure Channel

• RFC 5489 ECDHE_PSK (TLS)

TLS and DTLS protect the data during transmission

between endpoints. The optional secure channel provides

confidentiality with the host processor by supporting AES-

CBC, and integrity using AES-CBC-MAC. Secure mes-

saging performs a key exchange, and those keys sign

and encrypt the commands and the responses using AES.

TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA

TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA

TLS_ECDHE_PSK_WITH_AES_128_CBC_

SHA256

TLS_ECDHE_PSK_WITH_AES_256_CBC_

SHA384

• RFC 5289 AES-CBC/GCM ECC (TLS)

True Random Number Generator

The IC provides a hardware-based true random number

generator.

TLS_PSK_WITH_AES_128_CBC_SHA

TLS_ECDHE_ECDSA_WITH_AES_128_

CBC_SHA256

TLS_ECDHE_ECDSA_WITH_AES_256_

CBC_SHA

TLS_ECDHE_ECDSA_WITH_AES_256_

CBC_SHA384

TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA

TLS_ECDH_ECDSA_WITH_AES_128_CBC_

SHA256

TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA

TLS_ECDH_ECDSA_WITH_AES_256_CBC_

SHA384

Watchdog Timer

The MAXQ1061/MAXQ1062 can act as an external

watchdog timer (WDT) for a host microcontroller. When

enabled, the WDI pin must be toggled within the user-

configurable timeout period. Failure to toggle the pin

within the timeout period results in a WDT timeout. A WDT

timeout can assert a RESET_OUT pulse if enabled. A

timeout does not cause an internal reset.

Tamper Detection

TLS_ECDHE_ECDSA_WITH_AES_128_

GCM_SHA256

TLS_ECDHE_ECDSA_WITH_AES_256_

GCM_SHA384

TLS_ECDH_ECDSA_WITH_AES_128_GCM_

SHA256

TLS_ECDH_ECDSA_WITH_AES_256_GCM_

SHA384

Multiple tamper detection features ensure the security of

information contained within the MAXQ1061/MAXQ1062.

The security features are independently enabled and can

assert a RESET_OUT pulse if enabled.

Secure Boot

The integrity of the host processor’s data and code can

be verified through the hash and signature verification

mechanisms. Object access can be configured after a

successful secure boot.

• RFC 7251 AES-CCM ECC (TLS)

TLS_ECDHE_ECDSA_WITH_AES_128_CCM

TLS_ECDHE_ECDSA_WITH_AES_256_CCM

TLS_ECDHE_ECDSA_WITH_AES_128_CCM_8

TLS_ECDHE_ECDSA_WITH_AES_256_CCM_8

Life Cycle Management

A managed life cycle changes functions and properties

over time, as shown in Table 2. At each state of the

one-way life cycle, the device and parties are granted

initialization, read or modification rights to specific

information.

Cryptographic Services

• Symmetric-key algorithms: AES-128/-256 (ECB,

CBC, CCM)

• Asymmetric-key: ECC NIST P-256, -521, -384 and

Brainpool-256, -384, -512

TLS/DTLS Host Stack

The SSL/TLS/DTLS stack supports TLS1.2/DTLS 1.2, in

client mode. In this stack, security sensitive processing

is deported into the MAXQ1061/MAXQ1062. Therefore,

the TLS host stack does not need to manipulate or store

sensitive/secret data.

• Secure hash algorithms: SHA-256, -384, -51

• MAC digest algorithms: CBC-MAC, HMAC-

SHA256, HMAC-SHA384, HMAC-SHA512

• Signature schemes: ECDSA (FIPS 186-4)

• Key exchange algorithms: EC Difﬁe-Hellman (TLS)

• On-chip key generation: ECC, AES

• Random number generation: True RNG

The TLS host stack uses the Arm^®Mbed™ TLS.

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MAXQ1061/MAXQ1062

DeepCover Cryptographic Controller

for Embedded Devices

Secure EEPROM Storage

Serial Peripherals

Secure EEPROM is accessible in TLS toolbox mode.

Data objects can be volatile or not and can be stored

in the nonvolatile memory. To be resistant to power loss

during write operations, the object modification is atomic.

Key objects are stored in an integrity-protected manner

and can never be read in the clear. They are automati-

cally veriﬁed before use. Key pairs should be generated

internally and stored in a persistent key pair object. Key

pairs can also be generated externally and imported after

successful signature veriﬁcation using an import public

key present in the module. Arbitrary key pairs cannot be

used; veriﬁcation is mandatory.

SPI

The serial peripheral interface (SPI) is provided in the

SPI-AES and TLS (SPI) modes. SPI is a four-wire bus

providing fast, synchronous, full-duplex communication

between the IC and the host system. The peripheral pro-

vides the following features:

• Slave mode operation

• Active-low SSEL

• Characters transmitted LSB ﬁrst

• Data protocol uses SPI Mode 0

I C

Certiﬁcate Storage

The I C bus is provided in the TLS (I C) mode. It is a

bidirectional, two-wire serial bus that provides a medium-

speed communications network. It can operate as a one-

to-one, one-to-many, or many-to-many communications

medium. It provides the following features:

Certificates are stored in an integrity-protected manner.

They are automatically verified and trusted using one

or more parent certificates in the certification chain (cer-

tificates already stored in the IC). The device verifies the

digital signature of the certificates and can extract their

public key.

• Slave mode operation

• Maximum I C bit rate of 400kps (fast mode)

• Default address of 0x60 can be conﬁgured

• Supports standard (7-bit) addressing

Arbitrary certificates cannot be stored; verification by a par-

ent certificate or by a dedicated public key is mandatory.

• Supports I C clock stretching

Ordering Information

EEPROM SIZE

PART

PIN-PACKAGE

(KB)

MAXQ1061EUD+

MAXQ1061EUD+T

MAXQ1061ETP+

MAXQ1061ETP+T

MAXQ1062EUD+

MAXQ1062EUD+T

MAXQ1062ETP+

MAXQ1062ETP+T

14 TSSOP

20 TQFN

14 TSSOP

20 TQFN

+Denotes a lead(Pb)-free/RoHS-compliant device.

T = Tape and reel.

Note: All devices operate over the -40°C to +109°C temperature

range.

DeepCover is a registered trademark of Maxim Integrated Products, Inc.

Arm is a registered trademark and Mbed is a trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2019 Maxim Integrated Products, Inc.

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MAXQ1061ETP+ [MAXIM]

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