MAXQ611X-XXXX+ [MAXIM]
RISC Microcontroller, CMOS;
| 型号： | MAXQ611X-XXXX+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | RISC Microcontroller, CMOS 微控制器 外围集成电路 |
| 文件： | 总30页 (文件大小：1086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAXQ611
Infrared Remote Control System-On-Chip
General Description
Features
®
The MAXQ611 is a low-power, 16-bit MAXQ micro-
controller designed for low-power applications including
universal remote controls, consumer electronics, and
white goods. The device combines a powerful 16-bit RISC
microcontroller and integrated peripherals including a
universal synchronous/asynchronous receiver-transmitter
● High-Performance, Low-Power, 16-Bit RISC Core
● Internal 12MHz Oscillator Requires No External
Components
● 1.7V to 3.6V Operating Voltage
● Dedicated Pointer for Direct Read from Code Space
● 16-Bit Instruction Word, 16-Bit Data Bus
2
(USART), SPI master/slave and I C communications
ports, along with an IR module with carrier frequency
generation and flexible port I/O capable of multiplexed
keypad control. An internal amplifier eliminates the need
for external circuitry to drive the IR receiver pin.
● Memory Features
• 80KB Flash Memory
• 2KB Data SRAM
● Infrared Module Features
• IR Learning Circuit
The device provides 80KB of flash memory and 2KB of
data SRAM.
• Automatic IR Carrier Frequency Generation
and Modulation
• IR Transmit Driver with 200mA (min) Sink Current
at 1.8V
For the ultimate in low-power battery-operated perfor-
mance, the device includes an ultra-low-power stop mode.
In this mode, the minimum amount of circuitry is powered.
Wake-up sources include external interrupts, the power-fail
interrupt, and a timer interrupt.
● Additional Peripherals
• Power-Fail Warning
• Power-On Reset (POR)/Brownout Reset
• Two 16-Bit Programmable Timers/Counters
with Prescaler and Capture/Compare
Applications
● Universal Remote Controls for Tablets
● Universal Remote Controls for Smartphones
2
• SPI, I C, and USART Peripherals
• Programmable Watchdog Timer
• 8kHz Nanopower Ring Oscillator Wake-Up Timer
• Up to 32 (TQFN) or 38 (Bare Die) GPIO
Block Diagram
●
Low Power Consumption
•ꢀ0.15µA (typ), 2.0µA (max) in Stop Mode,
MAXQ611
T = +25NC, Power-Fail Monitor Disabled
A
•ꢀ2.0mA (typ) at 12MHz in Active Mode
16-BIT MAXQ
RISC CPU
IR DRIVER
IR TIMER
SPI
REGULATOR
80KB FLASH
MEMORY
VOLTAGE
MONITOR
Ordering Information/Selector Guide appears at end of
data sheet.
CLOCK
GPIO
2
I C
UTILITY
ROM
WATCHDOG
For documentation and recommended products to use with this part,
refer to www.maximintegrated.com/MAXQ611.resources.
2 x
8kHz NANO
RING
2KB
DATA SRAM
USART
For related parts, refer to www.maximintegrated.com/MAXQ611.related.
16-BIT TIMER
Note: Some revisions of this device may incorporate deviations from
published specifications known as errata. Multiple revisions of any
device may be simultaneously available through various sales channels.
For information about device errata, go to: www.maximintegrated.
com/errata.
MAXQ is a registered trademark of Maxim Integrated Products,
Inc.
19-7309; Rev 0; 3/14
MAXQ611
Infrared Remote Control System-On-Chip
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Stack Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IR Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Carrier Burst-Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Peripheral Interface (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
I C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-Fail Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Development and Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Ordering Information/Selector Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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MAXQ611
Infrared Remote Control System-On-Chip
TABLE OF CONTENTS (continued)
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Appendix A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
I C Serial Peripheral Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2
I C Serial Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Peripheral Interface (SPI) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
USART Mode 0 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
USART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
LIST OF FIGURES
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. IR Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Power-Fail Detection During Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Series Resistors (RS) for Protecting Against High-Voltage Spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. I2C Bus Controller Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 12. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. USART Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LIST OF TABLES
Table 1. Watchdog Timer Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 2. USART Mode Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . 21
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MAXQ611
Infrared Remote Control System-On-Chip
Absolute Maximum Ratings
(All voltages with respect to GND.)
Operating Temperature Range........................... -20°C to +70°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Voltage Range on V .........................................-0.3V to +3.6V
DD
Voltage Range on Any Lead Except V ....-0.3V to (V
+ 0.5V)
DD
DD
Continuous Power Dissipation (T = +70°C)
A
TQFN (multilayer board)
(derate 37mW/°C above +70°C)................................2963mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θ )...........27°C/W
JA
Junction-to-Case Thermal Resistance (θ )..................1°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(Limits are 100% tested at T = +25°C and T = +70°C. Limits over the operating temperature range and relevant supply voltage range
A
A
are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER
Supply Voltage
V
V
3.6
V
V
DD
RST
1.8V Internal Regulator
V
1.62
1.8
1.98
1.75
1.85
1.95
2.06
2.16
2.26
2.36
2.47
2.57
2.67
2.78
2.88
2.98
3.09
3.19
3.29
1.70
REG18
V
PFWARNCN = 0000
1.65
1.75
1.85
1.94
2.04
2.14
2.24
2.33
2.43
2.53
2.62
2.72
2.82
2.91
3.01
3.11
1.64
1.70
1.80
1.9
PFW1_70
PFW1_80
PFW1_90
PFW2_00
PFW2_10
PFW2_20
PFW2_30
PFW2_40
PFW2_50
PFW2_60
PFW2_70
PFW2_80
PFW2_90
PFW3_00
PFW3_10
PFW3_20
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PFWARNCN = 0001 (default), GBD
PFWARNCN = 0010, GBD
PFWARNCN = 0011, GBD
PFWARNCN = 0100, GBD
PFWARNCN = 0101, GBD
PFWARNCN = 0110, GBD
PFWARNCN = 0111, GBD
PFWARNCN = 1000, GBD
PFWARNCN = 1001, GBD
PFWARNCN = 1010, GBD
PFWARNCN = 1011, GBD
PFWARNCN = 1100, GBD
PFWARNCN = 1101, GBD
PFWARNCN = 1110, GBD
PFWARNCN = 1111, GBD
2.0
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
Power-Fail Warning Voltage
V
Power-Fail Reset Voltage
V
RST
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MAXQ611
Infrared Remote Control System-On-Chip
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage range
A
A
are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
PFWARNCN = 0000, V
MIN
TYP
MAX
UNITS
Power-Fail Warning/Reset
Offset
V
> V
RST
30
mV
PFWRST
PFW
Power-On Reset Voltage
V
V
Monitors V
1.2
1.0
V
V
POR
DD
RAM Data Retention Voltage
DRV
f
= 12MHz, executing code from
SYS
flash memory, all inputs connected to
Active Current
I
2
3.7
mA
µA
DD_1
GND/V , outputs do not source or
DD
sink current
T
T
T
T
= +25°C (power-fail off)
0.15
0.15
22
2.0
8
A
A
A
A
I
I
S1
S2
= -20°C to +70°C (power-fail off)
= +25°C (power-fail on)
Stop Mode Current
31
38
µA
nA
= -20°C to +70°C (power-fail on)
27.6
Power Consumption During
Power-On Reset
I
V
< V
POR
100
POR
DD
3/f
NANO
Stop Mode Resume Time
t
+ 1024/
µs
ON
f
OSC
CLOCKS
Internal Oscillator Frequency
f
12
MHz
OSC
T
T
T
= +25°C, V
= +25°C, V
= 1.8V ±5%
= 1.8V
±0.5%
A
DD
Internal Oscillator Variability
f
±0.5%
±1%
OSC_VAR
A
DD
= -20°C to +70°C
A
f
/system clock divisor
OSC
System Clock Frequency
System Clock Period
f
t
12
MHz
SYS
(1/2/4/8/256)
1/f
SYS
SYS
T
T
= +25°C
3.0
1.7
12.0
20.0
kHz
kHz
A
Nanopower Ring Frequency
f
NANO
= +25°C, V
= V
2.4
A
DD
POR
GENERAL-PURPOSE I/O AND SPECIAL FUNCTIONS
Input Low Voltage for IRRX
and All Port Pins
0.3 x
V
V
V
IL
GND
V
DD
Input High Voltage for IRRX
and All Port Pins
0.7 x
V
V
V
IH
DD
V
DD
Input Hysteresis (Schmitt)
V
V
V
V
V
= 3.3V, T = +25°C
300
0.4
0.4
0.4
mV
IHYS
DD
DD
DD
DD
A
= 3.6V, I = 11mA
0.5
0.5
0.5
OL
Output Low Voltage for All Port
Pins
V
= 2.35V, I = 8mA
V
V
OL
OL
= 1.8V, I = 4.5mA
OL
Output High Voltage All Port
Pins
V
0.5
-
DD
V
IOH = -2mA
V
DD
OH
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MAXQ611
Infrared Remote Control System-On-Chip
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant supply voltage range
A
A
are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input/Output Pin Capacitance
for All Port Pins
C
15
pF
IO
L
Input Leakage Current for All
Pins
I
-100
+100
nA
Input Pullup Resistor for
RESET, IRRX, and All Port
Pins
V
V
= 3.0V, V = 0.4V
16
18
28
31
39
43
DD
OL
R
kΩ
PU
= 1.8V, V = 0.4V
DD
OL
IR MODULE
IRRX Input Filter Pulse-Width
Reject
t
50
ns
IRRX_R
IRRX Input Filter Pulse-Width
Accept
t
300
200
ns
IRRX_A
IRTX Sink Current
I
V
≥ 0.25V
mA
IRTX
IRTX
WAKE-UP TIMER
1/
65,535/
f
NANO
Wake-Up Timer Interval
t
s
WAKEUP
f
NANO
FLASH MEMORY
Flash Memory Controller Clock
Frequency During Program/
Erase
f
/(FCKDIV[3:0] + 1) must equal
SRC
f
1MHz, verify PFI = 0 before calling
utility ROM
1
MHz
FP
Flash Mass Erase Time
Flash Page Erase Time
t
40
40
ms
ms
ME
t
ERASE
Flash Programming Time per
Word
t
Excluding utility ROM overhead
40
μs
PROG
Write/Erase Cycles
Data Retention
20,000
100
Cycles
Years
T
= +25°C
A
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MAXQ611
Infrared Remote Control System-On-Chip
Pin Configuration
TOP VIEW
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P2.4/TCK
P2.5/TDI
P1.5/INT5
P1.4/INT4
GND
P3.6/INT14
P3.7/INT15
P2.6/TMS
P2.7/TDO
RESET
V
DD
REG18
MAXQ611
GND
P3.3/INT11
P3.2/INT10
P1.3/INT3
P1.2/INT2
P1.1/INT1
V
DD
GND
IRTX
IRRX
*EP
+
TQFN
*EXPOSED PAD = GND
Pin Description
PIN
PIN
NAME
DIE
POWER
24, 26
TQFN
FUNCTION
19, 41
V
Supply Voltage. Bypass to ground with a 4.7µF capacitor.
Ground. Connect directly to the ground plane.
DD
17, 20,
28, 42
22, 47
23
GND
1.8V Regulator Output. This pin must be connected to ground through a 1.0μF external
capacitor. The capacitor should be placed as close to this pin as possible. No devices
other than the capacitor should be connected to this pin.
18
—
REG18
EP
—
Exposed Pad. Connect to GND or leave electrically unconnnected.
RESET
Digital, Active-Low Reset Input/Output. The device remains in reset while this bidirectional
pin is in its active state. When the pin transitions to its inactive state the device exits
reset and begins execution. External circuits must be able to sink in excess of 250µA to
overcome the internal pullup current source and take the pin to its active state. This pin
should be left unconnected if the application does not provide a reset signal to the device.
This pin is driven active as an output when an internal reset condition occurs.
45
40
RESET
IR FUNCTION
IR Receive Input. This pin functions as the dedicated IR receiver. This pin defaults to a
high-impedance input after reset.
49
44
43
IRRX
IRTX
IR Transmit Output. This pin functions as the dedicated IR transmitter. This pin defaults to
a high-impedance input after reset.
48
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MAXQ611
Infrared Remote Control System-On-Chip
Pin Description (continued)
PIN
NAME
FUNCTION
DIE
TQFN
GENERAL-PURPOSE I/O AND SPECIAL FUNCTIONS
P0.0: General-Purpose I/O, Port 0 Pin 0
IRTXM: IR Transmit Modulation
1
3
5
1
3
5
P0.0/IRTXM
P0.1/RX0
P0.2/TX0
P0.1: General Purpose I/O, Port 0 Pin 1
RX0: USART 0 Receive
P0.2: General-Purpose I/O, Port 0 Pin 2
TX0: USART 0 Transmit
P0.3: General-Purpose I/O, Port 0 Pin 3
RX1: USART 1 Receive
SCL: I C Clock
P0.3/RX1/
SCL
6
8
9
6
7
8
2
P0.4: General-Purpose I/O, Port 0 Pin 4
TX1: USART 1 Transmit
P0.4/TX1/
SDA
2
SDA: I C Data
P0.5: General-Purpose I/O, Port 0 Pin 5
TBA0: Timer B A0
TBA1: Timer B A1
P0.5/TBA0/
TBA1
P0.6: General-Purpose I/O, Port 0 Pin 6
TBB0: Timer B B0
11
13
15
17
18
19
25
17
31
32
33
34
37
9
P0.6/TBB0
P0.7/TBB1
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT3
P1.4/INT4
P1.5/INT5
P1.6/INT6
P1.7/INT7
P2.0/MOSI
P2.1/MISO
P2.2/SCLK
P0.7: General-Purpose I/O, Port 0 Pin 7
TBB1: Timer B B1
10
11
12
13
14
21
22
25
26
27
29
32
P1.0: General-Purpose I/O, Port 1 Pin 0
EXT0: External Interrupt 0
P1.1: General-Purpose I/O, Port 1 Pin 1
EXT1: External Interrupt 1
P1.2: General-Purpose I/O, Port 1 Pin 2
EXT2: External Interrupt 2
P1.3: General-Purpose I/O, Port 1 Pin 3
EXT3: External Interrupt 3
P1.4: General-Purpose I/O, Port 1 Pin 4
EXT4: External Interrupt 4
P1.5: General-Purpose I/O, Port 1 Pin 5
EXT5: External Interrupt 5
P1.6: General-Purpose I/O, Port 1 Pin 6
EXT6: External Interrupt 6
P1.7: General-Purpose I/O, Port 1 Pin 7
EXT7: External Interrupt 7
P2.0: General-Purpose I/O, Port 2 Pin 0
MOSI: SPI Master-Out/Slave-In
P2.1: General-Purpose I/O, Port 2 Pin 1
MISO: SPI Master-In/Slave-Out
P2.2: General-Purpose I/O, Port 2 Pin 2
SCLK: SPI Clock
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MAXQ611
Infrared Remote Control System-On-Chip
Pin Description (continued)
PIN
NAME
FUNCTION
DIE
TQFN
P2.3: General-Purpose I/O, Port 2 Pin 3
SSEL: SPI Slave Select
38
33
P2.3/SSEL
P2.4/TCK
P2.5/TDI
P2.4: General-Purpose I/O, Port 2 Pin 4
TCK: JTAG Clock. The POR default for the PD2.4 bit activates the weak pullup.
39
40
34
35
P2.5: General-Purpose I/O, Port 2 Pin 5
TDI: JTAG Data In. The POR default for the PD2.5 bit activates the weak pullup.
P2.6: General-Purpose I/O, Port 2 Pin 6
43
38
P2.6/TMS
TMS: JTAG Test Mode Select. The POR default for the PD2.6 bit activates the weak
pullup.
P2.7: General-Purpose I/O, Port 2 Pin 7
TDO: JTAG Data Output. The POR default for the PD2.7 bit activates the weak pullup.
44
2
39
2
P2.7/TDO
P3.0/INT8
P3.1/INT9
P3.2/INT10
P3.3/INT11
P3.4/INT12
P3.5/INT13
P3.6/INT14
P3.7/INT15
P3.0: General-Purpose I/O, Port 3 Pin 0
External Interrupt 8
P3.1: General-Purpose I/O, Port 3 Pin 1
External Interrupt 9
4
4
P3.2: General-Purpose I/O, Port 3 Pin 2
External Interrupt 10
20
21
35
36
41
42
15
16
30
31
36
37
P3.3: General-Purpose I/O, Port 3 Pin 3
External Interrupt 11
P3.4: General-Purpose I/O, Port 3 Pin 4
External Interrupt 12
P3.5: General-Purpose I/O, Port 3 Pin 5
External Interrupt 13
P3.6: General-Purpose I/O, Port 3 Pin 6
External Interrupt 14
P3.7: General-Purpose I/O, Port 3 Pin 7
External Interrupt 15
7
—
—
—
—
—
—
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.0: General-Purpose I/O, Port 4 Pin 0
P4.1: General-Purpose I/O, Port 4 Pin 1
P4.2: General-Purpose I/O, Port 4 Pin 2
P4.3: General-Purpose I/O, Port 4 Pin 3
P4.4: General-Purpose I/O, Port 4 Pin 4
P4.5: General-Purpose I/O, Port 4 Pin 5
10
12
14
16
26
NO CONNECTIONS
—
23, 24
—
D.N.C.
N.C.
Do Not Connect. Internally connected.
Do Not Connect
27, 29,
30
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MAXQ611
Infrared Remote Control System-On-Chip
accumulator module consists of sixteen 16-bit registers
and is tightly coupled with the arithmetic logic unit (ALU).
A configurable soft stack supports program flow.
Detailed Description
The MAXQ611 provides integrated, low-cost solutions
that simplify the design of IR communications equipment
such as universal remote controls. The internal 12MHz
oscillator requires no external components. Standard fea-
tures include the highly optimized, single-cycle, MAXQ,
16-bit RISC core; 80KB flash memory; 2KB data RAM;
soft stack; 16 general-purpose registers; and three data
pointers. The MAXQ core has the industry’s best MIPS/
mA rating, allowing developers to achieve the same per-
formance as competing microcontrollers at substantially
lower clock rates. Application-specific peripherals include
flexible timers for generating IR carrier frequencies and
modulation. A high-current IR drive pin operates with an
internal receiver amplifier without external components. It
also includes general-purpose I/O pins ideal for keypad
matrix input, and a power-fail-detection circuit to notify
the application when the supply voltage is nearing the
microcontroller’s minimum operating voltage.
Execution of instructions is triggered by data transfer
between functional register modules or between a func-
tional register module and memory. Because data move-
ment involves only source and destination modules, cir-
cuit switching activities are limited to active modules only.
This approach localizes power dissipation and minimizes
switching noise.
The MAXQ instruction set is highly orthogonal. All arith-
metical and logical operations can use any register in
conjunction with the accumulator. Data movement is sup-
ported from any register to any other register. Memory
is accessed through specific data-pointer registers with
autoincrement/decrement support.
Memory
The microcontroller incorporates several memory types:
The combination of high-performance instructions and
ultra-low stop-mode current increases battery life over
competing microcontrollers. An integrated POR circuit
with brownout support resets the device to a known con-
dition following a power-up cycle or brownout condition.
Additionally, a power-fail warning flag is set, and a power-
fail interrupt can be generated when the system voltage
•
•
•
•
80KB flash memory
2KB SRAM data memory
Dedicated utility ROM
Soft stack
Memory Protection
falls below the power-fail warning voltage, V
. The
The optional memory-protection feature segments code
memory into three areas with different access privileges.
This allows unique code segments to be loaded at differ-
ent steps in the manufacturing process, while restricting
access to higher-privilege segments that might have been
loaded earlier in the process. The memory protection seg-
ments are:
PFW
power-fail warning feature allows the application to notify
the user that the system supply is low and appropriate
action should be taken.
Microprocessor
The MAXQ611 is based on Maxim Integrated’s low-
power, 16-bit MAXQ20S. The core supports the Harvard
memory architecture with separate 16-bit program and
data address buses. A fixed 16-bit instruction word is
standard, but data can be arranged in 8 or 16 bits. The
MAXQ core is a pipelined processor. Almost all instruc-
tions execute in a single clock cycle, with performance
approaching 1MIPS per MHz. The 16-bit data path is
implemented around register modules, and each register
module contributes specific functions to the core. The
•
•
•
System (highest privilege)
User-loader (medium privilege)
User-application (lowest privilege)
Code in the system area is typically loaded by the OEM,
and can be read/write protected from code executing in
lower privilege segments. In a similar manner, the user-
loader segment can be read/write protected from code
executing in the user-application area.
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MAXQ611
Infrared Remote Control System-On-Chip
Stack Memory
Watchdog Timer
The MAXQ20S core provides a soft stack that can be
used to store program return addresses (for subroutine
calls and interrupt handling) and other general-purpose
data. This soft stack is located in data memory, which
means that the SRAM data memory must be shared
between the soft stack and general-purpose application
data storage. However, the location and size of the soft
stack is determined by the user, providing maximum flex-
ibility when allocating resources for a particular applica-
tion. The stack is used automatically by the processor
when the CALL, RET, and RETI instructions are executed
and when an interrupt is serviced. An application can
also store and retrieve values explicitly using the stack by
means of the PUSH, POP, and POPI instructions.
The internal watchdog timer greatly increases system reli-
ability. The timer resets the device if software execution
is disturbed. The watchdog timer is a free-running coun-
ter designed to be periodically reset by the application
software. If software is operating correctly, the counter is
periodically reset and never reaches its maximum count.
However, if software operation is interrupted, the timer
does not reset, triggering a system reset and optionally a
watchdog timer interrupt. This protects the system against
electrical noise or electrostatic discharge (ESD) upsets
that could cause uncontrolled processor operation. The
internal watchdog timer is an upgrade to older designs
with external watchdog devices, reducing system cost
and simultaneously increasing reliability.
The SP pointer indicates the current top of the stack,
which initializes by default to the top of the SRAM data
memory. As values are pushed onto the stack, the SP
pointer decrements, which means that the stack grows
downward towards the bottom (lowest address) of the
data memory. Popping values off the stack causes the SP
pointer value to increase.
The watchdog timer functions as the source of both the
watchdog timer timeout and the watchdog timer reset.
The timeout period is user-programmable using the WD
bits as shown in Table 1. An interrupt is generated when
the timeout period expires if the interrupt is enabled. All
watchdog timer resets follow the programmed interrupt
timeouts by 512 system clock cycles. If the watchdog
timer is not restarted for another full interval in this time
period, a system reset occurs when the reset timeout
expires. See Table 1.
Utility ROM
The utility ROM is located in program space beginning at
address 8000h. This ROM includes the following routines:
IR Carrier Generation and Modulation
Timer
The IR module provides a low-cost solution to IR commu-
nication. The dedicated IR timer/counter simplifies carrier
and modulation generation.
•
Production test routines (internal memory tests, mem-
ory loader, etc.), which are used for internal testing
only, and are generally of no use to the end-application
developer
•
User-callable routines for buffer copying and fast table
lookup
The IR timer is composed of a carrier generator and a
carrier modulator. The carrier generation module uses
the 16-bit IR carrier register (IRCA) to define the high
and low time of the carrier through the IR carrier high
byte (IRCAH) and IR carrier low byte (IRCAL). The carrier
modulator uses the IR data bit (IRDATA) and IR modulator
time register (IRMT) to determine whether the carrier or
the idle condition is present on IRTX.
Following any reset, execution begins in the utility ROM at
address 8000h. At this point, unless test mode has been
invoked (which requires special programming through
the JTAG interface), the utility ROM in the device always
automatically jumps to location 0000h, which is the begin-
ning of user application code.
Table 1. Watchdog Timer Settings
WD
(CD = 00)
PERIOD
INTERRUPT (f
= 12MHz)
RESET (f
= 12MHz)
SYS
SYS
15
00
01
10
11
2
2
2
2
/f
/f
/f
/f
2.7ms
42.7µs
42.7µs
42.7µs
42.7µs
SYS
SYS
SYS
SYS
18
21
24
21.9ms
174.7ms
1.4s
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Infrared Remote Control System-On-Chip
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the begin-
ning value for the carrier modulator. During transmission,
the IRV register is initially loaded with the IRMT value
and begins down counting towards 0000h, whereas in
receive mode it counts upward from the initial IRV register
value. During the receive operation, the IRV register can
be configured to reload with 0000h when capture occurs
on detection of selected edges or can be allowed to con-
tinue free-running throughout the receive operation. An
overflow occurs when the IR timer value rolls over from
0FFFFh to 0000h. The IR overflow flag (IROV) is set to 1
and an interrupt is generated if enabled (IRIE = 1).
rier modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV down counter
is clocked by the carrier frequency and thus the modula-
tion is a function of carrier cycles. When IRCFME = 1, the
IRV down counter is clocked by IRCLK, allowing carrier
modulation timing with IRCLK resolution.
The IRTXPOL bit defines the starting/idle state as well as
the carrier polarity for the IRTX pin. If IRTXPOL = 1, the
IRTX pin is set to a logic-high when the IR timer module is
enabled. If IRTXPOL = 0, the IRTX pin is set to a logic-low
when the IR timer is enabled.
A separate register bit, IR data (IRDATA), is used to determine
whether the carrier generator output is output to the IRTX pin
for the next IRMT carrier cycles. When IRDATA = 1, the car-
rier waveform (or inversion of this waveform if IRTXPOL = 1)
is output on the IRTX pin during the next IRMT cycles. When
IRDATA = 0, the idle condition, as defined by IRTXPOL, is
output on the IRTX pin during the next IRMT cycles.
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
IRDIV[2:0]
•
•
•
•
•
IR Input Clock (f
) = f
/2
IRCLK
SYS
Carrier Frequency (f
) = f
CARRIER
/(IRCAH + IRCAL + 2)
IRCLK
The IR timer acts as a down counter in transmit mode.
An IR transmission starts when the IREN bit is set to 1
when IRMODE = 1; when the IRMODE bit is set to 1 when
IREN = 1; or when IREN and IRMODE are both set to 1 in
the same instruction. The IRMT and IRCA registers, along
with the IRDATA and IRTXPOL bits, are sampled at the
beginning of the transmit process and every time the IR
timer value reload its value. When the IRV reaches 0000h
value, on the next carrier clock, it does the following:
Carrier High Time = IRCAH + 1
Carrier Low Time = IRCAL + 1
Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for each
IRV down-count interval, and is sampled along with the
IRTXPOL and IRDATA bits at the beginning of each new
IRV down-count interval so that duty-cycle variation and
frequency shifting is possible from one interval to the next,
which is illustrated in Figure 1.
1) Reloads IRV with IRMT.
2) Samples IRCA, IRDATA, and IRTXPOL.
3) Generates IRTX accordingly.
Figure 2 illustrates the basic carrier generation and its
path to the IRTX output pin. The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier
polarity of the IRTX pin when the IR timer is enabled.
4) Sets IRIF to 1.
5) Generates an interrupt to the CPU if enabled (IRIE = 1).
IR Transmission
To terminate the current transmission, the user can switch
to receive mode (IRMODE = 0) or clear IREN to 0.
During IR transmission (IRMODE = 1), the carrier gen-
erator creates the appropriate carrier waveform, while
the carrier modulator performs the modulation. The car-
Carrier Modulation Time = IRMT + 1 carrier cycles
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MAXQ611
Infrared Remote Control System-On-Chip
IRCA
IRCA = 0202h
IRMT = 3
IRCA = 0002h
IRMT = 5
IRMT
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV
DOWN-COUNT INTERVAL
3
2
1
0
5
4
3
2
1
0
CARRIER OUTPUT
(IRV)
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
IRTXPOL
0
1
CARRIER GENERATION
IRTX PIN
IRCLK
CARRIER
IRCAH + 1
IRCAL + 1
IRCFME
0
1
SAMPLE
IRDATA ON
IRV = 0000h
IR INTERRUPT
IRDATA
IRMT
CARRIER MODULATION
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
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MAXQ611
Infrared Remote Control System-On-Chip
IRMT = 3
CARRIER OUTPUT
(IRV)
3
2
1
0
3
2
1
0
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 3. IR Transmission Waveform (IRCFME = 0)
On the next qualified event, the IR module does the following:
IR Receive
When configured in receive mode (IRMODE = 0), the
IR hardware supports the IRRX capture function. The
IRRXSEL bits define which edge(s) of the IRRX pin
should trigger the IR timer capture function.
1) Captures the IRRX pin state and transfers its value to
IRDATA. If a falling edge occurs, IRDATA = 0. If a rising
edge occurs, IRDATA = 1.
2) Transfers its current IRV value to the IRMT.
3) Resets IRV content to 0000h (if IRXRL = 1).
4) Continues counting again until the next qualified event.
The IR module starts operating in the receive mode when
IRMODE = 0 and IREN = 1. Once started, the IR timer
(IRV) starts up counting from 0000h when a qualified
capture event as defined by IRRXSEL happens. The IRV
register is, by default, counting carrier cycles as defined
by the IRCA register. However, the IR carrier frequency
detect (IRCFME) bit can be set to 1 to allow clocking of
the IRV register directly with the IRCLK for finer resolu-
tion. When IRCFME = 0, the IRCA defined carrier is
counted by IRV. When IRCFME = 1, the IRCLK clocks
the IRV register.
If the IR timer value rolls over from 0FFFFh to 0000h
before a qualified event happens, the IR timer overflow
(IROV) flag is set to 1 and an interrupt is generated, if
enabled. The IR module continues to operate in receive
mode until it is stopped by switching into transmit mode
(IRMODE = 1) or clearing IREN = 0.
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MAXQ611
Infrared Remote Control System-On-Chip
CARRIER GENERATION
CARRIER MODULATION
IR TIMER OVERFLOW
INTERRUPT TO CPU
IRCLK
0
1
IRCAH + 1
IRCAL + 1
0000h
IRV
IRCFME
IR INTERRUPT
COPY IRV TO IRMT
ON EDGE DETECT
IRXRL
RESET IRV TO 0000h
IRRX PIN
EDGE DETECT
IRDATA
Figure 4. IR Capture
The IRCFME bit is still used to define whether the IRV
register is counting system IRCLK clocks or IRCA-defined
carrier cycles. The IRXRL bit defines whether the IRV
register is reloaded with 0000h on detection of a qualified
edge (per the IRRXSEL bits). Figure 5 and the descriptive
sequence embedded in the figure illustrate the expected
usage of the receive burst-count mode.
Carrier Burst-Count Mode
A special mode reduces the CPU processing burden
when performing IR learning functions. Typically, when
operating in an IR learning capacity, some number of
carrier cycles are examined for frequency determina-
tion. Once the frequency has been determined, the IR
receive function can be reduced to counting the number
of carrier pulses in the burst and the duration of the
combined mark-space time within the burst. To simplify
this process, the receive burst-count mode (as enabled
by the RXBCNT bit) can be used. When RXBCNT = 0,
the standard IR receive capture functionality is in place.
When RXBCNT = 1, the IRV capture operation is disabled
and the interrupt flag associated with the capture no lon-
ger denotes a capture. In the carrier burst-count mode,
the IRMT register only counts qualified edges. The IRIF
interrupt flag (normally used to signal a capture when
RXBCNT = 0) now becomes set if two IRCA cycles elapse
without getting a qualified edge. The IRIF interrupt flag
thus denotes absence of the carrier and the beginning of
a space in the receive signal. When the RXBCNT bit is
changed from 0 to 1, the IRMT register is set to 0001h.
16-Bit Timers/Counters
Two instances of the timer/counter B are provided. These
timer/counters provide the following functions:
•
•
•
•
•
•
•
•
16-bit timer/counter
16-bit up/down autoreload
Counter function of external pulse
16-bit timer with capture
16-bit timer with compare
Input/output enhancements for pulse-width modulation
Set/reset/toggle output state on comparator match
n
Prescaler with 2 divider (for n = 0, 2, 4, 6, 8, 10)
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MAXQ611
Infrared Remote Control System-On-Chip
CARRIER FREQUENCY
CALCULATION
IRMT = PULSE COUNTING
IRMT = PULSE COUNTING
IRV = CARRIER CYCLE COUNTING
IRRX
IRV
IRMT
1
2
3
4
6
7
8
9
5
CAPTURE INTERRUPT (IRIF = 1).
IRV ≥ IRMT.
IRV = 0 (IF IRXRL = 1).
1
TO
4
5
SOFTWARE SETS IRCA = CARRIER FREQUENCY.
SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE).
SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1.
SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT.
IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS).
QUALIFIED EDGE DETECTED: IRMT++
IRV RESET TO 0 IF IRXRL = 1.
6
7
IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE.
BURST MARK = IRMT PULSES.
SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE.
8
9
QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE).
SOFTWARE SET RXBCNT = 1 AS IN (5).
CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
Figure 5. Receive Burst-Count Example
Data can be transferred as an 8-bit or 16-bit value, MSB
first. In addition, the SPI module supports configuration of
the active SSEL state through the slave active-select pin.
Serial Peripherals
Serial Peripheral Interface (SPI)
One instance of the SPI peripheral is provided. The SPI
is an interdevice bus protocol that provides fast, synchro-
nous, full-duplex communications between devices. The
integrated SPI interface acts as either an SPI master or
slave device. The master drives the synchronous clock
and selects which of several slaves is being addressed.
Every SPI peripheral consists of a single shift register and
control circuitry so that an addressed serial peripheral
interface SPI peripheral is simultaneously transmitting
and receiving. The maximum SPI master transfer rate is
Four signals are used in SPI communication:
•
SCLK: The synchronous clock used by all devices.
The master drives this clock and the slaves receive the
clock. Note that SCLK can be gated and need not be
driven between SPI transactions.
•
MOSI: Master out-slave in. This is the main data line
driven by the master to all slaves on the SPI bus. Only
the selected slave clocks data from MOSI.
f . The maximum SPI slave transfer rate is f
SYS/2
.
SYS/4
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MAXQ611
Infrared Remote Control System-On-Chip
•
•
MISO: Master in-slave out. This is the main data line
driven by the selected slave to the master. Only the
selected slave may drive this circuit. In fact, it is the
only circuit in the SPI bus arrangement that a slave is
ever permitted to drive.
General-Purpose I/O
The microcontroller provides port pins for general-pur-
pose I/O that have the following features:
•
•
•
CMOS output drivers
Schmitt trigger inputs
SSEL: This signal is unique to each slave. When
active (generally low), the selected slave must drive
MISO.
Optional weak pullup to V
mode
when operating in input
DD
While the microcontroller is in a reset state, all port pins
become high impedance with both weak pullups and input
buffers disabled, unless otherwise noted.
2
I C Bus
One instance of the I2C bus master/slave peripheral is
provided. The I2C bus is a 2-wire, bidirectional bus using
two bus lines—the serial data line (SDA) and the serial
clock line (SCL)—and a ground line. Both the SDA and
SDL lines must be driven as open-collector/drain outputs.
External resistors are required to pull the lines to a logic-
high state.
General-purpose, digital I/O pins (GPIO) have their input
and output states controlled by direction (PDx), output
(POx), and input (PIx) registers. From a software per-
spective, each 8-bit port appears as a group of peripheral
registers with unique addresses. All port pins default to
high-impedance mode after a reset, unless otherwise
noted. Software must configure these pins after release
from reset to remove the high-impedance condition.
The device supports both the master and slave proto-
cols. In the master mode, the device has ownership of
the I2C bus, drives the clock, and generates the START
and STOP signals. This allows it to send data to a slave
or receive data from a slave as required. In slave mode,
the device relies on an externally generated clock to drive
SCL and responds to data and commands only when
requested by the I2C master device.
Many GPIO pins share special functions with device
peripherals. All special functions must be enabled from
software before they can be used.
On-Chip Oscillator
An internal 12MHz oscillator is provided that requires no
external components, thereby reducig system cost, PCB
area, and radiated EMI.
USART
Two instances of the USART peripheral are provided. The
USARTS provide the following features:
Operating Modes
•
•
•
•
2-wire interface
The lowest power mode of operation is stop mode. In this
mode, CPU state and memories are preserved, but the
CPU is not actively running. Wake-up sources include
external I/O interrupts, the power-fail warning interrupt,
wake-up timer, or a power-fail reset. Any time the micro-
controller is in a state where code does not need to be
executed, the user software can put the device into stop
mode. The nanopower ring oscillator is an internal ultra-
low-power 8kHz ring oscillator that can drive a wake-up
timer that exits stop mode. The wake-up timer is program-
mable by software in steps of 125Fs up to approximately
8s.
Full-duplex operation for asynchronous data transfers
Half-duplex operation for synchronous data transfers
Programmable interrupt when transmit or receive data
operation completes
•
•
•
Independent programmable baud-rate generator
Optional 9th bit parity support
Start/stop bit support
Table 2. USART Mode Details
MODE
Mode 0
Mode 1
Mode 2
Mode 3
TYPE
START BITS
DATA BITS
STOP BITS
Synchronous
Asynchronous
Asynchronous
Asynchronous
N/A
1
8
N/A
1
8
1
8 + 1
8 + 1
1
1
1
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MAXQ611
Infrared Remote Control System-On-Chip
11
The power-fail monitor is always active during normal
operation.
•
•
•
2
2
2
nanopower ring oscillator clocks (~256ms)
nanopower ring oscillator clocks (~512ms)
nanopower ring oscillator clocks (~1.024s)
12
13
During stop mode, the power-fail monitor can be enabled
using the power-fail monitor bit (PFD). It is disabled
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
nanopower ring-oscillator cycles. If V
detection, V
ring-oscillator period. If V
third nanopower ring period, the CPU exits the reset state
and resumes normal operation from utility ROM at 8000h
after satisfying the crystal warmup period.
(PFD = 1) by default after a POR. If disabled, the V
<
DD
V
RST
condition does not invoke a reset state. Regardless
> V
during
DD
RST
of the PFD bit, the V
< V
condition generates a
DD
POR
is monitored for an additional nanopower
DD
POR in stop mode.
remains above V
for the
DD
RST
Regardless of the state of the PFD bit, the power-fail
monitor is enabled immediately prior to exiting stop mode.
If a power-fail warning condition (V
< V ) is then
PFW
DD
detected, the power-fail interrupt flag is set on stop mode
exit. If a power-fail condition is detected (V < V ),
The voltage (V
generated is user configurable through the PFWARNCN
bits. See the Electrical Characteristics table for the V
) below that a power-fail warning is
PFW
DD
RST
the device remains in reset and drives the RESET pin low.
PFW
Power-Fail Detection
options and corresponding PFWARNCN values.
Figure 6, Figure 7, and Figure 8 show the power-fail
detection and response during normal and stop-mode
operation. If a reset is caused by a power-fail, the power-
fail monitor can be set to one of the following intervals:
If the RESET pin is being driven active by an external
source, or a watchdog timer reset occurs, the power-fail,
internal regulator, and crystal oscillator (if present) remain
on during the reset event. The reset is exited in less than
20 f
cycles after the reset source is removed.
•
Always on—continuous monitoring
OSC
V
DD
t < t
PFW
t ≥ t
PFW
t ≥ t
t ≥ t
PFW
PFW
C
V
PFW
G
V
RST
E
H
F
B
D
V
POR
I
A
INTERNAL RESET
(ACTIVE HIGH)
Figure 6. Power-Fail Detection During Normal Operation
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MAXQ611
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Table 3. Power-Fail Detection States During Normal Operation
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
A
On
Off
On
Off
On
—
—
V
V
< V
.
DD
POR
< V
< V
.
POR
DD
RST
B
On
Crystal warmup time, t
.
XTAL_RDY
CPU held in reset.
V
> V
.
DD
RST
C
D
On
On
On
On
On
On
—
—
CPU normal operation.
Power drop too short.
Power-fail not detected.
V
< V
< V
.
RST
DD
PFW
PFI is set when V
< V
< V
and
RST
DD
PFW
maintains this state for at least t
time a power-fail interrupt is generated (if
, at which
PFW
E
On
On
On
—
enabled).
CPU continues normal operation.
V
< V
< V
.
POR
DD
RST
On
Power-fail detected.
CPU goes into reset.
F
Off
On
Off
On
Yes
—
(Periodically)
Power-fail monitor turns on periodically.
> V
V
.
RST
DD
G
On
Crystal warmup time, t
.
XTAL_RDY
CPU resumes normal operation from 8000h.
V
< V < V
.
RST
POR
DD
On
Power-fail detected.
CPU goes into reset.
H
I
Off
Off
Off
Off
Yes
—
(Periodically)
Power-fail monitor turns on periodically.
< V
V
.
POR
DD
Off
Device held in reset. No operation allowed.
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MAXQ611
Infrared Remote Control System-On-Chip
V
DD
t < t
PFW
t ≥ t
PFW
t ≥ t
PFW
A
V
PFW
D
V
RST
B
C
E
V
POR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
Figure 7. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 4. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
Application enters stop mode.
A
B
On
On
Off
Off
Off
Off
Yes
Yes
V
> V
.
DD
RST
CPU in stop mode.
Power drop too short.
Power-fail not detected.
V
< V
< V
.
RST
DD
PFW
Power-fail warning detected.
C
D
On
On
On
Off
On
Off
Yes
Yes
Turn on regulator and crystal.
Crystal warmup time, t
Exit stop mode.
.
XTAL_RDY
Application enters stop mode.
> V
V
.
RST
DD
CPU in stop mode.
< V < V .
RST
V
POR
DD
On
Power-fail detected.
CPU goes into reset.
E
F
Off
Off
Off
Off
Yes
—
(Periodically)
Power-fail monitor turns on periodically.
< V
V
.
POR
DD
Off
Device held in reset. No operation allowed.
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MAXQ611
Infrared Remote Control System-On-Chip
V
DD
A
D
V
PFW
B
V
RST
C
E
V
POR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
INTERRUPT
Figure 8. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
Application enters stop mode.
A
Off
Off
Off
Off
Off
Yes
Yes
V
> V
.
DD
RST
CPU in stop mode.
V
< V .
PFW
DD
B
Off
On
Power-fail not detected because power-fail
monitor is disabled.
V
< V
< V
.
RST
DD
PFW
An interrupt occurs that causes the CPU to
exit stop mode.
Power-fail monitor is turned on, detects a
power-fail warning, and sets the power-fail
interrupt flag.
C
On
On
Yes
Turn on regulator and crystal.
Crystal warmup time, t
.
XTAL_RDY
On stop mode exit, CPU vectors to the
higher priority of power-fail and the interrupt
that causes stop mode exit.
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MAXQ611
Infrared Remote Control System-On-Chip
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
(continued)
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
STATE
POWER-FAIL
COMMENTS
Application enters stop mode.
D
Off
Off
Off
Yes
V
> V
.
DD
RST
CPU in stop mode.
< V < V .
RST
V
POR
DD
An interrupt occurs that causes the CPU to
On
exit stop mode.
E
F
Off
Off
Off
Off
Yes
—
(Periodically)
Power-fail monitor is turned on, detects a
power-fail, and puts CPU in reset.
Power-fail monitor is turned on periodically.
V
< V
.
DD
POR
Off
Device held in reset. No operation allowed.
CMOS design guidelines for any semiconductor require
that no pin be taken above V or below GND. Violation
Applications Information
DD
The low-power, high-performance RISC architecture of
this device makes it an excellent fit for many portable or
battery-powered applications. It is ideally suited for appli-
cations such as universal remote controls that require the
cost-effective integration of IR transmit/receive capability.
of this guideline can result in a hard failure (damage to
the silicon inside the device) or a soft failure (unintentional
modification of memory contents). Voltage spikes above
or below the device’s absolute maximum ratings can
potentially cause a devastating IC latchup.
Grounds and Bypassing
Microcontrollers commonly experience negative voltage
spikes through either their power pins or general-purpose
I/O pins. Negative voltage spikes on power pins are espe-
cially problematic as they directly couple to the internal
power buses. Devices such as keypads can conduct
electrostatic discharges directly into the microcontroller
and seriously damage the device. System designers must
protect components against these transients that can cor-
rupt system memory.
Careful PCB layout significantly minimizes system-level
digital noise that could interact with the microcontroller
or peripheral components. The use of multilayer boards
is essential to allow the use of dedicated power planes.
The area under any digital components should be a con-
tinuous ground plane if possible. Keep bypass capacitor
leads short for best noise rejection and place the capaci-
tors as close to the leads of the devices as possible.
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MAXQ611
Infrared Remote Control System-On-Chip
Additional Documentation
Engineers must have the following documents to fully use
this device:
Development and Technical Support
Contact technical support for information about highly
versatile, affordable development tools, available from
Maxim Integrated and third-party vendors.
•
•
This data sheet, containing pin descriptions, feature
overviews, and electrical specifications.
•
•
•
•
Evaluation kits
The device-appropriate user guide, containing detailed
information and programming guidelines for core features
and peripherals.
Compilers
Integrated development environments (IDEs)
USB interface modules for programming and debugging
•
Errata sheets for specific revisions noting deviations from
published specifications.
For technical support, go to
support.maximintegrated.com/micro.
For information regarding these documents, visit Technical
Support at support.maximintegrated.com/micro.
Ordering Information/Selector Guide
OPERATING
VOLTAGE (V)
PROGRAM
MEMORY (KB)
DATA
MEMORY (KB)
PART
TEMP RANGE
GPIO
PIN-PACKAGE
MAXQ611J-XXXX+T*
MAXQ611X-XXXX+
-20°C to +70°C
-20°C to +70°C
1.70 to 3.6
80 Flash
2
2
32
38
44 TQFN-EP**
Bare die
1.70 to 3.6
80 Flash
Note: The 4-digit suffix “-XXXX” indicates a device preprogrammed at Maxim Integrated with proprietary customer-supplied software.
For more information on factory preprogramming of this device, contact Maxim Integrated at support.maximintegrated.com/micro.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Future product—contact factory for availability.
**EP = Exposed pad.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0144
LAND PATTERN NO.
90-0128
44 TQFN-EP
T4477+3C
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MAXQ611
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Appendix A
2
I C Serial Peripheral Specifications
(See Figure 9 and Figure 10.)
STANDARD MODE
FAST MODE
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
Supply voltages that
2
mismatch I C bus levels
Input Low Voltage
V
-0.5
0.3 x V
-0.5
0.3 x V
DD
V
IL_I2C
DD
must relate input levels to
the R pullup voltage
P
Supply voltages that
2
mismatch I C bus levels
V
0.5V
+
DD
Input High Voltage
V
0.7 x V
0.7 x V
V
IH_I2C
DD
DD
must relate input levels to
the R pullup voltage
P
Input Hysteresis
(Schmitt)
0.05 x
V
V
V
> 2V
V
V
IHYS_I2C
DD
DD
V
DD
Output Logic-Low (Open
Drain or Open Collector)
> 2V, 3mA sink
V
0
0.4
0
0.4
OL_I2C
current
Capacitive Load for Each
Bus Line
C
400
400
pF
B
Output Fall Time from
t
t
exceeds
, which permits
R/F_I2C
OF_I2C
V
to V
with
20 +
IH_MIN
IL_MAX
t
250
250
50
ns
ns
OF_I2C
Bus Capacitance from
RS to be connected as
0.1C
B
10pF to 400pF
shown in figure
Pulse Width of Spike
Filtering That Must Be
Suppressed by Input
Filter
t
0
SP_I2C
Input voltage from
Input Current on I/O
I/O Capacitance
I
-10
0
+10
10
-10
+10
10
FA
pF
IN_I2C
0.1 x V
to 0.9 x V
DD
DD
C
IO_I2C
2
I C Bus Operating
f
100
0
400
kHz
I2C
Frequency
System Frequency
f
0.90
3.60
MHz
Hz
SYS
2
I C Bit Rate
f
f
/8
f
/8
SYS
I2C
SYS
Hold Time After
(Repeated) START
t
4.0
0.6
Fs
HD:STA
Clock Low Period
Clock High Period
t
4.7
4.0
1.3
0.6
Fs
Fs
LOW_I2C
t
HIGH_I2C
Setup Time for Repeated
START
t
4.7
0.6
Fs
SU:STA
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MAXQ611
Infrared Remote Control System-On-Chip
2
I C Serial Peripheral Specification (continued)
(See Figure 9 and Figure 10.)
STANDARD MODE
FAST MODE
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
MAX
A device must internally
provide a hold time
of at least 300ns for
V
to bridge the
IH_I2C(MIN)
undefined region of the
falling edge of SCL. The
Hold Time for Data
t
0
3.45
0
0.9
Fs
HD:DAT
maximum t
needs
HD:DAT
to be met only if the
device does not stretch
the SCL low period
2
A fast-mode I C bus
device can be used in
2
a standard-mode I C
bus system; if such a
device does not stretch
the low period of the SCL
signal, it must output
the next data bit to the
Setup Time for Data
t
250
100
ns
ns
SU:DAT
SDA line t
+
R_I2C(MAX)
t
= 1000 + 250
SU:DAT
= 1250ns (according to
2
the standard-mode I C
specification) before the
SCL line is released
20 +
SDA/SCL Fall Time
t
300
300
300
F_I2C
0.1C
B
20 +
SDA/SCL Rise Time
Setup Time for STOP
t
1000
ns
Fs
Fs
R_I2C
0.1C
B
t
4.0
4.7
0.6
SU:STO
Bus Free Time Between
STOP and START
t
1.3
BUF
Noise Margin at the
Low Level for Each
Connected Device
(Including Hysteresis)
V
0.1 x V
0.1 x V
V
V
nL_I2C
DD
DD
DD
DD
Noise Margin at the
Low Level for Each
Connected Device
(Including Hysteresis)
V
0.2 x V
0.2 x V
nH_I2C
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MAXQ611
Infrared Remote Control System-On-Chip
2
I C Serial Diagrams
V
DD
2
I C
2
I C
DEVICE
DEVICE
R
R
P
P
MAXQ617
R
S
R
R
R
S
S
S
SDA
SCL
Figure 9. Series Resistors (R ) for Protecting Against High-Voltage Spikes
S
S
SR
P
S
SDA
t
BUF
t
t
R_I2C
F_I2C
t
t
t
SU:STA
LOW_I2C
SU:DAT
SCL
t
t
HIGH_I2C
HD:STA
t
t
SU:STO
HD:DAT
NOTE: TIMING REFERENCED TO V
AND V
IL_I2C(MAX).
IH_I2C(MIN)
2
Figure 10. I C Bus Controller Timing Diagram
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MAXQ611
Infrared Remote Control System-On-Chip
Serial Peripheral Interface (SPI) Specifications
(See Figure 11 and Figure 12.)
PARAMETER
SPI Master Frequency
SPI Slave Frequency
SPI Master Period
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
f
f
f
/2
MCK
SYS
f
/4
MHz
SCK
MCK
SYS
t
1/f
MCK
SPI Slave Period
t
1/f
SCK
SCK
SCLK Output Pulse-Width High/
Low
t
t
,
t
t
t
/2
MCH
MCK
- 35
ns
ns
ns
ns
ns
MCL
MOSI Output Hold Time After SCLK
Sample Edge
/2
MCK
- 35
t
MOH
/2
MCK
- 35
MOSI Output Valid to Sample Edge
t
MOV
MISO Input Valid to SCLK Sample
Edge Rise/Fall Setup
t
35
0
MIS
MIH
MISO Input to SCLK Sample Edge
Rise/Fall Hold
t
SCLK Input Pulse-Width High/Low
SSEL Active to First Shift Edge
t
, t
t
/2
ns
ns
SCH SCL
SCK
50
t
SSE
MOSI Input to SCLK Sample Edge
Rise/Fall Setup
t
35
35
ns
ns
SIS
MOSI Input from SCLK Sample
Edge Transition Hold
t
SIH
MISO Output Valid After SCLK Shift
Edge Transition
t
70
ns
ns
SOV
SCLK Inactive to SSEL Rising
t
35
SD
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SPI Timing Diagrams
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
(ACTIVE LOW)
t
MCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
t
t
MCH
MCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
t
MOH
t
t
RF
t
MLH
MOV
MOSI
MISO
MSB
MSB-1
LSB
t
t
MIH
MIS
MSB
MSB-1
LSB
Figure 11. SPI Master Communication Timing
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
(ACTIVE LOW)
t
SSH
t
SSE
t
SD
t
SCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
t
t
SCH
SCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
t
t
SIH
SIS
MOSI
MISO
MSB
MSB-1
LSB
t
t
RF
t
SLH
SOV
MSB
MSB-1
LSB
Figure 12. SPI Slave Communication Timing
Maxim Integrated
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MAXQ611
Infrared Remote Control System-On-Chip
USART Mode 0 Specifications
(See Figure 13.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
USART Clock Period
t
1/f
CLCL
SYS
CLCL
CLCL
CLCL
CLCL
SM2 = 0
SM2 = 1
SM2 = 0
SM2 = 1
SM2 = 0
SM2 = 1
SM2 = 0
SM2 = 1
SM2 = 0
SM2 = 1
SM2 = 0
SM2 = 1
12t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TXD Clock Period
t
XLXL
4t
3t
2t
TXD Clock High Time
t
XHXL
10t
RXD Output Data Valid to TXD
Clock Rising Edge
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
t
QVXH
XHQH
3t
2t
RXD Output Data Hold from TXD
Clock Rising Edge
t
t
t
t
t
t
RXD Input Data Valid to TXD
Clock Rising Edge
t
DVXH
XHDH
RXD Input Data Hold after TXD
Clock Rising Edge
t
USART Timing
t
XLXL
TXD CLOCK
RXD INPUT
t
XHXL
t
t
XHDH
DVXH
BIT X
BIT X + 1
t
t
XHQH
QVXH
RXD OUTPUT
BIT X
Figure 13. USART Timing Diagram
Maxim Integrated
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MAXQ611
Infrared Remote Control System-On-Chip
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
3/14
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
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