MX7839AS [MAXIM]
Octal, 13-Bit Voltage-Output DAC with Parallel Interface; 八路， 13位电压输出DAC ，并行接口
| 型号： | MX7839AS |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Octal, 13-Bit Voltage-Output DAC with Parallel Interface |
| 文件： | 总14页 (文件大小：374K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2952; Rev 0; 7/03
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
General Description
Features
The MX7839 contains eight 13-bit, voltage-output digital-
to-analog converters (DACs). On-chip precision output
amplifiers provide the voltage outputs. The device oper-
ates from ±1ꢀ5 supplies. ꢁts bipolar output voltage sꢂing
is ±1ꢃ5 and is achieved ꢂith no eꢄternal components.
The MX7839 has three pairs of differential reference
inputs; tꢂo of these pairs are connected to tꢂo DACs
each, and a third pair is connected to four DACs. The
references are independently controlled, providing differ-
ent full-scale output voltages to the respective DACs.
o Full 13-Bit Performance without Adjustments
o Eight DACs in a Single Package
o Buffered Voltage Outputs
o Unipolar or Bipolar Voltage Swing to 1ꢀV
o 31µs Output Settling Time
o Low Power Consumption: 8mA (typ)
o Small 44-Pin MQFP Package
The MX7839 features double-buffered interface logic
ꢂith a 13-bit parallel data bus. Each DAC has an input
latch and a DAC latch. Data in the DAC latch sets the
output voltage. The eight input latches are addressed
ꢂith three address lines. Data is loaded to the input
latch ꢂith a single ꢂrite instruction. An asynchronous
load input (LDAC) transfers data from the input latch to
the DAC latch. The LDAC input controls all DACs;
therefore, all DACs can be updated simultaneously by
asserting LDAC.
o Double-Buffered Digital Inputs
o Asynchronous Load Updates All DACs
Simultaneously
o Asynchronous CLR Forces All DACs to
DUTGND_ _ Potential
Ordering Information
An asynchronous CLR input sets the output of all eight
DACs to the respective DUTGND input of the op amp.
Note that CLR is a CMOS input, ꢂhich is poꢂered by
INL
(LSB)
PART
TEMP RANGE
PIN-PACKAGE
5 . All other logic inputs are TTL/CMOS compatible.
DD
MX7839AS
-4ꢃ°C to +8ꢀ°C
44 MQFP
±±
The MX7839 is pin-for-pin compatible ꢂith AD7839.
Applications
Automatic Test Equipment (ATE)
ꢁndustrial Process Controls
Pin Configuration
TOP VIEW
Arbitrary Function Generators
Avionics Equipment
Minimum Component Count Analog Systems
Digital Offset/Gain Adjustment
SONET Applications
DUTGNDAB
OUTA
1
33 DUTGNDGH
32 OUTH
2
3
4
5
6
7
8
9
REFAB-
REFAB+
31 REFGH-
30 REFGH+
V
DD
29
V
SS
V
SS
28 CLR
27 DB12
26 DB11
25 DB10
24 DB9
23 DB8
MX7839
LDAC
A2
A1
A0 10
CS 11
Functional Diagram appears at end of data sheet.
MQFP
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
ABSOLUTE MAXIMUM RATINGS
5
5
5
to GND ...........................................................-ꢃ.35 to +175
to GND ........................................................... -175 to +ꢃ.35
to GND ............................................................ -ꢃ.35 to +65
Maꢄimum Current into Any Signal Pin ..............................±ꢀꢃmA
OUT_ Short-Circuit Duration to 5 , 5 , and GND ................1s
DD
SS
CC
DD SS
Continuous Poꢂer Dissipation (T = +7ꢃ°C)
A
A_, DB_, WR, CS, LDAC, CLR to GND .....+ꢃ.35 to (5
REF_ _ _ _+, REF_ _ _ _-,
+ ꢃ.35)
44-Pin MQFP (derate 11.1mW/°C above +7ꢃ°C).........87ꢃmW
Operating Temperature Range ...........................-4ꢃ°C to +8ꢀ°C
Junction Temperature......................................................+1ꢀꢃ°C
Storage Temperature Range.............................-6ꢀ°C to +1ꢀꢃ°C
Lead Temperature (soldering, 1ꢃs) .................................+3ꢃꢃ°C
CC
DUTGND_ _ .................................(5 - ꢃ.35) to (5
+ ꢃ.35)
SS
DD
OUT_ ..........................................................................5
Maꢄimum Current into REF_ _ _ _ _, DUTGND_ _ ...........±1ꢃmA
to 5
SS
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5 _ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, R = ꢀkΩ,
REF REF L
DD
SS
to T
CC
GND
DUTGND_ _
C = ꢀꢃpF, T = T
, unless otherꢂise noted. Typical values are at T = +±ꢀ°C.)
L
A
MꢁN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (ANALOG SECTION)
Resolution
N
13
Bits
LSB
LSB
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
ꢁNL
DNL
±±
±ꢃ.9
±8
Guaranteed monotonic
±±
±1
±1
±4
ppm
FSR/°C
Gain Temperature Coefficient
(Note 1)
(Note 1)
ꢃ.ꢀ
7ꢀ
1ꢃ
DC Crosstalk
1±ꢃ
µ5
REFERENCE INPUTS
ꢁnput Resistance
1ꢃꢃ
MΩ
µA
5
ꢁnput Current
±1
ꢀ
REF_ _ _ _+ ꢁnput Range
REF_ _ _ _- ꢁnput Range
ꢃ
-ꢀ
ꢃ
5
(REF_ _ _ _+) - (REF_ _ _ _-)
Range
±
1ꢃ
5
ANALOG OUTPUTS
Output 5oltage Sꢂing
Resistive Load to GND
Capacitive Load to GND
DC Output ꢁmpedance
-1ꢃ
ꢀ
+1ꢃ
kΩ
kΩ
pF
Ω
ꢀꢃ
(Note 1)
ꢃ.ꢀ
2
_______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5 _ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, R = ꢀkΩ,
REF REF L
DD
SS
to T
CC
GND
DUTGND_ _
C = ꢀꢃpF, T = T
, unless otherꢂise noted. Typical values are at T = +±ꢀ°C.)
L
A
MꢁN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DUTGND_ _ CHARACTERISTICS
ꢁnput ꢁmpedance per DAC
Maꢄimum ꢁnput Current per DAC
ꢁnput Range
6ꢃ
kΩ
µA
5
±3ꢃꢃ
-±
+±
DIGITAL INPUTS
ꢁnput 5oltage High
5
±.4
5
5
ꢁH
ꢁnput 5oltage Loꢂ
5
ꢃ.8
1ꢃ
ꢁL
ꢁnput Capacitance
C
(Note 1)
pF
µA
ꢁN
ꢁnput Current
ꢁ
ꢁN
Digital inputs = ꢃ5 or 5
±1
±1ꢃ
CC
POWER SUPPLIES
5
Analog Poꢂer-Supply
DD
5
14.±ꢀ
1ꢀ.7ꢀ
5
5
DD
Range
5
SS
Analog Poꢂer-Supply
5
-14.±ꢀ
4.7ꢀ
-1ꢀ.7ꢀ
SS
Range
5
CC
Digital Poꢂer Supply
5
CC
ꢀ.±ꢀ
1ꢃ
5
Positive Supply Current
Negative Supply Current
Digital Supply Current
ꢁ
R = ∞
8
8
mA
mA
mA
dB
dB
DD
L
ꢁ
SS
R = ∞
L
1ꢃ
ꢁ
Digital inputs = ꢃ5 or 5 (Note ±)
ꢃ.ꢀ
CC
CC
PSRR, ∆5
PSRR, ∆5
/ ∆5
/ ∆5
5
DD
5
SS
= +1ꢀ5 ±ꢀꢅ
= -1ꢀ5 ±ꢀꢅ
9ꢃ
9ꢃ
OUT
OUT
DD
SS
INTERFACE TIMING CHARACTERISTICS
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5
_ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, Figure ±a,
REF REF
DD
SS
CC
GND
DUTGND_ _
T
A
= T
to T
, unless otherꢂise noted.)
MꢁN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
ꢀꢃ
ꢀꢃ
ꢀꢃ
ꢃ
TYP
MAX
UNITS
ns
t
1
CS Pulse Width Loꢂ
t
±
ns
WR Pulse Width Loꢂ
t
3
ns
LDAC Pulse Width Loꢂ
CS Loꢂ to WR Loꢂ
t
4
ns
t
ꢀ
ꢃ
ns
CS High to WR High
t
±ꢃ
ꢃ
ns
Data 5alid to WR Setup
Data 5alid to WR Hold
Address 5alid to WR Setup
Address 5alid to WR Hold
CLR Pulse-Activation Time
6
t
7
ns
t
8
1ꢀ
ꢃ
ns
t
9
ns
t
1ꢃ
Figure ±b
3ꢃꢃ
ns
_______________________________________________________________________________________
3
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
DYNAMIC CHARACTERISTICS
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5 _ _ _ _+ = +ꢀ5, 5 _ _ _ _- = -ꢀ5, R = ꢀkΩ,
REF REF L
DD
SS
to T
CC
GND
DUTGND_ _
C = ꢀꢃpF, T = T
, unless otherꢂise noted. Typical values are at T = +±ꢀ°C.)
L
A
MꢁN
MAX A
PARAMETER
SYMBOL
CONDITIONS
To ±ꢃ.ꢀ LSB of full scale
MIN
TYP
MAX
UNITS
µs
Output Settling Time
Output Sleꢂ Rate
Digital Feedthrough
Digital Crosstalk
31
ꢃ.7
ꢃ.1
ꢃ.±
±3ꢃ
4ꢃ
5/µs
n5-s
n5-s
n5-s
n5-s
dB
(Note 3)
(Note 4)
Digital-to-Analog Glitch ꢁmpulse
DAC-to-DAC Crosstalk
Channel-to-Channel ꢁsolation
Output Noise Spectral Density
99
5
REF+
= 5
= ꢃ5
±ꢃꢃ
n5/√Hz
REF-
Note 1: Guaranteed by design. Not production tested.
Note 2: All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at GND or 5
potential.
CC
Note 3: All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at +ꢃ.85 or +±.45.
Note 4: All digital inputs (DBꢃ to DB1±) transition from GND to 5
ꢂith WR = 5
.
CC
CC
Typical Operating Characteristics
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5
_ _ _ _+ = +ꢀ5, 5
_ _ _ _- = -ꢀ5, T = +±ꢀ°C,
REF A
DD
SS
CC
GND
DUTGND_ _
REF
unless otherꢂise noted.)
INL AND DNL ERROR
vs. TEMPERATURE
INL vs. CODE
DNL vs. CODE
0.400
0.300
0.200
0.100
0
0.300
0.200
0.100
0.4
0.3
0.2
0.1
DNL
0
-0.100
-0.200
0
-0.100
-0.200
-0.300
-0.400
-0.1
-0.2
-0.3
-0.4
INL
-0.300
0
2048
4096
6144
8192
0
2048
4096
6144
8192
-40
-20
0
20
40
60
80
CODE
CODE
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Typical Operating Characteristics (continued)
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5
_ _ _ _+ = +ꢀ5, 5
_ _ _ _- = -ꢀ5, T = +±ꢀ°C,
REF A
DD
SS
CC
GND
DUTGND_ _
REF
unless otherꢂise noted.)
ZERO-SCALE AND FULL-SCALE ERROR
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
I
AND I
SS
DD
vs. TEMPERATURE
vs. TEMPERATURE
1.2
1.0
0.8
0.6
0.4
0.2
0
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
8.0
7.5
7.0
6.5
6.0
5.5
5.0
I
DD
ZERO SCALE
I
SS
-0.2
-0.4
-0.6
-0.8
FULL SCALE
-40
-20
0
20
40
60
80
-40 -25 -10
5
20 35 50 65 80
-40 -25 -10
5
20 35 50 65 80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SETTLING TIME
vs. CAPACITIVE LOAD
REFERENCE INPUT FREQUENCY RESPONSE
LARGE-SIGNAL STEP RESPONSE
100
90
80
70
60
50
40
30
20
10
0
5
REF_ _ _ _ _ = 200mV
P-P
0
LDAC
-5
5V/div
-10
-15
-20
-25
-30
-35
-40
OUT_
5V/div
10
100
1000
10,000
100,000
1k
10k
100k
1M
10M
10µs/div
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
NOISE VOLTAGE DENSITY
vs. FREQUENCY
POSITIVE SETTLING TIME
NEGATIVE SETTLING TIME
1000
LDAC
5V/div
LDAC
5V/div
OUT_
1mV/div
OUT_
1mV/div
100
10µs/div
10µs/div
10
100
1k
10k
FREQUENCY (Hz)
_______________________________________________________________________________________
5
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Typical Operating Characteristics (continued)
(5
= +1ꢀ5 ±ꢀꢅ, 5 = -1ꢀ5 ±ꢀꢅ, 5
= +ꢀ5 ±ꢀꢅ, 5
= 5
= ꢃ, 5
_ _ _ _+ = +ꢀ5, 5
_ _ _ _- = -ꢀ5, T = +±ꢀ°C,
REF A
DD
SS
CC
GND
DUTGND_ _
REF
unless otherꢂise noted.)
MAJOR CARRY GLITCH IMPULSE
REF
(0xOFFF–0x1000)
MX7839 toc13
1.0
0.8
0.6
0.4
0.2
0
LDAC
LDAC
5V/div
5V/div
OUT
OUT
5mV/div
-0.2
-0.4
-0.6
-0.8
5mV/div
-1.0
0
2µs/div
2µs/div
2
4
6
8
10
V
REF
(V)
FULL-SCALE ERROR
vs. V
(V
- V
)
)
)
REF REF+
REF-
1.0
0.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0.6
0.4
0.2
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
-0.8
-1.0
0
2
4
6
8
10
0
2
8
10
0
2
8
10
V (V)
REF
V
REF
(V)
V
REF
(V)
INL (MAX, MIN)
SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
vs. V
(V
- V
)
REF REF+
REF-
1.0
0.8
0.6
0.4
0.2
0
30
20
ZERO-SCALE OUTPUT,
SINKING CURRENT
10
0
-10
-20
-30
-40
-0.2
-0.4
-0.6
-0.8
-1.0
FULL-SCALE OUTPUT,
SOURCING CURRENT
0
2
4
6
8
10
-40 -25 -10
5
20 35 50 65 80
°
TEMPERATURE ( C)
V
REF
(V)
6
_______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Pin Description
PIN
NAME
FUNCTION
Device Sense Ground ꢁnput for OUTA and OUTB. ꢁn normal operation, OUTA and OUTB are referenced
to DUTGNDAB. When CLR is loꢂ, OUTA and OUTB are forced to the potential on DUTGNDAB.
1
DUTGNDAB
±
3
4
OUTA
REFAB-
REFAB+
DAC A Buffered Output 5oltage
Negative Reference ꢁnput for DACs A and B
Positive Reference ꢁnput for DACs A and B
Positive Analog Poꢂer Supply. Normally set to +1ꢀ5. Connect both pins to the supply voltage. See the
Power Supplies, Grounding, and Bypassing section for bypass requirements.
ꢀ, 38
6, ±9
5
DD
Negative Analog Poꢂer Supply. Normally set to -1ꢀ5. See the Power Supplies, Grounding, and
Bypassing section for bypass requirements.
5
SS
Load ꢁnput. Drive this asynchronous input loꢂ to transfer the contents of the input latches to their
7
LDAC
respective DAC latches. DAC latches are transparent ꢂhen LDAC is loꢂ and latched ꢂhen LDAC is
high.
8
9
A±
A1
Aꢃ
CS
Address Bit ± (MSB)
Address Bit 1
1ꢃ
11
Address Bit ꢃ (LSB)
Chip Select. Active-loꢂ input.
Write ꢁnput. Active-loꢂ strobe for conventional memory ꢂrite sequence. ꢁnput data latches are transpar-
ent ꢂhen WR and CS are both loꢂ. WR latches data into the DAC input latch selected by A±, A1, Aꢃ on
the rising edge of CS.
1±
13
WR
Digital Poꢂer Supply. Normally set to +ꢀ5. See the Power Supplies, Grounding, and Bypassing section
for bypass requirements.
5
CC
14
GND
Ground
1ꢀ–±7
DBꢃ–DB1±
Data Bits ꢃ–1±. Offset binary coding.
Clear ꢁnput. Drive CLR loꢂ to force all DAC outputs to the voltage on their respective DUTGND _ _.
±8
CLR
Does not affect the status of internal registers. All DACs return to their previous levels ꢂhen CLR goes
high.
3ꢃ
31
REFGH+
REFGH-
Positive Reference ꢁnput for DACs G and H
Negative Reference ꢁnput for DACs G and H
_______________________________________________________________________________________
7
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Pin Description (continued)
PIN
NAME
FUNCTION
3±
OUTH
DAC H Buffered Output 5oltage
Device Sense Ground ꢁnput for OUTG and OUTH. ꢁn normal operation, OUTG and OUTH are referenced
to DUTGNDGH. When CLR is loꢂ, OUTG and OUTH are forced to the potential on DUTGNDGH.
33
DUTGNDGH
34
3ꢀ
OUTG
OUTF
DAC G Buffered Output 5oltage
DAC F Buffered Output 5oltage
Device Sense Ground ꢁnput for OUTE and OUTF. ꢁn normal operation, OUTE and OUTF are referenced
to DUTGNDEF. When CLR is loꢂ, OUTE and OUTF are forced to the potential on DUTGNDEF.
36
DUTGNDEF
37
39
4ꢃ
41
OUTE
REFCDEF+
REFCDEF-
OUTD
DAC E Buffered Output 5oltage
Positive Reference ꢁnput for DACs C, D, E, and F
Negative Reference ꢁnput for DACs C, D, E, and F
DAC D Buffered Output 5oltage
Device Sense Ground ꢁnput for OUTC and OUTD. ꢁn normal operation, OUTC and OUTD are referenced
to DUTGNDCD. When CLR is loꢂ, OUTC and OUTD are forced to the potential on DUTGNDCD.
4±
DUTGNDCD
43
44
OUTC
OUTB
DAC C Buffered Output 5oltage
DAC B Buffered Output 5oltage
8
_______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
_______________Detailed Description
CLR
Analog Section
R
R
The MX7839 contains eight 13-bit voltage-output DACs.
OUT
These DACs are inverted R-±R ladder netꢂorks that
convert 13-bit digital inputs into equivalent analog out-
2R
2R
2R
2R
2R
2R
put voltages, in proportion to the applied reference volt-
ages (Figure 1). The MX7839 has three positive
reference inputs (REF_ _ _ _+) and three negative refer-
ence inputs (REF_ _ _ _-). The difference from
REF_ _ _ _+ to REF_ _ _ _-, multiplied by tꢂo, sets the
DAC output span.
D0
D12
D13
DUTGND
REF-
REF+
ꢁn addition to the differential reference inputs, the
MX7839 has four analog-ground input pins
(DUTGND_ _). When CLR is high (unasserted), the volt-
age on DUTGND_ _ offsets the DAC output voltage
range. ꢁf CLR is asserted, the output amplifier is forced
to the voltage present on DUTGND_ _.
Figure 1. DAC Simplified Circuit
Reference and DUTGND Inputs
All of the MX7839’s reference inputs are buffered ꢂith
precision amplifiers. This alloꢂs the fleꢄibility of using
resistive dividers to set the reference voltages. Because
of the relatively high multiplying bandꢂidth of the refer-
ence input (188kHz), any signal present on the reference
pin ꢂithin this bandꢂidth is replicated on the DAC output.
t
1
CS
t
4
t
5
The DUTGND pins of the MX7839 are connected to the
negative source resistor (nominally 11ꢀkΩ) of the out-
put amplifier. The DUTGND pins are typically connect-
ed directly to analog ground. Each of these pins has an
input current that varies ꢂith the DAC digital code. ꢁf
the DUTGND pins are driven by eꢄternal circuitry, bud-
get ±±ꢃꢃµA per DAC for load current.
t
2
WR
t
8
t
9
A0–A2
Output-Buffer Amplifiers
The MX7839’s voltage outputs are internally buffered by
precision gain-of-tꢂo amplifiers ꢂith a typical sleꢂ rate
of 15/µs. With a full-scale transition at its output, the
typical settling time to ±1/± LSB is 31µs. This settling
time does not significantly vary ꢂith capacitive loads
less than 1ꢃ,ꢃꢃꢃpF.
t
6
t
7
DB0–DB12
t
t
3
(NOTE 3)
3
LDAC
CLR
NOTES:
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. t = t = 5ns.
r
f
V
OUT_
2. MEASUREMENT REFERENCE LEVEL IS (V + V ) / 2.
INH
INL
t
10
t
10
3. IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW
FOR t OR LONGER AFTER WR GOES HIGH.
3
Figure 2a. Digital Timing Diagram
Figure 2b. Digital Timing Diagram
_______________________________________________________________________________________
9
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
input latches and the DAC latches are transparent
Output Deglitching Circuit
The MX7839’s internal connection from the DAC ladder
to the output amplifier contains special deglitch circuitry.
This glitch/deglitch circuitry is enabled on the falling
edge of LDAC to remove the glitch from the R-±R DAC.
This enables the MX7839 to eꢄhibit a fraction of the glitch
impulse energy of parts ꢂithout the deglitching circuit.
ꢂhen CS, WR, and LDAC are all loꢂ. Any change of
DBꢃ–DB1± during this condition appears at the output
instantly. Transfer data from the input latches to the
DAC latches by asserting the asynchronous LDAC sig-
nal. Each DAC’s analog output reflects the data held in
its DAC latch. All control inputs are level triggered.
Table ± is an interface truth table.
Digital Inputs and Interface Logic
All digital inputs are compatible ꢂith both TTL and
CMOS logic. The MX7839 interfaces ꢂith microproces-
sors using a data bus at least 13 bits ꢂide. The inter-
face is double buffered, alloꢂing simultaneous
updating of all DACs. There are tꢂo latches for each
DAC (see the Functional Diagram): an input latch that
receives data from the data bus, and a DAC latch that
receives data from the input latch. Address lines Aꢃ,
A1, and A± select ꢂhich DAC’s input latch receives
data from the data bus as shoꢂn in Table 1. Both the
Input Write Cycle
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch, and LDAC transfers
information from the input latch to the DAC latch. The
input latch is transparent ꢂhen CS and WR are loꢂ,
and the DAC latch is transparent ꢂhen LDAC is loꢂ.
The address lines (Aꢃ, A1, A±) must be valid for the
duration that CS and WR are loꢂ (Figure ±a) to prevent
data from being inadvertently ꢂritten to the ꢂrong DAC.
Data is latched ꢂithin the input latch ꢂhen either CS or
WR is high.
Table 1. MX7839 DAC Addressing
Loading the DACs
Taking LDAC high latches data into the DAC latches. ꢁf
LDAC is brought loꢂ ꢂhen WR and CS are loꢂ, the
DAC addressed by Aꢃ, A1, and A± is directly con-
trolled by the data on DBꢃ–DB1±. This alloꢂs the maꢄi-
mum digital update rate; hoꢂever, it is sensitive to any
glitches or skeꢂ in the input data stream.
A2
A1
Aꢀ
FUNCTION
ꢃ
ꢃ
ꢃ
DAC A input latch
DAC B input latch
DAC C input latch
DAC D input latch
DAC E input latch
DAC F input latch
DAC G input latch
DAC H input latch
ꢃ
ꢃ
1
ꢃ
1
ꢃ
ꢃ
1
1
Asynchronous Clear
The MX7839 has an asynchronous clear pin (CLR) that,
ꢂhen asserted, sets all DAC outputs to the voltage pre-
sent on their respective DUTGND pins. Deassert CLR to
return the DAC output to its previous voltage. Note that
CLR does not clear any of the internal digital registers.
See Figure ±b.
1
ꢃ
ꢃ
1
ꢃ
1
1
1
ꢃ
1
1
1
Table 2. Interface Truth Table
Applications Information
FUNCTION
CLR
X
LD
X
WR
ꢃ
CS
ꢃ
Multiplying Operation
The MX7839 can be used for multiplying applications.
ꢁts reference accepts both DC and AC signals. Since
the reference inputs are unipolar, the multiplying opera-
tion is limited to tꢂo quadrants. See the graphs in the
Typical Operating Characteristics for dynamic perfor-
mance of the DACs and output buffers.
ꢁnput register transparent
ꢁnput register latched
ꢁnput register latched
DAC register transparent
DAC register latched
X
X
X
1
X
X
1
X
X
ꢃ
X
X
X
1
X
X
Digital Code and
Analog Output Voltage
Outputs of DACs at
DUTGND_ _
ꢃ
1
X
1
X
X
X
X
The MX7839 uses offset binary coding. A 13-bit tꢂo’s
complement code is converted to a 13-bit offset binary
Outputs of DACs set to volt-
age defined by the DAC
register, the references,
and the corresponding
DUTGND_ _
1±
code by adding ± = 4ꢃ96.
X = Don’t care.
1ꢀ ______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Table 3. Analog Voltage vs. Digital Code
± REF+ − REF−
(
)
LSB =
OUTPUT
13
INPUT CODE
±
VOLTAGE (V)
1 1111 1111 1111
1 0000 0000 0000
0 1001 1101 1001
0 0000 0000 0001
0 0000 0000 0000
+9.997558
0
Reference Selection
Because the MX7839 has precision buffers on its refer-
ence inputs, the requirements for interfacing to these
inputs are minimal. Select a loꢂ-drift, loꢂ-noise refer-
ence ꢂithin the recommended REF+ and REF- voltage
ranges. The MX7839 does not require bypass capaci-
tors on its reference inputs. Add capacitors only if the
reference voltage source requires them to meet system
specifications.
-3.845215
-9.997558
-10
Note: Output voltage is based on REF+ = +5V, REF- = -5V, and
DUTGND = 0V.
Output Voltage Range
Minimizing Output Glitch
The MX7839’s internal deglitch circuitry is enabled on
the falling edge of LDAC. Therefore, to achieve opti-
mum performance, drive LDAC loꢂ after the inputs are
either latched or steady state. This is best accom-
plished by having the falling edge of LDAC occur at
least ꢀꢃns after the rising edge of CS.
For typical operation, connect DUTGND to signal ground,
5
+ to +ꢀ5, and 5
- to -ꢀ5. Table 3 shoꢂs the rela-
tionship betꢂeen digital code and output voltage.
REF
REF
The DAC digital code controls each leg of the 13-bit
R-±R ladder. A code of ꢃꢄꢃ connects all legs of the lad-
der to REF-, corresponding to a DAC output voltage
(5
) equal to REF-. A code of ꢃꢄ1FFF connects all
DAC
Power Supplies, Grounding,
and Bypassing
For optimum performance, use a multilayer PC board
ꢂith an unbroken analog ground. For normal operation,
connect the four DUTGND pins directly to the ground
plane. Avoid sharing the connections of these sensitive
pins ꢂith other ground traces.
legs of the ladder to REF+, corresponding to a 5
approꢄimately equal to REF+.
DAC
The output amplifier multiplies 5
by ±, yielding an out-
DAC
✕
✕
put voltage range of ± REF- to ± REF+ (Figure 1).
Further manipulation of the output voltage span is accom-
plished by offsetting DUTGND. The output voltage of the
MX7839 is described by the folloꢂing equation:
As ꢂith any sensitive data-acquisition system, connect
the digital and analog ground planes together at a sin-
gle point, preferably directly underneath the MX7839.
Avoid routing digital signals underneath the MX7839 to
minimize their coupling into the ꢁC.
DATA
5
= ± 5
− 5
+ 5
REF−
(
)
OUT
REF+
REF−
13
±
− 5
DUTGND
For normal operation, bypass 5
and 5 ꢂith ꢃ.1µF
SS
DD
ꢂhere DATA is the numeric value of the DAC’s binary
input code, and DATA ranges from ꢃ to 8191
(± - 1). The resolution of the MX7839, defined as
1 LSB, is described by the folloꢂing equation:
ceramic chip capacitors to the analog ground plane. To
enhance transient response and capacitive drive capa-
bility, add 1ꢃµF tantalum capacitors in parallel ꢂith the
ceramic capacitors. Note, hoꢂever, that the MX7839
does not require the additional capacitance for stability.
13
Bypass 5
ꢂith a ꢃ.1µF ceramic chip capacitor to the
CC
digital ground plane.
______________________________________________________________________________________ 11
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Power-Supply Sequencing
To guarantee proper operation of the MX7839, ensure
that power is applied to V
before V and V . Also
SS CC
DD
ensure that V
is never more than 300mV above
SS
V
SS
V
SS
V
SS
ground. To prevent this situation, connect a Schottky
diode between V and the analog ground plane, as
SS
shown in Figure 3. Do not power up the logic input pins
before establishing the supply voltages. If this is not
possible and the digital lines can drive more than
10mA, place current-limiting resistors (e.g., 470Ω) in
series with the logic pins.
MX7839
1N5817
GND
Driving Capacitive Loads
The MX7839 typically drives capacitive loads up to
0.01µF without a series output resistor. However, when-
ever driving high capacitive loads, it is prudent to use a
220Ω series resistor between the MX7839 output and
the capacitive load.
SYSTEM GND
Figure 3. Schottky Diode Between V and GND
SS
Chip Information
TRANSISTOR COUNT: 13,225
PROCESS: BiCMOS
12 ______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Functional Diagram
REFAB-
REFAB+
REFCDEF-
REFCDEF+
REFGH-
REFGH+
______________________________________________________________________________________ 13
Octal, 13-Bit Voltage-Output DAC
with Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
44L MQFP, 1.60 LEAD FORM
1
21-0826
D
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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