MX28F3204C3TXBI-70 [Macronix]
Memory Circuit, 2MX16, CMOS, PBGA66, 10 X 8 X 1.40 MM, 0.80 MM PITCH, MO-219, CSP-66;型号: | MX28F3204C3TXBI-70 |
厂家: | MACRONIX INTERNATIONAL |
描述: | Memory Circuit, 2MX16, CMOS, PBGA66, 10 X 8 X 1.40 MM, 0.80 MM PITCH, MO-219, CSP-66 静态存储器 内存集成电路 |
文件: | 总54页 (文件大小:470K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX28F3204C3T/B
32M-BIT[X16]FLASHAND4M-BIT[X16]SRAM
MIXEDMULTICHIPPACKAGEMEMORY
FEATURES
• Supply voltage range: 2.7V to 3.6V
• Fast access time: Flash memory:70/90ns
SRAM memory:70/85ns
• Automatic Suspend Enhance
- Word write suspend to read
- Sector erase suspend to word write
- Sector erase suspend to read register report
• Automatic sector erase, word write and sector lock/
unlockconfiguration
• Operation temperature range: -40 ~ 85°C
FLASH
• Word mode only
• 100,000 minimum erase/program cycles
• Boot Sector Architecture
• VCCf=2.7V~3.6V for read, erase and program opera-
tion
- T = Top Boot Sector
- B = Bottom Boot Sector
• VCCQ=1.65V~2.5V or 2.7V~3.6V I/O option
• VPP=12V for fast production programming
• Lowpowerconsumption
• Status Register feature for detection of program or
erase cycle completion
• Data protection performance
- 9mA typical active read current, f=5MHz
- 18mA typical program current (VPP=1.65~3.6V)
- 21mA typical erase current (VPP=1.65~3.6V)
-7uAtypicalstandbycurrentunderpowersavingmode
• Sectorarchitecture
- Sectors to be locked/unlocked
• Common Flash Interface (CFI)
• 128-bitProtectionRegister
- 64-bit Unique Device Identifier
-64-bitUser-Programmable
-Sectorstructure:4Kwordx2(bootsectors), 4Kword
x 6 (parameter sectors), 32Kword x 63 (main sectors)
- Top/Bottom Boot
• Latch-up protected to 100mA from -1V to VCC+1V
SRAM
• Auto Erase and Auto Program
- Automatically program and verify data at specified
address
• MX28F3204C3T/B: 256K wordx16 Bit
• 70mA maximum active current
• 1uA typical standby current
• Data retention supply voltage: 2.0V~3.6V
• Byte data control : LBs(Q0 to Q7) and UBs(Q8 to Q15)
- Auto sector erase at specified sector
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MX28F3204C3T/B
mand sequence to the CUI. A sector erase operation
erases one of the device's 32K-word sectors typically
within 1.0s, 4K-word sectors typically within 0.5s inde-
pendent of other sectors. Each sector can be indepen-
dently erased minimum 100,000 times. Sector erase
suspend mode allows system software to suspend sec-
tor erase to read or write data from any other sector.
GENERAL DESCRIPTION
The MXIC's mixed multi chip memory combines Flash
and SRAM into a single package. The mixed multi chip
memory operates 2.7 to 3.6V power supply to allow for
simple in-system operation.
The Flash memory of mixed multi chip memory manu-
factured with MXIC's advanced nonvolatile memory tech-
nology, the flash memory of mixed multi chip memory
is designed to be re-programmed and erased in system
or in standard EPROM programmers. The device offers
access times of 70ns/90ns, and 7uA typical standby
current.
Flash program automation allows program operation to
be executed using an industry-standard two-write com-
mand sequence to the CUI.Writing memory data is per-
formed in word increments of the device's 32K-word sec-
tors typically within 0.8s and 4K-word sectors typically
within 0.1s. Word program suspend mode enables the
system to read data or execute code from any other
memory array location.
Flash memories augment EPROM functionality with in-
circuit electrical erasure and programming and use a
command register to manage this functionality. The com-
mand register allows for 100% TTL level control inputs
and fixed power supply levels during erase and program-
ming, while maintaining maximum EPROM compatibil-
ity.
The Flash features with individual sectors locking by
using a combination of seventy-one sector lock-bits and
WP, to lock and unlock sectors.
The Flash status register indicates the status of theWSM
when the sector erase, word program or lock configura-
tion operation is done.
Flash memory reliably stores memory contents even af-
ter 100,000 erase and program cycles. The cell is de-
signed to optimize the erase and programming mecha-
nisms. In addition, the combination of advanced tunnel
oxide processing and low internal electric fields for erase
and program operations produces reliable cycling.
The Flash power saving mode feature substantially re-
duces active current when the device is in static mode
(addresses not switching). In this mode, the typical ICCS
current is 7uA (CMOS) at 3.0V VCC. As CEf and R E -
SET are at VCC, ICC CMOS standby mode is enabled.
When RESET is at GND, the reset mode is enabled which
minimize power consumption and provide data write pro-
tection.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamperes on
address and data pin from -1V to VCC + 1V.
The Flash require a reset time (tPHQV) from RESET
switching high until outputs are valid.Similarly, the flash
has a wake time (tPHEL) from RESET-high until writes
to the CUI are recognized. With RESET at GND, the
WSM is reset and the status register is cleared.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
The Flash contains both a Command User Interface (CUI)
and a Write State Machine (WSM). A Command User
Interface (CUI) serves as the interface between the sys-
tem processor and internal operation of the device. A
valid command sequence written to the CUI initiates
device automation. An internal Write State Machine
(WSM) automatically executes the algorithms and tim-
ings necessary for erase, word write and sector lock/
unlock configuration operations.
The 4M-bit SRAM of MX28F3204C3T/B is organized
256K-word by 16-bit.The advanced CMOS technology
and circuit techniques provide both high speed and low
power features of with a typical CMOS standby current
of 1uA and maximum access time of 70ns/85ns in 3V
operation.
The mixed multi chip memory is available in 10mm x
8mm FBGA Package to suit a variety of design applica-
tions.
Flash erase automation allows sector erase operation to
be executed using an industry-standard two-write com-
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MX28F3204C3T/B
Feature Summary
Feature
MX28F3204C3T/B
Vcc OperatingVoltage
Configuration
2.7~3.6V
Flash
32M:2MWord x16bit
SRAM 4M:256KWord x16bit
Fast Access Time
Block Architecture
- 70 :
- 90 :
Flash
Flash/70ns, SRAM/70ns
Flash/90ns, SRAM/85ns
2 x 4K Word Boot
6 x 4KWord Parameter
63 x 32K Word Main
A0~A20
Address Pin
Flash
SRAM A0~A17
Manufacture Code
Device ID Code
Flash
Flash
00C2H
MX28F3204C3T=88C4H
MX28F3204C3B=88C5H
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MX28F3204C3T/B
PIN ASSIGNMENT
66-ball CSP for MX28F3204C3T/B (Top View Balls Down, 10 x 8 x 1.4mm, Ball Pitch=0.8mm)
A15
A10
A14
A9
A13
A
B
C
D
E
F
NC
NC
A20
A12
GNDf VCCQ
NC
NC
A11
Q14
Q4
Q7
Q5
A16
WEf
A8
Q15
Q13
Q12
WEs
Q6
NC
VCCs VCCf
GNDs
CE2s
RESET
VPP
Q3
Q1
Q2
Q0
WP
LBs
A19
OEs
Q11
Q10
Q8
8.0 mm
UBs
Q9
G
H
A1
CE1s
NC
A18
NC
A17
A5
A7
A4
A6
A0
A3
A2
CEf
GNDf
OEf
NC
12
NC
1
NC
2
NC
11
3
4
5
6
7
8
9
10
10.0 mm
Notes:
1.To maintain compatibility with all JEDEC Variation B options for this ball location C6, this C6 land pad should be
connected directly to the land pad for ball G4 (A17).
Table 1. Pin Description
Symbol
Type
Description and Function
A0-A20
input
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Flash: 32Mbit, A0~A20
SRAM: 4Mbit, A0~A17
Q0-Q15
input/output Data inputs/outputs: Inputs array data on the second CEf and WEf cycle during a pro-
gram command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
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MX28F3204C3T/B
Symbol
Type
Description and Function
CEf
input
Flash Chip Enable : Activates the device's control logic, input buffers, and sense ampli-
fiers. CEf high de-selects the memory device and reduce power consumption to standby
level. CEf is active low.
CE1s
input
input
input
SRAM CHIP ENABLE: Activates the SRAM internal control logic, input buffers, decod-
ers and sense amplifiers. CE1s is active low.CE1s high de-selects the SRAM memory
device and reduces power consumption to standby levels.
CE2s
SRAM CHIP ENABLE: Activates the SRAM internal control logic, input buffers, decod-
ers and sense amplifiers. CE2s is active high. CE2s low de-selects the SRAM memory
device and reduces power consumption to standby levels.
RESET
Flash Reset/Deep Power Down: when RESET=VIL, the device is in reset/deep power
down mode, which drives the outputs to High Z, resets theWSM and minimizes current
level. When RESET=VIH, the device is normal operation. When RESET transitions
from VIL to VIH, the device defaults to the read array mode.
WEf
input
input
Flash Write Enable: to control write to CUI and array sector.WEf=VIL becomes active.
The data and addresses are latched on the rising edge of the second WEf pulse.
SRAM Write Enable: Controls writes to the SRAM memory array.WEs is active low.
WEs
VPP
input/supply Flash Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V±5% for faster program and erase in a production environment.
OEf
input
input
Flash Output Enable: gates the device's outputs during a real cycle.
SRAM Output Enable: Enables SRAM's outputs through the data buffers during a read
operation. OEs is active low.
OEs
WP
input
FlashWrite Protect:WhenWP isVIL, the sectors marked Lock Down can't be unlocked
through software. When WP is VIH, the lock down mechanism is disable and sectors
previously locked down are now locked and can be unlocked and locked through soft-
ware. AfterWP goes low, any sectors previously marked lock down revert to that state.
Flash power supply: (2.7V~3.6V).
VCCf
supply
input
VCCQ
Flash I/O Power Supply: supplies for input/output buffers. (Refer to DC characteristics
table)
VCCs
GND
UBs
supply
supply
input
SRAM power supply: (2.7C~3.6V)
Ground voltage: For all internal circuitry, all GND pins shall be connected.
SRAM Upper Byte Enable: Enables the upper bytes for SRAM (Q8-Q15).
UBs is active low. UBs and LBs must be tied together to restrict x16 mode.
SRAM Lower Byte Enable: Enables the lower bytes for SRAM (Q0-Q7).
LBs is active low. UBs and LBs must be tied together to restrict x16 mode.
No connection.
LBs
NC
input
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MX28F3204C3T/B
BLOCK DIAGRAM for MX28F3204C3T/B
GND VCCQ
VCCf VPP
A0~A20
A0~A20
CEf
OEf
2MWx16bit (32M)
Flash Memory
Q0 to Q15
WEf
RESET
WP
Q0 to Q15
Vccs
GND
A0~A17
CE1s
CE2s
OEs
WEs
UBs
4M bit
Static RAM
Q0 to Q15
LBs
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MX28F3204C3T/B
DEVICE BUS OPERATIONS for MX28F3204C3T/B
Notes CEf OEf WEf CE1s CE2s OEs WEs LBs
(1) (1) (1)
UBs
X
Q0~
Q7
Q8~ RESET
Q15
Full Standby
3,4
H
X
H
L
X
H
H
H
H
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
High Z High Z
H
H
H
H
H
H
H
L
X
H
X
H
X
H
X
H
X
H
X
H
X
H
X
L
X
L
Flash Output Disable 3,4
Array
L
L
L
L
L
L
X
X
High Z High Z
X
L
X
Dout
Dout
ID(2)
Dout
Din
Dout
Dout
ID(2)
Dout
Din
Read Query
from
L
X
L
X
Flash Configuration
L
X
L
X
Status
L
X
L
X
Register
Write to Flash
Reset
5,7
H
X
X
L
X
3,4,6
X
X
L
X
High Z High Z
High Z High Z
SRAM Output
Disable
3,4
H
H
X
X
X
X
L
L
H
H
H
X
L
H
X
H
X
H
L
X
H
L
H
Read from SRAM
Dout
High Z
Dout
Din
Dout
Dout
High Z
Din
H
H
H
H
H
H
H
L
L
H
L
Write to SRAM
Legend:
H
X
X
L
H
H
L
L
H
L
L
X
Din
H
Din
X
L=VIL, H=VIH, X at control pins=VIL or VIH. See "ELECTRIAL CHARACTERISTICS 1.DC Characteristics" for volt-
age levels.
Notes:
1. Do not apply CEf=VIL, CE1s=VIL and CE2s=VIH at a time.
2. ID=Device Identifier Code. See "Table 3.Configuration Code"
3. Outputs are dependent on a seperate device controlling bus output.
4. Modes of the flash and SRAM can be interleaved so that while one is disabled the other controls outputs.
5. To program or erase the lockable sectors hold WP at VIH.
6. RESET at GND ± 0.2V to ensure the lowest power consumption.
7. Refer to Table 2 for valid Din during a write operation.
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MX28F3204C3T/B
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operation Conditions" may
affect device reliability.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
OperatingTemperature
During Read, Sector Erase, Word
Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC
Voltage on Any Ball (except VCCf, VCCs, VCCQ and
VPP) with respect to GND . . . . . . . . .-0.5 V to +3.7V(1)
VPP SupplyVoltage (for Sector Erase and Word Write)
1. Minimum DC voltage is -0.5V on input/output pins.
During transitions, this level may undershoot to -2.0V
for periods <20ns. Maximum DC voltage on input/out-
put balls toVCCf/VCCs/VCCQ+0.5V which during tran-
sition; may overshoot toVCCf/VCCs/VCCQ+2.0V for
periods <20ns.
2. Maximum DC voltage on VPP may overshoot to
+14.0V for periods <20ns.
3. Output shorted for no more than one second.No more
than one output shorted at a time.
4. VPP voltage is normally 1.65V~3.6V. Connection to
supply of 11.4V~12.6V can only be done for 1000
cycles on the main sectors and 2500 cycles on the
parameter sectors during program/erase. VPP may
be connected to 12V for a total of 80 hours maximum.
with respect to GND . . . . . . . . . .-0.5V to +13.5V(1,2,4)
VCCf, VCCs andVCCQ SupplyVoltage
with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +3.6V(1)
Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3)
WARNING:Stressing the device beyond the "Absolute
Operating Conditions (Temperature andVCC Operating Conditions)
Symbol
TA
Parameter
Min.
-40
Max.
+85
3.6
Unit
oC
V
Notes
OperatingTemperature
FlashVCC SupplyVoltage
SRAM VCC SupplyVoltage
Flash I/O Supply Voltage
Flash I/O Supply Voltage
Flash I/O Supply Voltage
SupplyVoltage
VCCf
2.7
1
VCCs
VCCQ1
VCCQ2
VCCQ3
VPP1
VPP2
Cycling
2.7
3.6
V
2.7
3.6
V
1
1.65
1.8
2.5
V
1
2.5
V
1
1.65
11.4
100,000
3.6
V
1
SupplyVoltage
12.6
V
1,2
2
Sector Erase Cycling
NOTE:
1.VCCf and VCCQ must share the same supply when they are in the VCCf range.
2.Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors.VPP may be connected to 12V for a total of 80 hours maximum.
Capacitance (1) (TA=+25oC, f=1MHz)
Symbol
CIN
Parameter
Typ.
16
Max.
18
Unit
pF
Test Condition
VIN=0.0V
Input Capacitance
Output Capacitance
COUT
20
22
pF
VOUT=0.0V
NOTE:
1.Sampled, not 100% tested.
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MX28F3204C3T/B
FLASH SECTOR STRUCTURE (TOP)
Sector
Sector Size
4KWord
Address Range (h)
1FF000-1FFFFF
1FE000-1FEFFF
1FD000-1FDFFF
1FC000-1FCFFF
1FB000-1FBFFF
1FA000-1FAFFF
1F9000-1F9FFF
1F8000-1F8FFF
1F0000-1F7FFF
1E8000-1EFFFF
1E0000-1E7FFF
1D8000-1DFFFF
1D0000-1D7FFF
1C8000-1CFFFF
1C0000-1C7FFF
1B8000-1BFFFF
1B0000-1B7FFF
1A8000-1AFFFF
1A0000-1A7FFF
198000-19FFFF
190000-197FFF
188000-18FFFF
180000-187FFF
178000-17FFFF
170000-177FFF
168000-16FFFF
160000-167FFF
158000-15FFFF
150000-157FFF
148000-14FFFF
140000-147FFF
138000-13FFFF
130000-137FFF
128000-12FFFF
120000-127FFF
118000-11FFFF
110000-117FFF
108000-10FFFF
100000-107FFF
Boot Sector 0
Boot Sector 1
4KWord
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
4KWord
4KWord
4KWord
4KWord
4KWord
4KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
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MX28F3204C3T/B
Sector
Sector Size
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
Address Range (h)
0F8000-0FFFFF
0F0000-0F7FFF
0E8000-0EFFFF
0E0000-0E7FFF
0D8000-0DFFFF
0D0000-0D7FFF
0C8000-0CFFFF
0C0000-0C7FFF
0B8000-0BFFFF
0B0000-0B7FFF
0A8000-0AFFFF
0A0000-0A7FFF
098000-09FFFF
090000-097FFF
088000-08FFFF
080000-087FFF
078000-07FFFF
070000-077FFF
068000-06FFFF
060000-067FFF
058000-05FFFF
050000-057FFF
048000-04FFFF
040000-047FFF
038000-03FFFF
030000-037FFF
028000-02FFFF
020000-027FFF
018000-01FFFF
010000-017FFF
008000-00FFFF
000000-007FFF
Main Sector 31
Main Sector 32
Main Sector 33
Main Sector 34
Main Sector 35
Main Sector 36
Main Sector 37
Main Sector 38
Main Sector 39
Main Sector 40
Main Sector 41
Main Sector 42
Main Sector 43
Main Sector 44
Main Sector 45
Main Sector 46
Main Sector 47
Main Sector 48
Main Sector 49
Main Sector 50
Main Sector 51
Main Sector 52
Main Sector 53
Main Sector 54
Main Sector 55
Main Sector 56
Main Sector 57
Main Sector 58
Main Sector 59
Main Sector 60
Main Sector 61
Main Sector 62
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MX28F3204C3T/B
FLASH SECTOR STRUCTURE (BOTTOM)
Sector
Sector Size
Address Range (h)
00000-00FFF
01000-01FFF
02000-02FFF
03000-03FFF
04000-04FFF
05000-05FFF
06000-06FFF
07000-07FFF
08000-0FFFF
10000-17FFF
18000-1FFFF
20000-27FFF
28000-2FFFF
30000-37FFF
38000-3FFFF
40000-47FFF
48000-4FFFF
50000-57FFF
58000-5FFFF
60000-67FFF
68000-6FFFF
70000-77FFF
78000-7FFFF
80000-87FFF
88000-8FFFF
90000-97FFF
98000-9FFFF
A0000-A7FFF
A8000-AFFFF
B0000-B7FFF
B8000-BFFFF
C0000-C7FFF
C8000-CFFFF
D0000-D7FFF
D8000-DFFFF
E0000-E7FFF
E8000-EFFFF
F0000-F7FFF
F8000-FFFFF
Boot Sector 0
4KWord
4KWord
Boot Sector 1
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
4KWord
4KWord
4KWord
4KWord
4KWord
4KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
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Sector
Sector Size
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
Address Range (h)
100000-107FFF
108000-10FFFF
110000-117FFF
118000-11FFFF
120000-127FFF
128000-12FFFF
130000-137FFF
138000-13FFFF
140000-147FFF
148000-14FFFF
150000-157FFF
158000-15FFFF
160000-167FFF
168000-16FFFF
170000-177FFF
178000-17FFFF
180000-187FFF
188000-18FFFF
190000-197FFF
198000-19FFFF
1A0000-1A7FFF
1A8000-1AFFFF
1B0000-1B7FFF
1B8000-1BFFFF
1C0000-1C7FFF
1C8000-1CFFFF
1D0000-1D7FFF
1D8000-1DFFFF
1E0000-1E7FFF
1E8000-1EFFFF
1F0000-1F7FFF
1F8000-1FFFFF
Main Sector 31
Main Sector 32
Main Sector 33
Main Sector 34
Main Sector 35
Main Sector 36
Main Sector 37
Main Sector 38
Main Sector 39
Main Sector 40
Main Sector 41
Main Sector 42
Main Sector 43
Main Sector 44
Main Sector 45
Main Sector 46
Main Sector 47
Main Sector 48
Main Sector 49
Main Sector 50
Main Sector 51
Main Sector 52
Main Sector 53
Main Sector 54
Main Sector 55
Main Sector 56
Main Sector 57
Main Sector 58
Main Sector 59
Main Sector 60
Main Sector 61
Main Sector 62
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FLASH
2.0 BUS OPERATION
The local CPU reads and writes flash memory in-sys-
tem. All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
1.0 PRINCIPLES OF OPERATION
The product includes an on-chip WSM to manage sec-
tor erase, word write and lock-bit configuration functions.
2.1 Read
After initial device power-up or return from reset mode
(see section on Bus Operations), the device defaults to
read array mode. Manipulation of external memory con-
trol pins allow array read, standby and output disable
operations.
Information can be read from any sector, configuration
codes or status register independent of the VPP volt-
age. RESET can be at VIH.
The first task is to write the appropriate read mode com-
mand (Read Array, Read Configuration, Read Query or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from reset, the device automati-
cally resets to read array mode. In order to read data,
control pins set for CEf, OEf, WEf, RESET andWP must
be driven to active. CEf and OEf must be active to ob-
tain data at the outputs. CEf is the device selection con-
trol. OEf is the data output (Q0-Q15) control and active
drives the selected memory data onto the I/O bus, WEf
must be VIH, RESET must be VIH, WP must be at VIL
orVIH.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. All
functions associated with altering memory contents -
sector erase, word write, sector lock/unlock, status and
identifier codes - are accessed via the CUI and verified
through the status register.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the sector erase, word write and
sector lock/unlock.The internal algorithms are regulated
by theWSM, including pulse repetition, internal verifica-
tion and margining of data. Addresses and data are in-
ternally latched during write cycles. Address is latched
at falling edge of CEf and data latched at rising edge of
WEf.Writing the appropriate command outputs array data,
accesses the identifier codes or outputs status register
data.
2.2 Output Disable
With OEf at a logic-high level (VIH), the device outputs
are disabled. Output pins (Q0-Q15) are placed in a high-
impedance state.
Interface software that initiates and polls progress of
sector erase, word write and sector lock/unlock can be
stored in any sector.This code is copied to and executed
from system RAM during flash memory updates. After
successful completion, reads are again possible via the
Read Array command. Sector erase suspend allows
system software to suspend a sector erase to read/write
data from/to sectors other than that which is suspend.
Word write suspend allows system software to suspend
a word write to read data from any other flash memory
array location.
2.3 Standby
CEf at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. Q0~Q15 outputs are placed in a high-im-
pedance state independent of OEf. If deselected during
sector erase, word write or sector lock/unlock, the de-
vice continues functioning, and consuming active power
until the operation completes.
With the mechanism of sector lock, memory contents
cannot be altered due to noise or unwanted operation.
When RESET=VIH andVCCf<VLKO (lockout voltage),
any data write alteration can be failure. During read op-
eration, if writeVPP voltage is belowVPPLK, then hard-
ware level data protection is achieved. With CUI's two-
step command sequence sector erase, word write or
sector lock/unlock, software level data protection is
achieved also.
2.4 Reset
As RESET=VIL, it initiates the reset mode. The device
enters reset/deep power down mode.However, the data
stored in the memory has to be sustained at least 100ns
in the read mode before the device becomes deselected
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MX28F3204C3T/B
and output high impedance state.
mands require the command and address within the de-
vice or sector within the device (Sector Lock) to be
locked. The Clear Sector Lock-Bits command requires
the command and address within the device.
In read modes, RESET-low deselects the memory,
places output drivers in a high-impedance state and turns
off all internal circuits. RESET must be held low for a
minimum of 100ns.Time tPHQV is required after return
from reset mode until initial memory access outputs are
valid. After this wake-up interval tPHEL or tPHWL, nor-
mal operation is restored.The CUI is reset to read array
mode and status register is set to 80H. Sector lock bit is
set at lock status.
The CUI does not occupy an addressable memory loca-
tion. It is written when WEf and CEf are active (which-
ever goes high first). The address and data needed to
execute a command are latched on the rising edge of
WEf or CEf. Standard microprocessor write timings are
used.
During sector erase, word write or sector lock/unlock
modes, RESET-low will abort the operation.Memory con-
tents being altered are no longer valid; the data may be
partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode.When power is up and the
device reset subsequently, it is necessary to read sta-
tus register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
2.5 Read Configuration Codes
The read configuration codes operation outputs the manu-
facturer code, device code, sector lock configuration
codes, and the protection register. Using the manufac-
turer and device codes, the system CPU can automati-
cally match the device with its proper algorithms. The
sector lock codes identify locked and unlocked sectors.
2.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register. When VCCf=2.7V-
3.6V and VPP within VPP1 or VPP2 range, the CUI ad-
ditionally controls sector erase, word write and sector
lock/unlock.
The Sector Erase command requires appropriate com-
mand data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate com-
mand data and an address within the device.The Word
Write command requires the command and address of
the location to be written. Set Sector lock/unlock com-
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MX28F3204C3T/B
are disable duringVPP<VPPLK.PlacingVPP onVPP1/
2 enables successful sector erase, word write and sec-
tor lock/unlock.
3.0 COMMAND DEFINITIONS
The flash memory has four read modes:read array, read
configuration, read status, read query, and two write
modes: program, erase. These read modes are acces-
sible independent of the VPP voltage. But write modes
Device operations are selected by writing specific com-
mands into the CUI.Table 2 defines these commands.
Table 2. Command Definition (1)
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Operation Address
Data Operation Address Data
Required
(1)
(2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(3)
FFH
90H
(1)
(2)
(3)
Read Array
1
> 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Read Configuration
Read Query
2,4
2,7
3
Read
Read
Read
IA
QA
X
ID
98H
QD
Read Status Register
Clear Status Register
Sector Erase/Confirm
WordWrite
2
70H
SRD
1
3
50H
2
20H
Write
Write
SA
D0H
WD
2
2,5
6
40H/10H
B0H
D0H
60H
WA
Program/Erase Suspend
Program/Erase Resume
Sector Lock
1
1
2
Write
Write
Write
Write
Write
SA
SA
SA
PA
PA
01H
D0H
2FH
PD
Sector Unlock
2
60H
Lock-Down Sector
Protection Program
Lock Protection Register
2
60H
2
C0H
C0H
2
FFFD
Notes:
1. Bus operation are defined at page 6 and referred to ACTimingWaveform.
2. X=Any address within device.
IA=ID-Code Address (refer toTable 3).
ID=Data read from identifier code.
SA=Sector Address within the sector being erased.
WA=Address of memory location to be written.
WD=Data to be written at location WA.
PA=Program Address, PD=Program Data
QA=Query Address, QD=Query Data.
3. Data is latched from the rising edge of WEf or CEf (whichever goes high first)
SRD=Data read from status register, see Table 5 for description of the status register bits.
4. Following the Read Configuration codes command, read operation access manufacturer, device codes, sector
lock/unlock codes, see chapter 4.2.
5. Either 40H or 10H command is recognized by the WSM as word write setup.
6. The sector unlock operation simultaneously clear all sector lock.
7. Read Query Command is read for CFI query information.
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3.1 Read Array Command
3.3 Read Status Register Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode.This op-
eration is also initiated by writing the Read Array com-
mand. The device remains enabled for reads until an-
other command is written. Once the internal WSM has
started a sector erase, word write or sector lock con-
figuration the device will not recognize the Read Array
command until theWSM completes its operation unless
the WSM is suspended via a Sector Erase Suspend or
Word Write Suspend command. If RESET=VIL device
is in read Read Array command mode, this read opera-
tion no longer requires VPP.The Read Array command
functions independently of theVPP voltage and RESET
can be VIH.
CUI writes read status command (70H).The status reg-
ister may be read to determine when a sector erase,
word write or lock-bit configuration is complete and
whether the operation completed successfully. (refer to
table 5) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the sta-
tus register until another valid command is written.The
status register contents are latched on the falling edge
of CEf or OEf, whichever occurs last. CEf or OEf must
toggle to VIH before further reads to update the status
register latch.The Read Status Register command func-
tions independently of the VPP voltage. RESET can be
VIH.
3.2 Read Configuration Codes Command
3.4 Clear Status Register Command
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To re-
turn to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 3 retrieve the manufacturer,
device, sector lock configuration codes and the protec-
tion register(see Table 3 for configuration code values).
To terminate the operation, write another valid command.
Like the Read Array command, the Read Configuration
Codes command functions independently of the VPP
voltage and RESET can beVIH.Following the Read Con-
figuration Codes command, the information is shown:
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (seeTable 5).By allowing sys-
tem software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing sev-
eral words in sequence) may be performed.The status
register may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions indepen-
dently of the applied VPP Voltage. RESET can be VIH.
This command is not functional during sector erase or
word write suspend modes.
Table 3. Configuration Code
Code
Address
(A19-A0)
00000H
Data
(Q15-Q0)
00C2H
88C4/88C5H
LocK
Manufacturer Code
Device Code(Top/Bottom) 00001H
Sector Lock Configuration XX002H
- Sector is unlocked
Q0=0
- Sector is locked
Q0=1
- Sector is locked-down
Q1=1
Protection Register Lock 80
PR-LK
PR
Protection Register
81-88
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MX28F3204C3T/B
should be checked. If word write error is detected, the
status register should be cleared.The internalWSM verify
only detects errors for "1"s that do not successfully write
to "0"s. The CUI remains in read status register mode
until it receives another command.
3.5 Sector Erase Command
Erase is executed one sector at a time and initiated by a
two-cycle command. A sector erase setup is first writ-
ten (20H), followed by a sector erase confirm (D0H).This
command sequence requires appropriate sequencing and
an address within the sector to be erased. Sector pre-
conditioning, erase, and verify are handled internally by
the WSM. After the two-cycle sector erase sequence is
written, the device automatically outputs status register
data when read (see Figure 8).The CPU can detect sec-
tor erase completion by analyzing the output data of the
status register bit SR.7.
Reliable word writes can only occur when
VCCf=2.7V~3.6V andVPP=VPP1/2.IfVPP is not within
acceptable limits, theWSM doesn't execut the program
command.If word write is attempted whileVPP<VPPLK,
status register bits SR.3 and SR.4 will be set to "1".
Successful word write requires for boot sector that WP
is VIH the corresponding sector lock-bit be cleared. In
parameter and main sectors case, it must be cleared
the corresponding sector lock-bit. If word write is at-
tempted when the excepting above sector being clocked
conditions, SR.1 and SR.4 will be set to "1".Word write
is not functional.
When the sector erase is complete, status register bit
SR.5 should be checked. If a sector erase error is de-
tected, the status register should be cleared before sys-
tem software attempts corrective actions. The CUI re-
mains in read status register mode until a new com-
mand is issued.
3.7 Sector Erase Suspend Command
This two-step command sequence of set-up followed by
execution ensures that sector contents are not acciden-
tally erased. An invalid sector Erase command sequence
will result in both status register bits SR.4 and SR.5
being set to "1". Also, reliable sector erasure can only
occur when 2.7V~3.6V andVPP=VPP1/2.In the absence
of this high voltage, sector contents are protected against
erasure.If sector erase is attempted whileVPP<VPPLK
SR.3 and SR.5 will be set to "1". To successfully erase
the boot sector, the corresponding sector lock-bit must
be clear first. In parameter and sectors case, it must be
cleared the corresponding sector lock-bit. If sector erase
is attempted when the excepting above sector being
locked conditions, SR.1 and SR.5 will be set to "1". Sec-
tor erase is not functional.
The Sector Erase Suspend command (50H) allows sec-
tor-erase interruption to read or word write data in an-
other sector of memory.Once the sector erase process
starts, writing the Sector Erase Suspend command re-
quests that theWSM suspend the sector erase sequence
at a predetermined point in the algorithm. The device
outputs status register data when read after the Sector
Erase Suspend command is written.Polling status reg-
ister bits SR.7 and SR.6 can determine when the sector
erase operation has been suspended (both will be set to
"1"). Specification tWHRH2/tEHRH2 defines the sector
erase suspend latency.
When Sector Erase Suspend command is written to the
CUI, if sector erase was finished, the device would be
placed read array mode. Therefore, after Sector Erase
Suspend command is written to the CUI, Read Status
Register command (70H) has to be written to CUI, then
status register bit SR.6 should be checked if/when the
device is in suspend mode.
3.6 Word Write Command
Word write is executed by a two-cycle command se-
quence.Word write setup (standard 40H or alternate 10H)
is written, followed by a second write that specifies the
address and data.TheWSM then takes over, controlling
the word write and write verify algorithms internally. Af-
ter the word write sequence is written, the device auto-
matically outputs status register data when read (see
Figure 6). The CPU can detect the completion of the
word write event by analyzing the status register bit SR.7.
At this point, a Read Array command can be written to
read data from sectors other than that which is sus-
pended.AWordWrite commands sequence can also be
issued during erase suspend to program data in other
sectors. Using the Word Write Suspend command (see
Section 4.9), a word write operation can also be sus-
pended. During a word write operation with sector erase
suspended, status register bit SR.7 will return to "0".
When word write is complete, status register bit SR.4
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However, SR.6 will remain "1" to indicate sector erase
suspend status.
is suspended are Read Status Register Read Configura-
tion, Read Query and Word Write Resume. After Word
Write Resume command is written to the flash memory,
the WSM will continue the Word write process. Status
register bits SR.2 and SR.7 will automatically be cleared.
After the Word Write Resume command is written, the
device automatically outputs status register data when
read (see Figure 7).VPP must remain at VPP1/2 while
in word write suspend mode. RESET must also remain
at VIH (the same RESET level used for word write).
The only other valid commands while sector erase is
suspended are Read Status Register, Read Configura-
tion, Read Query, Program Setup, Program Resume,
Sector Lock, Sector Unlock, Sector Lock-Down and sec-
tor erase Resume. After a Sector Erase Resume com-
mand is written to the flash memory, the WSM will con-
tinue the sector erase process. Status register bits SR.6
and SR.7 will automatically be cleared. After the Erase
Resume command is written, the device automatically
outputs status register data when read (see Figure 9).
VPP must remain at VPP1/2 while sector erase is sus-
pended. RESET must also remain at VIH (the same
RESET level used for sector erase). Sector cannot re-
sume until word write operations initiated during sector
erase suspend has completed.
If the time between writing theWordWrite Resume com-
mand and writing the Word Write Suspend command is
short and both commands are written repeatedly, a longer
time is required than standard word write until the comple-
tion of the operation.
If the time between writing the Sector Erase Resume
command and writing the Sector Erase Suspend com-
mand is shorter than 15ms and both commands are writ-
ten repeatedly, a longer time is required than standard
sector erase until the completion of the operation.
3.8 Word Write Suspend Command
The Word Write Suspend command allows word write
interruption to read data in other flash memory locations.
Once the word write process starts, writing the Word
Write Suspend command requests that the WSM sus-
pend theWord write sequence at a predetermined point
in the algorithm. The device continues to output status
register data when read after the Word Write Suspend
command is written.Polling status register bits SR.7 and
SR.2 can determine when the word write operation has
been suspended (both will be set to "1"). Specification
tWHRH1/tEHRH1 defines the word write suspend latency.
WhenWord Write Suspend command write to the CUI, if
word write was finished, the device places read array
mode. Therefore, after Word Write Suspend command
write to the CUI, Read Status Register command (70H)
has to be written to CUI, then status register bit SR.2
should be checked for if/when the device is in suspend
mode.
At this point, a Read Array command can be written to
read data from locations other than that which is sus-
pended.The only other valid commands while word write
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3.9 Sector Lock/Unlock /Lockdown Command
3.9.1 Sector Locked State
3.9.4 Read Sector Lock Status
The lock status of every sector can be read through
Read Configuration mode.To enter this mode, first com-
mand write 90H to the device.The subsequent reads at
sector address +00002 will output the lock status of this
sector.The lock status can be read from the lowest two
output pins Q0 and Q1. Q0 indicates the sector lock/
unlock status and set by the lock command and cleared
by the unlock command.When entering lock-down, the
lock status is automatically set. Q1 indicates lock-down
status and is set by the lock-down command. It cannot
be further cleared by software, only by device reset or
power-down.
The default status of all sectors upon power-up or reset
is locked. Any attempt on program or erase operations
will result in an error on bit SR.1 of a locked sector.The
status of a locked sector can be changed to unlocked or
lock-down using software commands. An unlocked sec-
tor can be locked by writing the sector lock command
sequence, 60H followed by 01H.
3.9.2 Sector Unlocked State
An unlocked sector can be programmed or erased. All
unlocked sector return to the locked state when the de-
vice is either reset or powered down. The status of an
unlocked sector can be changed to locked or locked-
down using software commands. A locked sector can
be unlocked by writing unlock command sequence, 60H
followed by D0H.
Sector Lock ConfigurationTable
Lock Status
Data
Q0=0
Q0=1
Q1=1
Sector is unlocked
Sector is locked
Sector is locked-down
3.9.3 Sector Locked-Down State
Sectors which are locked-down are protected from pro-
gram and erase operation; however, the protection sta-
tus of these sectors cannot be changed using software
commands alone. Any sector locked or unlocked can be
locked-down by writing the lock-down command se-
quence, 60H followed by 2FH.When the device is reset
or powered down, the locked-down sectors will revert to
the locked state.
The status of WP will determine the function of sector
lock-down and is summarized is followed:
WP
Sector Lock-down Description
WP=0
- sectors are protected from program, erase,
and lock status changes
WP=1
- the sector lock-down function is disabled
- an individual lock-down sector can be un-
locked and relocked via software command.
Once WP goes low, sectors that previously
locked-down returns to lock-down state
regardless of any changes whenWP was
high.
In addition, sector lock-down is cleared only when the
device is reset or powered down.
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MX28F3204C3T/B
sector is being placed in erase suspend, the locking sta-
tus bits will be changed immediately, but when the erase
is resumed, the erase operation will complete.
3.9.5 Sector Locking while Erase Suspend
The sector lock status can be performed during an erase
suspend by using standard locking command sequences
to unlock, lock, or lock-down a sector.
Locking operation cannot be performed during a program
suspend.
In order to change sector locking during an erase opera-
tion, the write erase suspend command (B0H) is placed
first; then check the status register until it is shown that
the actual erase operation has been suspended. Subse-
quent writing the desired lock command sequence to a
sector and the lock status will be changed. When com-
pleting any desired lock, read or program operation, re-
sume the erase operation with the Erase Resume Com-
mand (D0H).
3.9.6 Status Register Error Checking
The operation of locking system for this device can be
used the term "state (X,Y,Z)" to specify locking status,
where X=value ofWP,Y=bit Q1 of the sector lock status
register, and Z=bit Q0 of the sector lock status register.
Q0 indicates if a sector is locked (1) or unlocked (0). Q1
indicates if a sector has been locked-down(1) or not (0).
If a sector is locked or locked-down during the same
Table 4. Sector Locking State Transitions
Current State
Erase/Prog.
Operation if
Lock Command Input Result (Next State)
(X,Y, Z)=
(X,Y, Z)=
WP
0
Q1
0
Q0
0
Name
Unlocked
Enable ?
Yes
No
Lock
(001)
Unlock
Unchanged
(000)
Lock-Down
(011)
0
0
1
Locked (default)
Locked-Down
Unlocked
Unchanged
Unchanged
(101)
(011)
0
1
1
No
Unchanged
Unchanged
(100)
Unchanged
(111)
1
0
0
Yes
No
1
0
1
Locked
Unchanged
(111)
(111)
1
1
0
Lock-Down Disabled
Lock-Down Disabled
Yes
No
Unchanged
(110)
(111)
1
1
1
Unchanged
Unchanged
Note:
At power-up or device reset, all sectors default to locked state (001) (if WP=0).
HoldingWP=0 is the recommended default.
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Table 5. Status Register Definition
WSMS
7
SESS
6
ES
5
PS
4
VPPS
3
PSS
2
SLS
1
R
0
NOTES:
Check WSM bit first to determine word program or sec-
tor Erase completion, before checking Program or Erase
Status bits.
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
When Sector Erase Suspend is issued, WSM halts ex-
ecution and sets bothWSMS and SESS bits to "1".SESS
bit remains set to "1" until an Sector Erase Resume
command is issued.
SR.6 = SECTOR ERASE SUSPEND STATUS (SESS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector Lock-
Bits
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
When this bit is set to "1",WSM has attempted but failed
to program a word.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
TheWSM interrogatesVPP level only after the Program
or Erase command sequences have been entered and
informs the system if VPP has not been switched on.
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK andVPP1 min.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
When program suspend is issued, WSM halts the ex-
ecution and sets both WSMS and PSS bits to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The op-
eration specified is aborted and the device is returned to
read status mode.
SR.1 = SECTOR LOCK STATUS (SLS)
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
SR. 0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
REV. 0.1, NOV. 06, 2002
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MX28F3204C3T/B
read cycles from addresses shown in Table 6 will re-
trieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
4.0 128-Bit Protection Register
The 128 bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are forbidden. The other segment is left empty for cus-
tomer to program. Once the customer segment is pro-
grammed, it can be locked to prevent further reprogram-
ming.
Two-cycle Protection Program Command is used to pro-
gram protection register bits. The 64-bit number is pro-
grammed 16 bits at a time. First, write C0H Protection
Program Setup command.The next write to the device
will latch in address and data and program the specified
location.The allowable address are also shown inTable
6. Refer to Figure 11 for the Protection Register Pro-
gramming Flowchart.
4.1 Protection Register Read & Programming
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program to a previously locked
protection register segment will result in a status regis-
ter error (SR.4=1, SR.1=1).
The protection register is read in the configuration read
mode, which follows the stated Command Bus Defini-
tions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once in this mode,
Table 6. Word-Wide Protection Register Addressing
Word
User
A7
1
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
Lock
Both
0
1
2
3
4
5
6
7
Factory
Factory
Factory
Factory
Customer
Customer
Customer
Customer
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
Table 7. Protection Register Memory Map
4.2 Protection Register Locking
The user-programmable segment of the protection reg-
ister is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the protection program command to program
"FFFD" to PR-LOCK location. After these bits have been
programmed, no further changes can be made to the
value stored in the protection register. Protection Pro-
gram command to a locked section will result in a status
register error (Program Error bit SR.4 and Lock Error bit
SR.1 will be set to 1). Protection register lockout state is
not reversible.
Protection Register Purpose
Bit Address
88H~85H
4 words User Program
Register
84H~81H
4 words Factory Program
Register
80H(Bit0 & Bit1)
Protection Register Lock
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MX28F3204C3T/B
AC Input/Output Test Conditions
VCCQ
VCCQ/2 Output
TEST POINTS
Input VCCQ/2
0.0
Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".
Figure 1.Transient Input/Output ReferenceWaveform
Figure 2. SWITCHINGTEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
Output Load
70
1 TTL gate
100
90
Unit
pF
DEVICE UNDER
TEST
2.7K ohm
3.3V
Output Load Capacitance, CL 30
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0-3.0
1.5
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
Input timing measurement
reference levels
V
Output timing measurement
reference levels
1.5
V
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MX28F3204C3T/B
AC Characteristic -- Read Only Operation (1)
-70
-90
Min.
Sym.
Parameter
Notes
Min.
Max.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read CycleTime
70
90
Address to Output Delay
CEf to Output Delay
OEf to Output Delay
RESET to Output Delay
CEf to Output in Low Z
OEf to Output in Low Z
CEf to Output in High Z
OEf to Output in High Z
Output Hold from Address,
CEf, or OEf Change,
Whichever Occurs First
70
70
90
90
2
2
20
30
150
150
3
3
3
3
3
0
0
0
0
20
20
20
20
0
0
Notes:
1. See ACWaveform:Read Operations at Figure 3.
2. OEf may be delayed up to tELQV-tGLQV after the falling edge of CEf without impact on tELQV.
3. Sampled, but not 100% tested.
4. See test Configuration.
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MX28F3204C3T/B
Figure 3. READ-ONLY OPERATION AC WAVEFORM
Device and
Address Selection
Data
Valid
Standby
VIH
Addresses(A)
Address Stable
VIL
tAVAV
VIH
CEf (E)
VIL
tEHQZ
tGHQZ
VIH
OEf (G)
VIL
VIH
WEf (W)
tGLQV
VIL
tOH
tGLQX
tELQV
tELQX
VOH
DATA
(D/Q)
High Z
High Z
Valid Output
VOL
tAVQV
VIH
tPHQV
RESET (P)
VIL
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MX28F3204C3T/B
AC Characteristic -- Write Operation
-70
Min.
150
0
-90
Min.
150
0
Sym.
tPHWL/tPHEL RESET High Recovery toWEf(CEf) Going Low
tELWL/tWLEL CEf(WEf) Setup toWEf(CEf) Going Low
Parameter
Note
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH/tELEH WEf(CEf) Pulse Width
4
2
2
45
40
50
0
60
50
60
0
tDVWH/tDVEH Data Setup to WEf(CEf) Going High
tAVWH/tAVEH Address Setup to WEf(CEf) Going High
tWHEH/tEHWH CEf(WEf) HoldTime from WEf(CEf) High
tWHDX/tEHDX Data HoldTime from WEf(CEf) High
tWHAX/tEHAX Address HoldTime from WEf(CEf) High
tWHWL/tEHEL WEf(CEf) Pulse Width High
2
2
4
3
3
3
3
3
0
0
0
0
25
200
0
30
200
0
tVPWH/tVPEH VPP Setup to WEf(CEf) Going High
tQVVL
VPP Hold from Valid SRD
tBHWH/tBHEH WP Setup to WEf(CEf)Going High
0
0
tQVBL
tWHGL
WP Hold fromValid SRD
0
0
WEf High to OEf Going Low
30
30
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Refer to Table 4 for valid AIN or DIN.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEf or WEf going low (whichever goes low last) to CEf or WEf going high
(whichever goes high first).Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.Similarly, Write pulse width high (tWPH)
is defined from CEf or WEf going high (whichever goes high first) to CEf or WEf going low (whichever goes low
first). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
5. SeeTest Configuration.
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MX28F3204C3T/B
Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM
A
B
C
D
E
F
VIH
VIL
Address (A)
AIN
AIN
tAVWH
(tAVEH)
tWHAX
(tEHAX)
(Note 1)
VIH
VIL
CEf(WEf)[E(W)]
tELWL
(tWLEL)
tWHEH
(tEHWH)
VIH
VIL
OEf(G)
Disable
tWHWL
(tEHEL)
tWHGL
(Note 1)
VIH
VIL
WEf,(CEf)[W(E)]
Enable
tELEH
(tWLWH)
tDVWH
(tEVEH)
tWHDX
(tEHDX)
VIH
VIL
High Z
Valid
SRD
DATA[D/Q]
RESET[P]
DIN
DIN
DIN
tPHWL
(tPHEL)
VOH
VOL
tQVBL
tQVVL
tBHWH
(tBHEH)
VIH
VIL
WP
tVPWH
(tVPEH)
VPPH2
VPPH1
VPP[V]
VPPLK
VIL
Notes:
1. CEf must be toggled low when reading Status Register Data. WEf must be inactive (high) when reading Status
Register Data.
A.VCCf Power-Up and Standby.
B.Write Program or Erase Setup Command.
C.WriteValid Address and Data (for Program) or Erase Confirm Command.
D.Automated Program or Erase Delay.
E.Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
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MX28F3204C3T/B
Erase and Program Timing (1)
Vpp
Note
2,3
1.65V-3.6V
11.4V-12.6V
Symbol
Parameter
Typ(1)
Max
Typ(1)
Max
Unit
tBWPB
4-KW Parameter Sector
Word ProgramTime
32-KW Main Sector
Word ProgramTime
Word ProgramTime
0.10
0.30
0.03
0.24
8
0.12
s
tBWMB
2,3
2,3
2,3
2,3
3
0.8
12
0.5
1
2.4
200
4
1
185
4.0
5
s
us
s
tWHQV1/
tEHQV1
tWHQV2/
tEHQV2
tWHQV3/
tEHQV3
tWHRH1/
tEHRH1
tWHRH2/
tEHRH2
4-KW Parameter Sector
Erase Time
0.4
0.6
15
32-KW Main Sector
Erase Time
5
s
Program Suspend Latency
15
15
20
20
20
20
us
us
Erase Suspend Latency
3
15
Notes:
1. Typical values measured at TA=+25°C and nominal voltage.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
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MX28F3204C3T/B
Figure 5. RESET WAVEFORM
VIH
VIL
RESET (P)
tPHQV
tPHWL
tPHEL
tPLPH
tPLRH
(A) Reset during Read Mode
tPHQV
Abort
Complete
tPHWL
tPHEL
VIH
RESET (P)
VIL
tPLPH
(B) Reset during Program or Sector Erase, tPLPH < tPLRH
Abort
Deep
Power-
Down
tPHQV
tPHWL
tPHEL
Complete
tPLRH
VIH
VIL
RESET (P)
tPLPH
(C) Reset Program or Sector Erase, tPLPH > tPLRH
AC Characteristic -- Under Reset Operation
Sym.
Parameter
VCCf=2.7V~3.6V
Unit
Notes
Min.
100
Max.
tPLPH RESET Low to Reset during Read
ns
1,3
(If RESET is tied to VCCf, this specification is not applicable)
tPLRH1 RESET Low to Reset during Sector Erase
tPLRH2 RESET Low to Reset during Program
22
12
us
us
1,4
1,4
Notes:
1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RESET is asserted while a sector erase or word program operation is not executing, the reset will complete
within 100ns.
4. Sampled, but not 100% tested.
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MX28F3204C3T/B
DC Characteristics
Sym. Parameter
VCCf
VCCQ
Note
1,2
2.7V-3.6V
2.7V-3.6V
2.7V-2.85V
1.65V-2.5V
2.7V-3.3V
1.8V-2.5V Unit Test Conditions
Typ. Max. Typ. Max.
Typ.
Max.
ILI
Input Load Current
± 1
± 10
15
± 1
± 1 uA VCCf=VCCf Max.
VCCQ=VCCQ Max.
VIN=VCCQ or GND
±10 uA VCCf=VCCf Max.
VCCQ=VCCQ Max.
VIN=VCCQ or GND
250 uA VCCf=VCCf Max.
CEf=RESET=VCCQ
or during Program/
ILO
Output Leakage
Current
1,2
1
0.2
7
0.2 ± 10
0.2
ICCS VCC Standby Current
20
50
150
Erase Suspend
WP=VCCQ or GND
20 uA VCCf=VCCf Max
VCCQ=VCCQ Max
VIN=VCCQ or GND
RESET=GND±0.2V
15 mA VCC=VCC Max
VCCQ=VCCQ Max
OEf=VIH, CEf=VIL
f=5MHz, IOUT=0mA
Inputs=VIL or VIH
ICCD VCC Power-Down
Current
1,2
7
9
15
18
7
8
20
15
7
9
ICCR VCC Read Current
1,2,3
IPPD VPP Deep Power-
Down Current
1
0.2
5
0.2
5
0.2
5
uA RESET=GND±0.2V
VPP < VCCf
IPPR VPP Read Current
1,4
1,4
2
±15
200
55
2
±15
200
55
2
±15 uA VPP < VCCf
200 uA VPP > VCCf
55 mA VPP=VPP1,
50
18
50
18
50
18
ICCW+ VCC+VPP Program
IPPW Current
Program in Progress
8
16
8
22
45
15
15
10
21
16
50
30
45
10
21
30 mA VPP=VPP2(12V)
Program in Progress
45 mA VPP=VPP1
Erase in Progress
1,4
1,4
ICCE+ VCC+VPP Erase
IPPE Current
45
16
45 mA VPP=VPP2(12V)
Erase in Progress
ICCES VCC Program
7
200
150
250 uA CEf=VCCf
Program or Erase
or
or Erase Suspend
ICCWS Current
Suspend in Progress
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MX28F3204C3T/B
VCCf
VCCQ
Note
2.7V-3.6V
2.7V-3.6V
2.7V-2.85V
1.65V-2.5V
2.7V-3.3V
1.8V-2.5V
SYM. Parameter
Unit Test Conditions
Typ. Max. Typ. Max.
Typ.
Max.
0.4
VIL
Input LowVoltage
-0.4 VCC* -0.4
0.22V
0.4
-0.4
V
VIH
VOL
Input HighVoltage
Output LowVoltage
2.0 VCCQ VCCQ VCCQ VCCQ VCCQ V
+0.3V -0.4V +0.3V -0.4V +0.3V
-0.1
0.1
-0.1
0.1
-0.1
0.1
1.0
V
V
V
VCCf=VCCf Min
VCCQ=VCCQ Min
IOL=100uA
VOH
Output HighVoltage
VCCQ
-0.1V
VCCQ
-0.1V
VCCQ
-0.1V
VCCf=VCCf Min
VCCQ=VCCQ Min
IOH=-100uA
VPPLK VPP Lock-Out Voltage
6
1.0
3.6
1.0
CompleteWrite
Protection
VPP1 VPP during Program/
VPP2 Erase Operations
VLKO VCC Prog/Erase
LockVoltage
6
6
1.65
1.5
V
V
V
11.4 12.6
1.5
1.5
1.2
VLKO2 VCCQ Prog/Erase
LockVoltage
1.2
1.2
V
Notes:
1. All currents are in RMS unless otherwise noted.Typical values at nominal VCCf, TA=+25°C.
2. The test conditions VCCf Max, VCCQ Max, VCCf Min, and VCCQ Min refer to the maximum or minimum VCCf or
VCCQ voltage listed at the top of each column.
3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
4. Sampled, but not 100% tested.
5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is
sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and
ICCR.
6. Erase and Program are inhibited whenVPP<VPPLK.
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MX28F3204C3T/B
Figure 6. Automated Word Programming Flowchart
Bus
Command Comments
Start
Operation
Write
Program
Setup
Data=40H
Write 40H
Write
Read
Program
Data=Data to Program
Addr=Location to Program
Status Register DataToggle
CEf or OEf to Update
Status Register Data
Check SR.7
Program Address/Data
Read Status Register
Standby
1=WSM Ready
0=WSM Busy
No
SR.7=1 ?
Repeat for subsequent programming operations.
SR full status check can be done after each program
or after a sequence of program operations.
Write FFH after the last program operation to reset
device to read array mode.
Yes
Full Status
Check if Desired
Program Ccomplete
Bus
Command
Comments
FULL STATUS CHECK PROCEDURE
Operation
Standby
Read Status Register
Data(See Above)
Check SR.3
1=VPP Low Detect
Check SR.4
Standby
Standby
1=VPP Program Error
Check SR.1
1
VPP Range Error
Programming Error
SR.3=
1=Attempted Program to
Locked Sector-Program
Aborted
0
1
1
SR.4=
0
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by theWrite
State Machine.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command, in cases where multiple
bytes are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Attempted Program to
Locked Sector- Aborted
SR.1=
0
Program Successful
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MX28F3204C3T/B
Figure 7. Program Suspend/Resume Flowchart
Start
Bus
Command Comments
Operation
Write
Program
Suspend
Data=B0H
Addr=X
Write B0H
Write 70H
Write
Read
Read Status Data=70H
Addr=X
Status Register DataToggle
Read
Status Register
CEf or OEf to Update
Status Register Data
Addr=X
0
Standby
Stanby
Check SR.7
SR.7=
1=WSM Ready
0=WSM Busy
1
Check SR.2
0
1=Program Suspended
0=Program Completed
SR.2=
Program Completed
1
Write
Read
Read Array Data=FFH
Addr=X
Write FFH
Read array data from
sector other than the one
being programmed.
Data=D0H
Read Array Data
Done Reading
Write
Program
Resume
Addr=X
No
Yes
Write D0H
Write FFH
Program Write Resumed
Read Array Data
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MX28F3204C3T/B
Figure 8. Automated Sector Erase Flowchart
Bus
Command Comments
Start
Operation
Write
Erase Setup Data=20H
Write 20H
Addr=Within Sector to Be
Erased
Write
Erase
Data=D0H
Write D0H and
Sector Address
Confirm
Addr=Within Sector to Be
Erased
Read
Status Register
Suspend
Erase Loop
Read
Status Register DataToggle
CEf or OEf to Update
Status Register Data
Check SR.7
No
Yes
0
SR.7=
Suspend Erase
Standby
1=WSM Ready
0=WSM Busy
1
Repeat for subsequent sector erasures.
Full status check can be done after each sector erase
or after a sequence of sector erasures.
Write FFH after the last write operation to reset device
to read array mode.
Full Status Check if Desired
Sector Erase Complete
FULL STATUS CHECK PROCEDURE
Bus
Command
Comments
Operation
Standby
Read Status Register
Data(See Above)
Check SR.3
1=VPP Low Detect
Check SR.4, 5
Both 1=Command
Sequence Error
Check SR.5
Standby
1
VPP Range Error
SR.3=
0
Standby
Standby
1=Sector Erase Error
Check SR.1
1
SR.4,5=
Command Sequence Error
1=Attempted Erase of
Locked Sector- Erase
Aborted
0
1
SR.5=
Sector Erase Error
SR.1 and SR.3 MUST be cleared, if set during an erase
attempt, before further attempts are allowed by the
Write State Machine.
0
SR.1,3,4,5 are only cleared by the Clear Status Reg-
ister Command, in cases where multiple bytes are
erased before full status is checked.
Attempted Erase of Locked
Sector - Aborted
1
SR.1=
0
If an error is detected, clear the status register before
attempting retry or other error recovery.
Sector Erase Successful
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MX28F3204C3T/B
Figure 9. Erase Suspend/Resume Flowchart
Bus
Command Comments
Start
Operation
Write
Erase
Data=B0H
Addr=X
Write B0H
Write 70H
Suspend
Write
Read
Read Status Data=70H
Addr=X
Status Register DataToggle
Read
Status Register
CEf or OEf to Update
Status Register Data
Addr=X
0
Standby
Stanby
Check SR.7
SR.7=
1=WSM Ready
0=WSM Busy
1
Check SR.6
0
1=Erase Suspended
0=Erase Completed
SR.6=
Erase Completed
Write
Read
Read Array Data=FFH
1
Addr=X
Write FFH
Read array data from
sector other than the one
being erased.
Data=D0H
Read Array Data
Done Reading
Write
Erase
Resume
Addr=X
No
Yes
Write D0H
Write FFH
Erase Write Resumed
Read Array Data
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MX28F3204C3T/B
Figure 10. Locking Operations Flowchart
Bus
Command
Comments
Operation
Write
Start
Config. Setup Data=60H
Addr=X
Write
Lock, unlock Data=01H (Sector Lock)
Write 60H
(Configuration Setup)
or Lockdown
D0H(Sector Unlock)
2FH(Sector Lockdown)
Addr=Within sector to lock
Write
01H, D0H, or 2FH
Write
Read Status Data=70H
(Optional) Register
Read
(Optional)
Stanby
Addr=X
Status Register Register
Addr=X
Check Status Register
80H=no error
Write 70H
(Read Status Register)
Lock Command
Read Status Register
Sequence Error
(Optional)
30H=Lock Command
Sequence Error
Data=90H
1,1
SR.4, SR.5=
Write
Read
(Optional) Configuration Addr=X
0,0
Read
Sector Lock Sector Lock Status Data
Write 90H
(Read Configuration)
(Optional)
Status
Addr=Second addr of
sector
Stanby
Confirm Locking Change
on Q1, Q0 (See Sector
Locking State Table for
valid combinations.)
Read Sector Lock Status
No
Locking Change
Confirmed ?
Yes
Locking Change
Complete
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MX28F3204C3T/B
Figure 11. Protection Register Programming Flowchart
Bus
Command Comments
Start
Operation
Write
Protection
Program
Setup
Data=C0H
Write C0H
(Protection Reg. Program Setup)
Write
Read
Protection
Program
Data=Data to Program
Addr=Location to Program
Status Register DataToggle
CEf or OEf to Update
Status Register Data
Check SR.7
Write Protect. Register
Address/Data
Read Status Register
Standby
1=WSM Ready
No
SR.7=1 ?
Yes
0=WSM Busy
Protection Program operations can only be addressed
within the protection register address space. Addresses
outside the defined space will return an error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program
or after a sequence of program operations.
Write FFH after the last operation to reset device to
read array mode.
Full Status
Check if Desired
Program Ccomplete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Standby
SR.1, SR.3, SR.4
0
0
1
0
1 VPP Low
1 Prot. Reg.
Prog. Error
1 Register
Locked:
1,1
VPP Range Error
SR.3, SR.4=
Standby
Stanby
1
0
Protection Register
programming Error
0,1
SR.1, SR.4=
Aborted
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by theWrite
State Machine.
Attempted Program to
Locked Register Aborted
1,1
SR.1,3,4 are only cleared by the Clear Status Regis-
ter Command, in cases of multiple protection register
program operations before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
SR.1, SR.4=
Program Successful
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MX28F3204C3T/B
5.0 VPP Program and Erase Voltage
MX28F3204C3T/B product provides in-system program-
ming and erase in the 1.65V~3.6V of VPP range. In ad-
dition,VPP pin on 12V provides fast production program-
ming.
5.1 VPP Fast manufacturing Programming
WhenVPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCCf pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications. When VPP is connected to a 12V power
supply, the device draws program and erase current di-
rectly from the VPP pin.
5.2 Protection Under VPP<VPPLK
VPP can off additional hardware write protection. The
VPP programming voltage can be kept low for the abso-
lute hardware protection of all sector in the flash device.
As VPP is below VPPLK, any program or erase opera-
tion will result in a error, prompting the corresponding
status register bit (SR.3) to be set.
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MX28F3204C3T/B
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Program Suspend, Standby mode, and Read ID mode;
however, it is ignored otherwise.
6. QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX28F3204C3T/B is capable of operating in the CFI
mode. This mode allows the host system to determine
the manufacturer of the device such as operating pa-
rameters and configuration.Two commands are required
in CFI mode. Query command of CFI mode is placed
first, then the Reset command exits CFI mode. These
are described inTable 3.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, Program Suspend
or read ID mode. The command is valid only when the
device is in the CFI mode.
Table 8-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Addressh
Datah
0051
0052
0059
0003
0000
0035
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
10
11
12
13
14
15
16
17
18
19
1A
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Table 8-2. CFI Mode: System Interface Data Values
Description
Addressh
Datah
0027
0036
00B4
00C6
0005
0000
000A
0000
0004
0000
0003
0000
VCC supply, minimum (2.7V)
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
VCC supply, maximum (3.6V)
VPP supply, minimum (11.4V)
VPP supply, maximum (12.6V)
Typical timeout for single word write (2N us)
Typical timeout for maximum size buffer write (2N us)
Typical timeout for individual sector erase (2N ms)
Typical timeout for full chip erase (2N ms) (not supported)
Maximum timeout for single word write times (2N X Typ)
Maximum timeout for maximum size buffer write times (2N X Typ)
Maximum timeout for individual sector erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
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MX28F3204C3T/B
Table 8-3. CFI Mode: Device Geometry Data Values
Description
Device size (2n bytes)
Addressh
Datah
0016
0001
0000
0000
0000
0002
27
28
29
2A
2B
2C
Flash device interface code (asynchronous x16)
Maximum number of bytes in write buffer=2n (not supported)
Number of erase sector regions within device (one or more continuous
same-size erase sectors at one sector region)
T B
3E 07
00 00
00 20
01 00
T B
Erase Sector Region 1 information
2D
2E
2F
30
[2E,2D] = number of same-size sectors in region 1-1
[30, 2F] = region erase sector size in multiples of 256-bytes
Erase Sector Region 2 information
31
32
33
34
07 3E
00 00
20 00
00 01
[32,31] = number of same-size sectors in region 2-1
[34,33] = region erase sector size in multiples of 256-bytes
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MX28F3204C3T/B
Table 8-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Addressh
Datah
0050
0052
0049
0031
0030
66
Query-unique ASCII string "PRI"
35
36
37
38
39
3A
3B
3C
3D
Major version number, ASCII
Minor version number, ASCII
OptionalFeature&CommandSupport
bit 0 Chip Erase Supported (1=yes, 0=no)
00
bit 1 Suspend Erase Supported (1=yes, 0=no)
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bit 5 Instant individual sector locking supported (1=yes, 0=no)
bit 6 Protection bits supported (1=yes, 0=no)
bit 7 Page mode read supported (1=yes, 0=no)
bit 8 Synchronous read support (1=yes, 0=no)
bits 9-31 revered for future use; undefined bits are "0"
Supported functions after suspend
00
00
3E
01
bit 0 Program supported after erase suspend (1=yes, 0=no)
bit 1-7 Reserved for other supported options; undefined bits are "0"
Sector Lock Status
3F
40
03
00
Define which bits in the sector status Register section of the Query are
implemented.
bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)
bit 1 sector Lock Status Register Lock-Down bit (bit 1) active; (1=yes, 0=no)
Bits 2-15 reserved for future use. Undefined bits are "0".
VCC Logic Supply Optimum Program/Erase Voltage (highest performance)
bits 7-4 BCD value in volts
41
42
43
33
C0
01
bits 3-0 BCD value in 100mV
VPP Supply Optimum Program/Erase Voltage
bits 7-4 HEX value in volts
bits 3-0 BCD value in 100mV
Number of protection register in JEDEC ID space "00" indicates that
256 protection bytes are available
ProtectionDescription
bit 0-7 = Lock/bytes JEDEC-plane physical low address
bit 8-15 = Lock/bytes JEDEC-plane physical high address
bit 16-23 = "n" such that 2n=factory pre-programmed bytes
bit 24-31 = "n" such that 2n=user programmed bytes
44
45
46
47
80
00
03
03
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MX28F3204C3T/B
2. SRAM--DESCRIPTION
cal CMOS standby current of 1uA and maximum ac-
cess time of 70ns in 3V operation.
The SRAM of mixed multi chip memory is a high perfor-
mance, very low power CMOS Static Random Access
Memory.
Easy memory expansion is provided by an active HIGH
chip enable 2(CE2s) active LOW chip enable (CE1s)
and active LOW output enable (OEs) and three-state
output drivers.
The SRAM of MX28F3204C3T/B is organized as 262,144
words by 16 bits and operates from a very low range of
2.7V to 3.6V supply voltage.
The SRAM of MX28F3204C3T/B has an autmatic power
down feature, reducing the power consumption signifi-
cantly when chip is deselected.
Advanced CMOS technology and circuit techniques pro-
vide both high speed and low power features with a typi-
DC ELECTRICAL CHARACTERISTICS
Parameter Parameter
Name
Test Conditions
MIN. TYP. MAX. Units
(1)
VIL
Guaranteed Input Low
-0.3
-
0.6
V
Voltage (2)
VIH
Guaranteed Input High
Voltage (2)
2.2
-
Vcc+0.3
V
IIL
Input Leakage Current
Vccs=Max, VIN=0V to Vcc
-
-
-
-
±1
±1
uA
uA
IOL
Output Leakage Current Vccs=Max, CE1s=VIH or CE2s=VIL
VI/O=0V to Vcc
or LB=UB=VIH or OEs=VIH,
VI/O=0V to Vcc
VOL
VOH
ICC1
Output LowVoltage
Output HighVoltage
Active supply current
(AC, MOS level)
Vccs=Max, IOL=2mA
-
2.4
-
-
-
0.4
-
V
V
Vccs=Min, IOH=-0.5mA
LBs and UBs<0.2V, CE1s<0.2V
CE2s>(Vccs)-0.2V other
inputs<0.2V or >(Vccs)-0.2V
Output-open (duty 100%)
LBs and UBs=VIL, CE1s=VIL
CE2s=VIH other inputs=VIH or VIL
Output-open (duty 100%)
f=10MHz
f=1MHz
f=10MHz
f=1MHz
50
70
mA
-
-
7
15
70
mA
mA
ICC2
Active supply current
(AC, TTL level)
50
-
-
7
1
15
40
mA
uA
ICC3
ICC4
Standby Power Suppply Vcc=max, CE1s=VIH or CE2s=VIL
Current (AC, CMOS) IDQ=0mA
Standby supply current 1)CE2s=VIL, Other inputs=0 - Vccs
(AC, TTL) 2)CE1s=VIH, CE2s=VIH or VIL, Other
-
-
1.0
mA
inputs=0 - Vccs
3) LBs and UBs=VIH, CE1s=VIH or VIL
CE2s=VIH or VIL, Other inputs=0 Vccs
1.Typical characteristics are at TA=25°C and Vcc=3.0V
2.These are absolute values with respect to device ground and all overshoots due to system or tester notice are
included.
3.Fmax=1/tRC.
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MX28F3204C3T/B
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Test Conditions
MIN.
2.0
TYP. MAX. Units
S-Vcc(PD) Power down supply voltage
VI(S-BC) Byte control input LBs, UBs
VI(CE1s) Chip select input CE1s
VI(CE2s) Chip select input CE2s
V
V
V
2.0
2.0
0.2
30
15
3
V
+70 ~ +85°C
+40 ~ +70°C
+25 ~ +40°C
-
-
-
-
-
-
uA
uA
uA
uA
ICC(PD)
Power Down supply current
VCCs=3.0V
CE2s<0.2V
1
other inputs=0~3V -40 ~ +25°C
0.3
1
(2) TIMING REQUIREMENTS
Limits
Symbol
tsu(PD)
trec(PD)
Parameter
Test Conditions
MIN.
TYP. MAX. Units
Power down set up time
Power down recovery time
0
5
ns
ms
(3) TIMING DIAGRAM
LBs, UBs control mode
S-Vcc
2.7V
2.7V
tsu(PD)
trec(PD)
2.2V
2.2V
LBs
UBs
LBs, UBs > (VCCs)-0.2V
CE1s control mode
VCCs
2.7V
2.7V
tsu(PD)
trec(PD)
2.2V
2.2V
CE1s
CE1s > (VCCs)-0.2V
CE2s control mode
VCCs
2.7V
2.7V
CE2s
0.2V
0.2V
tsu(PD)
trec(PD)
CE2s < 0.2V
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MX28F3204C3T/B
AC TEST LOADS AND WAVEFORMS
AC TEST LOADS AND WAVEFORMS
Input Pulse Levels
Input Rise and Fall Times
Input and OutputTiming
Reference Level
3.0/0V
5ns
DQ
1.5V
CL
Including scope and
jig capacitance
SupplyVoltage
2.7V~3.6V
Output loads:
CL=30pF
CL=5pF (for ten. tdis)
FIGURE 1. Output load
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MX28F3204C3T/B
AC ELECTRICAL CHARACTERISTICS
READ CYCLE
Limits SRAM
Symbol
Parameter
70
85
Units
MIN.
MAX.
MIN.
MAX.
tCR
Read cycle time
70
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
Address access time
70
70
70
70
70
45
30
30
30
30
30
85
85
85
85
85
45
30
30
30
30
30
ta(CE1)
ta(CE2)
ta(LB)
Chip select 1 access time
Chip select 2 access time
Lower Byte control access time
Upper Byte control access time
Output enable access time
ta(UB)
ta(OE)
tdis(CE1)
tdis(CE2)
tdis(LB)
tdis(UB)
tdis(OE)
ten(CE1)
ten(CE2)
ten(LB)
ten(UB)
ten(OE)
tv(A)
Output disable time after CE1s high
Output disable time after CE2s low
Output disable time after LBs high
Output disable time after UBs high
Output disable time after OEs high
Output enable time after CE1s low
Output enable time after CE2s low
Output enable time after LBs low
Output enable time after UBs low
Output enable time after OEs low
Data valid time after address
10
10
10
10
5
10
10
10
10
5
10
10
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MX28F3204C3T/B
READ CYCLE TIMING DIAGRAMS
tCR
A0~A16/A0~A17
ta(A)
tv(A)
ta(LB) or ta(UB)
LBs
UBs
(Note3)
(Note3)
(Note3)
(Note3)
(Note3)
tdis(LB) or tdis(UB)
tdis(CE1)
ta(CE1)
CE1s
(Note3)
(Note3)
(Note3)
ta(CE2)
CE2s
OEs
tdis(CE2)
tdis(OE)
ta(OE)
ten(OE)
WEs="H" level
ten(LB)
ten(UB)
ten(CE1)
ten(CE2)
VALID DATA
Q0~15
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MX28F3204C3T/B
AC ELECTRICAL CHARACTERISTICS
WRITE CYCLE
Limits SRAM
Symbol
Parameter
70
85
Units
MIN.
70
50
0
MAX.
MIN.
85
50
0
MAX.
tCW
Write cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(W)
Write pulse width
tsu(A)
Address setup time
tsu(A-WH)
tsu(LB)
tsu(UB)
tsu(CE1)
tsu(CE2)
tsu(D)
Address setup time with respect to WEs
Lower Byte control setup time
Upper Byte control setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
70
70
70
70
70
35
0
70
70
70
70
70
35
0
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write recovery time
0
0
Output disable time WEs low
Output disable time OEs high
Output enable time WEs high
Output enable time from OEs low
30
30
30
30
5
5
5
5
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MX28F3204C3T/B
WRITE CYCLE (WEs control mode)
tCW
A0~A16/A0~A17
LBs
tsu(LB) or tsu(UB)
UBs
(Note3)
(Note3)
(Note3)
(Note3)
tsu(CE1)
CE1s
(Note3)
tsu(CE2)
CE2s
(Note3)
OEs
WEs
tsu(A-WH)
tw(W)
trec(W)
tsu(A)
tdis(W)
ten(OE)
tdis(OE)
ten(W)
DATA IN
STABLE
Q0~15
tsu(D) th(D)
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MX28F3204C3T/B
WRITE CYCLE (LBs, UBs control mode)
tCW
A0~A16/A0~A17
tsu(LB) or
tsu(UB)
tsu(A)
trec(W)
LBs
UBs
CE1s
(Note3)
(Note3)
(Note3)
(Note3)
CE2s
(Note3)
(Note5)
WEs
(Note4)
tsu(D)
(Note3)
th(D)
DATA IN
STABLE
Q0~15
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during CE1s low, CE2s high overlaps LBs and/or UBs low and WEs low.
Note 5: When the falling edge of WEs is simultaneously or prior to the falling edge of LBs and/or UBs or the falling
edge of CE1s or rising edge of CE2s the outputs are maintained in the high impedance state.
Note 6: Don't apply inverted phase signal externally when I/O pin is in output mode.
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MX28F3204C3T/B
WRITE CYCLE (CE1s control mode)
tCW
A0~A16/A0~A17
LBs
UBs
(Note3)
(Note3)
tsu(A)
tsu(CE1)
trec(W)
CE1s
CE2s
(Note3)
(Note3)
(Note3)
(Note5)
WEs
(Note4)
tsu(D)
(Note3)
th(D)
DATA IN
STABLE
Q0~15
WRITE CYCLE (CE2s control mode)
tCW
A0~A16/A0~A17
LBs
UBs
(Note3)
(Note3)
tsu(A)
tsu(CE1)
trec(W)
CE1s
(Note3)
CE2s
(Note3)
(Note3)
(Note5)
WEs
(Note4)
tsu(D)
(Note3)
th(D)
DATA IN
STABLE
Q0~15
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MX28F3204C3T/B
ORDERING INFORMATION
PLASTICPACKAGE
PART NO.
Access Time
Temperature
Range
(ns)
70
Type
Package Type
FBGA
Ball Pitch
0.8mm
MX28F3204C3TXBI-70
MX28F3204C3BXBI-70
MX28F3204C3TXBI-90
MX28F3204C3BXBI-90
-40~85°C
-40~85°C
-40~85°C
-40~85°C
66 Ball FBGA
66 Ball FBGA
66 Ball FBGA
66 Ball FBGA
70
FBGA
0.8mm
90
FBGA
0.8mm
90
FBGA
0.8mm
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MX28F3204C3T/B
PACKAGE INFORMATION
REV. 0.1, NOV. 06, 2002
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MX28F3204C3T/B
REVISION HISTORY
Revision No. Description
Page
Date
0.1
1. Add Package Information
P52
NOV/06/2002
REV. 0.1, NOV. 06, 2002
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MX28F3204C3T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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VISHAY
SI9137LG
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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