MX29F200BTI-90_技术文档

MX29F200T/B

2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY

FEATURES

• 5.0V±10% for read, erase and write operation

• 131072x16/262144x8 switchable

• Fast access time: 55/70/90/120ns

• Low power consumption

- Superior inadvertent write protection

• Sector protection

- Hardware method to disable any combination of

sectors from program or erase operations

- Sector protect/unprotect for 5V only system or 5V/

12V system

- 40mA maximum active current@5MHz

- 1uA typical standby current

• Command register architecture

- Byte/Word Programming (7us/12us typical)

- Erase (16K-Bytex1, 8K-Bytex2, 32K-Bytex1, and

64K-Byte x3)

• 100,000minimumerase/programcycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

• Auto Erase (chip) and Auto Program

- Automatically erase any combination of sectors or

the whole chip with Erase Suspend capability.

- Automatically program and verify data at specified

address

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- 44-pin SOP

- 48-pin TSOP

• Erase suspend/ Erase Resume

- Suspends an erase operation to read data from, or

programdatatoasectorthatisnotbeingerased,then

resume the erase operation.

• Status Reply

- Data polling & Toggle bit for detection of program

and erase cycle completion.

• Ready/Busy pin(RY/BY)

- Provides a hardware method or detecting program

or erase cycle completion

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

• Hardware RESET pin

- Resets internal state mechine to the read mode

• 20 years data retention

GENERAL DESCRIPTION

TTL level control inputs and fixed power supply levels

duringeraseandprogramming,whilemaintainingmaxi-

mum EPROM compatibility.

The MX29F200T/B is a 2-mega bit, single 5 Volt Flash

memoryorganizedas1Mwordx16or2Mbytex8MXIC's

Flash memories offer the most cost-effective and reli-

able read/write non-volatile random access memory.

The MX29F200T/B is packaged in 44-pin SOP and 48-

pin TSOP. It is designed to be reprogrammed and

erasedin-systemorin-standardEPROMprogrammers.

MXICFlashtechnologyreliablystoresmemorycontents

evenafter100,000eraseandprogramcycles. TheMXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunneloxideprocessingandlowinternalelectricfieldsfor

erase and programming operations produces reliable

cycling. The MX29F200T/B uses a 5.0V ± 10% VCC

supply to perform the High Reliability Erase and auto

Program/Erasealgorithms.

The standard MX29F200T/B offers access time as fast

as55ns, allowingoperationofhigh-speedmicroproces-

sorswithoutwaitstates. Toeliminatebuscontention,the

MX29F200T/Bhasseparatechipenable(CE)andoutput

enable (OE ) controls.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up

protection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F200T/Busesacommandregistertomanagethis

functionality. The command register allows for 100%

P/N:PM0549

REV. 1.3, DEC. 24, 2001

1

MX29F200T/B

PIN CONFIGURATIONS

44 SOP(500mil)

48 TSOP(TYPE I) (12mm x 20mm)

RESET

WE

A8

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE

RESET

NC

RY/BY

NC

A7

A6

A5

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE

GND

CE

A0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

RY/BY

NC

A7

A9

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

A6

A5

A4

A3

A2

A1

A0

CE

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MX29F200T/B

(NORMAL TYPE)

A4

A3

A2

A1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE

RESET

NC

RY/BY

NC

A7

A6

A5

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE

GND

CE

A0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MX29F200T/B

(REVERSE TYPE)

A4

A3

A2

A1

PIN DESCRIPTION

SYMBOL PIN NAME

A0-A16

Q0-Q14

Q15/A-1

CE

Address Input

Data Input/Output

Q15(Wordmode)/LSBaddr.(Bytemode)

Chip Enable Input

OE

Output Enable Input

RESET

WE

Hardware Reset Pin, Active low

Write Enable Input

RY/BY

BYTE

VCC

Read/Busy Output

Word/Byte Selection Input

Power Supply Pin (+5V)

Ground Pin

GND

NC

Pin Not Connected Internally

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

2

MX29F200T/B

SECTOR STRUCTURE

MX29F200T Top Boot Sector Addresses Tables

Sector Size Address Range (in hexadecimal)

(Kbytes/

A16

0

A15

0

A14

X

A13

X

A12

X

Kwords)

64/32

32/16

8/4

(x8)Address Range

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-37FFFh

38000h-39FFFh

3A000h-3BFFFh

3C000h-3FFFFh

(x16) Address Range

00000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1BFFFh

1C000h-1CFFFh

1D000h-1DFFFh

1E000h-1FFFFh

SA0

SA1

SA2

SA3

SA4

SA5

SA6

0

1

X

1

0

X

1

0

X

1

0

1

0

1

8/4

1

X

16/8

MX29F200B Bottom Boot Sector Addresses Tables

Sector Size Address Range (in hexadecimal)

(Kbytes/

A16

0

A15

0

A14

0

A13

0

A12

X

0

Kwords)

16/8

(x8)Address Range

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

(x16) Address Range

00000h-01FFFh

02000h-02FFFh

03000h-03FFFh

04000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1FFFFh

SA0

SA1

SA2

SA3

SA4

SA5

SA6

0

1

8/4

0

1

8/4

0

1

X

32/16

64/32

0

1

X

1

0

X

1

X

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

3

MX29F200T/B

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

WE

MACHINE

(WSM)

LOGIC

STATE

MX29F200T/B

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A16

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

A-1/Q15

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q14

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

4

MX29F200T/B

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX29F200T/B is byte programmable using the

AutomaticProgrammingalgorithm. TheAutomaticPro-

grammingalgorithmdoesnotrequirethesystemtotime

out sequence or verify the data programmed. The

typical chip programming time of the MX29F200T/B at

room temperature is less than 2 seconds.

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

verifiestheerase andcountsthenumberofsequences.

A status bit toggling between consecutive read cycles

provides feedback to the user as to the status of the

programming operation.

AUTOMATIC CHIP ERASE

Register contents serve as inputs to an internal state-

machine which controls the erase and programming

circuitry. During write cycles, the command register

internally latches addresses and data needed for the

programming and erase operations. During a system

write cycle, addresses are latched on the falling edge,

and data are latched on the rising edge of WE .

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typicalerasureatroomtemperatureisaccomplishedin

less than two second. The Automatic Erase algorithm

automaticallyprogramstheentirearraypriortoelectrical

erase. Thetimingandverificationofelectricaleraseare

internally controlled by the device.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality,

reliability, and cost effectiveness. The MX29F200T/B

electrically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by

using the EPROM programming mechanism of hot

electron injection.

AUTOMATIC SECTOR ERASE

The MX29F200T/B is sector(s) erasable using MXIC's

AutoSectorErasealgorithm. Sectorerasemodesallow

sectorsofthearraytobeerasedinoneerasecycle. The

Automatic Sector Erase algorithm automatically pro-

grams the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are inter-

nally controlled by the device.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is complete,

the device stays in read mode. After the state machine

hascompleteditstask,itwillallowthecommandregister

to respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (include 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, verifies the pro-

gram, andcountsthenumberofsequences. Astatusbit

similartoDATApollingandastatusbittogglingbetween

consecutive read cycles, provides feedback to the user

as to the status of the programming operation.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

5

MX29F200T/B

TABLE1. SOFTWARE COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Bus

Cycle Addr Data

Addr Data Addr Data Addr

Data

Addr Data

Reset

1

4

XXXH F0H

RA RD

Read

Read Silicon ID

Word

Byte

555H AAH

AAAH AAH

555H AAH

2AAH 55H 555H 90H ADI

555H 55H AAAH 90H ADI

2AAH 55H 555H 90H (SA)

DDI

Sector Protect

Verify

Word

XX00H

X02H XX01H

Byte

4

AAAH AAH

555H 55H AAAH 90H (SA)

00

X04H 01

Porgram

Word

Byte

Word

Byte

Word

Byte

4

6

1

6

555H AAH

AAAH AAH

555H AAH

AAAH AAH

555H AAH

AAAH AAH

XXXH B0H

XXXH 30H

555H AAH

2AAH 55H 555H A0H PA

555H 55H AAAH A0H PA

PD

Chip Erase

Sector Erase

2AAH 55H 555H 80H 555H AAH

555H 55H AAAH 80H AAAH AAH

2AAH 55H 555H 80H 555H AAH

555H 55H AAAH 80H AAAH AAH

2AAH 55H

555H 55H

2AAH 55H

555H 55H

555H 10H

AAAH 10H

SA

30H

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

2AAH 55H 555H 80H 555H AAH

2AAH 55H

555H 20H

protect/unprotect

NOTE:

1. ADI = Address of Device identifier; A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to Table 3)

DDI = Data of Device identifier : C2H for manufacture code,51H/57H(x8) and 2251H/2257H(x16) for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.

Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).

Write Sequence may be initiated with A11~A16 in either state.

4. For Sector Protection Verify Operation : If read out data is 01H, it means the sector has been protected. If read out data is

00H, it means the sector is still not being protected.

COMMAND DEFINITIONS

command sequences. Note that the Erase Suspend

(B0H) and Erase Resume (30H) commands are valid

only while the Sector Erase operation is in progress.

Either of the two reset command sequences will reset

the device(when applicable).

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing

them in the improper sequence will reset the device to

the read mode. Table 1 defines the valid register

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

6

MX29F200T/B

TABLE 2. MX29F200T/B BUS OPERATION

Pins

CE OE

WE A0

A1

L

A6

X

A9

Q0 ~ Q15

Mode

Read Silicon ID

L

H

L

V_ID(2)

C2H(Byte mode)

Manfacturer Code(1)

Read Silicon ID

Device Code(1)

Read

00C2H(Word mode)

H

L

X

51H/57H(Byte mode)

2251H/2257H(Word mode)

L

H

L

H

X

H

L

A0

X

A1

X

A6

X

A9

X

D_OUT

Standby

X

H

HIGH Z

D_IN(3)

X

Output Disable

Write

X

A0

X

A1

X

A6

L

A9

V_ID(2)

Sector Protect with 12V

system(6)

V_ID(2) L

Chip Unprotect with 12V

system(6)

L

V_ID(2) L

X

H

X

H

X

L

V_ID(2)

H

X

Verify Sector Protect

with 12V system

Sector Protect without 12V

system (6)

L

H

L

Code(5)

H

L

X

Chip Unprotect without 12V

system (6)

L

H

X

H

X

Verify Sector Protect/

Unprotect without 12V

system (7)

H

Code(5)

Reset

X

HIGH Z

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5.Code=00H/0000Hmeansunprotected.

Code=01H/0001H means protected.

A16~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system"

command.

7. The "verify sector protect/unprotect without 12V sysytem" is only following "Sector protect/unprotect without 12V

system" command.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

7

MX29F200T/B

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the com-

mand register contents are altered.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up"command80H. Twomore "unlock"writecycles

are then followed by the chip erase command 10H.

If program-fail or erase-fail happen, the write of F0H will

resetthedevicetoaborttheoperation. Avalidcommand

must then be written to place the device in the desired

state.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic Chip Erase. Upon executing the Automatic

Chip Erase, the device will automatically program and

verify the entire memory for an all-zero data pattern.

When the device is automatically verified to contain an

all-zeropattern,aself-timedchiperaseandverifybegin.

Theeraseandverifyoperationsarecompletedwhenthe

data on Q7 is "1" at which time the device returns to the

Read mode. The system does not require to provide

any control or timing during these operations.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible

while the device resides in the target system. PROM

programmers typically access signature codes by rais-

ing A9 to a high voltage. However, multiplexing high

voltage onto address lines is not generally desired

system design practice.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erasemarginhasbeenachievedforthememoryarray(no

erase-verified command is required).

The MX29F200T/B contains a Silicon-ID-Read opera-

tiontosupplementtraditionalPROMprogrammingmeth-

odology. The operation is initiated by writing the read

silicon ID command sequence into the command regis-

ter. Following the command write, a read cycle with

A1=VIL,A0=VILretrievesthemanufacturercodeofC2H/

00C2H. A read cycle with A1=VIL, A0=VIH returns the

devicecodeof51H/2251HforMX29F200T,57H/2257H

for MX29F200B.

IftheEraseoperationwasunsuccessful, thedataonQ5

is"1"(seeTable4),indicatinganeraseoperationexceed

internal timing limit.

Theautomaticerasebeginsontherisingedgeofthelast

WE pulse in the command sequence and terminates

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins

A0

A1

Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex) Code

Manufacture code

Word

Byte

Word

Byte

VIL VIL

VIH VIL

00H

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00C2H

C2H

Device code

22H

X

2251H

for MX29F200T

Device code

51H

Word

Byte

22H

X

2257H

for MX29F200B

Sector Portection

Verification

57H

X

VIH

X

01H(Protected)

00H(Unprotected)

X

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

8

MX29F200T/B

SECTOR ERASE COMMANDS

ERASE SUSPEND

TheAutomaticSectorErasedoesnotrequirethedevice

to be entirely pre-programmed prior to executing the

AutomaticSet-upSectorErasecommandandAutomatic

SectorErasecommand. UponexecutingtheAutomatic

Sector Erase command, the device will automatically

program and verify the sector(s) memory for an all-zero

data pattern. The system does not require to provide

any control or timing during these operations.

This command is only valid while the state machine is

executing Automatic Sector Erase operation, and

thereforewillonlyberespondedtoperiodduringAutomatic

Sector Erase operation. Writing the Erase Suspend

commandduringtheSectorErasetime-outimmediately

terminates the time-out period and suspends the erase

operation. After this command has been executed, the

commandregisterwillinitiateerasesuspendmode. The

statemachinewillreturntoreadmodeautomaticallyafter

suspendisready. Atthistime,statemachineonlyallows

the command register to respond to the Read Memory

Array, Erase Resume and Program commands.

Whenthesector(s)isautomaticallyverifiedtocontainan

all-zeropattern,aself-timedsectoreraseandverification

begin. Theeraseandverificationoperationsarecomplete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system does

not require to provide any control or timing during these

operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend

program operation is complete, the system can once

again read array data within non-suspended sectors.

WhenusingtheAutomaticSectorErasealgorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase-verified command is required). Sector erase

isasix-buscycleoperation. Therearetwo"unlock"write

cycles. Thesearefollowedbywritingtheset-upcommand

80H. Two more "unlock" write cycles are then followed

by the sector erase command 30H. The sector address

is latched on the falling edge of WE, while the

command(data) is latched on the rising edge of WE.

Sectoraddressesselectedareloadedintointernalregister

on the sixth falling edge of WE. Each successive sector

load cycle started by the falling edge of WE must begin

within 30us from the rising edge of the preceding WE.

Otherwise, the loading period ends and internal auto

sectorerasecyclestarts. (MonitorQ3todetermineifthe

sector erase timer window is still open, see section Q3,

Sector Erase Timer.) Any command other than Sector

Erase (30H) or Erase Suspend (B0H) during the time-

out period resets the derice to read mode.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

9

MX29F200T/B

Table 4. Write Operation Status

Status

Q7

Q6

Q5

Q3

Q2 RY/BY

Note1

Note2

Byte Program in Auto Program Algorithm

Q7

Toggle

0

N/A

1

No

0

Toggle

Auto Erase Algorithm

0

1

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

No

Toggle

N/A Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

Q7

Data Data Data Data

1

0

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

0

1

N/A N/A

Byte Program in Auto Program Algorithm

Q7

N/A

1

No

Toggle

Exceeded

Time Limits Auto Erase Algorithm

0

Toggle

1

Toggle

0

Erase Suspend Program

Q7

N/A N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

10

MX29F200T/B

WRITE OPERATION STATUS DATA

ERASE RESUME

POLLING-Q7

This command will cause the command register to clear

thesuspendstateandreturnbacktoSectorErasemode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

otherconditions.AnotherEraseSuspendcommandcan

be written after the chip has resumed erasing.

The MX29F200T/B also features Data Polling as a

methodtoindicatetothehostsystemthattheAutomatic

Program or Erase algorithms are either in progress or

completed.

While the Automatic Programming algorithm is in

operation, anattempttoreadthedevicewillproducethe

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an

attempt to read the device will produce the true data last

written to Q7. The Data Polling feature is valid after the

risingedgeofthefourth WEpulseofthefourwritepulse

sequences for automatic program.

SET-UP AUTOMATIC PROGRAM

COMMANDS

To initiate Automatic Program mode, A three-cycle

commandsequenceisrequired. Therearetwo"unlock"

writecycles. ThesearefollowedbywritingtheAutomatic

Program command A0H.

While the Automatic Erase algorithm is in operation, Q7

willread"0"untiltheeraseoperationiscompeted. Upon

completion of the erase operation, the data on Q7 will

read"1". TheDataPollingfeatureisvalidaftertherising

edge of the sixth WE pulse of six write pulse sequences

for automatic chip/sector erase.

Once the Automatic Program command is initiated, the

next WE pulse causes a transition to an active

programming operation. Addresses are latched on the

fallingedge,and dataareinternally latchedon therising

edgeoftheWEpulse. TherisingedgeofWEalsobegins

the programming operation. The system does not

require toprovidefurthercontrolsortimings. Thedevice

will automatically provide an adequate internally

generated program pulse and verify margin.

The Data Polling feature is active during Automatic

Program/Erase algorithm or sector erase time-out.(see

section Q3 Sector Erase Timer)

If the program opetation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating the program operation

exceedinternaltiminglimit.Theautomaticprogramming

operation is completed when the data read on Q6 stops

togglingfortwoconsecutivereadcyclesandthedataon

Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read

mode(no program verify command is required).

RY/BY:Ready/Busy

The RY/BY is a dedicated, open-drain output pin that

indicateswhetheranAutomaticErase/Programalgorithm

is in progress or complete. The RY/BY status is valid

aftertherisingedgeofthefinalWEpulseinthecommand

sequence. SinceRY/BYisanopen-drainoutput,several

RY/BYpinscanbetiedtogetherinparallelwithapull-up

resistor to Vcc.

Iftheoutputsislow(Busy), thedeviceisactivelyerasing

or programming. (This includes programming in the

EraseSuspendmode.) Iftheoutputishigh(Ready), the

device is ready to read array data (including during the

Erase Suspend mode), or is in the standby mode.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

11

MX29F200T/B

Q2 toggles when the system reads at addresses within

thosesectorsthathavebeenselectedforerasure. (The

system may use either OE or CE to control the read

cycles.) ButQ2cannotdistinguishwhetherthesectoris

actively erasing or is erase-suspended. Q6, by

comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both

statusbitsarerequiredforsectorsandmodeinformation.

Refer to Table 4 to compare outputs for Q2 and Q6.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE pulse in the

command sequence(prior to the program or erase

operation), and during the sector time-out.

During an Automatic Program or Erase algorithm

operation,successivereadcyclestoanyaddresscause

Q6 to toggle. The system may use either OE or CE to

controlthereadcycles.Whentheoperationiscomplete,

Q6 stops toggling.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determinewhetheratogglebitistoggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completedtheprogramoreraseoperation. Thesystem

can read array data on Q7-Q0 on the following read

cycle.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Q6 toggles

and returns to reading array data. If not all selected

sectors are protected, the Automatic Erase algorithm

erasestheunprotectedsectors,andignorestheselected

sectors that are protected.

The system can use Q6 and Q2 together to determine

whetherasectorisactivelyerasingoriserasesuspended.

Whenthedeviceisactivelyerasing(thatis,theAutomatic

Erase algorithm is in progress), Q6 toggling. When the

device enters the Erase Suspend mode, Q6 stops

toggling. However, the system must also use Q2 to

determinewhichsectorsareerasingorerase-suspended.

Alternatively, the system can use Q7.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system

alsoshould notewhetherthevalueofQ5ishigh(seethe

sectiononQ5). Ifitis,thesystemshouldthendetermine

again whether the toggle bit is toggling, since the toggle

bit may have stopped toggling just as Q5 went high. If

the toggle bit is no longer toggling, the device has

successfuly completed the program or erase operation.

If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

If a program address falls within a protected sector, Q6

togglesforapproximately2usaftertheprogramcommand

sequence is written, then returns to reading array data.

Q6 also toggles during the erase-suspend-program

mode, and stops toggling once the Automatic Program

algorithm is complete.

Theremainingscenarioisthatsysteminitiallydetermines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the

status as described in the previous paragraph.

Alternatively, it may choose to perform other system

tasks. Inthiscase,thesystemmuststartatthebeginning

of the algorithm when it returns to determine the status

of the operation.

Table 4 shows the outputs for Toggle Bit I on Q6.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whetheraparticularsectorisactivelyerasing(thatis,the

Automatic Erase alorithm is in process), or whether that

sector is erase-suspended. Toggle Bit I is valid after the

rising edge of the final WE pulse in the command

sequence.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

12

MX29F200T/B

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

usedtodetermineifthesectorerasetimerwindowisstill

open. If Q3 is high ("1") the internally controlled erase

cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the

command has been accepted, the system software

shouldcheckthestatusofQ3priortoandfollowingeach

subsequent sector erase command. If Q3 were high on

the second status check, the command may not have

been accepted.

Q5

Exceeded Timing Limits

Q5willindicateiftheprogramorerasetimehasexceeded

the specified limits(internal pulse count). Under these

conditionsQ5willproducea"1". Thistime-outcondition

which indicates that the program or erase cycle was not

successfullycompleted. DataPollingandToggleBitare

the only operating functions of the device under this

condition.

If this time-out condition occurs during sector erase

operation, it specifies that a particular sector is bad and

it may not be reused. However, other sectors are still

functional and may be used for the program or erase

operation. The device must be reset to use other

sectors. Write the Reset command sequence to the

device, and then execute program or erase command

sequence. Thisallowsthesystemtocontinuetousethe

other active sectors in the device.

DATA PROTECTION

TheMX29F200T/Bisdesignedtoofferprotectionagainst

accidental erasure or programming caused by spurious

system level signals that may exist during power

transition. During power up the device automatically

resets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memorycontentsonlyoccursaftersuccessfulcompletion

of specific command sequences. The device also

incorporates several features to prevent inadvertent

write cycles resulting from VCC power-up and power-

down transition or system noise.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or

combination of sectors are bad.

If this time-out condition occurs during the byte

programming operation, it specifies that the entire

sectorcontainingthatbyteisbadandthissectormaynot

be reused, (other sectors are still functional and can be

reused).

TEMPORARY SECTOR UNPROTECT

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the

Automatic Algorithm operation. Hence, the system

never reads a valid data on Q7 bit and Q6 never stops

toggling. Once the Device has exceeded timing limits,

the Q5 bit will indicate a "1". Please note that this is not

adevicefailureconditionsincethedevicewasincorrectly

used.

Thisfeatureallowstemporaryunprotectionofpreviously

protectedsectortochangedatain-system. TheTempo-

rary Sector Unprotect mode is activated by setting the

RESET pin to VID(11.5V-12.5V). During this mode,

formerlyprotectedsectorscanbeprogrammedorerased

as un-protected sector. Once VID is remove from the

RESET pin,all the previously protected sectors are

protected again.

WRITE PULSE "GLITCH" PROTECTION

Q3

Noise pulses of less than 5ns(typical) on CE or WE will

not initiate a write cycle.

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

and Toggle Bit are valid after the initial sector erase

command sequence.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE = VIL, CE

= VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

13

MX29F200T/B

in the system by writing the Read Silicon ID command.

PerformingareadoperationwithA1=VIH,itwillproduce

00H at data outputs(Q0-Q7) for an unprotected sector.

It is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected

between its VCC and GND.

SECTOR PROTECTION WITH 12V SYSTEM

SECTOR PROTECTION WITHOUT 12V

SYSTEM

TheMX29F200T/Bfeatureshardwaresectorprotection.

This feature will disable both program and erase

operations for these sectors protected. To activate this

mode, the programming equipment must force VID on

address pin A9 and control pin OE, (suggest VID = 12V)

A6 = VIL and CE = VIL.(see Table 2) Programming of

the protection circuitry begins on the falling edge of the

WE pulse and is terminated on the rising edge. Please

refer to sector protect algorithm and waveform.

The MX29F200T/B also feature a hardware sector

protectionmethodinasystemwithout12Vpowersuppply.

The programming equipment do not need to supply 12

volts to protect sectors. The details are shown in sector

protectalgorithmandwaveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

To verify programming of the protection circuitry, the

programming equipment must force VID on address pin

A9(withCEandOEatVILandWEatVIH. WhenA1=1,

it will produce a logical "1" code at device output Q0 for

a protected sector. Otherwise the device will produce

00H for the unprotected sector. In this mode, the

addresses,except for A1, are in "don't care" state.

Address locations with A1 = VIL are reserved to read

manufacturer and device codes.(Read Silicon ID)

The MX29F200T/B also feature a hardware chip

unprotection method in a system without 12V power

supply. The programming equipment do not need to

supply 12 volts to unprotect all sectors. The details are

shown in chip unprotect algorithm and waveform.

POWER-UP SEQUENCE

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

PerformingareadoperationwithA1=VIH,itwillproduce

a logical "1" at Q0 for the protected sector.

TheMX29F200T/BpowersupintheReadonlymode. In

addition, thememorycontentsmayonlybealteredafter

successful completion of the predefined command

sequences.

CHIP UNPROTECT WITH 12V SYSTEM

The MX29F200T/B also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in

thecode.Itisrecommendedtoprotectallsectorsbefore

activating chip unprotect mode.

To activate this mode, the programming equipment

must force VID on control pin OE and address pin A9.

The CE pins must be set at VIL. Pins A6 must be set to

VIH.(seeTable2) Refertochipunprotect algorithmand

waveform for the chip unprotect algorithm. The

unprotection mechanism begins on the falling edge of

the WE pulse and is terminated on the rising edge .

It is also possible to determine if the chip is unprotected

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

14

MX29F200T/B

Temporary Sector Unprotect Operation

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

15

MX29F200T/B

TEMPORARY SECTOR UNPROTECT

ParameterStd. Description

TestSetup AllSpeedOptions Unit

tVIDR

tRSP

VID Rise and Fall Time (See Note)

RESET Setup Time for Temporary Sector Unprotect

Min

500

4

ns

us

Note:

Not 100% tested

Temporary Sector Unprotect Timing Diagram

12V

RESET

0 or 5V

Program or Erase Command Sequence

tVIDR

CE

WE

tRSP

RY/BY

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

16

MX29F200T/B

ParameterStd Description

TestSetup All Speed Options Unit

tREADY1

RESET PIN Low (During Automatic Algorithms)

MAX

MIN

20

us

to Read or Write (See Note)

tREADY2

RESET PIN Low (NOT During Automatic

Algorithms) to Read or Write (See Note)

RESET Pulse Width (During Automatic Algorithms)

500

ns

tRP1

tRP2

tRH

10

500

0

us

ns

RESET Pulse Width (NOT During Automatic Algorithms) MIN

RESET High Time Before Read(See Note)

RY/BY Recovery Time(to CE, OE go low)

RY/BY Recovery Time(to WE go low)

MIN

tRB1

tRB2

0

50

Note:Not 100% tested

RESET TIMING WAVFORM

RY/BY

tRH

CE, OE

RESET

tRP2

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY

CE, OE

WE

tRB1

tRB2

RESET

tRP1

Reset Timing during Automatic Algorithms

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

17

MX29F200T/B

NOTICE:

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under ABSOLUTE

MAXIMUMRATINGSmaycausepermanentdamageto

the device. This is a stress rating only and functional

operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended period may affect reliability.

RATING

VALUE

AmbientOperatingTemperature -40^oCto85^oC

AmbientTemperaturewithPower -55^oCto125^oC

Applied

StorageTemperature

Applied Input Voltage

AppliedOutputVoltage

VCC to Ground Potential

A9&OE

-65^oCto125^oC

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are

subject to change.

DC/AC Operating Conditions for Read Operation

-55

MX29F200T/B

-70

-90

-12

OperatingTemperature

Commercial

Industrial

0^oCto70^oC

-40^oCto85^oC -40^oCto85^oC -40^oCto85^oC

-40^oCto125^oC -40^oCto125^oC

Automotive

Vcc Power Supply

5V±5%

5V±10%

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL PARAMETER

MIN.

TYP

MAX.

UNIT

pF

CONDITIONS

CIN1

CIN2

COUT

InputCapacitance

8

VIN = 0V

VOUT = 0V

ControlPinCapacitance

OutputCapacitance

12

pF

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

18

MX29F200T/B

READ OPERATION

DC CHARACTERISTICS

Symbol PARAMETER

MIN.

TYP

MAX.

UNIT CONDITIONS

ILI

InputLeakageCurrent

OutputLeakageCurrent

Standby VCC current

1(Note3)

uA

mA

uA

VIN = GND to VCC

VOUT = GND to VCC

CE = VIH

ILO

10

1

ISB1

ISB2

ICC1

ICC2

VIL

1(Note5) 5(Note5)

CE = VCC + 0.3V

IOUT = 0mA, f=5MHz

IOUT = 0mA, f=10MHz

V

OperatingVCCcurrent

40(Note4) mA

50

mA

0.8

V

Input Low Voltage

-0.3(Note1)

2.0

VIH

Input High Voltage

VCC+0.3

0.45

VOL

VOH1

VOH2

OutputLowVoltage

OutputHighVoltage(TTL)

V

IOL = 2.1mA

2.4

V

IOH = -2mA

OutputHighVoltage(CMOS) VCC-0.4

V

IOH = -100uA,VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to ot less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. ILI=10uA for Industrial Grade.

4. ICC1=45mAforIndustrialGrade.

5. ISB2 maximum 20uA for automative grade.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

19

MX29F200T/B

AC CHARACTERISTICS

29F200T/B-55 29F200T/B-70

SYMBOL PARAMETER

MIN. MAX.

UNIT CONDITIONS

tACC

tCE

tOE

tDF

Address to Output Delay

55

20

70

40

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

OE to Output Delay

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

20

0

20

CE=VIL

tOH

CE=OE=VIL

29F200T/B-90 29F200T/B-12

SYMBOL PARAMETER

MIN. MAX.

UNIT CONDITIONS

tACC

tCE

tOE

tDF

Address to Output Delay

90

40

120

50

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

OE to Output Delay

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

30

0

30

CE=VIL

tOH

CE=OE=VIL

NOTE:

TESTCONDITIONS:

1.tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

• Inputpulselevels:0.45V/2.4Vfor70nsmax,0V/3Vfor

55ns

• Input rise and fall times: is equal to or less than 10ns

for 70ns max,5ns for 55ns

• Outputload:1TTLgate+100pF(Includingscopeand

jig) for 70ns max.

:1TTLgate+30pF for 55ns max.

• Reference levels for measuring timing: 0.8V, 2.0V for

70ns max.;1.5V for 55ns

READ TIMING WAVEFORMS

VIH

ADD Valid

A0~16

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOE

VIH

OE

tACC

VIL

tOH

HIGH Z

VOH

VOL

DATA

Q0~7

DATA Valid

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

20

MX29F200T/B

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC/AC Operating Conditions for Programming/Erase Operation

MX29F200T/B

-70

0^oC to 70^oC 0^oC to 70^oC

-55

-90

0^oC to 70^oC

-12

0^oC to 70^oC

OperatingTemperature

Commercial

Industrial

-40^oCto85^oC -40^oCto85^oC -40^oCto85^oC

-40^oCto125^oC -40^oCto125^oC

Automotive

Vcc Power Supply

5V±5%

5V±10%

DC CHARACTERISTICS

SYMBOL

PARAMETER

Operating VCC Current

MIN.

TYP

MAX.

UNIT CONDITIONS

ICC1 (Read)

ICC2

40(Note5) mA

IOUT=0mA, f=5MHz

IOUT=0mA, F=10MHz

In Programming

50

mA

ICC3 (Program)

ICC4 (Erase)

ICCES

In Erase

VCC Erase Suspend Current

2

CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming operation cannot be guranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

5. ICC1(Read)=45mAforIndustrialGrade.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

21

MX29F200T/B

AC CHARACTERISTICS

29F200T/B-55(Note2)

29F200T/B-70

SYMBOL PARAMETER

MIN.

0

MAX.

MIN.

0

MAX.

UNIT

ns

s

tOES

tCWC

tCEP

OE setup time

Command programming cycle

WE programming pulse width

70

45

20

0

70

45

20

0

tCEPH1 WE programming pluse width High

tCEPH2 WE programming pluse width High

tAS

Address setup time

tAH

Address hold time

45

20

0

45

30

0

tDS

Data setup time

tDH

Data hold time

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

Total erase time in auto sector erase

Total programming time in auto verify

Sector address load time

CE Hold Time

0

20

24

8

30

24

8

tAETC

tAETB

tAVT

tBAL

tCH

3(TYP.)

1(TYP.)

3(TYP.)

1(TYP.)

s

7/12(TYP.) 210/360

us

ns

us

ms

100

0

100

0

tCS

CE setup to WE going low

Voltge Transition Time

0

tVLHT

tOESP

tWPP

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

Write pulse width for sector unprotect

4

10

12

10

12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.Under condition of VCC=5V±5%,CL=30pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.

P/N:PM0549

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22

MX29F200T/B

AC CHARACTERISTICS

29F200T/B-90

29F200T/B-120

SYMBOL PARAMETER

MIN.

0

MAX.

MIN.

0

MAX.

UNIT

ns

s

tOES

tCWC

tCEP

OE setup time

Command programming cycle

WE programming pulse width

90

45

20

0

120

50

20

0

tCEPH1 WE programming pluse width High

tCEPH2 WE programming pluse width High

tAS

Address setup time

tAH

Address hold time

45

0

50

0

tDS

Data setup time

tDH

Data hold time

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

Total erase time in auto sector erase

Total programming time in auto verify

Sector address load time

CE Hold Time

0

40

24

8

40

24

8

tAETC

tAETB

tAVT

tBAL

tCH

3(TYP.)

1(TYP.)

3(TYP.)

1(TYP.)

s

7/12(TYP.) 210/360

us

ns

us

ms

100

0

100

0

tCS

CE setup to WE going low

Voltge Transition Time

0

tVLHT

tOESP

tWPP

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

Write pulse width for sector unprotect

4

10

12

10

12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.Under condition of VCC=5V±5%,CL=30pF,VIH/VIL=3.0V/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.

P/N:PM0549

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23

MX29F200T/B

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

1.6K ohm

+5V

CL

1.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance for 70ns max.

CL= 30pF Including jig capacitance for 55ns max.

SWITCHING TEST WAVEFORMS(I) for 29F200T/B-70, 29F200T/B-90, 29F200T/B-12

2.4V

2.0V

0.8V

2.0V

0.8V

TEST POINTS

0.45V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 10ns.

SWITCHING TEST WAVEFORMS(II) for 29F200T/B-55

3.0V

TEST POINTS

1.5V

0V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

24

MX29F200T/B

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

ADDRESS

A0~16

ADD Valid

VIL

tAH

tAS

VIH

VIL

WE

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

CE

OE

tCS

tCH

tDH

VIH

VIL

tDS

VIH

VIL

DATA

Q0-7

DIN

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

25

MX29F200T/B

AUTOMATIC PROGRAMMING TIMING

WAVEFORM

One byte data is programmed. Verify in fast algorithm

and additional programming by external control are not

required because these operations are executed auto-

matically by internal control circuit. Programming

completion can be verified by DATA polling and toggle

bit checking after automatic verification starts. Device

outputs DATA during programming and DATA after

programming on Q7.(Q6 is for toggle bit; see toggle bit,

DATA polling, timing waveform).

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

Vcc 5V

A11~A16

ADD Valid

2AAH

555H

A0~A10

WE

555H

tAS

tCWC

tCEPH1

tAH

tCESC

tAVT

CE

OE

tCEP

tDS tDH

tDF

DATA

Q0~Q2

Command In

Data In

DATA polling

,Q4(Note 1)

DATA

Command In

Q7

Command #A0H

Command #AAH

Command #55H

tOE

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

26

MX29F200T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Byte Ok

Command

YES

.

NO

Q5 = 1

Reset

Auto Program Completed

YES

Auto Program Exceed

Timing Limit

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

27

MX29F200T/B

AUTOMATICCHIPERASETIMINGWAVEFORM

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be

verified by DATA polling and toggle bit checking after

automaticerasestarts. Deviceoutputs0duringerasure

and1aftererasure0nQ7.(Q6isfortogglebit;seetoggle

bit, DATA polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

Vcc 5V

A11~A16

555H

2AAH

555H

2AAH

555H

A0~A10

WE

555H

tAS

tCWC

tAH

tCEPH1

tAETC

CE

OE

tCEP

tDS tDH

Command In

Q0,Q1,

Command In

Q4(Note 1)

DATA polling

Command In

Q7

Command #80H

Command #AAH

Command #55H

Command #10H

Command #AAH

(Q0~Q7)

Command #55H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

28

MX29F200T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

DATA Polling

Command

Q7 = 1

YES

.

NO

Q5 = 1

Auto Chip Erase Completed

YES

Reset

Auto Chip Erase Exceed

Timing Limit

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

29

MX29F200T/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector dataindicatedbyA12toA16areerased. External

erase verification is not required because data are

erased automatically by internal control circuit. Erasure

completion can be verified by DATA polling and toggle

bitcheckingafterautomaticerasestarts. Deviceoutputs

0 during erasure and 1 after erasure on Q7.(Q6 is for

togglebit;seetogglebit,DATApolling,timingwaveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)

Vcc 5V

Sector

Addressn

Sector

Address0

Sector

Address1

A12~A16

A0~A10

555H

tAS

2AAH

tCWC

tAH

WE

CE

tCEPH1

tBAL

tAETB

tCEP

tDS

OE

tDH

Command

In

Command

In

Q0,Q1,

Command

In

Command

In

Command

In

Command

In

Q4(Note 1)

DATA polling

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q7

Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H

(Q0~Q7)

Command #30H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

30

MX29F200T/B

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Toggle Bit Checking

Invalid Command

Q6 Toggled ?

YES

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

NO

Last Sector

to Erase

YES

NO

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

NO

.

Q5 = 1

DATA Polling

Q7 = 1

YES

Reset

Auto Sector Erase Completed

Auto Sector Erase Exceed

Timing Limit

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

31

MX29F200T/B

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Continue Erase

Another

.

NO

Erase Suspend ?

YES

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

32

MX29F200T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

A1

A6

12V

5V

A9

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 1

WE

CE

tOESP

Data

01H

tOE

A16-A12

Sector Address

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

A1

12V

5V

A9

tVLHT

A6

Verify

12V

5V

OE

tVLHT

tWPP 2

WE

tOESP

CE

Data

00H

tOE

A16-A12

Sector Address

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

33

MX29F200T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A16,A15,A14,A13,A12)

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

No

Data=01H?

Yes

PLSCNT=32?

Yes

.

Device Failed

Yes

Protect Another

Sector?

No

Remove VID from A9

Write Reset Command

Sector Protection

Complete

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

34

MX29F200T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Increment

PLSCNT

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

35

MX29F200T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE

tCEP

WE

* See the following Note!

CE

Don't care

(Note 2)

Data

01H

F0H

tOE

A16-A12

Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection

for a system without 12V provided.

Note2: Except F0H

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

36

MX29F200T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE

tCEP

WE

* See the following Note!

CE

Don't care

(Note 2)

Data

F0H

00H

tOE

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection

for a system without 12V provided.

Note2: Except F0H

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

37

MX29F200T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command(Table1)

Set Up Sector Addr

(A16,A15,A14,A13,A12)

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Toggle bit checking

DQ6 not Toggled

No

Yes

Increment PLSCNT

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

No

Data=01H?

Yes

PLSCNT=32?

Yes

Device Failed

.

Yes

Protect Another

Sector?

No

Write Reset Command

Sector Protection

Complete

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

38

MX29F200T/B

SECTOR UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command (Table 1)

Set OE=A9=VIH

CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

No

Toggle bit checking

DQ6 not Toggled

Increment

PLSCNT

Yes

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

39

MX29F200T/B

ID CODE READ TIMING WAVEFORM

VCC

5V

VID

ADD

A9

VIH

VIL

tACC

A1 VIH

VIL

ADD

A2-A8

VIH

A10-A17 ^VIL

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

C2H/00C2H

51H/57H (Byte mode)

2251H/2257H (Word mode)

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

40

MX29F200T/B

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.(3)

UNITS

Sector Erase Time

1

3

8

s

Chip Erase Time

24

Byte Programming Time

Word Programming Time

Chip Programming Time

Erase/Program Cycles

7

210

360

10.5

us

12

3.5

us

sec

Cycles

100,000

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,5V.

3.Maximum values measured at 25°C,4.5V.

LATCHUP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

13.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER

MIN.

UNIT

DataRetentionTime

20

Years

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

41

MX29F200T/B

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

Access Time Operating Current Standby Current

Temperature

Range

PACKAGE

(ns)

55

(mA)

40

MAX.(uA)

MX29F200TMC-55

MX29F200TMC-70

MX29F200TMC-90

MX29F200TMC-12

MX29F200TTC-55

5

0^oC~70^oC

44 Pin SOP

70

90

40

44 Pin SOP

120

55

40

44 Pin SOP

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

44 Pin SOP

MX29F200TTC-70

MX29F200TTC-90

MX29F200TTC-12

70

90

40

5

0^oC~70^oC

120

MX29F200BMC-55

MX29F200BMC-70

MX29F200BMC-90

MX29F200BMC-12

MX29F200BTC-55

55

70

90

40

5

0^oC~70^oC

44 Pin SOP

120

55

44 Pin SOP

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

44 Pin SOP

MX29F200BTC-70

MX29F200BTC-90

MX29F200BTC-12

70

90

40

5

0^oC~70^oC

120

MX29F200TMI-70

MX29F200TMI-90

MX29F200TMI-12

MX29F200TTI-70

70

90

120

70

45

5

-40^oC~85^oC

44 Pin SOP

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

44 Pin SOP

MX29F200TTI-90

MX29F200TTI-12

90

45

5

-40^oC~85^oC

120

MX29F200BMI-70

MX29F200BMI-90

MX29F200BMI-12

MX29F200BTI-70

70

90

45

5

-40^oC~85^oC

44 Pin SOP

120

70

44 Pin SOP

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

MX29F200BTI-90

MX29F200BTI-12

MX29F200TTA-90

MX29F200TTA-12

90

120

90

45

5

-40^oC~85^oC

-40^oC~125^oC

5

20

120

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

42

MX29F200T/B

PACKAGE INFORMATION

48-PIN PLASTIC TSOP

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

43

MX29F200T/B

44-PIN PLASTIC SOP

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

44

MX29F200T/B

REVISION HISTORY

Revision Description

Page

Date

1.0

1.To remove "Advanced Information" datasheet marking and

P1

DEC/20/1999

contain information on products in full production

2.The modification summary of Revision 0.9.9 to Revision 1.0:

2-1.Program/erase cycle times:10K cycles-->100K cycles

2-2.To add data retention 20 years

P1,42

2-3.Industrial grade range from "Read Mode" to "Full Range"

P20,21,22,40

2-4.To remove A9 from "timing waveform for sector protection for P35

system without 12V"

To remove A9 from "timing waveform for chip unprotection for P36

system without 12V"

1.1

1.2

1.3

To modify "Package Information"

AddautomotiveGrade

Correct sector address SA2 from 11XXX to 10XXX

P42,43

JUN/15/2001

P18,19,21,41 NOV/12/2001

P3

DEC/24/2001

P/N:PM0549

REV. 1.3 , DEC. 24, 2001

45

MX29F200T/B

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29F200BTI-90
厂家：	MACRONIX INTERNATIONAL
描述：	2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY 2M- BIT [ 256Kx8 / 128Kx16 ] CMOS FLASH MEMORY
文件：	总46页 (文件大小：720K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29F200BTI-90 [Macronix]

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