MX29LV401BXBI-70 [Macronix]
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY; 4M- BIT [ 512K ×8 / 256K ×16 ]的CMOS单电压3V仅限于Flash存储器
| 型号： | MX29LV401BXBI-70 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY |
| 文件： | 总56页 (文件大小：984K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX29LV401T/B
4M-BIT[512Kx8/256Kx16]CMOSSINGLEVOLTAGE
3VONLYFLASHMEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Singlepowersupplyoperation
• Status Reply
-Datapolling&Togglebitfordetectionofprogramand
eraseoperationcompletion.
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55R/70/90ns
• Ready/Busy pin (RY/BY)
-Providesahardwaremethodofdetectingprogramor
eraseoperationcompletion.
• Lowpowerconsumption
• Sectorprotection
- 20mA maximum active current
- 0.2uA typical standby current
• Commandregisterarchitecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
-Automaticallyeraseanycombinationofsectorswith
Erase Suspend capability.
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
• 100,000minimumerase/programcycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
- Automatically program and verify data at specified
address
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
• Erasesuspend/EraseResume
- 44-pin SOP
- Suspends sector erase operation to read data from,
orprogramdatato,any sectorthatisnotbeingerased,
then resumes the erase.
- 48-pin TSOP
- 48-ball CSP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29LV401T/B is a 4-mega bit Flash memory or-
ganized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV401T/B is packaged in 44-pin
SOP, 48-pinTSOP and 48-ball CSP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV401T/B uses a 2.7V~3.6VVCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The standard MX29LV401T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV401T/B has separate chip enable (CE) and
output enable (OE) controls.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV401T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
1
MX29LV401T/B
PIN CONFIGURATIONS
44 SOP(500 mil)
PIN DESCRIPTION
SYMBOL PIN NAME
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
NC
RY/BY
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0~A17
Q0~Q14
Q15/A-1
CE
Address Input
A9
Data Input/Output
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q15(Word mode)/LSB addr(Byte mode)
Chip Enable Input
WE
Write Enable Input
BYTE
RESET
OE
Word/Byte Selction input
Hardware Reset Pin/Sector Protect Unlock
Output Enable Input
RY/BY
VCC
Ready/Busy Output
Power Supply Pin (2.7V~3.6V)
Ground Pin
GND
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
GND
Q15/A-1
Q7
2
3
4
5
6
Q14
Q6
7
A8
8
Q13
Q5
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q12
Q4
WE
RSEET
NC
VCC
Q11
Q3
MX29LV401T/B
NC
RY/BY
NC
Q10
Q2
A17
A7
Q9
Q1
A6
Q8
A5
Q0
A4
OE
A3
GND
CE
A2
A1
A0
48-Ball CSP (6mm x 8mm, Ball Pitch = 0.8 mm),Top View, Balls Facing Down
A
B
C
D
E
F
G
H
6
5
4
3
2
1
A13
A9
WE
A12
A8
A14
A10
A15
A11
NC
NC
A5
A16
Q7
Q5
Q2
Q0
A0
BYTE
Q14
Q12
Q10
Q8
Q15/A-1 GND
Q13
Vcc
Q11
Q9
Q6
RESET NC
Q4
RY/BY NC
NC
A6
A2
Q3
A7
A3
A17
A4
Q1
A1
CE
OE
GND
P/N:PM0853
REV. 0.0, SEP. 14, 2001
2
MX29LV401T/B
BLOCK STRUCTURE
Table 1: MX29LV401T SECTOR ARCHITECTURE
Sector
Sector Size
Address range
Sector Address
Byte Mode Word Mode Byte Mode (x8)
Word Mode (x16) A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
32Kbytes 16Kwords
00000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-77FFF
78000-79FFF
7A000-7BFFF
7C000-7FFFF
00000-07FFF
08000-0FFFF
10000-17FFF
18000-1FFFF
20000-27FFF
28000-2FFFF
30000-37FFF
38000-3BFFF
3C000-3CFFF
3D000-3DFFF
3E000-3FFFF
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
8Kbytes
8Kbytes
4Kwords
4Kwords
8Kwords
1
1
0
1
SA10 16Kbytes
1
1
X
Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.
Table 2: MX29LV401B SECTOR ARCHITECTURE
Sector
Sector Size
Address range
Sector Address
Byte Mode Word Mode Byte Mode (x8)
Word Mode (x16) A17 A16 A15 A14 A13 A12
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
16Kbytes
8Kbytes
8Kbytes
8Kwords
4Kwords
4Kwords
00000-03FFF
04000-05FFF
06000-07FFF
08000-0FFFF
10000-1FFFF
20000-2FFFF
30000-3FFFF
40000-4FFFF
50000-5FFFF
60000-6FFFF
70000-7FFFF
00000-01FFF
02000-02FFF
03000-03FFF
04000-07FFF
08000-0FFFF
10000-17FFF
18000-1FFFF
20000-27FFF
28000-2FFFF
30000-37FFF
38000-3FFFF
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
0
0
1
X
0
0
1
1
32Kbytes 16Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
64Kbytes 32Kwords
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA10 64Kbytes 32Kwords
Note: Byte mode:address range A17:A-1, word mode:address range A17:A0.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
3
MX29LV401T/B
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
INPUT
PROGRAM/ERASE
STATE
MACHINE
(WSM)
HIGH VOLTAGE
LOGIC
RESET
STATE
REGISTER
MX29LV401T/B
ADDRESS
LATCH
FLASH
ARRAY
ARRAY
SOURCE
HV
A0-A17
AND
COMMAND
DATA
BUFFER
Y-PASS GATE
DECODER
PGM
SENSE
DATA
COMMAND
DATA LATCH
AMPLIFIER
HV
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q15/A-1
P/N:PM0853
REV. 0.0, SEP. 14, 2001
4
MX29LV401T/B
AUTOMATIC ERASE ALGORITHM
AUTOMATIC PROGRAMMING
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the erasing operation.
The MX29LV401T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29LV401T/B is less than 10 sec-
onds.
AUTOMATIC CHIP ERASE
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 25 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness.The MX29LV401T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
AUTOMATIC SECTOR ERASE
The MX29LV401T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
The device provides an unlock bypass mode with faster
programming. Only two write cycles are needed to pro-
gram a word or byte, instead of four. A status bit similar
to DATA polling and a status bit toggling between con-
secutive read cycles, provide feedback to the user as
to the status of the programming operation. Refer to write
operation status, table7, for more information on these
status bits.
AUTOMATIC SELECT
The automatic select mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on Q7~Q0.This mode is
mainly adapted for programming equipment on the de-
vice to be programmed with its programming algorithm.
When programming by high voltage method, automatic
select mode requires VID (11.5V to 12.5V) on address
pin A9 and other address pin A6, A1 as referring toTable
3. In addition, to access the automatic select codes in-
system, the host can issue the automatic select com-
P/N:PM0853
REV. 0.0, SEP. 14, 2001
5
MX29LV401T/B
mand through the command register without requiring
VID, as shown in table4.
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in table3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.
TABLE 3. MX29LV401T/B AUTOSELECT MODE OPERATION
A17 A11 A9 A8 A6 A5 A1 A0
Description
Mode CE
OE WE RESET
|
|
|
A7
X
|
A2
X
Q15~Q0
A12 A10
Read Silicon ID
Manfacturer Code
Read Silicon ID
(Top Boot Block)
Device ID
L
L
H
H
X
X
VID
L
L
L
C2H
Word
Byte
Word
Byte
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
VID
VID
VID
VID
X
X
X
X
L
L
L
L
X
X
X
X
L
L
L
L
H
H
H
H
22B9H
XXB9H
22BAH
(Bottom Boot Block)
XXBAH
XX01H
Sector Protection
Verification
L
L
H
H
SA
X
VID
X
L
X
H
L
(protected)
XX00H
(unprotected)
NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High
P/N:PM0853
REV. 0.0, SEP. 14, 2001
6
MX29LV401T/B
TABLE 4. MX29LV401T/B COMMAND DEFINITIONS
First Bus
Bus Cycle
Second Bus Third Bus
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Cycle
Cycle
Cycle Addr Data Addr
XXXH F0H
RA RD
Data Addr
Data Addr Data Addr
Data Addr Data
Reset
1
Read
1
Read Silicon ID Word
Byte
4
4
4
555H AAH 2AAH 55H 555H 90H ADI
AAAH AAH 555H 55H AAAH 90H ADI
DDI
DDI
Sector Protect
Verify
Word
555H AAH 2AAH 55H 555H 90H (SA) XX00H
x02H XX01H
Byte
4
AAAH AAH 555H 55H AAAH 90H (SA) 00H
x04H 01H
Porgram
Word
Byte
Word
Byte
Word
Byte
4
4
6
6
6
6
1
1
555H AAH 2AAH 55H 555H A0H PA
AAAH AAH 555H 55H AAAH A0H PA
PD
PD
Chip Erase
Sector Erase
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H
XXXH B0H
555H 10H
AAAH 10H
SA
SA
30H
30H
Sector Erase Suspend
Sector Erase Resume
XXXH 30H
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A17=do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, B9H/BAH (x8) and 22B9H/22BAH (x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or
555H to Address A10~A-1 in byte mode.
Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it
means the sector is still not being protected.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
7
MX29LV401T/B
COMMAND DEFINITIONS
sequences. Note that the Erase Suspend (B0H) and
Erase Resume (30H) commands are valid only while the
Sector Erase operation is in progress.
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing them
in the improper sequence will reset the device to the
read mode. Table 4 defines the valid register command
TABLE 5. MX29LV401T/B BUS OPERATION
ADDRESS
OE WE RESET A17 A10 A9 A8 A6 A5 A1 A0
Q8~Q15
DESCRIPTION
Read
CE
L
Q0~Q7
Dout
BYTE
=VIH
BYTE
=VIL
A11
A7
A2
L
H
L
H
H
AIN
Dout Q8~Q14=High Z
Q15=A-1
Write
L
H
AIN
DIN(3)
DIN Q8~Q14=High Z
Q15=A-1
Reset
X
X
X
X
H
X
X
X
H
X
L
VID
H
X
AIN
X
High Z
DIN
High Z
DIN
High Z
High Z
High Z
High Z
Temproary sector unlock
Output Disable
Standby
L
High Z
High Z
High Z
High Z
Vcc±
0.3V
L
Vcc±
0.3V
VID
VID
H
X
Sector Protect
H
H
L
L
L
SA
X
X
X
X
X
X
X
X
X
L
H
L
X
X
X
H
H
H
L
L
L
DIN
DIN
X
X
X
X
X
X
Chip Unprotect
L
Sector Protection Verify
L
H
SA
VID
CODE(5)
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 4 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H/XX00H means unprotected.
Code=01H/XX01H means protected.
6. A17~A12=Sector address for sector protect.
7. The sector protect and chip unprotect functions may also be implemented via programming equipment.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
8
MX29LV401T/B
Refer to the Autoselect Mode and Autoselect Command
Sequence section for more information.
REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE and OE pins toVIL. CE is the power control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode.The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory contect
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device
data outputs.The device remains enabled for read access
until the command register contents are altered.
STANDBY MODE
When using both pins of CE and RESET, the device
enter CMOS Standby with both pins held at Vcc±0.3V.
IF CE and RESET are held at VIH, but not within the
range ofVCC ± 0.3V, the device will still be in the standby
mode, but the standby currect will be larger.During Auto
Algorithm operation,Vcc active current (Icc2) is required
even CE = "H" until the operation is complated.The de-
vice can be read with standard access time (tCE) from
either of these standby modes, before it is ready to read
data.
WRITE COMMANDS/COMMAND
SEQUENCES
To program data to the device or erase sectors of memory
, the sysytem must drive WE and CE to VIL, and OE to
VIH.
OUTPUT DISABLE
With the OE input at a logic high level (VIH), output from
the devices are disabled.This will cause the output pins
to be in a high impedance state.
The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
Bypass mode, only two write cycles are required to
program a byte, instead of four. The "byte Program
Command Sequence" section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
RESET OPERATION
The RESET pin provides a hardware method of resetting
the device to reading array data.When the RESET pin is
driven low for at least a period of tRP, the device
immediately terminates any operation in progress,
tristates all output pins, and ignores all read/write
commands for the duration of the RESET pluse. The
device also resets the internal state machine to reading
array data.The operation that was interrupted should be
reinitated once the device is ready to accept another
command sequence, to ensure data integrity
An erase operation can erase one sector, multiple sectors
, or the entire device.Table indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences.Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data."section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS±0.3V, the device draws
CMOS standby current (ICC4). If RESET is held at VIL
but not within VSS±0.3V, the standby current will be
greater.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal
reqister (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.
The RESET pin may be tied to system reset circuitry. A
system reset would that also reset the Flash memory,
enabling the system to read the boot-up firm-ware from
P/N:PM0853
REV. 0.0, SEP. 14, 2001
9
MX29LV401T/B
the Flash memory.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
If RESET is asserted during a program or erase
operation, the RY/BY pin remains a "0" (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
sysytem can thus monitor RY/BY to determine whether
the reset operation is complete. If RESET is asserted
when a program or erase operation is commpleted within
a time of tREADY (not during Embedded Algorithms).
The system can read data tRH after the RESET pin
returns toVIH.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H
or sector erase command 30H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
Refer to the AC Characteristics tables for RESET
parameters and to Figure 22 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 7), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE or CE pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage(VID). However, multiplexing high voltage
onto address lines is not generally desired system de-
sign practice.
The MX29LV401T/B contains a Silicon-ID-Read opera-
tion to supple traditional PROM programming methodol-
ogy. The operation is initiated by writing the read silicon
ID command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H/00C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of B9H/22B9H for MX29LV401T, BAH/22BAH for
MX29LV401B.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
10
MX29LV401T/B
TABLE 6. EXPANDED SILICON ID CODE
Pins
A0
A1
VIL 00H
VIL
Q15~Q8 Q7 Q6 Q5
Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code Word VIL
Byte VIL
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
0
00C2H
X
C2H
Device code
Word VIH VIL 22H
Byte VIH VIL
Word VIH VIL 22H
22B9H
for MX29LV401T
Device code
X
B9H
22BAH
for MX29LV401B
Sector Protection
Verification
Byte VIH VIL
X
X
X
BAH
X
X
VIH
VIH
01H (Protected)
00H (Unprotected)
READING ARRAY DATA
RESET COMMAND
Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data.The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. After
completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See rase Suspend/Erase
Resume Commands” for more infor-mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the autoselect mode. See the "Reset Command"
section, next.
The reset command may be written between the se-
quence cycles in a program command sequence be-fore
programming begins. This resets the device to reading
array data (also applies to programming in Erase
Suspend mode). Once programming begins,however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the se-
quence cycles in an SILICON ID READ command
sequence. Once in the SILICON ID READ mode, the
reset command must be written to return to reading array
data (also applies to SILICON ID READ during Erase
Suspend).
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
P/N:PM0853
REV. 0.0, SEP. 14, 2001
11
MX29LV401T/B
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the de-
vice to be entirely pre-programmed prior to executing
the Automatic Sector Erase Set-up command and Au-
tomatic Sector Erase command. Upon executing the
Automatic Sector Erase command, the device will auto-
matically program and verify the sector(s) memory for
an all-zero data pattern. The system is not required to
provide any control or timing during these operations.
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two "un-
lock" write cycles. These are followed by writing the set-
up command 80H. Two more "unlock" write cycles are
then followed by the sector erase command 30H. The
sector address is latched on the falling edge of WE or
CE, whichever happens later, while the command(data)
is latched on the rising edge of WE or CE, whichever
happens first. Sector addresses selected are loaded
into internal register on the sixth falling edge of WE or
CE, whichever happens later. Each successive sector
load cycle started by the falling edge of WE or CE,
whichever happens later must begin within 50us from
the rising edge of the preceding WE or CE, whichever
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still open,
see section Q3, Sector EraseTimer.) Any command other
than Sector Erase(30H) or Erase Suspend(B0H) during
the time-out period resets the device to read mode.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and verify
begin. The erase and verify operations are complete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system is not
required to provide any control or timing during these
operations.
When using the Automatic sector Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
Table 7.Write Operation Status
Status
Q7
Q6
Q5
Q3
Q2 RY/BY
(Note1)
(Note2)
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Q7
Toggle
Toggle
0
N/A
1
No
0
Toggle
0
1
0
0
Toggle
0
1
Erase Suspend Read
(Erase Suspended Sector)
No
Toggle
N/A Toggle
In Progress
Erase Suspended Mode
Erase Suspend Read
Data
Q7
Data Data Data Data
1
0
0
(Non-Erase Suspended Sector)
Erase Suspend Program
Toggle
Toggle
0
1
N/A N/A
Byte Program in Auto Program Algorithm
Q7
N/A
1
No
Toggle
Exceeded
Time Limits Auto Erase Algorithm
0
Toggle
Toggle
1
1
Toggle
0
0
Erase Suspend Program
Q7
N/A N/A
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
12
MX29LV401T/B
The device provides Q2, Q3, Q5, Q6, Q7, and RY/BY to
determine the status of a write operation. If the program
operation was unsuccessful, the data on Q5 is "1"(see
Table 7), indicating the program operation exceed inter-
nal timing limit.The automatic programming operation is
completed when the data read on Q6 stops toggling for
two consecutive read cycles and the data on Q7 and Q6
are equivalent to data written to these two bits, at which
time the device returns to the Read mode(no program
verify command is required).
ERASE SUSPEND
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. When the Erase Suspend com-
mand is written during a sector erase operation, the de-
vice requires a maximum of 20us to suspend the erase
operations.However,When the Erase Suspend command
is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends
the erase operation. After this command has been ex-
ecuted, the command register will initiate erase suspend
mode. The state machine will return to read mode auto-
matically after suspend is ready. At this time, state ma-
chine only allows the command register to respond to
the Read Memory Array, Erase Resume and program
commands.
WORD/BYTE PROGRAM COMMAND SEQUENCE
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings.The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 1 shows the address
and data requirements for the byte program command
sequence.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend pro-
gram operation is complete, the system can once again
read array data within non-suspended sectors.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
Q7, Q6, or RY/BY. See "Write Operation Status" for
information on these status bits.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions. Another Erase Suspend command can
be written after the chip has resumed erasing.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming
operat ion.The Byte Program command sequence should
be reinitiated once the device has reset to reading array
data, to ensure data integrity.
AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a
"0" back to a "1". Attempting to do so may halt the
operation and set Q5 to "1" ,” or cause the Data Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still "0". Only erase operations can convert a "0" to a
"1".
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active program-
ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising edge
of the WE or CE, whichever happens first. The rising
edge of WE or CE, whichever happens first, also begins
the programming operation. The system is not required
to provide further controls or timings. The device will
automatically provide an adequate internally generated
program pulse and verify margin.
WRITE OPERSTION STATUS
The device provides several bits to determine the sta-
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/
BY.Table 10 and the following subsections describe the
P/N:PM0853
REV. 0.0, SEP. 14, 2001
13
MX29LV401T/B
functions of these bits. Q7, RY/BY, and DQ6 each offer
a method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
RY/BY:Ready/Busy
The RY/BY is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algorithm
is in progress or complete. The RY/BY status is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence. Since RY/BY
is an open-drain output, several RY/BY pins can be tied
together in parallel with a pull-up resistor to Vcc.
Q7: Data Polling
The Data Polling bit, Q7, indicates to the host sys-tem
whether an Automatic Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend. Data
Polling is valid after the rising edge of the finalWE pulse
in the program or erase command sequence.
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the Erase
Suspend mode.)If the output is high (Ready), the device
is ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
During the Automatic Program algorithm, the device out-
puts on Q7 the complement of the datum programmed
to Q7.This Q7 status also applies to programming dur-
ing Er ase Suspend.When the Automatic Program algo-
rithm is complete, the device outputs the datum pro-
grammed to Q7.The system must provide the program
address to read valid status information on Q7. If a pro-
gram address falls within a protected sector, Data Poll-
ing on Q7 is active for approximately 1 us, then the de-
vice returns to reading array data.
Table 7 shows the outputs for RY/BY during write opera-
tion.
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence(prior to the pro-
gram or erase operation), and during the sector time-
out.
During the Automatic Erase algorithm, Data Polling pro-
duces a "0" on Q7. When the Automatic Erase algo-
rithm is complete, or if the device enters the Erase Sus-
pend mode, Data Polling produces a "1" on Q7. This is
analogous to the complement/true datum out-put de-
scribed for the Automatic Program algorithm: the erase
function changes all the bits in a sector to "1" prior to
this, the device outputs the "complement,” or "0".” The
system must provide an address within any of the sec-
tors selected for erasure to read valid status information
on Q7.
During an Automatic Program or Erase algorithm opera-
tion, successive read cycles to any address cause Q6
to toggle.The system may use either OE or CE to con-
trol the read cycles.When the operation is complete, Q6
stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Q6 toggles and
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data Polling on
Q7 is active for approximately 100 us, then the device
returns to reading array data. If not all selected sectors
are protected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended.When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
When the system detects Q7 has changed from the
complement to true data, it can read valid data at Q7-Q0
on the following read cycles. This is because Q7 may
change asynchr onously with Q0-Q6 while Output En-
able (OE) is asserted low.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
14
MX29LV401T/B
If a program address falls within a protected sector, Q6
toggles for approximately 2 us after the program com-
mand sequence is written, then returns to reading array
data.
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase opera-
tion. If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
Q6 also toggles during the erase-suspend-program mode,
and stops toggling once the Automatic Program algo-
rithm is complete.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the sta-
tus as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In
this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation.
Table 7 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit II is valid
after the rising edge of the final WE or CE, whichever
happens first, in the command sequence.
Q5
ExceededTiming Limits
Q5 will indicate if the program or erase time has ex-
ceeded the specified limits(internal pulse count). Under
these conditions Q5 will produce a "1". This time-out
condition indicates that the program or erase cycle was
not successfully completed. Data Polling andToggle Bit
are the only operating functions of the device under this
condition.
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by com-
parison, indicates whether the device is actively eras-
ing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sectors and mode information. Refer to
Table 7 to compare outputs for Q2 and Q6.
If this time-out condition occurs during sector erase op-
eration, it specifies that a particular sector is bad and it
may not be reused. However, other sectors are still func-
tional and may be used for the program or erase opera-
tion. The device must be reset to use other sectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence. This
allows the system to continue to use the other active
sectors in the device.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read cycle.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or com-
bination of sectors are bad.
If this time-out condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector maynot be re-
used, (other sectors are still functional and can be re-
used).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
The time-out condition will not appear if a user tries to
program a non blank location without erasing. Please
note that this is not a device failure condition since the
device was incorrectly used.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
15
MX29LV401T/B
Q3
POWER SUPPLY DECOUPLING
Sector Erase Timer
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween itsVCC and GND.
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
andToggle Bit are valid after the initial sector erase com-
mand sequence.
POWER-UP SEQUENCE
The MX29LV401T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of the predefined command
sequences.
If Data Polling or theToggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of Q3 prior to and following each sub-
sequent sector erase command. If Q3 were high on the
second status check, the command may not have been
accepted.
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously
protected sector to change data in-system.TheTempo-
rary Sector Unprotect mode is activated by setting the
RESET pin toVID(11.5V-12.5V). During this mode, for-
merly protected sectors can be programmed or erased
as un-protected sector. Once VID is remove from the
RESET pin,all the previously protected sectors are pro-
tected again.
DATA PROTECTION
The MX29LV401T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically re-
sets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences. The device also
incorporates several features to prevent inadvertent write
cycles resulting fromVCC power-up and power-down tran-
sition or system noise.
SECTOR PROTECTION
The MX29LV401T/B features hardware sector protec-
tion. This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
address pin A9 and OE (suggestVID = 12V). Program-
ming of the protection circuitry begins on the falling edge
of the WE pulse and is terminated on the rising edge.
Please refer to sector protect algorithm and waveform.
To verify programming of the protection circuitry, the pro-
gramming equipment must forceVID on address pin A9
( with CE and OE atVIL andWE atVIH). When A1=VIH,
A0=VIL, A6=VIL, it will produce a logical "1" code at
device output Q0 for a protected sector. Otherwise the
device will produce 00H for the unprotected sector. In
this mode, the addresses,except for A1, are don't care.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes.(Read Silicon ID)
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected sector.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
16
MX29LV401T/B
CHIP UNPROTECT
The MX29LV401T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotectiscompletedtoincorporateanychangesinthe
code. It is recommended to protect all sectors before
activating chip unprotect mode.
Toactivatethismode,theprogrammingequipmentmust
forceVIDoncontrolpinOEandaddresspinA9. TheCE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table2) Refertochipunprotect algorithmandwaveform
for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
PerformingareadoperationwithA1=VIH,itwillproduce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
17
MX29LV401T/B
OPERATING RATINGS
ABSOLUTE MAXIMUM RATINGS
StorageTemperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
AmbientTemperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
Ambient Temperature (TA ). . . . . . . . . . -40°C to +85°C
VCC Supply Voltages
VCC for regulated voltage range . . . . . +3.0 V to 3.6 V
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE, and
RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Operating ranges define those limits between which the
functionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns.
2. Minimum DC input voltage on pins A9, OE, and
RESET is -0.5 V. During voltage transitions, A9, OE,
and RESET may overshootVSS to -2.0V for periods
of up to 20 ns. See Figure 6. Maximum DC input volt-
age on pin A9 is +12.5 V which may overshoot to
14.0 V for periods up to 20 ns.
3.No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Rat-ings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
18
MX29LV401T/B
Table 8. CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN1
PARAMETER
MIN.
TYP
MAX.
8
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Control Pin Capacitance
Output Capacitance
CIN2
12
pF
VIN = 0V
COUT
12
pF
VOUT = 0V
READ OPERATION
Table 9. DC CHARACTERISTICS
TA = -40oC TO 85oC, VCC = 2.7V to 3.6V
Symbol PARAMETER
MIN.
TYP
MAX.
UNIT
CONDITIONS
ILI
Input Leakage Current
±1
35
±1
12
4
uA
uA
VIN = VSS to VCC
ILIT
ILO
ICC1
A9 Input Leakage Current
Output Leakage Current
VCC Active Read Currect
VCC=VCC max; A9=12.5V
VOUT = VSS to VCC, VCC=VCC max
uA
7
2
mA
mA
mA
mA
mA
uA
CE=VIL, OE=VIH
(Byte Mode)
@5MHz
@1MHz
@5MHz
@1MHz
7
12
4
CE=VIL, OE=VIH
(Word Mode)
2
ICC2
ICC3
ICC4
VCC Active write Currect
VCC Standby Currect
VCC Standby Currect
During Reset
15
0.2
0.2
30
5
CE=VIL, OE=VIH
CE; RESET=VCC ±0.3V
RESET=VSS ±0.3V
5
uA
ICC5
VIL
Automative sleep mode
Input Low Voltage(Note 1)
Input High Voltage
Voltage for Automative
Select and Temporary
Chip Unprotect
0.2
5
uA
V
VIH=VCC ±0.3V;VIL=VSS ±0.3V
-0.5
0.8
VIH
VID
0.7xVCC
VCC+ 0.3
V
11.5
12.5
0.45
V
V
VCC=3.3V
VOL
Output Low Voltage
Output High Voltage(TTL)
Output High Voltage
(CMOS)
IOL = 4.0mA, VCC= VCC min
IOH = -2mA, VCC=VCC min
IOH = -100uA, VCC min
VOH1
VOH2
0.85xVCC
VCC-0.4
VLKO
Low VCC Lock-out
Voltage
2.3
2.5
V
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3.Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
19
MX29LV401T/B
AC CHARACTERISTICS
TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 10. READ OPERATIONS
29LV401T/B-70 29LV401T/B-90
SYMBOL PARAMETER
MIN.
MAX.
70
MIN.
MAX.
90
UNIT CONDITIONS
tRC
tACC
tCE
Read Cycle Time (Note 1)
Address to Output Delay
CE to Output Delay
ns
70
90
ns
ns
ns
ns
ns
ns
CE=OE=VIL
OE=VIL
70
90
tOE
OE to Output Delay
30
35
CE=VIL
tDF
OE High to Output Float (Note1)
Output Enable Read
0
25
0
30
CE=VIL
tOEH
0
0
Hold Time
Toggle and
Data Polling
10
10
tOH
Address to Output hold
0
0
ns
CE=OE=VIL
NOTE:
TEST CONDITIONS:
1. Not 100% tested.
2. tDF is defined as the time at which the output achieves
the open circuit condition and data is no longer driven.
• Input pulse levels: 0V/3.0V.
• Input rise and fall times is equal to or less than 5ns.
• Outputload:1TTLgate+100pF(Includingscopeand
jig), for MX29LV401T/B-90. 1 TTL gate + 30pF
(Including scope and jig) for MX29LV401T/B-70.
• Reference levels for measuring timing: 1.5V.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
20
MX29LV401T/B
Figure 1. SWITCHING TEST CIRCUITS
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
CL=30pF for MX29LV401T/B-70
Figure 2. SWITCHING TEST WAVEFORMS
3.0V
0V
1.5V
TEST POINTS
1.5V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
21
MX29LV401T/B
Figure 3. READ TIMING WAVEFORMS
tRC
VIH
ADD Valid
Addresses
VIL
tACC
tCE
VIH
CE
VIL
VIH
WE
VIL
tOE
tDF
tOEH
VIH
OE
VIL
tACC
tOH
HIGH Z
HIGH Z
VOH
VOL
Outputs
RESET
DATA Valid
VIH
VIL
P/N:PM0853
REV. 0.0, SEP. 14, 2001
22
MX29LV401T/B
AC CHARACTERISTICS
TA = -40oC to 85oC, VCC = 2.7V~3.6V
Table 11. Erase/Program Operations
29LV401T/B-70
29LV401T/B-90
SYMBOL PARAMETER
MIN.
70
0
MAX.
MIN.
90
0
MAX.
UNIT
ns
tWC
tAS
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
ns
tAH
45
35
0
45
45
0
ns
tDS
ns
tDH
Data Hold Time
ns
tOES
tGHWL
Output Enable Setup Time
Read Recovery Time Before Write
(OE High to WE Low)
CE Setup Time
0
0
ns
0
0
ns
tCS
0
0
ns
ns
ns
ns
us
tCH
CE Hold Time
0
0
tWP
tWPH
Write Pulse Width
35
30
35
30
Write Pulse Width High
tWHWH1 ProgrammingOperation(Note2)
(Byte/Wordprogramtime)
9/11(TYP.)
9/11(TYP.)
tWHWH2 Sector Erase Operation (Note 2)
0.7(TYP.)
0.7(TYP.)
sec
us
tVCS
tRB
VCC Setup Time (Note 1)
50
0
50
0
Recovery Time from RY/BY
Program/Erase Vaild to RY/BY Delay
ns
tBUSY
90
90
us
NOTES:
1. Not 100% tested.
2.See the "Erase and Programming Performance" section for more information.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
23
MX29LV401T/B
AC CHARACTERISTICS
TA = -40oC to 85oC,VCC = 2.7V~3.6V
Table 12. Alternate CE Controlled Erase/Program Operations
29LV401T/B-70
29LV401T/B-90
SYMBOL PARAMETER
MIN.
MAX.
MIN.
MAX. UNIT
tWC
tAS
Write CycleTime (Note 1)
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
sec
Address SetupTime
Address HoldTime
Data SetupTime
0
0
tAH
45
45
tDS
35
45
tDH
Data HoldTime
0
0
tOES
tGHEL
tWS
tWH
tCP
Output Enable SetupTime
Read RecoveryTime BeforeWrite
WE Setup Time
0
0
0
0
0
0
WE HoldTime
0
0
CE Pulse Width
35
35
tCPH
CE Pulse Width High
30
30
tWHWH1 Programming
Operation(note2)
Byte
9(Typ.)
11(Typ.)
0.7(Typ.)
9(Typ.)
11(Typ.)
0.7(Typ.)
Word
tWHWH2 Sector Erase Operation (note2)
NOTE:
1. Not 100% tested.
2.See the "Erase and Programming Performance" section for more information.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
24
MX29LV401T/B
Figure 4. COMMAND WRITE TIMING WAVEFORM
VCC
3V
VIH
Addresses
ADD Valid
VIL
tAH
tAS
VIH
VIL
WE
tOES
tWPH
tWP
tCWC
VIH
VIL
CE
OE
tCS
tCH
tDH
VIH
VIL
tDS
VIH
VIL
Data
DIN
P/N:PM0853
REV. 0.0, SEP. 14, 2001
25
MX29LV401T/B
AUTOMATIC PROGRAMMING TIMING
WAVEFORM
after automatic programming starts. Device outputs
DATA during programming and DATA after programming
on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,
timing waveform)
One byte data is programmed. Verify in fast algorithm
and additional verification by external control are not re-
quired because these operations are executed automati-
cally by internal control circuit. Programming comple-
tion can be verified by DATA polling and toggle bit checking
Figure 5. AUTOMATIC PROGRAMMING TIMING WAVEFORM
Program Command Sequence(last two cycle)
Read Status Data (last two cycle)
tWC
tAS
PA
PA
555h
PA
Address
tAH
CE
tCH
tGHWL
OE
tWHWH1
tWP
WE
tCS
tWPH
tDS tDH
Status
A0h
PD
DOUT
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address
P/N:PM0853
REV. 0.0, SEP. 14, 2001
26
MX29LV401T/B
Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data Poll
Increment
Address
from system
No
No
Verify Word Ok ?
YES
Last Address ?
YES
Auto Program Completed
P/N:PM0853
REV. 0.0, SEP. 14, 2001
27
MX29LV401T/B
Figure 7. CE CONTROLLED PROGRAMTIMINGWAVEFORM
PA for program
555 for program
2AA for erase
SA for sector erase
555 for chip erase
Data Polling
Address
PA
tWC
tWH
tAS
tAH
WE
OE
tGHEL
tCP
tWHWH1 or 2
CE
tWS
tDS
tCPH
tBUSY
tDH
DOUT
DQ7
Data
PD for program
30 for sector erase
10 for chip erase
A0 for program
55 for erase
tRH
RESET
RY/BY
NOTES:
1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.
2.Figure indicates the last two bus cycles of the command sequence.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
28
MX29LV401T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is verified automatically by
internal control circuit. Erasure completion can be veri-
fied by DATA polling and toggle bit checking after auto-
matic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)
Figure 8. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
VA
tWC
tAS
VA
2AAh
555h
Address
tAH
CE
tCH
tGHWL
OE
tWHWH2
tWP
WE
tCS
tWPH
tDS tDH
In
Progress
55h
10h
Complete
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0853
REV. 0.0, SEP. 14, 2001
29
MX29LV401T/B
Figure 9. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data Pall from System
NO
Data=FFh ?
YES
Auto Chip Erase Completed
P/N:PM0853
REV. 0.0, SEP. 14, 2001
30
MX29LV401T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector indicated by A12 to A17 are erased. External
erase verify is not required because data are verified
automatically by internal control circuit. Erasure comple-
tion can be verified by DATA polling and toggle bit check-
ing after automatic erase starts. Device outputs 0 dur-
ing erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
Figure 10. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Erase Command Sequence(last two cycle)
Read Status Data
tWC
tAS
VA
VA
2AAh
SA
Address
tAH
CE
tCH
tGHWL
OE
tWHWH2
tWP
WE
tCS
tWPH
tDS tDH
In
Progress
55h
30h
Complete
Data
tBUSY
tRB
RY/BY
tVCS
VCC
NOTES:
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").
P/N:PM0853
REV. 0.0, SEP. 14, 2001
31
MX29LV401T/B
Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase
YES
Data Poll from System
NO
Data=FFh
YES
Auto Sector Erase Completed
P/N:PM0853
REV. 0.0, SEP. 14, 2001
32
MX29LV401T/B
Figure 12. ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
NO
Erase Suspend ?
YES
P/N:PM0853
REV. 0.0, SEP. 14, 2001
33
MX29LV401T/B
Figure 13. IN-SYSTEM SECTOR PROTECT/UNPROTECT TIMING WAVEFORM (RESET Control)
VID
VIH
RESET
SA, A6
A1, A0
Valid*
Valid*
Valid*
Sector Protect or Sector Unprotect
Verify
40h
Status
Data
60h
60h
Sector Protect =150us
Sector Unprotect =15ms
1us
CE
WE
OE
Note: When sector protect, A6=0, A1=1, A0=0. When sector unprotect, A6=1, A1=1, A0=0.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
34
MX29LV401T/B
Figure 14. SECTOR PROTECT TIMING WAVEFORM(A9, OE Control)
A1
A6
12V
3V
A9
tVLHT
tVLHT
Verify
12V
3V
OE
tVLHT
tWPP 1
WE
CE
tOESP
Data
01H
F0H
tOE
Sector Address
A18-A12
P/N:PM0853
REV. 0.0, SEP. 14, 2001
35
MX29LV401T/B
Figure 15. SECTOR PROTECTION ALGORITHM (A9, OE Control)
START
Set Up Sector Addr
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 150us
Set WE=VIH, CE=OE=VIL
A9 should remain VID
.
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
Remove VID from A9
Write Reset Command
Sector Protection
Complete
P/N:PM0853
REV. 0.0, SEP. 14, 2001
36
MX29LV401T/B
Figure 16. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET=VID
START
PLSCNT=1
RESET=VID
Wait 1us
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60H
Yes
Set up sector address
Write 60H to sector address
with A6=0, A1=1, A0=0
Wait 150us
Verify sector protect :
write 40H with A6=0,
A1=1, A0=0
Increment PLSCNT
Reset PLSCNT=1
Read from sector address
No
No
PLSCNT=25?
Data=01H ?
Yes
Yes
Device failed
Yes
Protect another
sector?
No
Remove VID from RESET
Write reset command
Sector protect complete
P/N:PM0853
REV. 0.0, SEP. 14, 2001
37
MX29LV401T/B
Figure 17. IN-SYSTEM SECTOR UNPROTECTION ALGORITHM WITH RESET=VID
START
PLSCNT=1
RESET=VID
Wait 1us
No
No
Temporary Sector
Unprotect Mode
First Write
Cycle=60H ?
Yes
All sector
Protect all sectors
protected?
Yes
Set up first sector address
Sector unprotect :
write 60H with
A6=1, A1=1, A0=0
Wait 50ms
Verify sector unprotect
write 40H to sector address
with A6=1, A1=1, A0=0
Increment PLSCNT
Read from sector address
with A6=1, A1=1, A0=0
No
No
Set up next sector address
PLSCNT=1000?
Data=00H ?
Yes
Yes
Device failed
Yes
Last sector
verified?
No
Remove VID from RESET
Write reset command
Sector unprotect complete
P/N:PM0853
REV. 0.0, SEP. 14, 2001
38
MX29LV401T/B
Figure 18. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE Control)
A1
12V
3V
A9
A6
tVLHT
Verify
12V
3V
OE
tVLHT
tVLHT
tWPP 2
WE
CE
tOESP
Data
00H
F0H
tOE
A17-A12
Sector Address
Notes: tWPP1 (Write pulse width for sector protect)=100ns min.
tWPP2 (Write pulse width for sector unprotect)=100ns min.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
39
MX29LV401T/B
Figure 19. CHIP UNPROTECTION ALGORITHM (A9, OE Control)
START
Protect All Sectors
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 50ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
PLSCNT=1000?
Increment
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
40
MX29LV401T/B
WRITE OPERATION STATUS
Figure 20. DATA POLLING ALGORITHM
Start
Read Q7~Q0
Add.=VA(1)
Yes
Q7 = Data ?
No
No
Q5 = 1 ?
Yes
Read Q7~Q0
Add.=VA
Yes
Q7 = Data ?
(2)
No
FAIL
Pass
NOTE : 1.VA=Valid address for programming
2.Q7 should be re-checked even Q5="1" because Q7 may change
simultaneously with Q5.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
41
MX29LV401T/B
Figure 21. TOGGLE BIT ALOGRITHM
Start
Read Q7-Q0
Read Q7-Q0
(Note 1)
NO
Toggle Bit Q6 =
Toggle ?
YES
NO
Q5= 1?
YES
Read Q7~Q0 Twice
(Note 1,2)
NO
Toggle bit Q6=
Toggle?
YES
Program/Erase Operation
Not Complete,Write
Reset Command
Program/Erase
operation Complete
Note:1.Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".
P/N:PM0853
REV. 0.0, SEP. 14, 2001
42
MX29LV401T/B
Figure 22. DATA POLLING TIMINGS (DURING AUTOMATIC ALOGRITHMS)
tRC
VA
VA
VA
Address
CE
tACC
tCE
tCH
tOE
OE
tOEH
tDF
WE
tOH
High Z
High Z
Complement
Status Data
Complement
Status Data
True
True
Valid Data
Valid Data
DQ7
Q0-Q6
tBUSY
RY/BY
NOTES:
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
43
MX29LV401T/B
Figure 23. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS)
tRC
VA
VA
VA
VA
Address
CE
tACC
tCE
tCH
tOE
OE
tDF
tOEH
WE
tOH
High Z
Valid Status
(second read)
Valid Status
(first raed)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
tBUSY
RY/BY
NOTES:
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
44
MX29LV401T/B
Table 13. AC CHARACTERISTICS
Parameter Std Description
Test Setup All Speed Options Unit
tREADY1
RESET PIN Low (During Automatic Algorithms)
MAX
20
us
to Read or Write (See Note)
tREADY2
RESET PIN Low (NOT During Automatic
Algorithms) to Read orWrite (See Note)
RESET Pulse Width (During Automatic Algorithms)
RESET HighTime Before Read(See Note)
RY/BY Recovery Time(to CE, OE go low)
MAX
500
ns
tRP
tRH
tRB
MIN
MIN
MIN
500
50
0
ns
ns
ns
Note:Not 100% tested
Figure 24. RESET TIMING WAVFORM
RY/BY
CE, OE
tRH
RESET
tRP
tReady2
Reset Timing NOT during Automatic Algorithms
tReady1
RY/BY
tRB
CE, OE
RESET
tRP
Reset Timing during Automatic Algorithms
P/N:PM0853
REV. 0.0, SEP. 14, 2001
45
MX29LV401T/B
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE)
Parameter
Description
Speed Options
Unit
JEDEC Std
-70
-90
tELFL/tELFH CE to BYTE Switching Low or High
Max
Max
Min
5
ns
ns
ns
tFLQZ
tFHQV
BYTE Switching Low to Output HIGH Z
BYTE Switching High to Output Active
25
70
30
90
Figure 25. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from byte
mode to word mode)
CE
OE
tELFH
BYTE
DOUT
(Q0-Q7)
DOUT
(Q0-Q14)
Q0~Q14
Q15/A-1
DOUT
(Q15)
VA
tFHQV
P/N:PM0853
REV. 0.0, SEP. 14, 2001
46
MX29LV401T/B
Figure 26. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from word
mode to byte mode)
CE
OE
tELFH
BYTE
DOUT
(Q0-Q14)
DOUT
(Q0-Q7)
Q0~Q14
Q15/A-1
DOUT
(Q15)
VA
tFLQZ
Figure 27. BYTE TIMING WAVEFORM FOR PROGRAM OPERATIONS
CE
The falling edge of the last WE signal
WE
BYTE
tAS
tAH
P/N:PM0853
REV. 0.0, SEP. 14, 2001
47
MX29LV401T/B
Table 14. TEMPORARY SECTOR UNPROTECT
Parameter Std. Description
Test Setup AllSpeed Options Unit
tVIDR
tRSP
VID Rise and Fall Time (See Note)
Min
Min
500
4
ns
us
RESET SetupTime forTemporary Sector Unprotect
Note:
Not 100% tested
Figure 28. TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM
12V
RESET
0 or Vcc
0 or Vcc
Program or Erase Command Sequence
tVIDR
tVIDR
CE
WE
tRSP
RY/BY
Figure 29. Q6 vs Q2 for Erase and Erase Suspend Operations
Enter Embedded
Erasing
Erase
Enter Erase
Erase
Suspend
Suspend Program
Resume
Erase
Erase
Erase Suspend
Read
Erase
Erase
WE
Q6
Suspend
Program
Complete
Q2
NOTES:
The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
P/N:PM0853
REV. 0.0, SEP. 14, 2001
48
MX29LV401T/B
Figure 30.TEMPORARY SECTOR UNPROTECT ALGORITHM
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Note : 1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
49
MX29LV401T/B
Figure 31. ID CODE READ TIMING WAVEFORM
VCC
3V
VID
ADD
A9
VIH
VIL
VIH
VIL
ADD
A0
tACC
tACC
VIH
VIL
A1
ADD
A2-A8
VIH
A10-A17 VIL
CE
VIH
VIL
VIH
VIL
tCE
WE
OE
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q15
DATA OUT
DATA OUT
B9H/BAH (Byte)
C2H/00C2H
22B9H/22BAH (Word)
P/N:PM0853
REV. 0.0, SEP. 14, 2001
50
MX29LV401T/B
Table 15. ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
TYP.(2)
PARAMETER
MIN.
MAX.(3)
UNITS
Sector Erase Time
0.7
11
9
15
sec
sec
Chip Erase Time
Byte Programming Time
Word Programming Time
Chip Programming Time
300
360
13.5
9
us
11
4.5
3
us
Byte Mode
Word Mode
sec
sec
Erase/Program Cycles
100,000
Cycles
Note: 1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C, 3V.
3.Maximum values measured at 25°C, 2.7V.
Table 16. LATCHUP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
12.5V
Vcc + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
P/N:PM0853
REV. 0.0, SEP. 14, 2001
51
MX29LV401T/B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESSTIME
OPERATING CURRENT STANDBY CURRENT PACKAGE
(ns)
70
MAX.(mA)
MAX.(uA)
MX29LV401TMC-70
MX29LV401BMC-70
MX29LV401TMC-90
MX29LV401BMC-90
MX29LV401TTC-70
30
30
30
30
30
5
5
5
5
5
44 Pin SOP
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
44 Pin SOP
44 Pin SOP
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
70
90
90
70
MX29LV401BTC-70
MX29LV401TTC-90
MX29LV401BTC-90
70
90
90
30
30
30
5
5
5
MX29LV401TXBC-70
MX29LV401BXBC-70
MX29LV401TXBC-90
MX29LV401BXBC-90
MX29LV401TMI-70
MX29LV401BMI-70
MX29LV401TMI-90
MX29LV401BMI-90
MX29LV401TTI-70
70
70
90
90
70
70
90
90
70
30
30
30
30
30
30
30
30
30
5
5
5
5
5
5
5
5
5
MX29LV401BTI-70
MX29LV401TTI-90
MX29LV401BTI-90
70
90
90
30
30
30
5
5
5
MX29LV401TXBI-70
MX29LV401TXBI-90
MX29LV401BXBI-70
MX29LV401BXBI-90
70
90
70
90
30
30
30
30
5
5
5
5
P/N:PM0853
REV. 0.0, SEP. 14, 2001
52
MX29LV401T/B
PACKAGE INFORMATION
48-PIN PLASTICTSOP
P/N:PM0853
REV. 0.0, SEP. 14, 2001
53
MX29LV401T/B
44-PIN PLASTIC SOP
P/N:PM0853
REV. 0.0, SEP. 14, 2001
54
MX29LV401T/B
48-Ball CSP
P/N:PM0853
REV. 0.0, SEP. 14, 2001
55
MX29LV401T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
56
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明