MLX83100 [MELEXIS]
MLX83100 Automotive 2-Phase DC Pre-Driver;
| 型号： | MLX83100 |
| 厂家： | 
Melexis Microelectronic Systems |
| 描述： | MLX83100 Automotive 2-Phase DC Pre-Driver |
| 文件： | 总41页 (文件大小：2100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
1. Features and Benefits
.
2-phase DC gate driver
.
.
Integrated current sense amplifier
Level shifting between MCU PWM
outputs and 2 external half-bridges
Compatible with 3.3V-5V microcontrollers
Low offset and low offset drift
Fast settling time < 1µs
Programmable gain: 8x-48x
.
Supported supply voltage range
Extensive diagnostics
Absolute maximum rating: 45V
Operating range: 4.5V-28V
12V-28V Battery systems
Under/over voltage detection
Over temperature warning
Programmable VDS monitoring
VGS monitoring
Automotive qualified for 12V
Sleep mode with current <30µA
.
.
.
Serial, PWM diagnostics interface
.
.
Two charge pump configuration modes for
Configurable diagnostics
Full diagnostic feedback
Low voltage operation
Reverse polarity N-FET protection
Customer configurable EEPROM
High-side gate drivers with bootstrap circuits
Driver configuration
Diagnostics configuration
Integrated 12V voltage regulator
Supports 6x 350nC N-FETs at 20kHz PWM
Supports 100% PWM operation
Small package
28-pin TSSOP-EP, AEC-Q100 grade 0
qualification (TJ=175˚C)
2. Application Examples
.
Automotive 12V DC applications
.
Industrial DC motor drivers up to 28V
Water pump / Oil pump / Fuel pump
Engine Cooling fan
HVAC blower / compressor
Wiper
Pumps
Fans
Blowers
Compressors
Sunroof
EPS
3. Ordering Information
Product
Temperature
Package
GO (TSSOP28-EP 4.4x9.8mm)
Option Code Packing Form
MLX83100
L(-40°C to 150°C)
DBA-000
RE (Reel)
Ordering Example: “MLX83100LGO-DBA-000-RE”.
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
4. Functional Diagram
VBAT
VSUP
CP
VBOOST
3.3V-5V
Supply
VREG
Charge Pump
12V Regulator
CP1
CP2
CP3
-
Driver Supply
VDD
Internal Supply
VBATF
MLX83100
DC Pre-Driver
VDD Supply
GATET1
GATET2
HS
MCU
Gate Drivers
Driver Logic
FETT2-3
FETB2-3
PHASE1
Shoot
Dead
M
PWM
I/O
Through
Time
PHASE2
GATEB1
Protection
EN
LS
MISO
ICOM
Gate Drivers
CustomInterface
Error Output
EEPROM
GATEB2
Diagnostics
I/O
VREF
IBP
Current Sense Amplifier
ADC
ISENSE
IBM
AGND
DGND
Figure 4-1 Typical application diagram
VBAT
VSUP
CP
VBOOST
3.3V-5V
Supply
VREG
Charge Pump
12V Regulator
CP1
CP2
CP3
-
Driver Supply
VDD
Internal Supply
VBATF
MLX83100
DC Pre-Driver
VDD Supply
GATET1
GATET2
HS
MCU
Gate Drivers
Driver Logic
FETT2-3
FETB2-3
PHASE1
Shoot
Dead
M
PWM
I/O
Through
Time
PHASE2
GATEB1
Protection
EN
LS
MISO
ICOM
Gate Drivers
CustomInterface
Error Output
EEPROM
GATEB2
Diagnostics
I/O
VDD
VREF
IBP
Current Sense Amplifier
ADC
ISENSE
IBM
AGND
DGND
Figure 4-2 Alternative application diagram with reverse polarity N-FET
REVISION 5.1 –DECEMBER 13, 2016
Page 2 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
5. General Description
The MLX83100 is a two phase pre-driver (also called ‘bridge’ or ‘gate’ driver) IC with integrated current
sense amplifier. This device is used to drive brushed DC motors in combination with a microcontroller and
four discrete power N-FETs.
The device is able to control four external N-FETs for full H-bridge control in the supply range from 4.5V to
28V, by means of the integrated charge pump. The high side gate drivers are supplied via bootstrap circuits.
The trickle charge pump allows 100% PWM operation despite the use of bootstrap capacitors. The bootstrap
voltage regulator is optimized for gate charges up to 500nC per FET at 20 kHz PWM.
The device comprises various monitoring and protection functions, including under voltage and over voltage
detection at multiple internal voltage nodes, over temperature detection, drain-source and gate-source
voltage monitoring of the external N-FETs. In case of fault detection, the ICOM diagnostics interface will
inform the microcontroller with a PWM signal, where the duty cycle indicates the nature of the error.
An integrated fast, high-bandwidth, low offset current sense amplifier allows for precise torque control, with
programmable gain selection.
The MLX83100 provides an EEPROM for configurability, avoiding the need for a high pin-count package. The
configuration allows the customer to optimize the pre-driver’s operation for different applications.
REVISION 5.1 –DECEMBER 13, 2016
Page 3 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
6. Contents
1. Features and Benefits............................................................................................................................ 1
2. Application Examples............................................................................................................................. 1
3. Ordering Information ............................................................................................................................ 1
4. Functional Diagram ............................................................................................................................... 2
5. General Description............................................................................................................................... 3
6. Contents................................................................................................................................................ 4
7. Pin Configuration & Definition............................................................................................................... 5
7.1. Pin Configuration ................................................................................................................................5
7.2. Pin Definition.......................................................................................................................................6
8. Absolute Maximum Ratings................................................................................................................... 7
9. Operating Range.................................................................................................................................... 7
10. General Electrical Specifications.......................................................................................................... 8
10.1. MLX83100 Typical Performance Graphs .......................................................................................15
11. Block Diagram.................................................................................................................................... 16
12. Functional Description....................................................................................................................... 17
12.1. Supply System.................................................................................................................................17
12.2. Gate Drivers ....................................................................................................................................22
12.3. Integrated Current Sense Amplifier...............................................................................................23
12.4. Protection and Diagnostic Functions.............................................................................................24
12.5. EEPROM Configuration...................................................................................................................29
13. ESD Protection................................................................................................................................... 36
14. Package Information.......................................................................................................................... 37
14.1. Package Marking.............................................................................................................................37
14.2. Package Data...................................................................................................................................38
15. Standard information regarding manufacturability of Melexis products with different soldering
processes............................................................................................................................................ 39
16. ESD Precautions................................................................................................................................. 39
17. Revision History................................................................................................................................. 40
18. Disclaimer.......................................................................................................................................... 41
REVISION 5.1 –DECEMBER 13, 2016
Page 4 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
7. Pin Configuration & Definition
7.1. Pin Configuration
Figure 7-1 Pin configuration
REVISION 5.1 –DECEMBER 13, 2016
Page 5 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
7.2. Pin Definition
Pin #
Name
FETT2
FETT3
VDD
Description
1
2
3
4
5
6
7
8
High-side FET2 PWM control input (active high)
High-side FET3 PWM control input (active high)
Digital supply for IO’s and current sense amplifier
Current sense amplifier reference input
Current sense amplifier negative input
Current sense amplifier positive input
Current sense amplifier output
VREF
IBM
IBP
ISENSE
MISO
MISO output for SPI
Low-side FET2 PWM control input (active low)
CLK input for SPI
9
FETB2
FETB3
ICOM
Low-side FET3 PWM control input (active low)
MOSI input for SPI
10
11
Bidirectional, serial diagnostics interface
CSB input for SPI
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
EN
Enable input for gate driver outputs (active high)
Motor phase 2
PHASE2
GATET2
CP2
High-side FET2 gate driver output
High-side FET2 bootstrap capacitor
Motor phase 3
PHASE3
GATET3
CP3
High-side FET3 gate driver output
High-side FET3 bootstrap capacitor
Charge pump boosted supply output
Driver supply output for bootstrap capacitors
Low-side FET2 gate driver output
Low-side FET3 gate driver output
Driver ground
VBOOST
VREG
GATEB2
GATEB3
DGND
CP
Charge pump floating capacitor
Power supply input (Battery input)
Battery voltage connection for VDS-monitoring
Not connected
VSUP
VBATF
n.c.
AGND
PAD
Analog ground
Exposed pad
Table 7-1 Pin definition
REVISION 5.1 –DECEMBER 13, 2016
Page 6 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
8. Absolute Maximum Ratings
Parameter
Symbol
VVSUP, VBATF
VVSUP, VBATF
IVSUP
Min
-0.3
-0.3
-15
Typ
Max
45
28
-
Unit
V
Condition
Power supply voltage
Power supply voltage
Negative input current
-
-
-
t < 500ms (during load dump)
Permanent (functional)
V
mA
Defines with max. reverse
polarity voltage the RVBATF
Negative input current
IVBATF
VVDD
-10
-
-
mA
Digital supply voltage
Analog input voltage
Analog output voltage
-0.3
-
-
-
5.5
V
V
V
VVREF, VIBM,VIBP -0.3
VDD+0.3
VDD+0.3
VISENSE
-0.3
VFETBx, VFETTx
VEN
,
Digital input voltage
-0.3
-
VDD+0.3
V
Digital input current
Digital output voltage
Output voltage
-10
-0.3
-0.3
-0.3
-0.3
-0.7
-
-
-
-
-
-
10
VDD+0.3
17
mA
V
VICOM
VGATEBx, VREG
VGATETx
VCPx
V
Output voltage
VREG+35
VREG+35
45
V
Input voltage on CPx pins
V
Input voltage on PHASEx pins VPHASEx
V
Maximum latch-up free
current at any pin
According to JEDEC JESD78,
AEC-Q100-004
ILATCH
-100
-
100
mA
ESD capability
ESD
Tstg
TJ
-2
-
-
-
+2
kV
˚C
˚C
Human Body Model
Storage temperature
Junction temperature
-55
-40
150
175
In free air on multilayer PCB
(JEDEC 1s2p)
Thermal resistance SOIC-16 Rth-JA
Thermal resistance SOIC-16 Rth-JC
-
-
37
10
-
-
K/W
K/W Referring center of exposed pad
Table 8-1 Absolute maximum ratings
Exceeding the absolute maximum ratings may cause permanent damage. Exposure to absolute maximum-
rated conditions for extended periods may affect device reliability.
9. Operating Range
Parameter
Symbol
Min
4.5
3
Typ
Max Unit
Condition
Power supply voltage range VVSUP
Digital supply voltage range VVDD
-
-
-
-
28
5.5
150
175
V
V
Full functionality
CP discharged, power FETs off
Ambient temperature
Junction temperature
TA
TJ
-40
-40
˚C
˚C
Table 9-1 Operating range
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
10. General Electrical Specifications
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Power Supply VSUP
Supply voltage range
No.1
No.2
. Functional
VSUP
7
-
-
18
7
V
V
. Functional w. decreased
gate drive voltage
Supply voltage
extended range low
VSUP_ERL
4.5
Supply voltage
extended range high
No.3
No.4
VSUP_ERH
18
-
-
-
28
30
V
. VDD = Low
Quiescent current from VSUP ISUP_SLEEP
Operating current from VSUP ISUP_INT
µA
. Pre-driver operation
25kHz PWM, no load
No.5
-
-
5
mA
No.6
No.7
. Warning on ICOM
. ICOM released
Supply over voltage high
Supply over voltage low
VSUP_OVH
VSUP_OVL
-
-
-
35
-
V
V
30
Supply over voltage
hysteresis
No.8
No.9
VSUP_OVHY
0.4
-
-
-
1
2
V
Supply over voltage
debounce time
VSUP_OV_DEB
µs
No.10
No.11
. ICOM released
Supply under voltage high
Supply under voltage low
VSUP_UVH
VSUP_UVL
-
-
-
6
-
V
V
. Warning on ICOM
5
Supply under voltage
hysteresis
No.12
No.13
VSUP_UVHY
0.2
-
-
-
0.5
10
V
Supply under voltage
debounce time
VSUP_UV_DEB
µs
. Reset released on rising
edge VSUP when VDD=high
No.14
Power on reset level
VPOR
2.6
-
4.5
V
VVBATF
No.15
. Pre-driver not in sleep
Leakage from VBATF to GND
Temperature Warning
RVBATF_LEAK
-
-
30
µA
No.16
No.17
. Warning on ICOM
. ICOM released
Over temperature high
Over temperature low
OVTH
OVTL
-
-
185
168
-
-
C
C
On-Chip Oscillator
No.18
. Internal Oscillator
Oscillator frequency
fOSC
6.8
8
9.2
MHz
REVISION 5.1 –DECEMBER 13, 2016
Page 8 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Charge Pump CP, VBOOST
No.19
No.20
Output slew rate
VCP
fCP
-
100
200
-
V/µs
kHz
Charge pump frequency
170
230
. CP Mode 1
. VSUP > 7V
. IREG < 20mA
Reverse polarity N-FET gate-
No.21
No.22
No.23
No.24
VGS_RPFET
5
6
12
8
-
13
-
V
MOhm
V
source voltage (VBOOST-VSUP
)
. RTyp at room temperature
. RMin at 150C TJ
. (excl. RVREG_LEAK
Resistive load from VBOOST to
GND
RBOOST_LEAK
VBOOST_UVH
VBOOST_UVL
)
ICOM released
. CP Mode 0 (VBOOST)
. CP Mode 1 (VBOOST-VSUP
VBOOST under voltage high
VBOOST under voltage low
6.1
5.6
7.2
6.7
)
Warning on ICOM
. CP Mode 0 (VBOOST)
. CP Mode 1 (VBOOST-VSUP
-
V
)
)
. CP Mode 1 (VBOOST-VSUP
. Discharge activated by
VSUP_OV and topped by
VBOOST_DIS_STOP
VBOOST_DISST
OP
No.25
No.26
VBOOST discharge stop
V -0.2
SUP
-
-
V +0.8
SUP
V
. CP Mode 1 (VBOOST-VSUP
. From VBOOST to DGND
)
VBOOST discharge current
IBOOST_DIS
25
90
mA
REVISION 5.1 –DECEMBER 13, 2016
Page 9 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Driver Supply VREG
. VREG > 11V
. CP Mode 0, EN_CP = 1
IREG_CPMODE0
-
-
-
-
40
20
mA
mA
No.27
Load current on VREG
. VREG > 11V
. CP Mode 1, EN_CP = 1
IREG_CPMODE1
. CP Mode 0, EN_CP = 1
. VSUP > 8V
. IREG < 40mA
11
10
12
-
13
13
V
V
. CP Mode 0, EN_CP = 1
. 7V< VSUP < 8V
No.28
No.29
Output voltage VREG
VREG
. IREG < 40mA
. CP Mode 1, EN_CP = 1
. VSUP > 8V
. IREG < 20mA
11
12
13
-
V
. RTyp at room temperature
. RMin at 150C TJ
Internal resistive load from
VREG to GND
RVREG_LEAK
0.3
0.4
MOhm
No.30
No.31
No.32
No.33
No.34
No.35
. Warning on ICOM
. ICOM released
VREG over voltage high
VREG over voltage low
VREG_OVH
VREG_OVL
14.2
13.5
0.65
7.2
-
-
-
-
-
-
16.5
15.8
1.5
V
V
V
V
V
V
VREG over voltage hysteresis VREG_OVHY
. ICOM released
VREG under voltage high
VREG under voltage low
VREG_UVH
VREG_UVL
8.1
. Warning on ICOM
6.9
7.8
VREG under voltage hysteresis VREG_UVHY
0.3
0.7
Digital Supply VDD
. Incl. ICOM current
sourcing
No.36
VDD operating current
IDD
4
-
7
mA
No.37
No.38
No.39
No.40
No.41
No.42
No.43
No.44
VDD pull down resistance
VDD input voltage
VDD_RPD
VDD
VDD_UVH
VDD_UVL
200
3
300
370
5.5
kOhm
V
. VDD = 3.3V or 5V
. ICOM released
. Warning on ICOM
-
VDD under voltage high
VDD under voltage low
2.55
2.45
0.08
2.1
-
2.95
2.85
0.14
2.7
V
-
0.10
-
V
VDD under voltage hysteresis VDD_UVHY
V
. Out of sleep
. Go to sleep
VDD sleep voltage high
VDD sleep voltage low
VDD_SLEEPH
VDD_SLEEPL
V
1.6
-
2.1
V
VDD sleep voltage hysteresis VDD_SLEEPHY
0.45
0.58
0.80
V
REVISION 5.1 –DECEMBER 13, 2016
Page 10 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Gate Drivers
No.45 Rise time
No.46 Fall time
tr
tf
. CLOAD = 1nF, 20% to 80%
. CLOAD = 1nF, 80% to 20%
. VSUP > 7V
6
4
7
7
15
15
ns
ns
Pull-up ON resistance
10
15
10
15
-
-
-
-
-
-
30
30
30
30
Ohm
Ohm
Ohm
Ohm
A
low-side pre-driver
. -10mA, TJ = -40C
. -10mA, TJ = 175C
No.47
RON_UP
Pull-up ON resistance
high-side pre-driver
Pull-down ON resistance
low-side pre-driver
. VSUP > 7V
. 10mA, TJ = -40C
. 10mA, TJ = 175C
No.48
RON_DN
Pull-down ON resistance
high-side pre-driver
. VGS = 0V, VSUP > 7V
. VGS = 12V, VSUP > 7V
Turn-on gate drive
peak current (sourcing)
-1.4
(-0.45)
No.49
No.50
IGON
Turn-off gate drive
peak current (sinking)
1.6
(0.45)
IGOFF
A
. From logic input
threshold to 2V VGS drive
output at no load
No.51
No.52
Propagation delay
tPDDRV
20
-
-
1201
20
ns
ns
. Transitions at the
different phases at no
load condition
Propagation delay matching tPDDRVM
-20
. DEAD_TIME [ 2:0] = 000
0.00
0.51
0.80
1.10
1.67
2.30
3.40
6.90
001
010
011
100
101
110
111
Programmable dead time :
asynchronous internal delay
between high-side and low- tDEAD
side pre-driver of one half
bridge
No.53
No.54
-25%
-15
+25%
15
µs
%
Dead time matching
tDEAD_TOL
-
between different channels
1 For bare it is specified to 200ns max due measurement accuracy at wafer level
REVISION 5.1 –DECEMBER 13, 2016
Page 11 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
. VDSMON[2:0] =
000
Disabled
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0.40
0.60
0.85
1.05
1.25
1.50
1.70
0.60
0.90
1.15
1.45
1.75
2.00
2.30
001
010
011
100
101
110
111
Programmable drain-source
voltage for monitoring of
external N-FETs
No.55
VVDS_MON
V
Programmable drain-source
monitor blanking time: Delay
between gate high and
enabling corresponding VDS
monitor
VDS_BLANK_TIME[1:0] = 00
0.60
1.28
2.55
5.10
0.80
1.70
3.40
6.80
1.00
2.13
4.25
8.50
01
10
11
No.56
No.57
tVDS_BL
µs
. Internal resistance
between FET gate-source
pins to switch-off FET.
VDD = 0V (sleep mode)
. VGS = 0.5V
Sleep gate discharge resistor Rsgd
-
-
1
kOhm
. VSUP > 12V
. PHASEx = VSUP
. CPx = PHASEx + 6.5V
. ITCP,max @150C TJ
. ITCP,min @-40C TJ
Trickle charge pump current
capability
No.58
No.59
ITCP
-160
42
-
-
-25
70
µA
VGS under voltage threshold
high
. ICOM released
VGS_UVH
VGS_UVL
fDR_PWM
%V
REG
VGS under voltage threshold
low
No.60
No.61
. Warning on ICOM
36
-
-
63
%V
REG
PWM frequency
20
100
kHz
. RTyp at room temperature
. RMin at 150C TJ
No.62
Leakage from CPx - PHASEx
RCP_LEAK
0.5
1
-
MOhm
. Activated by VSUP_OVH
event
No.63
VCPx discharge current
IBOOST_DIS
8
-
40
mA
. From VCPx to VPHASEx
Logic IO’s - FET inputs, MISO
No.64
No.65
No.66
No.67
. Min. voltage logical high
. Max. voltage logical low
. FETBx
Digital input high voltage
Digital input low voltage
Input pull-up resistance
Input pull-down resistance
VIN_DIG_H
VIN_DIG_L
RIN_DIG_PU
RIN_DIG_PD
80
-
-
-
-
-
-
%V
DD
20
%V
DD
90
90
410
410
kOhm
kOhm
. FETTx
REVISION 5.1 –DECEMBER 13, 2016
Page 12 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Logic IO’s - EN input
No.68
No.69
. EN
Input pull-down resistance
R_EN_PD
90
-
-
-
410
1
kOhm
µs
. From bridge disable
EN<0.2VDD to VGS < 0.5V,
CLOAD = 1nF
Bridge disable propagation
delay
ENPR_DEL
Logic IO’s - ICOM
No.70
No.71
No.72
No.73
. VICOM = 0V
. VICOM = VDD
Pull-up current
ICOMPU
ICOMPD
fICOMF
-2.2
5.0
-
-5.0
2.6
mA
mA
kHz
kHz
Pull-down current
-
ICOM PWM frequency fast
ICOM PWM frequency slow
85
100
12.5
115
14.4
fICOMS
10.6
. EN = Low
. FETTx = Low, FETBx =
High
SPI start-up pulse duration
on ICOM to enter SPI mode
2048/
fOSC
4096/
fOSC
No.74
tSPI_SU
-
s
SPI Timing
No.75
No.76
No.77
No.78
No.79
No.80
No.81
No.82
No.83
No.84
No.85
No.86
SPI initial setup time
SPI clock frequency
Rise/fall times
tSPI_ISU
fSPI
2
-
-
-
µs
kHz
ns
-
500
. CLK, CSB, MISO, MOSI
tSPI_RF
tCSB_SU
tCSB_H
tCLK_H
tCLK_L
tDI_SU
tDI_H
-
-
200
CSB setup time
1
-
-
-
-
-
-
µs
µs
µs
µs
µs
ns
CSB high time
2
-
Clock high time
1
-
Clock low time
1
-
Data in setup time
Data in hold time
Data out ready delay
EEPROM read delay
EEPROM write delay
1
-
500
-
-
500
-
. CLOAD at FETB1 < 50pF
. EE_RD = 1
tDO_R
tEE_RD
tEE_WR
-
ns
6
µs
ms
. EE_WR = 1
12
-
-
Temperature for EEPROM
read
No.87
No.88
. Junction temperature
. Junction temperature
TJ_EE_RD
-40
-40
-
-
150
C
C
Temperature for EEPROM
write
T J_EE_WR
150
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Current Sense Amplifier
No.89
No.90
Input offset voltage
VIS_IO
-7.6
-10
-
-
7.6
10
mV
Input offset voltage
thermal drift
VIS_IO_TDRIFT
µV/C
Input common mode
rejection ratio DC
. Input differential voltage
within ±100mV
Common mode [-0.5, 1.0]
V
No.91
No.92
No.93
No.94
ISCMRR_DC
ISCMRR_AC
ISPSRR_DC
ISPSRR_AC
60
40
60
40
-
-
-
-
-
-
-
-
dB
dB
dB
dB
Input common mode
rejection ratio 1MHz
Input power supply rejection
ratio DC for VDD supply
Input power supply rejection
ratio 1MHz for VDD supply
. Current sense gain = 000
8.0
10.3
13.3
17.2
22.2
28.7
37.0
47.8
001
010
011
100
101
110
111
No.95
Closed loop gain
ISGAIN
-3%
+3%
. Amplified output to 99%
of final value after input
change
No.96
Output settling time
ISSET
VISENSE_MAX
VISENSE_MIN
-
-
1.0
VDD
µs
No.97
No.98
. ISENSE output max level
. ISENSE output min level
Output voltage range high
Output voltage range low
VDD-0.02
GND
-
-
V
V
GND+0.0
2
. Output current saturation
level
Output short circuit current
to ground
No.99
IISENSE_SC
-
1.4
-
mA
No.10
Gain bandwidth (GBW)
ISGBW
ISSR
6
--
-
-
-
MHz
V/µs
No.10
Output slew rate
8
. CM spike = ±1.5V,
t=250ns
No.10
CM spike recovery
ISCM_REC
-
-
-
730
50
ns
No.10
VREF voltage input
VREF
Table 10-1 General Electrical Specifications
0
%V
DD
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
10.1. MLX83100 Typical Performance Graphs
Figure 10-1 MLX83100 Regulated output voltage vs.
supply voltage
Figure 10-2 MLX83100 Regulated output voltage vs.
supply voltage
Figure 10-3 MLX83100 High-side driver FET RON
resistance vs. supply voltage
Figure 10-4 MLX83100 High-side driver FET ROFF
resistance vs. supply voltage
Figure 10-5 MLX83100 Low-side driver FET RON
resistance vs. supply voltage
Figure 10-6 MLX83100 Low-side driver FET ROFF
resistance vs. supply voltage
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
11. Block Diagram
VBAT
VSUP
CP
VBOOST
ChargePump
SupplyMonitor
VSUP_OV
VSUP
Charge
Pump
Control
VREG
VSUP
VSUP_UV
VSUP
12VRegulator
Charge
COMP
Pump
Mode
VBOOST_UV
VBOOST
VBATF
CPx
VREG_OV
VREG
DriverStage
VDD
3.3V
RCO
VREG_UV
VREG
Trickle
VDD_UV
VDD
ChargePump
POR
Bandgap
GateDriverLogic
ExternalFET
Monitoring
2
2
FETTx
GATETx
PHASEx
Top
Driver
DeadTime
VBATF
2xHSVDS_OV
2xHSVGS_UV
2xLSVDS_OV
PHASEx
GATETX
EN
PHASEx
PHASEx
VDD
IBP
FETBx
GATEBx
Bottom
Driver
DeadTime
2x
Custom
SPIInterface
EEPROM
ERR
MISO
EEPROM
2x
Bi-directional,SerialDiagnosticsInterface
CurrentSenseAmplifier
Temperature
OVT
Warning
VDD
1
ICOM_OUT
IBP
ICOM
VDD
Error
Controller
Gain
IBM
ICOM_IN
AGND DGND
VREF
ISENSE
Figure 11-1 Block diagram
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12. Functional Description
12.1. Supply System
The MLX83100 is supplied via pins VSUP and VDD. The power supply VSUP supplies the internal operation of
the pre-driver, the charge pump and the voltage regulator used for the bootstrap based architecture. The
digital supply VDD supplies the IO’s and the current sense amplifier.
Inputs
Outputs
Internal
VSUP
POR
VBOOST
VREG
VDD
CSA
3.3V
VBG
CP
IO’s
EEPROM
RCO
Diagnostics
Drivers
Figure 12-1 Principle organization of the supply system
12.1.1. Power Supply - VSUP
The internal operation of the pre-driver is supplied from the power supply input pin VSUP. It supplies the
bandgap reference, power-on-reset system and internal 3.3V regulator. This 3.3V regulator in turn supplies
the EEPROM, RC-oscillator and diagnostics. For safety reasons the pre-driver provides integrated under
voltage and over voltage detection on VSUP.
12.1.2. Charge Pump - VBOOST
The IC comprises a charge pump, supplied from VSUP, which allows full device operation down to 4.5V. The
charge pump boosted output voltage is available on VBOOST. This boosted voltage powers the voltage
regulator VREG used to supply the low-side drivers directly, and high-side drivers via the bootstrap
architecture. See Figure 4-1 for the standard charge pump configuration where VBOOST is regulated relative
to ground. The charge pump will not be switching when VSUP > VREG + 2xVf, diode
.
An alternative mode of operation for the charge pump supports the use of an external low drop N-FET for
reverse polarity protection. In this mode the charge pump boosts the output voltage relative to the supply
voltage instead of relative to ground, see application diagram in Figure 4-2. The disadvantage is an
additional amount of dissipation inside the driver to regulate VREG.
The charge pump architecture is a supply voltage doubler with feedback loop for stable output voltage
generation, as shown in Figure 12-2. It can be configured in EEPROM to either regulate the boosted output
voltage VBOOST relative to ground or relative to the supply voltage, see Figure 12-3 for the typical output
voltage. Furthermore the EEPROM configuration allows disabling the charge pump for applications not
requiring the low voltage operation, in order to reduce the overall power consumption.
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
For safety reasons the pre-driver provides integrated under voltage detection on VBOOST. In addition the
charge pump comprises a discharge switch in order to keep VBOOST output voltage in a safe operating area
in case of over voltage on the supply input pin. The discharge switch is activated as soon as the supply
voltage VSUP exceeds the VSUP_OVH threshold level and is deactivated when it drops below the VSUP_OVL
threshold. At the same time the charge pump is deactivated.
EN_CP
CPMODE
Charge pump configuration
0
x
Charge pump disabled
Charge pump configured to regulate VBOOST relative to ground, to support
low voltage operation
1
1
0
1
Charge pump configured to regulate VBOOST relative to the supply, to
support the use of a reverse polarity N-FET
Table 12-1 Charge pump configuration options
CPMODE
VSUP
CP
VBOOST
EN_CP
Level shift
with
dead time
&
VSUP
fCP
Control
CP_FB
CP_DSCHG
CPMODE
VSUP
slope
COMP
OPA
VBOOST_UV
COMP
Figure 12-2 Charge pump principle schematic
Charge Pump and Voltage Regulator Output vs Power Supply Input
25 V
23 V
20 V
18 V
15 V
13 V
10 V
8 V
CP Mode 0 - VBOOST
CP Mode 1 - VBOOST
VREG
5 V
3 V
CPx-GATETx
0 V
4.0 V
6.0 V
8.0 V
10.0 V
12.0 V
VSUP [V]
Figure 12-3 Charge pump output and driver supply
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.1.3. Voltage Regulator - VREG
The voltage regulator regulates the power supply down to 12V, in order to supply the low-side gate drivers
and switch the external low-side N-FETs without gate-source over voltage at high battery voltages. The
regulated output voltage VREG further provides the bootstrap voltage for driving the high-side N-FETs.
For safety reasons the pre-driver provides integrated under voltage and over voltage detection on VREG.
12V
regulator
VREG
VBATF
CPx
Trickle
ChargePump
2
2
2
2
Ccpx
GATETx
PHASEx
GATEBx
Top Driver
Bottom
Driver
Rshunt
Figure 12-4 Voltage regulator for driver supply – VREG
12.1.4. Digital Supply - VDD
The MLX83100 comprises a current sense amplifier. The current sense amplifier and IO’s are supplied from
the digital supply VDD.
For safety reasons the pre-driver provides integrated under voltage detection on VDD.
Note:
When supplying VDD with a limited output impedance (e.g. from a microcontroller IO) the performance of
the amplifier may be affected.
12.1.5. Sleep Mode
Sleep mode is activated when the digital supply input VDD is pulled below “VVDD sleep voltage
threshold low”. In sleep mode the charge pump is disabled and the current consumption on VSUP is
reduced. All gate drivers are switched off via sleep gate discharge resistors RSGD. The pre-driver will wake-up
as soon as the voltage level on VDD rises above “VVDD sleep voltage threshold high”.
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Pin Name
State in sleep mode
CP
The charge pump is disabled.
Since the charge pump is disabled VBOOST is pulled to the supply voltage via the external
charge pump diodes.
VBOOST
GATEBx
GATETx
In sleep mode, gate-discharge resistors (RSGD) between GATEBx and DGND are activated,
ensuring all low-side gate drivers are switched off
In sleep mode, gate-discharge resistors (RSGD) between GATETx and PHASEx are activated,
ensuring all high-side gate drivers are switched off
PHASEx
VREG
CPx
Phases are kept low with GATETx through the internal body diode of the pre-driver
Voltage regulator is disabled
Any charge that remains after VREG is disabled will leak to ground
Current sense amplifier is supplied from VDD, and thus not active
ISENSE
FETBx, FETTx
EN, ICOM, MISO
All IO’s are supplied from VDD, and thus not active
Table 12-2 Drivers in Sleep Mode
Notes:
1. In case any of the digital input pins are externally pulled high while VDD is low, current will flow into
VDD via internal ESD protection diodes. This condition is not allowed.
2. When VDD is pulled low, also ICOM will go low. This should not be interpreted as a diagnostic
interrupt.
CPx
GATETx
RSGD
PHASEx
VREG
GATEBx
RSGD
Figure 13-1-5 Drivers in Sleep Mode
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.2. Gate Drivers
12.2.1. PWM Input Control Logic – FETBx & FETTx
Each of the 4 external N-FETs can be controlled independently via the 4 digital PWM input pins: FETBx and
FETTx. However, the digital logic provides the option to control the 2 external half bridges with only 2
control signals, by shorting high-side and low-side PWM input pins for each half bridge.
The IC provides internal shoot through protection since the digital logic prevents simultaneous activation of
both high-side and low-side driver of one half bridge. A configurable dead time ensures the high-side (low-
side) N-FET is fully switched off, before switching on the complementary low-side (high-side) N-FET.
For safety reasons the pre-driver provides integrated drain-source and gate-source monitoring for each of
the 4 external N-FETs.
FETTx
GATETx
DeadTime
PHASEx
EN
FETBx
GATEBx
DeadTime
Figure 12-5 Input control logic of the driver stage
12.2.2. Enable Input EN
The enable input pin EN enables the gate driver outputs when set high. When reset, all gate driver outputs
are switched to the low state, switching off all external N-FETs. This is performed by pulling all gate drivers
to ground via the pull-down on-resistances. The enable pin can be used by the microcontroller to disable all
drivers in case of any fault detection.
While EN is low, the programming of the EEPROM via SPI can be initiated by pulling ICOM low for the SPI
start-up time specified by tSPI_SU
.
12.2.3. Gate Driver Supply and Bootstrap Architecture – VREG & CPx
The voltage regulator regulates the power supply voltage down to 12V. The regulated voltage is used to
directly supply the low-side drivers. To provide sufficient supply voltage for the high-side drivers a bootstrap
architecture is used. When the low-side N-FET is switched on, the phase voltage will be pulled low and the
bootstrap capacitor is charged from the VREG buffer capacitor through the bootstrap diode. Afterwards, if
the low-side N-FET is switched off and the high-side N-FET is switched on, the charge of the bootstrap
capacitor is used to supply sufficient gate drive voltage to the high-side N-FET. The integrated trickle charge
pump assures the bootstrap capacitor will not be discharged, and allows 100% PWM operation.
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.3. Integrated Current Sense Amplifier
The IC comprises an integrated fast, high-bandwidth, low offset current sense amplifier.
The current sense amplifier is supplied from the digital supply. It senses the voltage over the low-side shunt,
amplifies it with the gain programmed in EEPROM and adds the offset provided on VREF. The output of the
amplifier is available on ISENSE.
ꢀꢁꢂꢀꢁ ꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊ ꢀꢋꢅꢈꢉꢌ ꢊ ꢍꢎꢏꢈꢐꢐꢑꢒꢓꢔ ꢕ ꢖꢗꢒꢐꢘ
VDD
1
VREF
IBP
OPA
OPA
ISENSE
IBM
Figure 12-6 Current Sense Amplifier
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.4. Protection and Diagnostic Functions
12.4.1. Power Supply Over Voltage Shutdown (VSUP_OV)
The pre-driver has an integrated VSUP over voltage shut down to prevent destruction of the IC at high
supply voltages.
12.4.2. Power Supply Under Voltage Warning (VSUP_UV)
The pre-driver has an integrated VSUP under voltage detection. The diagnostics interface will give a warning
to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable
operation.
12.4.3. Digital Supply Under Voltage Warning (VDD_UV)
The pre-driver has an integrated VDD under voltage detection. The diagnostics interface will give a warning
to the microcontroller. It is the responsibility of the microcontroller to take action in order to ensure reliable
communication between microcontroller and pre-driver.
12.4.4. VBOOST Under Voltage Warning (VBOOST_UV)
The integrated charge pump boosts the supply voltage in low voltage operation on the VBOOST output.
There is an under voltage detection on VBOOST to warn the microcontroller the charge pump is not ready. It
is the responsibility of the microcontroller to take action in order to ensure reliable motor operation.
12.4.5. Gate Driver Supply Over Voltage Warning/Shutdown (VREG_OV)
The MLX83100 comprises an integrated VREG over voltage detection. The reaction of the pre-driver on this
VREG_OV event depends on the status of the Bridge Feedback bit in EEPROM. If this VREG_OV_BF_EN bit is
set the pre-driver will disable all gate drivers, switching off all external N-FETs. If the bit is reset it will just
give a warning to the microcontroller.
VREG_OV_BF_EN
Pre-driver reaction VREG_OV event
0
1
VREG_OV is reported on ICOM, but the drivers remain active
VREG_OV is reported on ICOM and the drivers are disabled
Table 12-3 EEPROM Configuration for VREG over voltage detection
12.4.6. Gate Driver Supply Under Voltage Warning (VREG_UV)
The pre-driver detects when the regulated voltage drops below the under voltage threshold. The diagnostics
interface will give a warning to the microcontroller. It is the responsibility of the microcontroller to take
action in order to ensure reliable switching of the external N-FETs, since the VREG voltage directly supplies
the low-side gate drivers.
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.4.7. Gate Source Voltage Monitoring Warning (VGS_UV)
In order to ensure reliable switching of the high-side N-FETs, the MLX83100 comprises gate-source monitors
for each of the high-side N-FETs. In case of an under voltage, the diagnostics interface will give a warning to
the microcontroller, if the gate-source comparators are enabled in EEPROM. It is the responsibility of the
microcontroller to take action in order to ensure reliable switching of the high-side gate drivers.
12.4.8. Over Temperature Warning (OVT)
If the junction temperature exceeds the specified threshold, a warning will be communicated to the
microcontroller. The pre-driver will continue in normal operation. It is the responsibility of the
microcontroller to protect the IC against over temperature destruction.
12.4.9. Shoot Through Protection and Dead Time
The pre-drivers’ internal implementation guarantees that low-side and high-side N-FET of the same external
half bridge cannot be conducting at the same time, preventing a short between the supply and ground. In
addition the pre-driver provides a programmable dead time in EEPROM. The dead time sets the delay
between the moment when the high-side (low-side) N-FET is switched off, and the moment when the
complementary low-side (high-side) N-FET can be switched on.
12.4.10. Drain-Source Voltage Monitoring Warning/Shutdown (VDS_ERR)
The MLX83100 provides a drain-source voltage monitoring feature for each external N-FET to protect against
short circuits to ground or supply. For the high-sides the drain-source voltage are sensed via the VBATF –and
PHASEx-pins. For the low-sides the PHASEx –and IBP-pins are used. The drain-source voltage comparator can
be enabled or disabled in EEPROM.
The drain-source voltage monitor for a certain external N-FET is activated when the corresponding input is
switched on and the dead time has passed. An additional blanking time can be programmed in EEPROM. If
the drain-source voltage remains higher than the VDS monitor threshold voltage, the VDS error is raised. The
threshold voltage is configurable in EEPROM.
The reaction of the pre-driver on a VDS error can be configured in EEPROM with the Bridge Feedback bit. If
this bit is set the pre-driver automatically disables the drivers when a VDS error is detected. If the bit is
reset, the drivers remain active. In both cases the VDS error will be reported to the microcontroller.
VDS_COMP_EN
VDS_BF_EN
Pre-driver reaction on VDS-error event
0
1
1
x
0
1
Any VDS error is ignored and no error is reported on ICOM
VDS_ERR is reported on ICOM, but the drivers remain active
VDS_ERR is reported on ICOM and the drivers are disabled
Table 12-4 EEPROM Configuration for drain-source error detection
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.4.11. EEPROM Error Warning (EEP_ERR)
To ensure reliable communication with EEPROM the pre-driver provides an automatic single bit error
correction and double error detection. If two bits in the addressed word are bad the EEPROM gives the
EEP_ERR warning, indicating a double error was detected.
12.4.12. Diagnostics Interface – ICOM
All diagnostic events described above are reported to the microcontroller via a single pin, ICOM. In normal
operation, when no error is detected, ICOM is default high.
The ICOM interface acts as a serial interface that feeds back detailed diagnostics information. If an error is
detected, ICOM goes from default high to communicating a PWM-signal. The speed of this PWM signal
depends on the EEPROM configuration of bit PWM_SPEED. Each error corresponds to a duty cycle with a 5-
bit resolution. Thus the microcontroller can distinguish different errors by reading the duty cycle, see Table
12-7.
PWM_SPEED
Description
0
1
Slow mode: for slow microcontrollers
Fast mode : for fastest response of microcontroller
Table 12-5 EEPROM Configuration for diagnostics communication speed
The duty cycle is transmitted until the microcontroller sends the acknowledgement. This is done by pulling
ICOM low for more than a PWM-period, tAck > tICOM. At each ICOM falling edge the pre-driver checks the
actual voltage on ICOM in order to detect an acknowledgement. After acknowledgement the duty cycle of
the next error is transmitted, if multiple errors were detected. All errors have been reported when the end-
of-frame duty cycle is send. When all errors are physically removed, and the end-of-frame message is
acknowledged by the microcontroller, ICOM returns to its default high state.
Physical
Error
ICOM
Default high
Error Information
End-of-Frame
Default high
MCU
Acknowledge
Figure 12-7 ICOM Diagnostics Communication
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Page 26 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Notes:
1. When VDD is pulled low to put the pre-driver in sleep mode, ICOM will go low as well. This should
not be interpreted as a diagnostic interrupt. As soon as VDD goes high, the pre-driver wakes-up and
ICOM will return to its default high state.
2. At POR it is possible that the voltages on VSUP and VREG were not above the under voltage
thresholds (e.g. due to charging of external capacitors). It is possible that ICOM reports these under
voltage errors after POR. This implies that the microcontroller has to acknowledge these errors
before ICOM will be in its default high state and the pre-driver is ready for normal operation.
The drivers are disabled when
The drivers are enabled again as soon as
An error condition is detected for which the hardware
protection is activated
VSUP_OV
The microcontroller acknowledges the error
VREG_OV
VDS_ERR
VDD = Low (sleep mode)
EN = Low
VDD = High (wake-up)
EN = High
Table 12-6 Pre-Driver Output State Summary
VDD
VDD
Microcontroller
Pre-Driver
ICOM_OUT
<5mA
<5mA
Interrupt / Read duty cycle
Acknowledge
ICOM
Cload
<100pF
ICOM_IN
Figure 12-8 ICOM Diagnostics Interface
In case multiple errors occur at the same time, the priority is as defined in Table 12-7. The highest priority is
0 and 16 is the lowest priority.
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Priority
Error Event
% Duty Cycle
Debounce Time Description
11
ICOM_EOF
93.5
n/a
End of frame
VDS Error = VDS_T1 | VDS_T2 | VDS_T3 |
VDS_B1 | VDS_B2 | VDS_B3
This event can be masked by setting
VDS_COMP_EN = 0
10
VDS_ERR
82.5
2 µs
To avoid erroneous triggering due to
switching there is a programmable
blanking time on top of the debounce
time: VDS_BLANK_TIME[1:0].
9
8
7
6
5
4
EEP_ERR
VDD_UV
VSUP_OV
VSUP_UV
OVT
55.0
49.5
44.0
38.5
33.0
27.5
n/a
8 µs
2 µs
8 µs
2 µs
16 µs
EEPROM dual error detected
VDD under voltage
VSUP over voltage
VSUP under voltage
OVT over temperature
VREG under voltage
VGS under voltage
VREG_UV
3
2
1
VGS_UV
VBOOST_UV
VREG_OV
22.0
16.5
11.0
2 µs
16 µs
2 µs
This event can be masked by setting
VGS_UV_COMP_EN = 0
VBOOST under voltage
VREG over voltage
This event can be masked by setting
VGS_UV_COMP_EN = 0
Table 12-7 Overview Diagnostics over ICOM with Priority Definitions
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.5. EEPROM Configuration
The MLX83100 provides an EEPROM for configuration of the IC, the current sense amplifier and over current
comparator, protection and diagnostic functions. This allows to optimize the pre-drivers’ operation for the
application requirements. The configuration can be done at customer production testing by using the PTC-
04, or by the microcontroller via a custom program interface.
The EEPROM features single error correction and double error detection.
12.5.1. Memory Map
The MLX83100 comprises 6 bytes of EEPROM for user configurability. The first two bytes are not used for
the internal configuration of the pre-driver, and can thus be used by the customer for traceability purposes.
The other 4 bytes are used for configuration of the current sense amplifier and configuration of the
diagnostics.
The pre-driver is programmed with default settings per table below.
Address
0
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
Res.
0
-
0
-
-
-
0
-
-
0
-
-
-
0
-
-
0x00
1
0
0
0
-
-
-
Res.
0
0x00
2
0
0
0
0
0
VDSMON[2:0]
111
0
0
CPMODE
0
DEAD_TIME[2:0]
011
Res.
0
0x7C
3
VDS_BLANK_TIME[1:0] PWM_SPEED
-
0
CUR_GAIN[2:0]
011
Res.
0
0x86
10
0
VREG_OV
_BF_EN
VDS
_BF_EN
VDS
VGS_UV
4
EN_TCP
EN_CP
-
Res.
_COMP_EN _COMP_EN
0xF4
5(-6-7)
0xC0
1
SPI_EN
1
1
Res.
1
1
-
1
-
0
-
1
-
0
-
0
Res.
0
0
0
0
0
0
Table 12-8 EEPROM Memory Map and Default Configuration
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Bit Name
Description
Default
Configuration of the IC
CPMODE
Defines the mode of operation of the internal charge pump
1: VBOOST voltage is regulated relative to VSUP
for reverse polarity N-FET protection
0
0: VBOOST voltage is regulated relative to GND
for low voltage operation with minimal power consumption
EN_CP
EN_TCP
SPI_EN
Defines the status of the pre-drivers’ internal charge pump
1: Charge pump active
0: Charge pump not active
1
0
1
Defines the status of the pre-drivers’ trickle charge pump
1: Trickle charge pump active
0: Trickle charge pump not active
Defines the accessibility of EEPROM through the custom SPI interface
1: EEPROM accessible via the custom SPI interface
0: EEPROM not accessible via the custom SPI interface
Configuration of the Current Sense Amplifier and Over Current Comparator
CUR_GAIN[2:0] Defines the gain of the current sense amplifier
Configuration of the Protection and Diagnostic Functions
011
0
PWM_SPEED
Defines the diagnostics communication speed on ICOM
1: Fast mode for fastest response of microcontroller
0: Slow mode for low-end microcontrollers
VREG_OV_BF_EN
Defines the pre-drivers’ reaction on a regulated supply over voltage:
1: Report VREG_OV on ICOM and disable gate drivers
1
0: Report VREG_OV on ICOM without effect on gate drivers
DEAD_TIME[2:0]
VDSMON[2:0]
Defines the dead time between switching off high-side (low-side) N-FET 011
and switching on complementary low-side (high-side) N-FET
Defines the threshold level for the VDS monitoring of the external N-
FETs
111
VDS_BLANK_TIME[1:0] Defines the duration of the VDS blanking time after switching on the N- 10
FET
VDS_COMP_EN
Defines the status of the pre-drivers’ drain-source monitoring
1: Drain-source comparators active
0: Drain-source comparators not active
1
1
1
VDS_BF_EN
Defines the pre-drivers’ reaction on a drain-source fault:
1: Report VDS_ERR on ICOM and disable gate drivers
0: Report VDS_ERR on ICOM without effect on gate drivers
VGS_UV_COMP_EN
Defines the status of the pre-drivers’ gate-source monitoring
1: Drain-source comparators active
0: Drain-source comparators not active
Table 12-9 EEPROM Bit Description
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.5.2. “SPI Program Mode”
The EEPROM memory can be accessed through a custom SPI interface. It allows the user to read/program
the EEPROM by the microcontroller in the application. This custom interface re-uses the low-side driver pins
for SPI communication.
Since the same pins are used for both reading/writing the EEPROM and for controlling the motor, the
EEPROM is only accessible when the motor is not running. Furthermore it is necessary to apply a certain
sequence of conditions before the pre-driver will enter the “SPI Program Mode”. Once in this mode, the
EEPROM can be accessed for reading and writing, until the IC enters “Normal Mode” again and motor
operation is possible.
EN
FETTx
DriverLogic
FETBx
MISO
Custom
EEPROM
ICOM
SPI
Diagnostics
Figure 12-9 Custom SPI interface
Pin Name
SPI Signal
Description
ICOM
CSB
SPI-frames are defined by CSB low
The MOSI (Master Out – Slave In) shift register is reading in
data on the rising edge of CLK
FETB3
FETB2
MISO
MOSI
CLK
Clock input, each SPI-frame has to consist of 16 clock periods
The MISO (Master In – Slave Out) output is guaranteed to be
stable while the CLK is low
MISO
Table 12-10 SPI Signals
12.5.2.1. Entering “SPI Program Mode”
The MLX83100 enters “SPI Program Mode” when all below conditions are satisfied:
.
.
.
.
EN = 0
FETTx = Low (High-side FET inputs off)
FETBx = High (Low-side FET inputs off)
ICOM
.
.
Any pending errors have been removed and acknowledged, so ICOM is in default high state
A low level pulse is applied on ICOM for a time tSPI_SU
.
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.5.2.2. Exiting “SPI Program Mode”
The MLX83100 will exit the “SPI Program Mode” when the enable input EN is pulled high. Similar to when
the MLX83100 comes out of POR, after leaving the “SPI Program Mode” the pre-driver is blocked until the
data have been copied to the registers. Meaning that before entering “Normal Mode” the EEPROM write will
be completed and the EEPROM state machine will copy all EEPROM contents into registers. During this time
ICOM is kept low. When it returns to its default high state the pre-driver is ready for normal operation.
12.5.2.3. Protocol
Once the IC is in “SPI Program Mode” the microcontroller can read/write the EEPROM, following the
protocol depicted below.
EE_READY=1
Data in
DATA latch
EE_READY=1
Data in
DATA LATCH register
READ INSTRUCTION
WRITE INSTRUCTION
Copy latched DATA
(not read from EEPROM!)
into MISO [10:4]
If COMM_ERR = 0
Start EE_RD
Copy latched DATA into
MISO [10:4]
If comm_err = 0
Start EE_WR
Latch data into
MOSI register on
CLK Rising edge
>tEE_RD
> tEE_WR
CSB
CLK
n[0]
n+1[0]
n+1[15]
n+2[0]
n[1]
n[2]
n[15]
n[1]
n+1[1] n+1[2]
n[1]
n+2[1]
MOSI
MISO
n+1[0]
n+1[15]
n[0]
n[1]
n[15]
n+1[1]
n+2[0]
n+2[1]
Data on MISO stable
(valid) while CLK is
LOW
MISO[10:4] contains DATA
requested in previous Read
instruction
MISO[10:4] contains previous
MOSI[10:4] DATA
Figure 12-10 SPI Protocol (LSB first)
12.5.2.4. Registers Description
MOSI [15:0]
Bit [15]
MOSI_PAR
Bit [7]
Bit [14]
x
Bit [13]
x
Bit [12]
Bit [11]
Bit [10]
Bit [2]
Bit [9]
Bit [8]
Bit [0]
CMD [1:0]
MOSI_DATA [7:5]
Bit [1]
Bit [6]
Bit [5]
Bit [4]
Bit [3]
x
MOSI_DATA [4:1]
ADDRESS [2:0]
Table 12-11 MOSI frame description
MISO[15:0]
Bit [15]
Bit [14]
Bit [13]
Bit [12]
Bit [11]
Bit [10]
Bit [2]
Bit [9]
MISO_DATA [7:5]
Bit [1]
Bit [8]
Bit [0]
MISO_PAR COMM_ERR EE_READY
Bit [7] Bit [6] Bit [5]
MISO_DATA [4:1]
CMD [1:0]
Bit [4]
Bit [3]
x
ADDRESS [2:0]
Table 12-12 MISO frame description
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
Bit
Description
ADDRESS
Address of the byte in EEPROM that needs to be read/written to.
In case of write command, the data that needs to be written. Don’t care for any read
command.
MOSI_DATA[7:1]
MISO_DATA[7:1]
In case previous command was write instruction, it returns the data that was written. In
case of a read instruction, it returns the data read from EEPROM.
Read/Write command
00: EE_RD: Read command
01: EE_WR: Write command
10: EE_RDAW1
CMD [1:0]
11: EE_RDAW2
Reading/writing the EEPROM takes a certain time, specified by tEE_RD and tEE_WR
respectively. These times define the minimum time CSB (ICOM) has to remain high
between two SPI-frames in order to finish the read/ write action.
As soon as the read/write action starts, the EE_READY bit is reset. After completion of
the read/write action the bit is set.
EE_READY
If the read/write delay between SPI-frames was long enough to execute the read/write
action, the EE_READY bit will thus be set, signaling the read/write action was finished. If
the time was too short, the bit will still be 0.
This bit indicates if the previous MOSI-frame was received correctly. If no
communication error occurred the bit will be reset, and the read/write action was
started as soon as CSB was pulled high.
COMM_ERR
If a communication error occurred in the previous MOSI-frame the read/write command
was not executed. Possible communication errors are:
Odd parity bit was set incorrect
Number of clock periods was not equal to 16
MOSI_PAR,
MISO_PAR
Odd parity bit of the current MOSI/MISO frame.
Table 12-13 MOSI/MISO frames bit description
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
15
14
X
13
X
[11:12]
[10:4]
3
[2:0]
MOSI_
PAR
CMD[1:0]
MOSI_DATA[6:0]
X
ADDRESS[2:0]
MOSI
CLK COUNTER=16
COMM
_ERR
EEPROM
EE_
READY
Latches
DATA[6:0]
MISO_ COMM
EE_
READY
CMD[1:0]
MISO_DATA[6:0]
X
ADDRESS[2:0]
MISO
PAR
_ERR
Figure 12-11 MOSI/MISO registers and relation to internal data latches
12.5.2.5. Read Instruction
In order to read one of the EEPROM bytes, the microcontroller should compose the MOSI(N) frame
according to Table 12-11 with the address it wants to read, the read command and set the odd parity bit in a
correct way.
After transmission of this MOSI(N)-frame and when the CSB signal is pulled high, the pre-driver will start to
read the data at the specific address. If CSB is kept high long enough for the pre-driver to execute the read
action, it will transmit the read data on the next MISO(N+1)-frame.
The data in this MISO(N+1)-frame is valid only if
.
.
.
COMM_ERR = 0 :
EE_READY = 1 :
no communication error was detected on the previous MOSI(N)-frame
the read delay was long enough to finish the read
MISO_PAR = correct : the MISO(N+1)-frame has a correct odd parity bit
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
12.5.2.6. Write Instruction
The MLX83100 provides different configuration options through the EEPROM programming. In order to
program one of the EEPROM bytes, the microcontroller should compose the MOSI(N) frame according to
Table 12-11 with the address and data it wants to write, the write command and set the odd parity bit in a
correct way.
After transmission of this MOSI(N)-frame and when the CSB signal is pulled high, the pre-driver will start to
write the data at the specific address. If CSB is kept high long enough the pre-driver will be able to complete
the write instruction.
In total three verification steps are possible in order to ensure successful writing of the EEPROM. On the first
MISO-frame after the write command, it can be checked if the write command is received correctly and the
correct address and data are used. In the next two MISO-frames the data written in EEPROM can be read in
order to guarantee the desired data has been written in EEPROM
.
.
.
Verification Step 1: Correct receive of the write instruction using the MISO(N+1)-frame
.
.
.
.
COMM_ERR = 0 :
EE_READY = 1 :
no communication error detected on MOSI(N)-write command
the write delay was long enough to finish the write instruction
MISO_PAR = correct : the MISO(N+1)-frame has a correct odd parity bit
MISO_DATA(N+1) = MOSI_DATA(N) : the correct data was used for the write instruction
Verification Step2: EE_RDAW1 using the MISO(N+2)-frame
.
.
.
.
COMM_ERR = 0 :
EE_READY = 1 :
no communication error detected on MOSI(N+2)-RDAW1 command
the read delay was long enough to finish the read instruction
MISO_PAR = correct : the MISO(N+2)-frame has a correct odd parity bit
MISO_DATA(N+2) = MOSI_DATA(N) : the correct data is written
Verification Step3: EE_RDAW2 using the MISO(N+3)-frame
.
.
.
.
COMM_ERR = 0 :
EE_READY = 1 :
no communication error detected on MOSI(N+3)-RDAW2 command
the read delay was long enough to finish the read instruction
MISO_PAR = correct : the MISO(N+3)-frame has a correct odd parity bit
MISO_DATA(N+3) = MOSI_DATA(N) : the correct data is written
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
13. ESD Protection
VBATF
VSUP
CP
VBOOST
VREG
VDD
Supply ESD Connections
55V
18.5V
8V
AGND
55V
DGND
DGND
DGND
DGND
DGND
DGND
Gate Driver ESD Connections
Digital IO ESD Connections
CPx
VREG
VDD
VDD
VDD
55V
18.5V
GATETx
GATEBx
FETBx
FETTx
ICOM
EN
PHASEx
18.5V
10V
DGND
DGND
DGND
DGND
DGND
DGND
DGND
VDD
VDD
Current Sense Amplifier ESD Connections
VDD
IBP
ISENSE
OPA
IBM
OCIN
VREF
9V
DGND
DGND
DGND
DGND
Figure 13-1 Principle Schematic highlighting ESD Connections
Note:
All pins are referenced to the driver ground DGND as depicted in the picture above, but only for the ESD
protection.
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
14. Package Information
14.1. Package Marking
Product name: MLX83100
Lot number: ZZZZZZZZ
Date code: YYWW
format free
year and week
MLX83100
ZZZZZZZZ
YYWW
Figure 14-1 Package marking
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
14.2. Package Data
A
A1
A2
D
E
H
e
L
b
c
α
P
P1
2.9
3.0
3.1
Min
0.05
0.85
0.90
0.95
9.70 4.30
9.80 4.40
9.90 4.50
0.50 0.19 0.09
0°
5.4
5.5
5.6
6.4
0.65
Nom.
B.S.C. B.S.C.
Max. 1.10
0.15
0.75 0.30 0.20
8°
Table 14-1 Mechanical dimensions
Figure 14-2 Package drawing
REVISION 5.1 –DECEMBER 13, 2016
Page 38 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
15. Standard information regarding manufacturability
of Melexis products with different soldering processes
Our products are classified and qualified regarding soldering technology, solderability and moisture
sensitivity level according to following test methods:
Reflow Soldering SMD’s (Surface Mount Devices)
IPC/JEDEC J-STD-020: Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface
Mount Devices (classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113: Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability
Testing (reflow profiles according to table 2)
Wave Soldering SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EN60749-20: Resistance of plastic- encapsulated SMD’s to combined effect of moisture and soldering
heat
EIA/JEDEC JESD22-B106 and EN60749-15: Resistance to soldering temperature for through-hole
mounted devices
Iron Soldering THD’s (Through Hole Devices)
EN60749-15: Resistance to soldering temperature for through-hole mounted devices
Solderability SMD’s (Surface Mount Devices) and THD’s (Through Hole Devices)
EIA/JEDEC JESD22-B102 and EN60749-21: Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after
consulting Melexis regarding assurance of adhesive strength between device and board.
Melexis recommends reviewing on our web site the General Guidelines soldering recommendation
(http://www.melexis.com/Quality_soldering.aspx)
as
well
as
trim&form
recommendations
(http://www.melexis.com/Assets/Trim-and-form-recommendations-5565.aspx).
Melexis is contributing to global environmental conservation by promoting lead free solutions. For more
information on qualifications of RoHS compliant products (RoHS = European directive on the Restriction Of
the use of certain Hazardous Substances) please visit the quality page on our website:
http://www.melexis.com/quality.aspx
16. ESD Precautions
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro
Static Discharge control procedures whenever handling semiconductor products.
REVISION 5.1 –DECEMBER 13, 2016
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MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
17. Revision History
Revision
Date
Description
1.0
01-02-12 . Initial Draft version
. First draft
1.0
1.1
21-12-12
21-12-12
. Driver related parameters updated
. Protection and diagnostic functions updated
. Trickle Charge Pump included
1.2
15-01-13
. First Release
2.0
2.1
2.2
26-02-13
06-05-13
04-12-13
. Max voltage on phase pins updated
. Entering SPI mode by disabling all 6x FET input signals
. Abs. max. rating updated
. Block diagram and application diagrams updated
. Exposed pad size confirmed
2.3
01-03-14
. Qualification for TA = 150°C
. Changed ICOM duty cycle for VDS_ERR from 5.5% to 82.5%
. General update according to new template
3.0
3.1
4.0
09-05-14
24-07-14
31-07-14
. Drain-source monitor blanking
. Trickle charge pump current capability
. Largest dead time value
. ICOM pull-up current
. Performance graphs added
. Electrical specifications updated
. Operating current from VSUP (with PWM operation)
. VSUP under and over voltage hysteresis
. Internal leakage from VBATF to GND
4.2
20-11-15
. VDD operating current
. Drivers resistance for MLX83202
. Discharge currents for VBOOST and VCPx specified in case of VSUP_OVH
. “Data in hold time” and “Data out ready delay” units corrected to ns
4.3
4.4
17-03-16
31-08-16
. Default EEPROM configuration corrected for PWM_SPEED & EN_TCP
. Minimum specification on input PWM frequency removed
. Drain-source voltage monitoring description updated with pin-description
. New Melexis template
5.0
5.1
01-09-16
13-12-16
. MLX83100 Qualified for TJ = 175˚C
Table 17-1 Revision history
REVISION 5.1 –DECEMBER 13, 2016
Page 40 of 41
MLX83100 Automotive 2-Phase DC Pre-Driver
Datasheet
18. Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term
of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set
forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the
right to change specifications and prices at any time and without notice. Therefore, prior to designing this product
into a system, it is necessary to check with Melexis for current information. This product is intended for use in
normal commercial applications. Applications requiring extended temperature range, unusual environmental
requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment
are specifically not recommended without additional processing by Melexis for each application. The information
furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or
any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss
of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection
with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to
recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services.
© 2016 Melexis NV. All rights reserved.
www.melexis.com
REVISION 5.1 –DECEMBER 13, 2016
Page 41 of 41
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