EDI88512CA15KC [MERCURY]
Standard SRAM, 512KX8, 15ns, CMOS, CDSO36, CERAMIC, LCC-36;
| 型号： | EDI88512CA15KC |
| 厂家： | 
MERCURY UNITED ELECTRONICS INC |
| 描述： | Standard SRAM, 512KX8, 15ns, CMOS, CDSO36, CERAMIC, LCC-36 CD 静态存储器 |
| 文件： | 总10页 (文件大小：1121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Data Retention Function (LPA version)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard
for the four megabit device. All 32 pin packages are pin for pin
upgrades for the single chip enable 128K x 8, the EDI88128CS.
Pins 1 and 30 become the higher order addresses.
Organized as 512Kx8
The 36 pin revolutionary pinout also adheres to the JEDEC
standard for the four megabit device. The center pin power and
ground pins help to reduce noise in high performance systems.
The 36 pin pinout also allows the user an upgrade path to the
future 2Mx8.
Commercial, Industrial and Military Temperature Ranges
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
A Low Power version with Data Retention (EDI88512LPA) is
also available for battery backed applications. Military product is
available compliant to Appendix A of MIL-PRF-38535.
36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
*This product is subject to change without notice.
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
Single +5V (±10%) Supply Operation
FIGURE 1 – PIN CONFIGURATION
PIN DESCRIPTION
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
I/O0-7
A0-18
WE#
CS#
OE#
VCC
VSS
Output Enable
Power (+5V ±10%)
Ground
36 PIN
32 PIN
TOP VIEW
TOP VIEW
NC
Not Connected
1
2
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE#
30 I/O7
29 I/O6
32 Vcc
31 A15
30 A17
29 WE#
28 A13
27 A8
A0
A1
A18
A16
A14
A12
A7
1
2
3
A2
3
4
A3
4
BLOCK DIAGRAM
5
A4
5
6
CS#
I/O0
I/O1
Vcc
Vss
I/O2
I/O3
WE#
A5
A6
6
26 A9
7
A5
7
32 pin
Evolutionary
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
8
8
A4
36 pin
Revolutionary
Memory Array
9
Vss
Vcc
I/O5
I/O4
A14
A13
A12
A11
A10
NC
28
27
26
25
24
23
22
21
20
19
9
A3
10
11
12
13
14
15
16
17
18
10
11
12
13
14
A2
A1
A0
Address
Buffer
Address
Decoder
I/O
Circuits
A
0-18
I/O0-7
I/O0
I/O1
A6
I/O2 15
A7
Vss
16
WE#
CS#
OE#
A8
A9
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
OE#
X
H
L
X
CS#
H
L
L
L
WE#
X
H
H
L
Mode
Standby
Output Deselect
Read
Output
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc1
Icc1
Icc1
Parameter
Value
Unit
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient)
Commercial
-0.5 to 7.0
V
Write
°C
°C
°C
°C
W
0 TA +70
-40 TA +85
-55 TA +125
-65 TA +150
1.5
Industrial
Military
RECOMMENDED OPERATING CONDITIONS
Storage Temperature, Plastic
Power Dissipation
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
VSS
VIH
VIL
4.5
0
5.0
0
5.5
0
V
V
V
V
Output Current
20
mA
°C
Supply Voltage
Junction Temperature, TJ
NOTE:
175
Input High Voltage
Input Low Voltage
2.2
-0.3
—
—
VCC + 0.3
+0.8
Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(TA = +25°C)
Parameter
Address Lines
Data Lines
Symbol
Condition
Max
Unit
CI
VIN = Vcc or Vss, f = 1.0MHz
VOUT = Vcc or Vss, f = 1.0MHz
12
14
pF
pF
CO
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
(VCC = 5V, TA = -55°C to +125°C)
Parameter
Symbol
ILI
Conditions
Min
-10
-10
Max
10
Units
μA
Input Leakage Current
Output Leakage Current
VIN = 0V to VCC
ILO
VI/O = 0V to VCC
10
μA
WE#, CS# = VIL, II/O = 0mA, Min Cycle
(17ns)
—
—
250
225
mA
mA
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
ICC1
(20 -55ns)
ICC
2
CS# VIH, VIN VIL, VIN VIH
—
60
mA
CA
—
—
25
20
mA
mA
CS# VCC -0.2V
ICC
3
VIN Vcc -0.2V or VIN 0.2V
LPA
VOL
VOH
IOL = 6.0mA
IOH = -4.0mA
—
0.4
—
V
V
Output High Voltage
2.4
NOTE: DC test conditions: VIL = 0.3V, VIH = Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Figure 2
Vcc
Vcc
Input Pulse Levels
Input Rise and Fall Times
VSS to 3.0V
5ns
480Ω
480Ω
5pF
Input and Output Timing Levels
Output Load
1.5V
Q
Q
Figure 1
30pF
255Ω
255Ω
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2)
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C)
Symbol
JEDEC
15ns
17ns
20ns
25ns
35ns
45ns
55ns
Parameter
Alt.
tRC
Min Max
Min Max
Min Max
Min Max
Min Max
Min Max
Min Max Units
Read Cycle Time
tAVAV
tAVQV
tELQV
tELQX
15
15
15
2
17
17
17
3
20
20
20
3
25
25
25
3
35
35
35
3
45
45
45
3
55
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
tAA
55
55
tACS
tCLZ
3
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tCHZ
tOH
0
0
7
8
7
0
0
7
8
7
0
0
8
10
8
0
0
10
12
10
0
0
15
15
15
0
0
20
25
20
0
0
20
30
20
ns
ns
ns
ns
ns
tOE
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
tOLZ
tOHZ
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C)
Symbol
JEDEC
15ns
Min Max
15
17ns
Min Max
17
20ns
Min Max
20
25ns
Min Max
25
35ns
45ns
55ns
Min Max Units
Parameter
Alt.
Min Max
Min Max
Write Cycle Time
tAVAV
tWC
35
45
55
ns
tELWH
tELEH
tCW
tCW
13
13
14
14
15
15
17
17
25
25
30
30
50
50
ns
ns
Chip Enable to End of Write
Address Setup Time
tAVWL
tAVEL
tAS
tAS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
tAVWH
tAVEH
tAW
tAW
13
13
14
14
15
15
17
17
25
25
30
30
50
50
ns
ns
Address Valid to End of Write
Write Pulse Width
tWLWH
tWLEH
tWP
tWP
13
13
14
14
15
15
17
17
25
25
30
30
45
45
ns
ns
tWHAX
tEHAX
tWR
tWR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
Write Recovery Time
tWHDX
tEHDX
tDH
tDH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
tWLQZ
tWHZ
0
8
0
8
0
8
0
10
0
25
0
30
0
30
ns
tDVWH
tDVEH
tDW
tDW
8
8
8
8
10
10
12
12
20
20
25
25
40
30
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
0
0
0
0
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
FIGURE 2 – TIMING WAVEFORM – READ CYCLE
tAVAV
ADDRESS
tAVAV
tAVQV
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
CS#
tEHQZ
tELQV
tELQX
tAVQV
tAVQX
DATA 1
OE#
DATA 2
tGLQV
tGLQX
tGHQZ
DATA OUT
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE – WE# CONTROLLED
tAVAV
ADDRESS
tAVWH
tWHAX
tELWH
CS#
tAVWL
tWLWH
WE#
tDVWH
tWHDX
DATA IN
DATA VALID
tWLQZ
tWHQX
HIGH Z
DATA OUT
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE – CS# CONTROLLED
tAVAV
ADDRESS
tAVEH
tELEH
tEHAX
CS#
tAVEL
tWLEH
WE#
tDVEH
tEHDX
DATA IN
DATA VALID
HIGH Z
DATA OUT
WRITE CYCLE 2, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)
(-55°C ≤ TA ≤ +125°C)
Characteristic
Low Power Version only
Sym
Conditions
Min
Typ
Max
Units
Data Retention Voltage
Data Retention Quiescent Current
VCC
ICCDR
VCC = 2.0V
CS# VCC -0.2V
2
–
–
–
–
2
V
mA
Chip Disable to Data Retention Time
Operation Recovery Time
tCDR
TR
VIN VCC -0.2V
or VIN 0.2V
0
tAVAV
–
–
–
–
ns
ns
FIGURE 5 – DATA RETENTION – CS# CONTROLLED
DATA RETENTION MODE
4.5V
4.5V
VCC
CS#
VCC
tCDR
tR
CS# = VCC -0.2V
DATA RETENTION, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP, SMD 5962-95600XXMXA
1.616
1.584
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.200
0.125
0.155
0.115
0.600
NOM
0.020
0.016
0.100
TYP
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
ALL DIMENSIONS ARE IN INCHES
ALL DIMENSIONS ARE IN INCHES
PACKAGE 326: 32 LEAD SIDEBRAZED CERAMIC DIP
1.616
1.584
0.420
0.400
Pin 1 Indicator
1
1
0.200
0.125
0.155
0.400
0.020
0.016
0.100
TYP
0.115
NOM
0.061
0.017
15 x 0.100 = 1.500
PACKAGE 140: 32 LEAD CERAMIC SOJ, SMD 5962-95600XXMUA
0.010
0.006
0.019
0.015
0.840
0.820
0.050
TYP
0.444
0.430
0.379
0.155
0.106
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
6
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
PACKAGE 316: 36 PIN CERAMIC FLATPACK, SMD 5962-95600XXMTA
0.920 0.010
0.007
0.370
0.003
0.250
1.00 REF
0.395
0.385
0.515
0.505
0.040
0.030
Pin 1
0.045
0.020
0.019
0.015
0.125
0.100
0.050
TYP
ALL DIMENSIONS ARE IN INCHES
PACKAGE 321: 32 PIN THINPACK™ FLATPACK, SMD 5962-95600XXMYA
0.838
MAX
0.567
0.427
0.559
0.429
0.118
MAX.
0.020
0.030
0.008
0.005
0.050
TYP
0.016 0.008
ALL DIMENSIONS ARE IN INCHES
PACKAGE 344: 32 PIN CERAMIC FLATPACK, SMD 5962-95600XXM9A
0.423
0.004
+0.002
0.006 -0.001
0.024 REF.
0.112 MAX.
0.838 MAX.
0.050 0.002
TYP.
0.016
0.008
0.300
0.010
ALL DIMENSIONS ARE IN INCHES
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
7
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
PACKAGE 327: 36 LEAD CERAMIC SOJ, SMD 5962-95600XXMMA
0.010
0.006
0.019
0.015
0.920
0.940
0.050
TYP
0.444
0.434
0.155
0.379
0.106
ALL DIMENSIONS ARE IN INCHES
PACKAGE 502: 36 LEAD CERAMIC LCC
0.135
0.100
0.080
0.115
0.100
TYP
36
1
0.009 TYP
0.028
0.022
0.930
0.910
0.860
0.840
0.050
BSC
0.066
0.054
0.460
0.445
ALL DIMENSIONS ARE IN INCHES
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
8
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
ORDERING INFORMATION
EDI 8 8 512 CA X X X
MICROSEMI CORPORATION:
SRAM:
ORGANIZATION, 512Kx8:
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power
ACCESS TIME (ns):
PACKAGE TYPE:
C
K
N
T
= 32 lead Sidebrazed DIP, 600 mil (Package 9)
= 36 lead Ceramic LCC (Package 502)
= 32 lead Ceramic SOJ (Package 140)
= 32 lead Sidebrazed DIP, 400 mil (Package 326)
B32 = 32 pin Ceramic Thinpack™ Flatpack (Package 321)
F32 = 32 pin Ceramic Flatpack (Package 344)
F36 = 36 pin Ceramic Flatpack (Package 316)
N36 = 36 lead Ceramic SOJ (Package 327)
DEVICE GRADE:
B = Military Grade*
M = Military Screened -55°C ≤ TA ≤ +125°C
I = Industrial
-40°C ≤ TA ≤ +85°C
0°C ≤ TA ≤ +70°C
C = Commercial
*This product is processed the same as the 5962-XXXXXMXX product but all test and mechanical requirements are per the Microsemi data sheet.
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
9
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
EDI88512CA
Document Title
512Kx8 Monolithic SRAM, SMD 5962-95600
Revision History
Rev # History
Release Date Status
Rev 13
Changes (Pg. 1-10)
February 2011
Final
13.1 Change document layout from White Electronic Designs to Microsemi
13.2 Add document Revision History page
Rev 14
Rev 15
Changes (Pg. 2)
August 2012
May 2014
Final
Final
14.1 Change units on Input/Output Leakage to 10μA verses 10A
Change (Pg. 9)
15.1 Changed Device Grade “B” description from “MIL-STD-883 Compliant” to
“Military Grade*.”
Microsemi Corporation reserves the right to change products or specifications without notice.
May 2014 © 2014 Microsemi Corporation. All rights reserved.
Rev. 15
10
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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