W3H128M72E2-667SBM [MERCURY]
DDR DRAM, 128MX72, 1.25ns, CMOS, PBGA208, BGA-208;型号: | W3H128M72E2-667SBM |
厂家: | MERCURY UNITED ELECTRONICS INC |
描述: | DDR DRAM, 128MX72, 1.25ns, CMOS, PBGA208, BGA-208 动态存储器 双倍数据速率 |
文件: | 总31页 (文件大小:1030K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1GB – 128M x 72 DDR2 SDRAM
208 PBGA Multi-Chip Package
W3H128M72E-XSBX / W3H128M72E-XNBX
BENEFITS
FEATURES
56% space savings vs. FBGA
Data rate = 667, 533, 400
Reduced part count
Package:
50% I/O reduction vs FBGA
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm
• 1.0mm pitch
Core Supply Voltage = 1.8V
I/O Supply Voltage = 1.8V - (SSTL_18 compatible)
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
* This product is subject to change without notice.
TYPICAL APPLICATION
DLL for alignment of DQ and DQS transitions with clock
signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
RAM
DDR2 / DDR3
Host
W3H128M72E-XSBX / -XNBX
FPGA/
Adjustable data – output drive strength
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
CK/CK# Termination options available
• 0 ohm, 20 ohm
Processor
SSD (SLC)
MSM032 / MSM064 (SATA BGA)
W7N16GVHxxBI (PATA BGA)
MSD1TB / 512 / 256 / 128 (SATA, 2.5i)
Write latency = Read latency - 1* tCK
Commercial, Industrial and Military Temperature Ranges
Organized as 128M x 72
Weight: W3H128M72E-XSBX - 4 grams max
Weight: W3H128M72E-XNBX - TBD
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
W3H128M72E-XXXX
S
A
V
I
N
G
S
11.5
11.5
11.5
11.5
11.5
22
84
FBGA
84
FBGA
84
FBGA
84
FBGA
84
FBGA
14.0
W3H128M72E-XXXX
16
Area
5 x 161mm2 = 805mm2
5 x 84 balls = 420 balls
352mm2
56%
50%
I/O Count
208 Balls
1
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4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CS#
WE#
RAS#
CAS#
CKE
CS# WE# RAS# CAS# CKE
ODT
A0-13
BA0-2
ODT
A0-13
BA0-2
DQ0
DQ0
CK0
CK0#
CK
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
CK#
LDM0
LDM
U0
UDM0
UDM
LDQS0
LDQS0#
UDQS0
UDQS0#
LDQS
LDQS#
UDQS
UDQS#
¥
DQ15
DQ15
CS# WE# RAS# CAS# CKE
ODT
A0-13
BA0-2
CK
DQ0
¥
¥
¥
DQ16
¥
¥
¥
CK1
CK1#
CK#
LDM1
LDM
U1
¥
¥
¥
¥
¥
¥
UDM1
UDM
LDQS1
LDQS1#
UDQS1
UDQS1#
LDQS
LDQS#
UDQS
UDQS#
DQ15
DQ31
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
¥
¥
¥
¥
¥
DQ32
¥
¥
¥
¥
¥
BA0-2
CK2
CK2#
CK
CK#
U2
LDM2
LDM
UDM2
UDM
LDQS2
LDQS2#
UDQS2
UDQS2#
LDQS
LDQS#
UDQS
UDQS#
¥
¥
DQ15
DQ47
CS# WE# RAS# CAS# CKE
ODT
A0-13
DQ0
¥
¥
¥
DQ48
¥
¥
¥
BA0-2
CK3
CK3#
CK
CK#
LDM3
LDM
U3
¥
¥
¥
¥
¥
¥
UDM3
UDM
LDQS3
LDQS3#
UDQS3
UDQS3#
LDQS
LDQS#
UDQS
UDQS#
DQ15
DQ63
CS# WE# RAS# CAS# CKE
ODT
A0-13
BA0-2
DQ0
DQ64
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
CK4
CK4#
CK
CK#
LDM4
LDM
U4
VCC
UDM
LDQS4
LDQS4#
UDQS4
UDQS4#
LDQS
LDQS#
UDQS
UDQS#
¥
DQ7
DQ71
NOTE: Connect UDQS4 to ground via a resistor and UDQS4#
to VCC via a resistor. UDM4 is internally tied to VCC
.
2
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W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 3 – PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
7
8 9 10 11
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
A
B
C
D
E
F
A
B
C
D
E
F
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
VSS
VCC
VSS
DQ35
DQ52
LDM3
DQ38
UDM3
VCC
NC
NC
NC
NC
NC
NC
DQ34
DQ53
CK3
DQ37
CK3#
CK2#
VSS
DQ51
DQ36
LDM2
DQ54
DQ44
A6
NC
NC
NC
NC
DQ50
CK2
DQ32
DQ33
DQ49
DQ60
DQ41
A10
NC
BA2
DQ59
DNU
DNU
VSS
VCC
VSS
VREF
VSS
VCC
VSS
ODT
DQ39 LDQS2 LDQS3 DQ48
DQ43
DQ55
DQ63
DQ58
DQ56
DQ42 LDQS2# LDQS3#
DQ57 UDM2
DQ40
DQ61
DQ45
G
H
J
G
H
J
DQ46
A9
DQ62
VCC
UDQS2# DQ47 UDQS2 UDQS3 UDQS3#
VCC
VSS
A3
A12
A1
A13
BA1
VCC
VSS
VSS
A0
A11
VCC
VSS
VCC
K
L
K
L
VCC
A2
A4
A8
VCC
VCC
BA0
A5
A7
VCC
UDQS1# UDQS1
UDQS0
DQ8
DQ10
DQ15
DQ24
DQ26
UDQS0#
DQ31
DQ23
DQ7
DQ18
RAS#
CS#
DQ30
UDM0
DQ27
DQ14
DQ25
DQ11
DQ9
DQ28
DQ17
DQ1
DQ12
DQ22
LDM0
DQ4
DQ19
DQ68
VSS
UDM1
DQ6
LDM1
DQ20
DQ3
M
N
P
R
T
M
N
P
R
T
DQ13
DQ29
LDQS1# LDQS0#
DQ0
CK0
VSS
DQ16 LDQS1 LDQS0
LDQS4# UDQS4 UDQS4#
CK0#
CK1#
VSS
DQ5
CK1
CK4#
VSS
DQ21
DQ2
CK4
VCC
LDQS4
CAS#
DQ66
VSS
DQ71
DQ64
DQ69
Vcc
CKE
DQ70
LDM4
VCC
WE#
DQ65
DQ67
VSS
VSS
U
V
W
U
V
W
VCC
VSS
VCC
VCC
VCC
VCC
VSS
1
2
3
4
5
6
7
8 9 10 11
NOTE: Connect UDQS4 to ground via a resistor and UDQS4# to VCC via a resistor.
UDM4 is internally tied to VCC
Balls F6 and E6 are reserved for A14 and A15 on future densities.
3
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W3H128M72E-XSBX / W3H128M72E-XNBX
TABLE 1 – BALL DESCRIPTIONS
Symbol
Type
Description
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#. The ODT input will be ignored if
disabled via the LOAD MODE command.
ODT
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
CK, CK#
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
PRECHARGE power-down mode and SELF-REFRESH action (all banks idle), or ACTIVE power-down (row active in any bank). CKE
is synchronous for power-down entry, Power-down exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMO SLOW level once VCC is applied during first power-up. After VREF has
become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For
proper SELF-REFRESH operation, VREF must be maintained.
CKE
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when
CS# is registered HIGH.
CS#
Input
Input
RAS#, CAS#, WE#
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for upper byte DQ8–DQ15, of each of U0-U4
LDM, UDM
BA0–BA2
Input
Input
Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0–
BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10
HIGH) The address inputs also provide the op-code during a LOAD MODE command.
A0-A13
Input
DQ0-71
I/O
I/O
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. UDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
UDQS, UDQS#
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. LDQS# is only used when differential data strobe mode is enabled via the LOAD MODE
command.
LDQS, LDQS#
I/O
VCC
VREF
VSS
Supply
Power Supply: I/O + core, VCCQ is common to VCC
SSTL_18 reference voltage.
Supply
Supply
Ground
NC
-
-
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities.
DNU
4
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W3H128M72E-XSBX / W3H128M72E-XNBX
DESCRIPTION
GENERAL NOTES
The 8Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-
access memory containing five 2Gb 2,147,483,648 bits chips. Each
of the five chips in the MCP are internally configured as 8-bank
DRAM. The block diagram of the device is shown in Figure 2. Ball
assignments are shown in Figure 3.
The functionality and the timing specifications discussed in this
data sheet are for the DLL-enabled mode of operation.
Throughout the data sheet, the various figures and text refer to
DQs as “DQ.” The DQ term is to be interpreted as any and all
DQ collectively, unless specifically stated otherwise. Additionally,
each chip is divided into 2 bytes, the lower byte and upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS
refers to LDQS. For the upper byte (DQ8–DQ15), DM refers to
UDM and DQS refers to UDQS. Note that the there is no upper
byte for U4 and therefore no UDM4.
The 8Gb DDR2 SDRAM uses a double-data-rate architecture to
achieve high-speed operation. The double data rate architecture is
essentially a 4n-prefetch architecture, with an interface designed
to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 8Gb DDR2 SDRAM effectively consists
of a single 4n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and four corresponding n-bit-wide, one-half-clock-cycle
data transfers at the I/O balls.
Complete functionality is described throughout the document
and any page or diagram may have been simplified to convey a
topic and may not be inclusive of all requirements.
A bidirectional data strobe (DQS, DQS#) is transmitted externally,
along with data, for use in data capture at the receiver. DQS is a
strobe transmitted by the DDR2 SDRAM during READs and by the
memory controller during WRITEs. DQS is edge-aligned with data
for READs and center-aligned with data for WRITEs. Two strobes
per chip, one for the lower byte (LDQS, LDQS#) and one for the
upper byte (UDQS, UDQS#).
Any specific requirement takes precedence over a general
statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. The following
sequence is required for power up and initialization and is
shown in Figure 4 on page 6.
The 8Gb DDR2 SDRAM operates from a differential clock (CK and
CK#); the crossing of CK going HIGH and CK# going LOW will
be referred to as the positive edge of CK. Commands (address
and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of anACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered coincident
with the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write
burst lengths of four or eight locations. DDR2 SDRAM supports
interrupting a burst read of eight with another read, or a burst
write of eight with another write. An auto precharge function may
be enabled to provide a self-timed row precharge that is initiated
at the end of the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent operation,
thereby providing high, effective bandwidth by hiding row precharge
and activation time.
Aself refresh mode is provided, along with a power-saving power-
down mode.
All inputs are compatible with the JEDEC standard for SSTL_18.
All full drive-strength outputs are SSTL_18-compatible.
5
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W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 4 – POWER-UP AND INITIALIZATION
VCC
VCCL
VCCQ
1
tVTD
1
VTT
VREF
Tk0
Tl0
Tm0
Tg0
Th0
Ti0
Tj0
Te0
Tf0
Tb0
Tc0
Td0
T0
Ta0
tCK
CK#
CK
tCL
tCL
LVCMOS
SSTL_18
low level2
CKE low level2
ODT
LM11
LM12
LM13
Valid14
LM5
LM6
LM7
LM8
PRE9
REF10
REF10
NOP3
Command
PRE
DM15
Address16
Code
Code
Code
A10 = 1
Code
Code
Code
Code
A10 = 1
Valid
High-Z
DQS15
DQ15
High-Z
High-Z
RTT
T = 400ns (MIN)4
T = 200μs (MIN)3
tRPA
tMRD
tMRD
tMRD
tMRD
tRPA
tRFC
tRFC
tMRD
tMRD
tMRD
See note 10
Power-up:
VCC and stable
clock (CK, CK#)
EMR(2)
EMR(3)
EMR
MR without
EMR with
EMR with
OCD exit
DLL RESET OCD default
Indicates a Break in
Time Scale
200 cycles of CK are required before a READ command can be issued
Don’t care
Normal
operation
MR with
DLL RESET
NOTES:
1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled. To guarantee
TT (ODT resistance) is off, VREF must be valid and a low level must be applied to the ODT ball
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide LOW
to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropriate self refresh
rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2 (EMR2) for all EMR(2)
requirements).
R
(all other inputs may be undefined, I/Os and outputs must be less than VCCQ during voltage ramp
time to avoid DDR2 SDRAM device latch-up). At least one of the following two sets of conditions
(A or B) must be met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF
,
and VTT are between their minimum and maximum values as stated in DC Operating Conditions
table):
A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must take no longer
than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V. Once supply voltage ramping
is complete (when VCCQ crosses VCC (MIN), DC Operating Conditions table specifications
apply.
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide HIGH
to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3 (EMR3) for all
EMR(3) requirements.
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set to “0” or
“1;” It is recommended setting them to “0;” remaining EMR bits must be “0.” Extended Mode
Register (EMR) for all EMR requirements.
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is required
to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0;
CKE must be HIGH the entire time the DLL is resetting; remaining MR bits must be “0.” Mode
Register (MR) for all MR requirements.
•
•
•
V
V
V
CC, VCCQ are driven from a single power converter output
TT is limited to 0.95V MAX
REF tracks VCCQ/2; VREF must be within ±0.3V with respect to VCCQ/2 during supply ramp
time.
VCCQ ≥ VREF at all times
•
B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage ramping,
9. Issue PRECHARGE ALL command.
for both AC and DC levels, until supply voltage ramping completes (VCCQ crosses
10. Issue two or more REFRESH commands.
V
CC [MIN]). Once supply voltage ramping is complete, DC Operating Conditions table
11. Issue a LOAD MODE command to the MR with LOW to A8 to initialize device operation (that
is, to program operating parameters without resetting the DLL). To access the MR, set BA0 and
BA1 LOW; remaining MR bits must be set to desired settings. Mode Register (MR) for all MR
requirements.
specifications apply.
• Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must be ≤ 200ms
from when VCC ramps from 300mV to VCC (MIN)
• Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time from when
12. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the EMR, set BA0 HIGH and
BA1 LOW (see Extended Mode Register (EMR) for all EMR requirements.
13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9 to
“0,” and then setting all other desired parameters. To access the extended mode registers, EMR,
set BA0 HIGH and BA1 LOW for all EMR requirements.
14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after the
DLL RESET at Tf0.
15. DM represents UDM and LDM; DQS represents UDQS, UDQS#, LDQS and LDQS#. DQ
represents DQ[71:0].
VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤ 500ms; while VCC is
ramping, current can be supplied from VCC through the device to VCCQ
VREF must track VCCQ/2, VREF must be within ±0.3V with respect to VCCQ/2 during supply
ramp time; VCCQ ≥ VREF must be met at all times
•
• Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to when VTT (MIN)
is achieved must be no greater than 500ms
2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device power-
up prior to VREF. being stable. After state T0, CKE is required to have SSTL_18 input levels.
Once CKE transitions to a high level, it must stay HIGH for the duration on the initialization
sequence.
3. For a minimum of 200μs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
16. A10 = PRECHARGE ALL, CODE = desired values for mode registers (bank addresses are
required to be decoded).
6
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W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
The mode register is used to define the specific mode of operation
of the DDR2 SDRAM. This definition includes the selection of a
burst length, burst type, CAS latency, operating mode, DLLRESET,
write recovery, and power-down mode, as shown in Figure 5.
Contents of the mode register can be altered by re-executing the
LOAD MODE (LM) command. If the user chooses to modify only
a subset of the MR variables, all variables must be programmed
when the command is issued.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
16 15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
8
Mode Register (Mx)
0
MR
0
PD
WR
DLL TM CAS# Latency BT Burst Length
Mode
Normal
Test
M7
0
M2 M1 M0
Burst Length
Reserved
Reserved
4
The mode register is programmed via the LM command will
retain the stored information until it is programmed again or the
device loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the contents of
the memory array, provided it is performed correctly.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode
Fast Exit
(Normal)
Slow Exit
M12
0
DLL Reset
No
M8
0
8
1
Reserved
Reserved
Reserved
Reserved
1
Yes
(Low Power)
The LM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts are in
progress. The controller must wait the specified time tMRD before
initiating any subsequent operations such as anACTIVE command.
Violating either of these requirements will result in unspecified
operation.
WRITE RECOVERY
M11 M10 M9
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
Burst Type
Sequential
Interleaved
M3
0
1
BURST LENGTH
CAS Latency (CL)
M6 M5 M4
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst length is defined by bits M0–M2, as shown in Figure 5. Read
and write accesses to the DDR2 SDRAM are burst-oriented, with
the burst length being programmable to either four or eight. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
Reserved
Reserved
Mode Register Definition
Mode Register (MR)
M15 M14
3
4
5
6
7
0
1
0
1
0
0
1
1
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for
that burst take place within this block, meaning that the burst
will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL =
8 (where Ai is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s)
is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
NOTE: Not all listed CL options are supported in any individual speed grades.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved. The burst type is selected via bit M3,
as shown in Figure 5. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting
column address, as shown in Table 2. DDR2 SDRAM supports
4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode,
full interleaved address ordering is supported; however, sequential
address ordering is nibble-based.
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WR values of 2, 3, 4, 5, 6, 7 or 8 clocks may be used for
programming bits M9–M11. The user is required to program the
value of WR, which is calculated by dividing tWR (in ns) by tCK (in
ns) and rounding up a non integer value to the next integer; WR
[cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used
as unknown operation or incompatibility with future versions may
result.
TABLE 2 – BURST DEFINITION
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Burst
Length
Starting Column
Address
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
0
1
1
0
POWER-DOWN MODE
1
1
Active power-down (PD) mode is defined by bit M12, as shown
in Figure 5. PD mode allows the user to determine the active
power-down mode, which determines performance versus power
savings. PD mode bit M12 does not apply to precharge PD mode.
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-0-5-6-7-4
2-3-0-1-6-7-4-5
3-0-1-2-7-4-5-6
4-5-6-7-0-1-2-3
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
0
0
1
0
1
0
When bit M12 = 0, standard active PD mode or “fast-exit” active PD
mode is enabled. The tXARD parameter is used for fast-exit active
PD exit timing. The DLL is expected to be enabled and running
during this mode.
8
0
1
1
1
0
0
1
0
1
5-6-7-4-1-2-3-0
5-4-7-6-1-0-3-2
When bit M12 = 1, a lower-power active PD mode or “slow-exit”
active PD mode is enabled. The tXARDS parameter is used for slow-
exit active PD exit timing. The DLL can be enabled, but “frozen”
during active PD mode because the exit-to-READ command timing
is relaxed. The power difference expected between PD normal and
PD low-power mode is defined in the ICC table.
1
1
0
6-7-4-5-2-3-0-1
6-7-4-5-2-3-0-1
1
1
1
7-4-5-6-3-0-1-2
7-6-5-4-3-2-1-0
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the starting column
within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the starting column
within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the starting
column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
OPERATING MODE
The normal operating mode is selected by issuing a command
with bit M7 set to “0,” and all other bits set to the desired values,
as shown in Figure 5. When bit M7 is “1,” no other bits of the
mode register are programmed. Programming bit M7 to “1” places
the DDR2 SDRAM into a test mode that is only used by the
manufacturer and should not be used. No operation or functionality
is guaranteed if M7 bit is ‘1.’
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DLL RESET function.
Bit M8 is self-clearing, meaning it returns back to a value of “0”
after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must
occur before a READ command can be issued to allow time for the
internal clock to be synchronized with the external clock. Failing
to wait for synchronization to occur may result in a violation of the
t
AC or tDQSCK parameters.
WRITE RECOVERY
Write recovery (WR) time is defined by bits M9–M11, as shown in
Figure 5. The WR register is used by the DDR2 SDRAM during
WRITE with auto precharge operation. During WRITE with auto
precharge operation, the DDR2 SDRAM delays the internal auto
precharge operation by WR clocks (programmed in bits M9–M11)
from the last data burst.
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CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure
5. CL is the delay, in clock cycles, between the registration of a
READ command and the availability of the first bit of output data.
The CL can be set to 4, 5, 6 or 7 clocks, depending on the speed
grade option being used.
DDR2 SDRAM also supports a feature called posted CAS additive
latency (AL). This feature allows the READ command to be issued
prior to tRCD (MIN) by delaying the internal command to the DDR2
SDRAM by AL clocks.
An example of CL = 4 is shown in Figure 6; assume AL = 0. If a
READ command is registered at clock edge n, and the CL is m
clocks, the data will be available nominally coincident with clock
edge n+m (this assumes AL = 0).
DDR2 SDRAM does not support any half-clock latencies. Reserved
states should not be used as unknown operation or incompatibility
with future versions may result.
FIGURE 6 – CAS LATENCY (CL)
T0
T1
T2
T3
T4
T5
T6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUT
D
OUT
D
OUT
DOUT
n + 3
DQ
n
n + 1
n + 2
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal tAC, tDQSCK and tDQSQ
TRANSITIONING DATA
DON’T CARE
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EXTENDED MODE REGISTER (EMR)
The extended mode register controls functions beyond those
controlled by the mode register; these additional functions are DLL
enable/disable, output drive strength, on die termination (ODT),
posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/
enable. These functions are controlled via the bits shown in Figure
7. The EMR is programmed via the LOAD MODE (LM) command
and will retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will not alter
the contents of the memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts
are in progress, and the controller must wait the specified time
tMRD before initiating any subsequent operation. Violating either
of these requirements could result in an unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA2 BA1 BA0A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL
out
0
MRS
0
E0
DLL Enable
E12 Outputs
E6 E2 RTT (nominal)
0
1
0
1
Enabled
Disabled
Enable (Normal)
R
TT disabled
75Ω
0
0
1
1
0
1
0
1
Disable (Test/Debug)
E11 RDQS Enable
E1
Output Drive Strength
Full strength (18Ω target)
150Ω
0
1
No
50Ω
0
1
Yes
Reduced strength (40Ω target)
E10 DQS# Enable
E5 E4 E3 Posted CAS# Additive Latency (AL)
0
1
Enable
Disable
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
E9 E8 E7 OCD Operation1
3
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD exit
Reserved
Reserved
Reserved
4
5
6
Reserved
Enable OCD defaults
E15 E14
Mode Register Set
Mode register set (MRS)
0
1
0
1
0
0
1
1
Extended mode register (EMR)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
NOTES:
1.
During initialization, all three bits must be set to "1" for OCD default state, then must be set to "0" before
initialization is finished.
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“sw1,” which enables all R1 values that are 150Ω each, enabling
an effective resistance of 75Ω (RTT2(EFF) = R2/2). Similarly, if “sw2”
is enabled, all R2 values that are 300Ω each, enable an effective
ODT resistance of 150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables
R1 values of 100Ω enabling effective resistance of 50Ω.
DLL ENABLE/DISABLE
The DLL may be enabled or disabled by programming bit E0
during the LM command, as shown in Figure 7. The DLL must
be enabled for normal operation. DLL enable is required during
power-up initialization and upon returning to normal operation after
having disabled the DLLfor the purpose of debugging or evaluation.
Enabling the DLL should always be followed by resetting the DLL
using an LM command.
The ODT control ball is used to determine when RTT(EFF) is turned
on and off, assuming ODT has been enabled via bits E2 and E6 of
the EMR. The ODT feature and ODT input ball are only used during
active, active power-down (both fast-exit and slow-exit modes),
and precharge power-down modes of operation. ODT must be
turned off prior to entering self refresh mode. During power-up and
initialization of the DDR2 SDRAM, ODT should be disabled until
issuing the EMR command to enable the ODT feature, at which
point the ODT ball will determine the RTT(EFF) value. Anytime the
EMR enables the ODT function, ODT may not be driven HIGH until
eight clocks after the EMR has been enabled. See “ODT Timing”
section for ODT timing diagrams.
The DLL is automatically disabled when entering SELF REFRESH
operation and is automatically re-enabled and reset upon exit of
SELF REFRESH operation.
Any time the DLL is enabled (and subsequently reset), 200 clock
cycles must occur before a READ command can be issued, to
allow time for the internal clock to synchronize with the external
clock. Failing to wait for synchronization to occur may result in a
violation of the tAC or tDQSCK parameters.
OUTPUT DRIVE STRENGTH
OFF-CHIP DRIVER (OCD) IMPEDANCE
CALIBRATION
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC
feature not supported and thereby must be set to the default state.
Enabling OCD beyond the default settings will alter the I/O drive
characteristics and the timing and output I/O specifications will no
longer be valid.
The output drive strength is defined by bit E1, as shown in Figure
7. The normal drive strength for all outputs is specified to be
SSTL_18. Programming bit E1 = 0 selects normal (full strength)
drive strength for all outputs. Selecting a reduced drive strength
option (E1 = 1) will reduce all outputs to approximately 45 to 60
percent of the SSTL_18 drive strength. This option is intended
for the support of lighter load and/or point-to-point environments.
DQS# ENABLE/DISABLE
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the
complement of the differential data strobe pair DQS/DQS#. When
disabled (E10 = 1), DQS is used in a single ended mode and the
DQS# ball is disabled. When disabled, DQS# should be left floating;
however, it may be tied to ground via a resistor. This function is
also used to enable/disable RDQS#. If RDQS is enabled (E11 =
1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS#
will be enabled. RDQS is not available on this device.
OUTPUT ENABLE/DISABLE
The OUTPUT ENABLE function is defined by bit E12, as shown in
Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS, DQS#)
function normally. When disabled (E12 = 1), all DDR2 SDRAM
outputs (DQs, DQS, DQS#) are disabled, thus removing output
buffer current. The output disable feature is intended to be used
during ICC characterization of read current.
ON-DIE TERMINATION (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6
of the EMR, as shown in Figure 7. The ODT feature is designed
to improve signal integrity of the memory channel by allowing the
DDR2 SDRAM controller to independently turn on/off ODT for any
or all devices. RTT effective resistance values of 50Ω ,75Ω, and
150Ω are selectable and apply to each DQ, UDQS/UDQS#, LDQS/
LDQS#, and UDM/LDM signals. Bits (E6, E2) determine what ODT
resistance is enabled by turning on/off “sw1,” “sw2,” or “sw3.” The
ODT effective resistance value is selected by enabling switch
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POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AL) is supported to make the
command and data bus efficient for sustainable bandwidths in
DDR2 SDRAM. Bits E3–E5 define the value of AL, as shown in
Figure 7. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an AL of 0, 1, 2, 3, 4, 5 or 6 clocks. Reserved states should
not be used as unknown operation or incompatibility with future
versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE
command to be issued prior to tRCD (MIN) with the requirement
that AL ≤ tRCD (MIN). A typical application using this feature would
set AL = tRCD (MIN) - 1x tCK. The READ or WRITE command is
held for the time of the AL before it is issued internally to the
DDR2 SDRAM device. RL is controlled by the sum of AL and CL;
RL = AL+CL. Write latency (WL) is equal to RL minus one clock;
WL = AL + CL - 1 x tCK
.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA2
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
Extended mode
register (Ex)
16 15 14 13 12 11 10
9
0
8
0
7
SRT
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
MRS
0
0
0
0
E7
0
SRT Enable
1X refresh rate (+85°C max junction temp.)
1
2X refresh rate (+85°C to +95°C junction temp.)
E15 E14
Mode Register Set
Mode register (MR)
0
0
1
1
0
1
0
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
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is programmed again or the device loses power. Reprogramming
the EMR will not alter the contents of the memory array, provided
it is performed correctly.
EXTENDED MODE REGISTER 2
The extended mode register 2 (EMR2) controls functions beyond
those controlled by the mode register. Currently all bits in EMR2
are reserved except for E7, as shown in Figure 8. The EMR2
is programmed via the LM command and will retain the stored
information until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the memory
array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
COMMAND TRUTH TABLE
The following table provides a quick reference of DDR2 SDRAM
available commands, including CKE power-down modes, and
bank-to-bank commands.
Bit E7 (A7) must be programmed as"1" to provide a faster refresh
rate on devices if the junction temperature (TJ) exceeds 85°C but
doesn't exceed 95°C. Refer to operating junction temperature
limits in "DC operating conditions" table. Self refresh function is
not available for military grade devices.
EMR2 must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified time tMRD
before initiating any subsequent operation. Violating either of these
requirements could result in unspecified operation.
EXTENDED MODE REGISTER 3
The extended mode register 3 (EMR3) controls functions beyond
those controlled by the mode register. Currently, all bits in EMR3
are reserved, as shown in Figure 9. The EMR3 is programmed
via the LM command and will retain the stored information until it
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
BA2
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
Extended mode
register (Ex)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
0
1
0
0
MRS
0
0
0
0
0
0
0
0
0
0
0
0
0
E15 E14
Mode Register Set
Mode register (MR)
0
0
1
1
0
1
0
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
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TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
CKE
BA2
BA1
BA0
A13
A12
A11
Function
CS#
RAS#
CAS#
WE#
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
REFRESH
H
H
H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
X
H
L
L
L
L
L
L
H
H
X
H
L
BA
X
OP Code
2
X
X
X
X
X
X
SELF-REFRESH Entry
L
X
X
H
H
H
H
SELF-REFRESH Exit
L
H
X
X
X
X
7
2
Single bank precharge
All banks PRECHARGE
Bank activate
H
H
H
H
H
H
BA
X
X
X
L
H
X
X
L
H
BA
Row Address
Column
Address
Column
Address
WRITE
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
BA
BA
BA
BA
L
H
L
2, 3
2, 3
2, 3
2, 3
Column
Address
Column
Address
WRITE with auto precharge
READ
Column
Address
Column
Address
H
H
Column
Address
Column
Address
READ with auto precharge
H
NO OPERATION
H
H
X
X
L
H
H
L
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
X
X
X
X
X
X
Device DESELECT
POWER-DOWN entry
H
L
L
X
X
X
X
X
X
X
X
4
4
H
L
POWER-DOWN exit
H
NOTES:
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
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FIGURE 10 – ACTIVE COMMAND
DESELECT
The DESELECT function (CS# HIGH) prevents new commands
from being executed by the DDR2 SDRAM. The DDR2 SDRAM
is effectively deselected. Operations already in progress are not
affected. DESELECT is also referred to as COMMAND INHIBIT.
CK#
CK
NO OPERATION (NOP)
CKE
CS#
The NO OPERATION (NOP) command is used to instruct the
selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,
CAS#, and WE are HIGH). This prevents unwanted commands
from being registered during idle or wait states. Operations already
in progress are not affected.
RAS#
CAS#
WE#
LOAD MODE (LM)
The mode registers are loaded via inputs BA2–BA0, andA13–A0.
BA2–BA0 determine which mode register will be programmed.
See “Mode Register (MR)”. The LM command can only be issued
when all banks are idle, and a subsequent execute able command
cannot be issued until tMRD is met.
Row
ADDRESS
BANK ADDRESS
Bank
ACTIVATE COMMAND
The ACTIVATE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on the
BA2–BA0 inputs selects the bank, and the address inputs select
the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the
same bank.
DON’T CARE
ACTIVE OPERATION
A subsequent ACTIVATE command to a different row in the
same bank can only be issued after the previous active row has
been closed (precharged). The minimum time interval between
successive ACTIVATE commands to the same bank is defined
Before any READ or WRITE commands can be issued to a
bank within the DDR2 SDRAM, a row in that bank must be
opened (activated), even when additive latency is used. This is
accomplished via the ACTIVATE command, which selects both
the bank and the row to be activated.
by tRC
.
AsubsequentACTIVATE command to another bank can be issued
while the first bank is being accessed, which results in a reduction
of total row-access overhead. The minimum time interval between
successive ACTIVATE commands to different banks is defined by
After a row is opened with an ACTIVATE command, a READ or
WRITE command may be issued to that row, subject to the tRCD
specification. tRCD (MIN) should be divided by the clock period and
rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or
WRITE command can be entered. The same procedure is used
to convert other specification limits from time units to clock cycles.
For example, a tRCD (MIN) specification of 20ns with a 266 MHz clock
(tCK = 3.75ns) results in 5.3 clocks, rounded up to 6.
tRRD. This device has an additional requirement: tFAW. This requires
no more than four ACTIVATE commands may be issued in any
given tFAW (MIN) period.
15
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FIGURE 11 – READ COMMAND
READ COMMAND
The READ command is used to initiate a burst read access to an
active row. The value on the BA2–BA0 inputs selects the bank,
and the address provided on inputs A0–i (where i = A9) selects
the starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end
of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
CK#
CK
CKE
CS#
DDR2 SDRAM also supports theAL feature, which allows a READ
or WRITE command to be issued prior to tRCD (MIN) by delaying the
actual registration of the READ/WRITE command to the internal
device by AL clock cycles.
RAS#
CAS#
READ OPERATION
WE#
READ bursts are initiated with a READ command. The starting
column and bank addresses are provided with the READ
command, and auto precharge is either enabled or disabled for
that burst access. If auto precharge is enabled, the row being
accessed is automatically precharged at the completion of the
burst. If auto precharge is disabled, the row will be left open after
the completion of the burst.
ADDRESS
Col
ENABLE
A10
AUTO PRECHARGE
BANK ADDRESS
DISABLE
Bank
During READ bursts, the valid data-out element from the starting
column address will be available READ latency (RL) clocks later.
RL is defined as the sum of AL and CL; RL = AL + CL. The value
forAL and CL are programmable via the MR and EMR commands,
respectively. Each subsequent data-out element will be valid
nominally at the next positive or negative clock edge (at the next
crossing of CK and CK#).
DON’T CARE
DQS/DQS# is driven by the DDR2 SDRAM along with output data.
The initial LOW state on DQS and HIGH state on DQS# is known
as the read preamble (tRPRE). The LOW state on DQS and HIGH
state on DQS# coincident with the last data-out element is known
as the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have
been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with data from
a subsequent READ command to provide a continuous fl ow of
data. The first data element from the new burst follows the last
element of a completed burst. The new READ command should
be issued x cycles after the first READ command, where x equals
BL / 2 cycles.
DDR2 SDRAM does not allow interrupting or truncating of any
READ burst using BL = 4 operations. Once the BL = 4 READ
command is registered, it must be allowed to complete the entire
READ burst. However, a READ (with auto precharge disabled)
using BL = 8 operation may be interrupted and truncated only by
another READ burst as long as the interruption occurs on a 4-bit
boundary due to the 4n prefetch architecture of DDR2 SDRAM.
Data from any READ burst must be completed before a subsequent
WRITE burst is allowed.
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where the two extreme cases (tDQSS [MIN] and tDQSS [MAX]) might
not be intuitive, they have also been included. Upon completion of
a burst, assuming no other commands have been initiated, the DQ
will remain High-Z and any additional input data will be ignored.
WRITE COMMAND
The WRITE command is used to initiate a burst write access to an
active row. The value on the BA2–BA0 inputs selects the bank,
and the address provided on inputs A0–9 selects the starting
column location. The value on input A10 determines whether or
not auto precharge is used. If auto precharge is selected, the
row being accessed will be precharged at the end of the WRITE
burst; if auto precharge is not selected, the row will remain open
for subsequent accesses.
Data for any WRITE burst may be concatenated with a subsequent
WRITE command to provide continuous flow of input data. The first
data element from the new burst is applied after the last element
of a completed burst. The new WRITE command should be issued
x cycles after the first WRITE command, where x equals BL/2.
DDR2 SDRAM supports concurrent auto precharge options, as
shown in Table 4.
DDR2 SDRAM also supports theAL feature, which allows a READ
or WRITE command to be issued prior to tRCD (MIN) by delaying the
actual registration of the READ/WRITE command to the internal
device by AL clock cycles.
DDR2 SDRAM does not allow interrupting or truncating any WRITE
burst using BL = 4 operation. Once the BL = 4 WRITE command is
registered, it must be allowed to complete the entire WRITE burst
cycle. However, a WRITE (with auto precharge disabled) using BL
= 8 operation might be interrupted and truncated ONLY by another
WRITE burst as long as the interruption occurs on a 4-bit boundary,
due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst
BL = 8 operations may not to be interrupted or truncated with any
command except another WRITE command.
Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory; if the DM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE will
not be executed to that byte/column location.
WRITE operation
Data for any WRITE burst may be followed by a subsequent READ
command. The number of clock cycles required to meet tWTR is
either 2 or tWTR/tCK, whichever is greater. Data for any WRITE burst
may be followed by a subsequent PRECHARGE command. tWR
must be met. tWR starts at the end of the data burst, regardless of
the data mask condition.
WRITE bursts are initiated with a WRITE command, as shown in
Figure 12. DDR2 SDRAM uses WL equal to RL minus one clock
cycle [WL = RL - 1CK]. The starting column and bank addresses
are provided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the completion
of the burst.
During WRITE bursts, the first valid data-in element will be
registered on the first rising edge of DQS following the WRITE
command, and subsequent data elements will be registered on
successive edges of DQS. The LOW state on DQS between the
WRITE command and the first rising edge is known as the write
preamble; the LOW state on DQS following the last data-in element
is known as the write postamble.
The time between the WRITE command and the first rising DQS
edge is WL ± tDQSS. Subsequent DQS positive rising edges are
timed, relative to the associated clock edge, as ± tDQSS. tDQSS is
specified with a relatively wide range (25 percent of one clock
cycle). All of the WRITE diagrams show the nominal case, and
17
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FIGURE 12 – WRITE COMMAND
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
CA
ADDRESS
A10
EN AP
DIS AP
BANK ADDRESS
BA
DON’T CARE
NOTE: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge.
TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE
Minimum Delay
(With Concurrent Auto
Precharge)
From Command (Bank n)
To Command (Bank m)
Units
READ OR READ w/AP
WRITE or WRITE w/AP
PRECHARGE or ACTIVATE
(CL-1) + (BL/2) + tWTR
tCK
tCK
tCK
WRITE with Auto Precharge
(BL/2)
1
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FIGURE 13 – PRECHARGE COMMAND
PRECHARGE COMMAND
The PRECHARGE command, illustrated in Figure 13, is used
to deactivate the open row in a particular bank or the open row
in all banks. The bank(s) will be available for a subsequent row
activation a specified time (tRP) after the PRECHARGE command
is issued, except in the case of concurrent auto precharge, where
a READ or WRITE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current bank and
does not violate any other timing parameters. Once a bank has
been precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank. A
PRECHARGE command is allowed if there is no open row in that
bank (idle state) or if the previously open row is already in the
process of precharging. However, the precharge period will be
determined by the last PRECHARGE command issued to the bank.
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
PRECHARGE OPERATION
InputA10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs BA2–
BA0 select the bank. Otherwise BA2–BA0 are treated as “Don’t Care.”
ADDRESS
A10
ALL BANKS
ONE BANK
BA
When all banks are to be precharged, inputs BA2–BA0 are treated
as “Don’t Care.” Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. tRPA timing applies when the
PRECHARGE (ALL) command is issued, regardless of the number
of banks already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies. tRPA (MIN) applies to all
8-bank DDR2 devices.
BA0 - BA2
DON’T CARE
NOTE: BA = bank address (if A10 is LOW; otherwise "Don't Care").
SELF REFRESH COMMAND*
The SELF REFRESH command can be used to retain data in the
DDR2 SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the DDR2 SDRAM retains data
without external clocking. All power supply inputs (including VREF
)
must be maintained at valid levels upon entry/exit and during SELF
REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH
command except CKE is LOW. The DLL is automatically disabled
upon entering self refresh and is automatically enabled upon exiting
self refresh (200 clock cycles must then occur before a READ
command can be issued). The differential clock should remain
stable and meet tCKE specifications at least 1 x tCK after entering
self refresh mode. All command and address input signals except
CKE are “Don’t Care” during self refresh.
The procedure for exiting self refresh requires a sequence of
commands. First, the differential clock must be stable and meet
tCK specifications at least 1 x tCK prior to CKE going back HIGH.
Once CKE is HIGH (tCLE(MIN) has been satisfied with four clock
registrations), the DDR2 SDRAM must have NOP or DESELECT
commands issued for tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm
for meeting both refresh and DLL requirements is to apply NOP
or DESELECT commands for 200 clock cycles before applying
any other command.
*NOTE:
Self refresh not available at military temperature above 95°C.
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ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
Max
2.3
2.3
2.3
125
25
Unit
V
Notes
Voltage on VCC pin relative to VSS
-1.0
-0.5
-0.5
-55
-25
-5
1
1, 2
3
VCCQ
VIN, VOUT
TSTG
Voltage on VCCQ pin relative to VSS
V
Voltage on any pin relative to VSS
V
Storage temperature
°C
ꢀA
ꢀA
ꢀA
IL
Input leakage current; Any input 0V<VIN<VCC; ; Other pins not under test = 0V
Output leakage current; 0V<VOUT<VCCQ; DQs and ODT are disabled
VREF leakage current; VREF = Valid VREF level
IOZ
5
IVREF
-10
10
NOTES:
Stresses greater than those listed may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions outside those
indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
1.
V
CC and VCCQ must be within 300mV of each other at all times; this is not required when power
is ramping down.
REF ≤ 0.6 x VCCQ; however, VREF may be ≥ VCCQ provided that VREF ≤ 300mV.
2.
V
3. Voltage on any I/O may not exceed voltage on VCCQ
.
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1 .7
1 .7
Typical
1 .8
Max
1 .9
Unit
V
Notes
Supply voltage
1, 5
4, 5
2
I/O Supply voltage
VCCQ
VREF
VTT
1 .8
1 .9
V
I/O Reference voltage
I/O Termination voltage
Operating Junction Temp. (Mil.)
Operating Junction Temp. (Ind.)
Operating Junction Temp. (Com.)
NOTES:
0.49 x VCCQ
0.50 x VCCQ
VREF
0.51 x VCCQ
VREF + 0.04
+125
V
VREF - 0.04
V
3
TJ
-55
-40
0
°C
°C
°C
TJ
+85
TJ
+70
1.
2.
V
V
CC and VCCQ must track each other. VCC and VCCQ are tied on this device.
REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed ±1 percent of the DC value. Peak-to-peak AC noise
on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
3.
4. VCCQ tracks with VCC
5. VSSQ = VSS
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 1MHz
Parameter
Symbol
CIN1
Max
24
Unit
pF
Input capacitance (A0 - A12, BA0 - BA2 ,CS#, RAS#, CAS#, WE#, CKE, ODT)
Input capacitance CK, CK#
CIN2
9.5
pF
Input capacitance DM
CIN3
10.5
10.5
pF
I/O capacitance DQ0 - 71, DQS, DQS#
COUT
pF
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BGA THERMAL
Junction to Board Matrix (JB)
Junction to Case Matrix (JC)
11.23 10.34
9.86
9.55
9.37
16.53 13.70 11.26
13.76 15.25 12.41
9.01
9.87
6.92
7.56
8.33
10.42 13.91 13.09 12.59 12.32
9.96
9.65
9.46
13.07 16.66 15.87 15.46
12.56 15.85 19.51 18.87
12.27 15.40 18.80 22.71
11.31 12.38 13.84 10.91
9.04
6.94
9.85
7.53
10.89 12.26 9.29
8.73
9.24 10.59
SIMULATION CONDITIONS AND NOTES:
The JEDEC JESD51 specifications are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input
to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board definition specifications; therefore, Mercury Systems recommends a customized
evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request. Refer to Mercury Systems Application Note AN0061
for matrix use.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.1 25
-0.300
Max
Unit
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VCCQ + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
—
Unit
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667
VREF + 0.250
V
V
V
V
VREF + 0.200
—
—
—
VREF - 0.250
VREF - 0.200
ODT DC ELECTRICAL CHARACTERISTICS
All voltages referenced to VSS
Parameter
Symbol
RTT1(EFF)
RTT2(EFF)
RTT3(EFF)
∆VM
Min
52
Nom
75
Max
97
Unit
Ω
Notes
RTT effective impedance value for 75Ω setting EMR (A6, A2) = 0, 1
1
1
1
2
R
TT effective impedance value for 150Ω setting EMR (A6, A2) = 1, 0
TT effective impedance value for 50Ω setting EMR (A6, A2) = 1, 1
105
35
150
50
195
65
Ω
R
Ω
Deviation of VM with respect to VCCQ/2
-6
6
%
NOTE: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL (AC) to the ball being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.
RTT(EFF)
=
VIH(AC) - VIL(AC)
I(VIH(AC)) - I(VIL(AC)
)
2. Measure voltage (VM) at tested ball with no load
∆VM =
(
2 x VM - 1
VCC
)
x 100
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DDR2 ICC SPECIFICATIONS AND CONDITIONS
667
CL6
533
CL5
400
CL4
Symbol
Proposed Conditions
Units
Operating one bank active-precharge current;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC0
t
675
800
55
575
675
55
575
675
55
mA
Operating one bank active-read-precharge current;
ICC1
ICC2P
ICC2Q
ICC2N
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is
mA
mA
mA
mA
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
325
350
225
300
200
250
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
200
50
175
50
150
50
mA
mA
ICC3P
Active standby current;
ICC3N
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
375
275
950
250
800
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC4W
1,250
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as IDAD6W
ICC4R
1,375
975
900
mA
Burst auto refresh current;
ICC5
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,400
45
1,300
45
1,250
45
mA
mA
Self refresh current;
ICC6
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC),
RRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
ICC7
t
1,975
1,775
1,775
mA
are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing
conditions
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AC TIMING PARAMETERS
667Mbs CL6
533Mbs CL5
400Mbs CL4
Parameter
Symbol
Unit
Min
Max
8,000
8,000
8,000
0.52
Min
Max
Min
Max
CL=6
CL=5
CL=4
tCK(6)
tCK(5)
tCK(6)
tCH
3,000
3,000
Clock cycle time
3,750
5,000
8,000
8,000
0.52
5,000
5,000
8,000
8,000
0.52
ps
ps
tCK
tCK
ps
5,000
CK high-level width
CK low-level width
Half clock period
0.48
0.48
0.48
tCL
0.48
0.52
0.48
0.52
0.48
0.52
tHP
MIN (tCH, tCL)
MIN (tCH, tCL)
MIN (tCH, tCL)
AVG
AVG
AVG
AVG
AVG
AVG
tCK
tCK
tCK
tCK
tCK
tCK
abs
PER
PER
DTY
DTY
PER
PER
DTY
DTY
PER
PER
Absolute tCK
tCK
(MIN)+ tJIT
(MAX)+ tJIT
(MIN)+ tJIT
(MAX)+ tJIT
(MIN)+ tJIT
(MAX)+ tJIT
ps
(MIN)
(MAX)
(MIN)
(MAX)
(MIN)
(MAX)
AVG
AVG
tCK
tCK
AVG
AVG
AVG
AVG
tCK
tCK
tCK
tCK
*
*
(MAX)
(MAX)
AVG
AVG
AVG
AVG
DTY
(MIN)* tCH
(MIN)+ tJIT
(MIN)* tCH
(MIN)+ tJIT
(MIN)* tCH
(MIN)+ tJIT
(MAX)* tCH
(MAX)+ tJIT
abs
AVG
AVG
Absolute CK high-level width
tCH
tCH
tCH
ps
DTY
DTY
DTY
(MAX)+ tJIT
(MAX)+ tJIT
(MIN)
(MIN)
(MIN)
(MAX)
(MAX)
(MAX)
AVG
AVG
AVG
AVG
AVG
AVG
tCK
tCK
tCK
tCK
tCK
tCK
*
*
*
*
*
*
(MIN)
AVG
(MAX)
AVG
(MIN)
AVG
(MAX)
AVG
(MIN)
AVG
(MAX)
AVG
abs
Absolute CK low-level width
tCL
tCL
tCL
tCL
tCL
tCL
tCL
ps
DTY
DTY
DTY
DTY
(MIN)+ tJIT
(MAX)+ tJIT
(MIN)+ tJIT
(MAX)+ tJIT
(MIN)+ tJIT
(MAX)+ tJIT
(MIN)
-125
-125
(MAX)
(MIN)
-125
-125
(MAX)
(MIN)
-125
-125
(MAX)
PER
Clock jitter - period
tJIT
125
125
125
125
125
125
ps
ps
ps
ps
ps
ps
ps
ps
ps
DUTY
Clock jitter - half period
tJIT
CC
Clock jitter - cycle to cycle
tJIT
250
250
250
Cumulative jitter error, 2 cycles
Cumulative jitter error, 3 cycles
Cumulative jitter error, 4 cycles
Cumulative jitter error, 5 cycles
Cumulative jitter error, 6-10 cycles
Cumulative jitter error, 11-50 cycles
tERR2per
tERR3per
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
tERR4per
tERR5per
tERR6-10per
tERR11-50per
23
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Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
AC TIMING PARAMETERS (continued)
667Mbs CL6
533Mbs CL5
400Mbs CL4
Min Max
Parameter
DQ hold skew factor
Symbol
Unit
Min
-
Max
400
Min
-
Max
400
tQHS
tAC
-
450
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
DQS Low-Z window from CK/CK#
DQ Low-Z window from CK/CK#
-100
1,250
-100
1,350
-100
1,350
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
1
tLZ
tAC(MN)
2*tAC(MN)
400
tAC(MN)
2*tAC(MN)
400
tAC(MN)
2*tAC(MN)
400
2
tLZ
tDSa
tDHa
tDSb
tDHb
tDIPW
tQHS
350
350
400
DQ and DM input setup time relative to DQS
100
100
150
225
225
275
DQ and DM input pulse width (for each input)
Data hold skew factor
0.35
0.35
0.35
400
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per
access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tQH - tDQSQ
0.35*tCK
0.35*tCK
-100
tQH - tDQSQ
0.35*tCK
0.35*tCK
-100
tQH - tDQSQ
0.35*tCK
0.35*tCK
-100
ns
tCK
tCK
ps
DQS input low pulse width
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
1,250
240
1,350
300
1,350
350
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
0.2*tCK
tCK
tCK
tDSH
DQS-DQ skew, DOS to last DQ valid, per group, per
access
tDQSQ
ps
DQS read preamble
tRPRE
tRPST
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
0.9*tCK
0.4*tCK
0
1.1*tCK
0.6*tCK
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
tWPRES
DQS write preamble
tWPRE
0.35*tCK
0.25*tCK
0.25
tCK
DQS write postamble
tWPST
tDQSS
0.4*tCK
-0.25*tCK
WL-TDQSS
0.6*tCK
0.25*tCK
0.4*tCK
-0.25*tCK
WL-TDQSS
0.6*tCK
0.25*tCK
0.4*tCK
-0.25*tCK
WL-TDQSS
0.6*tCK
0.25*tCK
tCK
tCK
tCK
Positive DQS latching edge to associated clock edge
Write command to first DQS latching transition
WL+TDQSS
WL+TDQSS
WL+TDQSS
24
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
AC TIMING PARAMETERS (continued)
667Mbs CL6
533Mbs CL5
400Mbs CL4
Parameter
Address and control input pulse width for each input
Symbol
Unit
Min
Max
Min
Max
Min
Max
tIPW
tISa
0.6
0.6
0.6
tCK
ps
ps
ps
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
400
500
600
Address and control input setup time
Address and control input hold time
tISb
200
250
350
tIHa
400
500
600
tIHb
275
375
475
CAS# to CAS# command delay
tCCD
tRC
2
2
2
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
55
55
55
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
10
10
10
15
15
15
50
50
50
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
40
70,000
40
70,000
40
70,000
7.5
7.5
7.5
15
15
15
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tDAL
tWTR
tRP
tWR + tRP
tWR + tRP
tWR + tRP
7.5
7.5
10
15
15
15
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
tRPA
tMRD
tDELAY
15
2
15
2
15
2
tIS +tIH + tCK
tIS +tIH + tCK
tIS +tIH + tCK
REFRESH to Active or Refresh to Refresh command
interval
tRFC
tREFI
tRIFIM
tREFIM
195
70,000
7.8
195
70,000
7.8
195
70,000
7.8
ns
ꢀs
ꢀs
ꢀs
Average periodic refresh interval (commercial and
industrial)
Average periodic refresh interval
(military 85 to 95°C junction)
3.9
3.9
3.9
Average periodic refresh interval
(military 95 to 125°C junction)
1.95
1.95
1.95
Exit self refresh to non-READ command
Exit self refresh to READ
Exit self refresh timing reference
ODT turn-on delay
tXSNR
tXSRD
tlSXR
tAOND
tAON
tRFC(MIN) + 10
tRFC(MIN) + 10
tRFC(MIN) + 10
ns
tCK
ps
tCK
ps
tCK
ps
200
tIS
200
tIS
200
tIS
2
2
2
2
2
2
ODT turn-on
tAC(MIN)
2.5
tAC(MAX) + 1000
2.5
tAC(MIN)
2.5
tAC(MAX) + 1000
2.5
tAC(MIN)
2.5
tAC(MAX) + 1000
2.5
ODT turn-off delay
tAOFD
tAOF
ODT turn-off
tAC(MIN)
tAC(MAX) + 600
tAC(MIN)
tAC(MAX) + 600
tAC(MIN)
tAC(MAX) + 600
tAC(MIN)
2000
+
2 x tCK
tAC(MAX) + 1000
2 x tCK
tAC(MAX) + 1000
+
tAC(MIN)
2000
+
2 x tCK
tAC(MAX) + 1000
2 x tCK
tAC(MAX) + 1000
+
tAC(MIN)
2000
+
2 x tCK
tAC(MAX) + 1000
2 x tCK
tAC(MAX) + 1000
+
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAOFPD
ps
ps
tAC(MIN)
2000
+
+
tAC(MIN)
2000
+
+
tAC(MIN)
2000
+
+
ODT to power-down entry latency
ODT power-down exit latency
ODT enable from MRS command
tANPD
tAXPD
tMOD
3
8
3
8
3
8
tCK
tCK
ns
12
12
12
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
Exit precharge power-down to any non-READ
command
tXP
2
3
2
3
2
3
tCK
tCK
CKE minimum high/low time
tCKE
25
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 14 – W3H128M72E-XSBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
208 x Ø 0.60 (0.024) NOM
11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1.0 (0.039)NOM
0.50
(0.020)
NOM
10.0 (0.394) NOM
16.10 (0.634) MAX
4.57 (0.180) MAX
Pads are Solder Mask Defined (SMD), pad opening is 0.48mm
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
26
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
FIGURE 15 – W3H128M72E-XNBX PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY LOW PROFILE (PBGA)
BOTTOM VIEW
208 x Ø 0.60 (0.024) NOM
11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1.0 (0.039)NOM
0.50
(0.020)
NOM
10.0 (0.394) NOM
16.10 (0.634) MAX
3.94 (0.155) MAX
Pads are Solder Mask Defined (SMD), pad opening is 0.48mm
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
27
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
ORDERING INFORMATION
W 3H 128M 72 E X - XXX XX X
MERCURY SYSTEMS
DDR2 SDRAM
CONFIGURATION, 128M x 72
1.8V POWER SUPPLY
OPTIONS*
Blank = 0 ohm termination on CK\CK#
2 = 20 ohm termination on CK\CK#
DATA RATE (Mbs)
400 = 400Mb/s
533 = 533Mb/s
667 = 667Mb/s
PACKAGE:
SB = 4.57 mm package (Fig. 14)
NB = 3.94 mm package (Fig. 15)
DEVICE GRADE:
M = Military
-55°C to +125°C
I
= Industrial
-40°C to +85°C
0°C to +70°C
C
= Commercial
* Other termination values may be available, contact factory for options.
28
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
Document Title
1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
May 2008
Advanced
Rev 1
Changes (Pg. 1, 2, 22, 33)
September 2008
Advanced
1.1 Weight 4 grams max
1.2 Changed A0-12 to A0-13
1.3 Added input/output capacitance
1.4 Added BGA thermal resistance
Rev 2
Rev 3
Change (Pg. 1)
October 2008
October 2008
Preliminary
Preliminary
2.1 Change SPACE SAVINGS to space savings
Change (Pg. 24)
3.1 Reduce DDR2 ICC7
• CL6 from (1,975 to 1,580) mA
• CL5 from (1,775 to 1,420) mA
• CL4 from (1,775 to 1,420) mA
Rev 4
Change (Pg. 1, 5, 6, 19, 22, 23, 30)
December 2008
Final
4.1 Remove "P" from FBGA, take out "Actual Size" off of Figure 1
4.2 Remove VCCQ; and I/O + core; VCCQ is common to VCC in VCC box
4.3 Change page 8 to page 7 in initialization paragraph
4.4 Change tWT to tWT
4.5 In BGA thermal resistance, change note to read - to obtain the junction
temperature increase, multiply the thermal resistance by the power dissipated
in each die in the MCP
4.6 In DC operating conditions add "and" to note 1
4.7 Put "/" in between Mbs to read Mb/s
4.8 Change data sheet to final
29
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
Document Title
1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History Continued
Rev #
History
Release Date Status
Rev 5
Changes (Pg. 1)
March 2009
Final
5.1 Change "This product is under development, is not fully qualified or
characterized and is subject to change without notice
5.2 Add thinner "NB" version of part is under development. Only difference
between "NB" and "SB" is thickness. "SB" = 4.65mm (0.283) max and
"NB" = 3.97mm (0.156) max; a difference of .68mm (0.027) max
Rev 6
Changes (Pg. 24, 26)
September 2009
Final
6.1 Change ICC2P to 55mA on all speed grades
6.2 Change ICC6 to 45mA on all speed grades
6.3 Change ICC7 to 1,775mA on "400 and 533" speed grades and 1,975mA
on 667 speed grade
6.4 Change tAC to -100ps min on all speed grades and 1,250ps max on 667
speed grade, 1,350ps on 400 and 533 speed grades
6.5 Change tDSA to 400ps on 533 speed grade
6.6 Change tDQSCK to -100ps min on all speed grades and 1,250ps max on
667 speed grade, 1,350ps on 400 and 533 speed grades
Rev 7
Changes (Pg. 1, 29, 30)
March 2010
Final
7.1 Add weight of W3H128M72E-XNBX
7.2 Remove Thinner "NB" note
7.3 Add new W3H128M72E-XNBX package dimension
7.4 Change W3H128M72E-XSBX from 4.65 mm to 4.57 mm
7.5 Change length to 22.10 (0.870) max and width to 16.10 (0.634) max on
both "SB" and "NB" packages.
7.6 Remove note from BGA thermal resistance.
Rev 8
Rev 9
Changes (Pg. 25)
February 2011
August 2011
Final
Final
8.1 Correct tRFC = 195 ns for all speed grades
Changes (Pg. 1, 29, 30)
9.1 Add "1GB" to doc title
9.2 Add "Typical Applications" diagram
Rev 10
Changes (Pg. 26-28)
10.1 Fix typos
January 2012
Final
30
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
W3H128M72E-XSBX / W3H128M72E-XNBX
Document Title
1GB – 128M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History Continued
Rev #
History
Release Date Status
Rev 11
Changes (Pg. 1-3, 5-27)
September 2012
Final
11.1 Remove ±0.1V from Core Supply Voltage and I/O Supply Voltage
11.2 Remove numbers from CAS latency
11.3 Change note in Figure 2
11.4 Change note in Figure 3
11.5 Correct typos in Description
11.6 Update diagram in Figure 4
11.7 Update notes 3-16 for Figure 4
11.8 Correct typos on page 7; update diagram in Figure 5
11.9 Correct typos on page 8
11.10 Correct typos on page 9
11.11 Correct typos and update diagram in Figure 7 on page 10
11.12 Correct typos on page 11
11.13 Correct typos update diagram in Figure 8 on page 12
11.14 Correct typos update diagram in Figure 9 on page 13
11.15 Update Table 3 – Truth Table - DDR2 Commands
11.16 Correct typos on page 15, 16, and 17
11.17 Correct typo in Table 4
11.18 Correct typos on page 19
11.19 Update Absolute Maximum Ratings, DC Operating Conditions and
Input/Output Capacitance charts on page 20
11.20 Update BGA Thermal Resistance chart on page 21
11.21 Update DDR2 ICC Specifications and Conditions chart on page 22
11.22 Delete subtitle from AC Timing Parameters chart on pages 23, 24 and
25; update Refresh values same chart
11.23 Update BGA Thermal Resistance chart on page 21
11.24 Add note to Figures 14 and 15
Rev 12
Changes (Pg. All)
July 2016
Final
12.1 Change document layout from Microsemi to Mercury Systems
Mercury Systems reserves the right to change products or specifications without notice.
© 2016 Mercury Systems. All rights reserved.
31
4163.12E-0716-ss-W3H128M72E-XSBX / XNBX
Mercury Corp. - Memory and Storage Solutions • (602) 437-1520 • www.mrcy.com
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