W3J512M32K-1066B2C_技术文档

W3J512M32K-XBX

W3J512M32KT-XB2X

*PRELIMINARY

2GB – 512M x 32 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip

Package

FEATURES

BENEFITS

 DDR3 Data Rate = 800, 1,066, 1333 Mb/s

 67% Space savings vs. FBGA

 Reduced part count

 35% I/O reduction vs. FBGA

 Optional:

 Packages:

• 136 PBGA, 204 PBGA 10 x 14.5mm

• 0.8mm pitch

• Moisture Sensitivity Level (MSL): 3

 Supply Voltage = 1.35V

• Address/control terminations

 Differential clock terminations (not populated in XBX

package)

 Center terminated push/pull I/O

 Differential bidirectional data strobe

 Differential clock inputs (CK, CK#)

 8n-bit prefetch architecture

 Output drive calibration resistors (RZQ)

 Reduced trace lengths for lower parasitic capacitance

 Suitable for hi-reliability applications

 Enhanced thermal management

 Eight internal banks

 Fixed Burst length (BL) of 8 and Burst Chop (BC) of 4

 Selectable BC4 or BL8 on-the-ﬂy (OTF)

 Auto Refresh and Self Refresh Modes

 Nominal and dynamic On Die Termination (ODT)

 Programmable CAS read latency (CL)

 Posted CAS additive latency

* This product is under development, is not qualiﬁed or characterized and is subject to change or

cancellation without notice.

TYPICAL APPLICATION

 Write leveling

RAM

Smart

 Programmable CAS write latency (CWL) based on t_CK

 Commercial, industrial and military temperature ranges

 Organized as 1 rank of 512M x 32

Fusion2

DDR3

W3J512M32K-XBX

Host

FPGA/

Processor

SSD (SLC)

 1.5V option available in same packages.

Refer to W3J512M32G data sheet.

 W3J512M32K-XBX is footprint compatible with Micron^®

MSM32/MSM64 (SATA BGA)

W7N16GVHxxBI (PATA BGA)

MSD1TB / 512 / 256 / 128 (SATA, 2.5in)

M41K256M32 device.

Micron^©is a registered trademark of Micron Technology, Inc.

FIGURE 1 – DENSITY COMPARISONS

CSP Approach (mm)

S

A

V

I

N

G

S

W3J512M32KT-XB2X

2.0

9

78

10.5

14.5

FBGA

W3J512M32KT-XB2X

10

Area

441 mm²

4 x 78 balls = 312 balls

145 mm²

204 Balls

67%**

35%

I/O Count

** not including terminations

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

1

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 2A – FUNCTIONAL BLOCK DIAGRAM FOR W3J512M32K-XBX

A0-15, BA0-2, RAS#, CAS#

WE#, RST#, CKE, ODT, CS#

CK#

CK

26

CK# CK

DM

11

DQS0, DQS0#

DM0, DQ0-7

512M x 8

IC1

DQ

DQS

240Ω

ZQ

26

CK# CK

DM

DQ

DQS

11

DQS1, DQS1#

DM1, DQ8-15

512M x 8

IC2

240Ω

ZQ

26

CK# CK

DM

DQ

DQS

11

DQS2, DQS2#

DM2, DQ16-23

512M x 8

IC3

240Ω

ZQ

26

CK# CK

DM

DQ

DQS

11

DQS3, DQS3#

DM3, DQ24-31

512M x 8

IC4

240Ω

ZQ

NOTES: Block diagram shows actual ﬂy-by order.

Calibration resistors (RZQ) are included.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

2

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 2B – FUNCTIONAL BLOCK DIAGRAM FOR W3J512M32KT-XB2X

A0-15, BA0-2, RAS#, CAS#

WE#, RST#, CKE, ODT, CS#

CK#

CK

26

CK# CK

DM

11

DQS0, DQS0#

DM0, DQ0-7

512M x 8

IC1

DQ

DQS

240Ω

ZQ

26

CK# CK

DM

DQ

DQS

11

DQS1, DQS1#

DM1, DQ8-15

512M x 8

IC2

240Ω

ZQ

26

CK# CK

DM

DQ

DQS

11

DQS2, DQS2#

DM2, DQ16-23

512M x 8

IC3

240Ω

ZQ

26

CK# CK

DM

DQ

DQS

11

DQS3, DQS3#

DM3, DQ24-31

512M x 8

IC4

NOTES:

240Ω

ZQ

25

• Block diagram shows actual ﬂy-by order.

• Calibration resistors (RZQ) are included.

• Clock termination is included.

• Address/Control terminations are included.

V_TT

R_TT

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

3

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 3 – 136 PBGA (XBX) PIN CONFIGURATION

TOP VIEW

1

2

3

4

9

10

11

12

A

B

C

D

E

F

V_CCGND GND DQ1

V_CCDQ0 GND DQ3

V_CCDQ2 GND DM0

GND V_CCDQS0 DQS0#

GND DQ4 V_CCDQ5

GND DQ6 V_CCDQ7

DQ9 GND GND V_CC

DQ11 GND DQ8 V_CC

DM1 GND DQ10 V_CC

DQS1# DQS1 V_CCGND

DQ13 V_CCDQ12 GND

DQ15 V_CCDQ14 GND

A

B

C

D

E

F

G

H

V_CC

NC CAS# RAS#

CK

A10

A1

CK# CKE V_CC

A14 A15 NC

NC GND V_REFCA

G

H

J

RST# BA2 ODT CS#

J V_REFDQGND NC

WE#

A0

K

L

BA0

V_CC

A9

A7

A2

A5

A4

A6

A12 BA1

A13 V_CC

K

L

A3

A8

A11

M

N

P

R

T

GND DQ24 V_CCDQ25

GND DQ26 V_CCDQ27

GND V_CCDQS3 DQS3#

V_CCDQ28 GND DM3

V_CCDQ30 GND DQ29

V_CCGND GND DQ31

DQ17 V_CCDQ16 GND

DQ19 V_CCDQ18 GND

DQS2# DQS2 V_CCGND

DM2 GND DQ20 V_CC

DQ21 GND DQ22 V_CC

DQ23 GND GND V_CC

M

N

P

R

T

U

1

2

3

4

9

10

11

12

NOTE: Calibration resistors (RZQ) are included inside the package.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

4

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 3A – 204 PBGA PIN CONFIGURATION (XB2X)

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

V_CCGND GND DQ1 V_CCV_TT** V_TT** V_CCDQ9 GND GND V_CC

V_CCDQ0 GND DQ3 GND V_TT** V_TT** GND DQ11 GND DQ8 V_CC

V_CCDQ2 GND DM0 GND V_TT** NC GND DM1 GND DQ10 V_CC

A

B

C

D

E

F

GND V_CCDQS0 DQS0# V_CC

GND DQ4 V_CCDQ5 V_CC

NC

V_CCDQS1# DQS1 V_CCGND

V_CCDQ13 V_CCDQ12 GND

GND DQ6 V_CCDQ7 GND NC

V_CCNC CAS# RAS# GND NC

RST# BA2 ODT CS#

NC GND DQ15 V_CCDQ14 GND

G

H

NC GND

CK

A10

A1

CK# CKE V_CC

A14 A15 NC

NC GND V_REFCA

G

H

J

V_CC

NC

V_CC

J V_REFDQGND NC

WE# V_CC

K

L

BA0

V_CC

A9

A7

A2

A5

A0

A3

GND NC

NC GND

V_CCGND

A4

A6

A12 BA1

A13 V_CC

K

L

A8

A11

M

N

P

R

T

GND DQ24 V_CCDQ25 V_CCGND GND V_CCDQ17 V_CCDQ16 GND

GND DQ26 V_CCDQ27 V_CCGND GND V_CCDQ19 V_CCDQ18 GND

M

N

P

R

T

GND V_CCDQS3 DQS3# GND V_CC

V_CCDQ28 GND DM3 GND V_CC

V_CCGND DQS2# DQS2 V_CCGND

V_CCGND DM2 GND DQ20 V_CC

V_CCDQ30 GND DQ29 V_CCGND GND V_CCDQ21 GND DQ22 V_CC

V_CCGND GND DQ31 V_CCGND GND V_CCDQ23 GND GND V_CC

U

1

2

3

4

5

6

7

8

9

10

11

12

NOTE: Calibration resistors (RZQ) are included inside the package.

** V_TTis only used with address/control terminations option

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

5

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 1 – BALL DESCRIPTIONS

Symbol

ODT

Type

Input

Description

On-Die termination: ODT (registered HIGH) enables and (registered LOW) disables termination resistance internal to the

DDR3 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM. The ODT

input will be ignored if disabled via the LOAD MODE command. ODT is referenced to V_REFCA

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of CK#. Output data (DQS and DQS#) is referenced to the crossings of CK and CK#.

CK, CK#

Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The

speciﬁc circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM conﬁguration and operating mode. Taking

CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle),or active power-down (row

active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for

self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers

(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to V_REFCA.

CKE

Input

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are

masked when CS# is registered HIGH. CS# is considered part of the command code. CS# is referenced to V_REFCA

CS#

Input

RAS#, CAS#, WE#

Command inputs: RAS#, CAS#, WE# (along with CS#) deﬁne the command being entered and are referenced to V_REFCA

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the

input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and

DQS balls. DM is referenced to V_REFDQ.

DM0-7

BA0–BA2

RST#

Input

Bank address inputs: BA0–BA2 deﬁne to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being

applied. BA0–BA2 deﬁne which mode register including (MR, MR0, MR1, MR2, MR3) is loaded during the LOAD MODE

command. BA0-2 are referenced to V_REFCA

Reset = RST# or RESET# is an active low CMOS input referenced to V_SS. The RST# input receiver is a CMOS input

deﬁned as a rail-to-rail signal with DC HIGH ≥ 0.8 x V_CCQand DC LOW ≤ 0.2 x V_CCQ. RST# assertion and desertion are

asynchronous

Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10)

for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a

PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0])

or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs

are referenced to V_REFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE

commands to determine whether burst chop (on-the-ﬂy) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst

chop).

A0-A15

Input

DQ0-X

DQS0-X, DQS0-X#

V_CC

I/O

Data input/output: Bidirectional data bus. DQs are referenced to V_REFDQ.

Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data.

Single Power Supply – V_CCand V_CCQare internally tied together

Termination supply

Supply

-

V_TT

Reference voltage for control, command, and address. V_REFCA must be maintained at all times (including self refresh) for

proper device operation.

V_REFCA

V

_REFDQ

GND

NC

Reference voltage for data. V_REFDQ must be maintained at all times (including self refresh) for proper device operation.

Ground.

No connect: These balls should be left unconnected.

Future use

DNU

-

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

6

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

DESCRIPTION

GENERAL NOTES

The 2GB DDR3 SDRAM is a high-speed CMOS, dynamic random-

access memory containing 4 4Gb, (4,294,967,296) bit chips. Each

of the 4 chips in the MCP are internally conﬁgured as 8-bank

DRAM. The block diagram of the device is shown in Figure 2. Ball

assignments and are shown in Figure 3.

• The functionality and the timing speciﬁcations discussed

in this data sheet are for the DLL-enabled mode of

operation. (normal operation)

• Throughout the data sheet, the various ﬁgures and text

refer to DQs as “DQ.” The DQ term is to be interpreted

as any and all DQ collectively, unless speciﬁcally stated

otherwise. The terms "DQS" and "CK" found throughout

the data sheet are to be interpreted as DQS, DQS#

and CK, CK# respectively, unless speciﬁcally stated

otherwise.

The 2GB DDR3 SDRAM uses a double-data-rate architecture to

achieve high-speed operation. The double data rate architecture

is a 8n-prefetch architecture, with an interface designed to transfer

two data words per clock cycle at the I/O balls. A single read or

write access for the 2GB DDR3 SDRAM consists of a single 8n-bit-

wide, one-clock-cycle data transfer at the internal DRAM core and

eight corresponding n-bit-wide, one-half-clock-cycle data transfers

at the I/O balls.

• Complete functionality is described throughout the

document and any page or diagram may have been

simpliﬁed to convey a topic and may not be inclusive of

all requirements.

A differential data strobe (DQS, DQS#) is transmitted externally,

along with data, for use in data capture at the receiver. DQS is

center-aligned with data for writes. The read data is transmitted by

the DDR3 SDRAM and edge-aligned to the data strobes.

• Any speciﬁc requirement takes precedence over a

general statement.

• Any functionality not speciﬁcally stated here within is

considered illegal, and not supported and can result in

unknown operations.

The 2GB DDR3 SDRAM operates from a differential clock (CK and

CK#); the crossing of CK going HIGH and CK# going LOW will be

referred to as the positive edge of CK. Commands (address and

control signals) are registered at every positive edge of CK. Input

data is registered in the ﬁrst rising edge of "DQS" after the "WRITE"

preamble, and output data is referenced on the ﬁrst rising edge of

"DQS" after the "READ" preamble.

Read and write accesses to the DDR3 SDRAM are burst

oriented; accesses start at a selected location and continue for

a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an ACTIVATE command,

which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVATE command

are used to select the bank and row to be accessed. The address

bits registered coincident with the READ or WRITE command are

used to select the bank and the starting column location for the

burst access.

DDR3 SDRAM use "READ" and "WRITE" BL8 and "BC4" An auto

precharge function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access.

As with standard DDR SDRAMs, the pipelined, multibank

architecture of DDR3 SDRAMs allows for concurrent operation,

thereby providing high, effective bandwidth by hiding row precharge

and activation time.

Aself refresh mode is provided, along with a power-saving power-

down mode.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

7

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

INITIALIZATION

DDR3 SDRAMs must be powered up and initialized in a

predeﬁned manner. Operational procedures other than those

speciﬁed may result in undeﬁned operation. The following

sequence is required for power up and initialization and is

shown in Figure 4.

5. After this CKE LOW time, CKE may be brought HIGH

(synchronously) and only NOP or DES commands may be

issued. The clock must be present and valid for at least 10ns

(and a minimum of ﬁve clocks) and ODT must be driven

LOW at least t_ISprior to CKE being registered HIGH. When

CKE is registered HIGH, it must be continuously registered

HIGH until the full initialization process is complete.

1. Applying power; RST# is recommended to be below 0.2

x V_CCQduring power ramp to ensure the outputs remain

disabled. (HIGH-Z) and ODT off (R_TTis also HIGH-Z). All

other inputs, including ODT, may be undeﬁned.

6. After CKE is registered HIGH and after t_XPRhas been

satisﬁed, MRS commands may be issued. Issue an MRS

(LOAD MODE) command to MR2 with the applicable settings

(provide LOW to BA2 and BA0 and HIGH to BA1).

During power up, either of the following conditions may

exist and must be met:

7. Issue an MRS command to MR3 with the applicable settings.

Condition A:

8. Issue an MRS command to MR1 with the applicable settings,

• V_CCand V_CCQare driven from a single-power converter

output and are ramped with a maximum delta voltage

between them of ΔV ≤ 300mV. Slope reversal of any

power supply signal is allowed. The voltage levels on

all balls other than V_CC, V_CCQ, V_SS, V_SSQmust be less

than or equal to V_CCQand V_CCon one side, and must be

greater than or equal to V_SSQand V_SSon the other side.

including enabling the DLL and conﬁguring ODT.

9. Issue an MRS command to MR0 with the applicable settings,

including a DLL RESET command. t_DLLK(512) cycles of clock

input are required to lock the DLL.

10. Issue a Z_QCLcommand to calibrate R_TTand RON values

for the process voltage temperature (PVT). Prior to normal

operation, t_ZQINITmust be satisﬁed.

• Both V_CCand V_CCQpower supplies ramp to V_CC(MIN)

and V_CCQC(MIN) within t_VDDPR= 200ms.

11. When t_DLLKand t_ZQINIThave been satisﬁed, the DDR3

• V_REFDQtracks V_CC× 0.5, V_REFCAtracks V_CC× 0.5.

SDRAM will be ready for normal operation.

• V_TTis limited to 0.875V when the power ramp is complete

and is not applied directly to the DRAM components;

however, t_VTDshould be greater than or equal to zero to

avoid device latchup.

Condition B:

• Vcc may be applied before or at the same time as V_CCQ

• V_CCQmay be applied before or at the same time as V_TT,

_REFDQ, and V_REFCA.

.

V

• No slope reversals are allowed in the power supply ramp

for this condition.

2. Until stable power, maintain RST# LOW to ensure the

outputs remain disabled (High-Z). After the power is

stable, RST# must be LOW for at least 200μs to begin the

initialization process. ODT will remain in the High-Z state

while RST# is LOW and until CKE is registered HIGH.

3. CKE must be LOW 10ns prior to RST# transitioning HIGH.

4. After RST# transitions HIGH, wait 500μs (minus one clock)

with CKE LOW.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

8

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 4 – POWER-UP AND INITIALIZATION

Notes appear on page 8

T (MAX) = 200ms

VCC

See power-up

conditions

in the

initialization

sequence text,

set up 1

VTT

VREF

Stable and

valid clock

Tc0

Td 0

Tb0

T1

T0

Ta0

Power-up

ramp

t

CK

VTD

CK#

CK

t

CL

CKSRX

t

IO

= 20ns

z

RESET#

t

IS

T (MIN) = 10ns

Valid

CKE

ODT

t

IS

NOP

Command

DM

MRS

ZQCL

Valid

Address

A10

Valid

Code

Valid

A10 = H

BA0 = L

BA1 = H

BA2 = L

BA0 = H

BA1 = H

BA2 = L

BA0 = H

BA1 = L

BA2 = L

BA0 = L

BA1 = L

BA2 = L

BA[2:0]

DQS

DQ

RTT

t

MOD

T = 200μs (MIN)

T = 500μs (MIN)

t

ZQ^INIT

MRD

XPR

MRD

MR0 with

DLL reset

MR1 with

DLL enable

MR2

MR3

ZQ calibration

All voltage

supplies valid

and stable

t

DLLK

DRAM ready for

external commands

Normal

operation

Indicates A Break in

Time Scale

Don’t Care

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

9

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

a burst is determined by the burst length, the burst type, and the

starting column address, as shown in Table 4. DDR3 only supports

4-bit burst chop and 8-bit burst access modes. Full interleave

address ordering is supported for READs, while WRITEs are

restricted to nibble (BC4) or word (BL8) boundaries.

MODE REGISTERS

Mode registers (MR0–MR3) are used to deﬁne various modes of

programmable operations of the DDR3 SDRAM. A mode register

is programmed via the MODE REGISTER SET (MRS) command

during initialization, and it retains the stored information (except

for MR0[8] which is self-clearing) until it is either reprogrammed,

RESET# goes LOW, or until the device loses power. Contents of a

mode register can be altered by re-executing the MRS command.

If the user chooses to modify only a subset of the mode register’s

variables, all variables must be programmed when the MRS

command is issued. Reprogramming the mode register will not alter

the contents of the memory array, provided it is performed correctly.

The MRS command can only be issued (or reissued) when all banks

are idle and in the precharged state (t_RPis satisﬁed and no data

bursts are in progress). After an MRS command has been issued,

two parameters must be satisﬁed: t_MRDand t_MOD. The controller

must wait t_MRDbefore initiating any subsequent MRS commands

The controller must also wait t_MODbefore initiating any non MRS

commands (excluding NOP and DES). The DRAM requires t_MODin

order to update the requested features, with the exception of DLL

RESET, which requires additional time. Until t_MODhas been satisﬁed,

the updated features are to be assumed unavailable.

DLL RESET

DLL RESET is deﬁned by MR0[8] (see Figure 5). Programming

MR0[8] to “1” activates the DLL RESET function. MR0[8] is self-

clearing, meaning it returns to a value of “0” after the DLL RESET

function has been initiated. Anytime the DLL RESET function is

initiated, CKE must be HIGH and the clock held stable for 512

(t_DLLK) clock cycles before a READ command can be issued. This

is to allow time for the internal clock to be synchronized with the

external clock. Failing to wait for synchronization to occur may

result in invalid output timing speciﬁcations, such as t_DQSCKtimings.

WRITE RECOVERY

WRITE recovery time is deﬁned by MR0[11:9] (see Figure 5).

Write recovery values of 5, 6, 7, 8, 10, 12 or 14 may be used by

programming MR0[11:9]. The user is required to program the

correct value of write recovery and is calculated by dividing t_WR

(ns) by t_CK(ns) and rounding up a non integer value to the next

integer: WR (cycles) = roundup (t_WR[ns]/t_CK[ns]).

MODE REGISTER 0 (MR0)

The base register, MR0, is used to deﬁne various DDR3 SDRAM

modes of operations. These deﬁnitions include the selection of a

burst length, burst type, CAS latency, operating mode, DLLRESET,

write recovery, and precharge power-down mode.

PRECHARGE POWER-DOWN

(PRECHARGE PD)

The precharge PD bit applies only when precharge power-down

mode is being used. When MR0[12] is set to “0,” the DLL is off

during precharge power-down providing a lower standby current

mode; however, t_XPDLLmust be satisﬁed when exiting. When

MR0[12] is set to “1,” the DLL continues to run during precharge

power-down mode to enable a faster exit of precharge power-down

mode; however, t_XPmust be satisﬁed when exiting.

BURST LENGTH

Burst length is deﬁned by MR0[1: 0]. (see ﬁgure 9) Read and

write accesses to the DDR3 SDRAM are burst-oriented, with

the burst length being programmable to “4” (chop mode), “8”

(ﬁxed), or selectable using A12 during a READ/WRITE command

(on-the-ﬂy). The burst length determines the maximum number

of column locations that can be accessed for a given READ or

WRITE command. When MR0[1:0] is set to “01” during a READ/

WRITE command, if A12 = 0, then BC4 (chop) mode is selected.

If A12 = 1, then BL8 mode is selected. Speciﬁc timing diagrams,

and turnaround between READ/WRITE, are shown in the READ/

WRITE sections of this document. When a READ or WRITE

command is issued, a block of columns equal to the burst length

is effectively selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected byA[i:2] when

the burst length is set to “4” and by A[i:3] when the burst length is

set to “8” (where Ai is the most signiﬁcant column address bit for a

given conﬁguration). The remaining (least signiﬁcant) address bit(s)

is (are) used to select the starting location within the block. The

programmed burst length applies to both READ and WRITE bursts.

CAS LATENCY (CL)

The CAS latency (CL) is deﬁned by MR0[6:4], as shown in Figure

6. CL is the delay, in clock cycles, between the internal READ

command and the availability of the ﬁrst bit of output data. The CL

can be set to 5, 6, 7, 8, 9, 10, 11, 12, or 13. DDR3 SDRAM does

not support any half-clock latencies.

MODE REGISTER 1 (MR1)

The mode register 1 (MR1) controls additional functions and

features not available in the other mode registers: Q OFF (OUTPUT

DISABLE), TDQS (for the x8 conﬁguration only, DLLENABLE/DLL

DISABLE, R_{TT_NOM}value (ODT), WRITE LEVELING, POSTED

CASADDITIVE latency, and OUTPUT DRIVE STRENGTH. These

functions are controlled via the bits shown in Figure 7. The MR1

register is programmed via the MRS command and retains the

stored informations until it is reprogrammed, until RESET# goes

LOW, or until the device loses power. Reprogramming the MR1

register will not alter the contents of the memory array, provided

it is performed correctly.

BURST TYPE

Accesses within a given burst may be programmed to either a

sequential or an interleaved order. The burst type is selected via

MR0[3], as shown in Figure 5. The ordering of accesses within

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PRELIMINARY

FIGURE 5 – MODE REGISTER 0 (MR0) DEFINITIONS

BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus

18 17 16 15 14 13 12 11 10

9

8

7

1

6

5

4

3

2

1

0

Mode register 0 (MR0)

1

0

PD

WR

DLL

0

CAS# latency BT

M1 M0

Burst Length

M17 M16

Mode Register

0

1

0

1

0

1

Fixed BL8

4 or 8 (on-the-fly via A12)

Fixed BC4 (chop)

Reserved

0

1

0

1

0

1

Mode register 0 (MR0)

Mode register 1 (MR1)

Mode register 2 (MR2)

Mode register 3 (MR3)

M12 Precharge PD

M8 DLL Reset

0

1

DLL off (slow exit)

DLL on (fast exit)

0

1

No

Yes

M11 M10 M9 Write Recovery

M6 M5 M4 M2

CAS Latency

M3

READ Burst Type

Sequential (nibble)

Interleaved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16

5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

0

1

5

6

7

8

10

12

14

9

10

11

12

13

NOTE: 1. MR0[18, 15:13, 7] are reserved for future use and must be programmed to 0.

TABLE 4 – BURST ORDER

Burst

READ/

WRITE

Burst Length

Starting Column Address

Notes

Type = Sequential

0, 1, 2, 3, Z, Z, Z, Z

1, 2, 3, 0, Z, Z, Z, Z

2, 3, 0, 1, Z, Z, Z, Z

3, 0, 1, 2, Z, Z, Z, Z

4, 5, 6, 7, Z, Z, Z, Z

5, 6, 7, 4, Z, Z, Z, Z

6, 7, 4, 5, Z, Z, Z, Z

7, 4, 5, 6, Z, Z, Z, Z

0, 1, 2, 3, Z, Z, Z, Z

4, 5, 6, 7, Z, Z, Z, Z

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 0, 5, 6, 7, 4

2, 3, 0, 1, 6, 7, 4, 5

3, 0, 1, 2, 7, 4, 5, 6

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 4, 1, 2, 3, 0

5, 6, 7, 4, 5, 2, 3, 0, 1

7, 4, 5, 6, 3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

Type = Interleaved

0, 1, 2, 3, Z, Z, Z, Z

0

1

0

1

0

1

V

0

1

0

1

V

0

1

0

1

V

0

1

0

1

0

1

0

1

V

0

1

0

1

0

1

0

1

V

1, 2

1, 3, 4

1

1, 0, 3, 2, Z, Z, Z, Z

2, 3, 0, 1, Z, Z, Z, Z

3, 2, 1, 0, Z, Z, Z, Z

4, 5, 6, 7, Z, Z, Z, Z

5, 4, 7, 6, Z, Z, Z, Z

6, 7, 4, 5, Z, Z, Z, Z

7, 6, 5, 4, Z, Z, Z, Z

0, 1, 2, 3, X, X, X, X

4, 5, 6, 7, X, X, X, X

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

READ

4 CHOP

WRITE

1

READ

8

1

WRITE

1, 3

NOTES:

1. Internal read and write operations start at the same point in time for BC4 as they do for BL8

2. Z = Data strobe output drives are in tri-state

3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins

4. X = "Don't care".

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PRELIMINARY

The MR1 register must be loaded when all banks are idle and no

bursts are in progress. The controller must satisfy the speciﬁed

timing parameters. t_MRDand t_MODbefore initiating a subsequent

operation

disabled (MR1[12] = 1), all DDR3 SDRAM outputs (DQ and DQS,

DQS#) are tri-stated. The output disable feature is intended to be

used during I_CCcharacterization of the READ current and during

t_DQSSmargining (write leveling) only.

DLL ENABLE/DLL DISABLE

ON-DIE TERMINATION (ODT)

The DLL may be enabled or disabled by programming MR1[0]

during the LOAD MODE command, as shown in Figure 11.

The DLL must be enabled for normal operation. DLL enable is

required during power-up initialization and upon returning to

normal operation after having disabled the DLL for the purpose

of debugging or evaluation. Enabling the DLL should always be

followed by resetting the DLL using the appropriate LOAD MODE

command.

ODT resistance RTT_NOM is deﬁned by MR1[9, 6, 2] (see Figure

7). The RTT termination value applies to the DQ, DM, DQS,

DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT

termination values based on RZQ/n where n can be 2, 4, 6, 8, or

12 and RZQ is 240Ω. Unlike DDR2, DDR3 ODT must be turned

off prior to reading data out and must remain off during a READ

burst. RTT_NOM termination is allowed any time after the DRAM

is initialized, calibrated, and not performing read access, or when

it is not in self refresh mode. Additionally, write accesses with

dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM

with RTT_WR.

If the DLL is enabled prior to entering self refresh mode, the

DLL is automatically disabled when entering SELF REFRESH

operation an is automatically reenabled and reset upon exit of SELF

REFRESH operation. IF the DLL is disabled prior to entering self

refresh mode, the DLL remains disabled even upon exit of SELF

REFRESH operation until it is reenabled and reset.

The actual effective termination, RTT_EFF, may be different from

the RTT targeted due to nonlinearity of the termination.

The ODT feature is designed to improve signal integrity of the

memory channel by enabling the DDR3 SDRAM controller to

independently turn on/off ODT for any or all devices. The ODT

input control pin is used to determine when RTT is turned on

(ODTL on) and off (ODTL off), assuming ODT has been enabled

via MR1[9, 6, 2].

The DRAM is not tested to check-nor does Microsemi warrant

compliance with normal mode timings or functionality when the

DLL is disabled. An attempt has been made to have the DRAM

operate in the normal mode where reasonably possible when the

DLL has been disabled; however, by industry standard, a few

known exceptions are deﬁned:

WRITE LEVELING

1. ODT is not allowed to be used.

The WRITE LEVELING function is enabled by MR1[7], as shown in

Figure 7. Write leveling is used (during initialization) to deskew the

DQS strobe to clock offset as a result of ﬂy-by topology designs.

For better signal integrity, DDR3 SDRAM memory adopted ﬂy-by

topology for the commands, addresses, control signals, and clocks.

2. The output data is no longer edge-aligned to the clock.

3. CL and CWL can only be six clocks.

When the DLL is disabled, timing and functionality can vary from

the normal operation speciﬁcations when the DLL is enabled (see

"DLL Disable Mode"). Disabling the DLL also implies the need to

change the clock frequency.

The ﬂy-by topology beneﬁts from a reduced number of stubs and

their lengths. However, ﬂy-by topology induces ﬂight time skews

between the clock and DQS strobe (and DQ) at each DRAM.

Controllers will have a difﬁcult time maintaining t_DQSS, t_DSS, and

t_DSHspeciﬁcations without supporting write leveling in systems

which use ﬂy-by topology-based designs.

OUTPUT DRIVE STRENGTH

The DDR3 SDRAM uses a programmable impedance output buffer.

The drive strength mode register setting is deﬁned by MR1[5,

1]. RZQ/7 (34Ω [NOM]) is the primary output driver impedance

setting for DDR3 SDRAM devices. To calibrate the output driver

impedance, an external precision resistor (RZQ) is connected

between the ZQ ball and V_SSQ. The value of the resistor must be

240Ω ±1 percent. The output impedance is set during initialization.

Additional impedance calibration updates do not affect device

operation, and all data sheet timings and current speciﬁcations

are met during an update.

POSTED CAS ADDITIVE LATENCY (AL)

Posted CAS additive latency (AL) is supported to make the

command and data bus efﬁcient for sustainable bandwidths in

DDR3 SDRAM. MR1 [4, 3] deﬁne the value of AL, as shown in

Figure 7. MR1 [4, 3] enable the user to program the DDR3 SDRAM

with an Al = 0, CL-1 or CL -2.

With this feature, the DDR3 SDRAM enables a READ or WRITE

command to be issued after theACTIVATE command for that bank

prior to t_RCD(MIN). The only restriction is ACTIVATE to READ or

WRITE + AL ≥ t_RCD(MIN) must be satisﬁed. Assuming t_RCD(MIN)

To meet the 34Ω speciﬁcation, the output drive strength must be

set to 34Ω during initialization. To obtain a calibrated output driver

impedance after power-up, the DDR3 SDRAM needs a calibration

command that is part of the initialization and reset procedure

= CL, a typical application using this feature sets AL = CL - 1t_CK

=

t

_RCD(MIN) - 1 t_CK. The READ or WRITE command is held for the

OUTPUT ENABLE/DISABLE

The OUTPUT ENABLE function is deﬁned by MR1[12], as shown

in Figure 7. When enabled (MR1[12] = 0), all outputs (DQ, DQS,

DQS#) function when in the normal mode of operation. When

time of the AL before it is released internally to the DDR3 SDRAM

device. READ latency (RL) is controlled by the sum of the AL and

CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum

of CAS WRITE latency and AL, WL = AL + CWL.

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PRELIMINARY

FIGURE 6 – READ LATENCY

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

READ

NOP

Command

AL = 0, CL = 6

DQS, DQS#

DQ

DI

n

DI

n + 1

n + 2

n + 3

n + 4

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK#

CK

Command

NOP

READ

NOP

AL = 0, CL = 8

DQS, DQS#

DQ

DI

n

NOTES:

1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible.

2. Shown with nominal t_DQSCKand nominal t_DSDQ

Transitioning Data

Don’t Care

.

automatically from 1X to 2X when temperature exceeds 85°C.

This enables the user to operate the DRAM beyond the 85°C

temperature limit up to 95°C for military grade devices while in

self refresh mode.

MODE REGISTER 2 (MR2)

The mode register 2 (MR2) controls additional functions and

features not available in the other mode registers. These additional

functions are CAS WRITE latency (CWL), AUTO SELF REFRESH

(ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC

ODT (R_{TT_WR}). These functions are controlled via the bits shown in

Figure 9. The MR2 is programmed via the MRS command and will

retain the stored information until it is programmed again or until the

device loses power. Reprogramming the MR2 register will not alter

the contents of the memory array, provided it is performed correctly.

The MR2 register must be loaded when all banks are idle and not

data bursts are in progress, and the controller must wait the speciﬁed

time t_MRDand t_MODbefore initiating a subsequent operation.

SELF REFRESH TEMPERATURE (SRT)

Mode register MR2[7] is used to disable/enable the SRT function.

When SRT is disabled, the self refresh mode’s refresh rate is

assumed to be at the 85°C max temperature (sometimes referred

to as 1X refresh rate). In the disabled mode, SRT requires the user

to ensure the DRAM never exceeds a temperature of 85°C while

in self refresh mode unless the user enables ASR.

When SRT is enabled, the DRAM self refresh is changed internally

from 1X to 2X, regardless of the temperature. This enables the

user to operate the DRAM beyond 85°C up to 95°C while in self

refresh mode. The standard self refresh current test speciﬁes test

conditions to 85°C only, meaning if SRT is enabled, the standard

self refresh current speciﬁcations do not apply.

CAS WRITE LATENCY (CWL)

CWL is deﬁned by MR2[5:3] and is the delay, in clock cycles, from

the releasing of the internal write to the latching of the ﬁrst data in.

CWL must be correctly set to the corresponding operating clock

frequency (see Figure 9). The overall WRITE latency (WL) is equal

to CWL + AL (Figure 10)

SRT vs. ASR

If the temperature limit of 85°C is not exceeded then neither

SRT nor ASR is required, and both can be disabled throughout

operation. However, if the temperature exceeds 85°C (but lower

than 95°C), the user is required to provide a 2X refresh rate during

(manual) refresh and to enable either the SRT or theASR to ensure

self refresh is performed at the 2X rate. Beyond 95°C , neither SRT

or ASR are functional and user is required to provide 4X refresh

rate using (manual) refresh commands.

AUTO SELF REFRESH (ASR)

Mode register MR2[6] is used to disable/enable the ASR function.

When ASR is disabled, the self refresh mode’s refresh rate is

assumed to be at the maximum temperature of 85°C (sometimes

referred to as 1X refresh rate). In the disabled mode,ASR requires

the user to ensure the DRAM never exceeds a temperature of 85°C

while in self refresh unless the user enables the SRT feature listed

below when temperature is between 85°C and 95°C.

SRT forces the DRAM to switch the internal self refresh rate from

1X to 2X. Self refresh is performed at the 2X refresh rate regardless

of the temperature.

Enabling ASR assumes the DRAM self refresh rate is changed

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PRELIMINARY

ASR automatically switches the DRAM’s internal self refresh rate

from 1X to 2X. However, while in self refresh mode, ASR enables

the refresh rate to automatically adjust between 1X to 2X over the

supported temperature range. One other disadvantage with ASR is

the DRAM cannot always switch from a 1X to a 2X refresh rate at

an exact temperature of 85°C. Although the DRAM will support data

integrity when it switches from a 1X to a 2X refresh rate, it may switch

at a lower temperature than 85°C. Since only one mode is necessary,

SRT and ASR cannot be enabled at the same time.

Dynamic ODT is only applicable during WRITE cycles. If ODT

(RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted.

RTT_NOM and RTT_WR can be used independent of one

other. Dynamic ODT is not available during write leveling mode,

regardless of the state of ODT (RTT_NOM).

MODE REGISTER 3 (MR3)

The mode register 3 (MR3) controls additional functions and

features not available in the other mode registers. Currently

deﬁned is the MULTIPURPOSE REGISTER (MPR). This function is

controlled via the bits shown in Figure 11. The MR3 is programmed

via the LOAD MODE command and retains the stored information

until it is programmed again or until the device loses power.

Reprogramming the MR3 register will not alter the contents of the

memory array, provided it is performed correctly. The MR3 register

must be loaded when all banks are idle and no data bursts are in

progress, and the controller must wait the speciﬁed time t_MRDand

For military grade devices (max temperature of +125°C), it is

recommended to use manual 4X refresh rate.

DYNAMIC ODT

The dynamic ODT (RTT_WR) feature is deﬁned by MR2[10, 9].

Dynamic ODT is enabled when a value is selected. This new DDR3

SDRAM feature enables the ODT termination value to change

without issuing an MRS command, essentially changing the ODT

termination “on-the-ﬂy.”

t_MODbefore initiating a subsequent operation.

With dynamic ODT (RTT_WR) enabled, the DRAM switches

from normal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when

beginning a WRITE burst and subsequently switches back to ODT

(RTT_NOM) at the completion of the WRITE burst. If RTT_NOM

is disabled, the RTT_NOM value will be High-Z. Special timing

parameters must be adhered to when dynamic ODT (RTT_WR)

is enabled: ODTLCNW, ODTLCNW4, ODTLCNW8, ODTH4,

MULTIPURPOSE REGISTER (MPR)

The MULTIPURPOSE REGISTER function is used to output a

predeﬁned system timing calibration bit sequence. Bit 2 is the

master bit that enables or disables access to the MPR register,

and bits 1 and 0 determine which mode the MPR is placed in. The

basic concept of the multipurpose register is shown in Figure 12.

ODTH8, and t_ADC

.

FIGURE 7 – MODE REGISTER 1 (MR1) DEFINITION

BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

BA2

Address bus

18 17 16 15 14 13 12 11 10

9

R_TT

8

7

6

R_TT

5

ODS

4

AL

3

2

R_TT

1

0

Mode register 1 (MR1)

0¹

0

1

0¹

1

0¹

TDQS 0¹

0¹WL

ODS DLL

Q Off

M0

0

DLL Enable

Enable (normal)

Disable

M17 M16

Mode Register

M12

Q Off

M11

TDQS

Disabled

Enabled

0

1

0

1

0

1

Mode register set 0 (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

1

0

1

Enabled

Disabled

0

1

M5 M1 Output Drive Strength

0

1

0

1

0

1

RZQ/6 (40Ω [NOM])

RZQ/7 (34Ω [NOM])

Reserved

R_{TT, nom}(ODT)²

Non-Writes

R_{TT, nom}(ODT)³

Writes

M7

Write Levelization

Disable (normal)

Enable

0

1

M9 M6 M2

R

_{TT, nom}disabled

R_{TT, nom}disabled

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

RZQ/4 (60Ω [NOM]) RZQ/4 (60Ω [NOM])

RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM])

RZQ/6 (40Ω [NOM]) RZQ/6 (40Ω [NOM])

Additive Latency (AL)

Disabled (AL = 0)

AL = CL - 1

M4 M3

0

1

0

1

0

1

RZQ/12 (20Ω [NOM])

RZQ/8 (30Ω [NOM])

Reserved

n/a

AL = CL - 2

Reserved

NOTES:

1. R1[18, 15:13, 10, 8] are reserved for future use and must be programmed to 0.

2. During write leveling, if MR1[7] and MR1[12] are 1, then all R_{TT, nom}values are available for use.

3. During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only R_{TT, nom}write values are available for use.

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PRELIMINARY

If MR3[2] is a “0,” then the MPR access is disabled, and the

DRAM operates in normal mode. However, if MR3[2] is a “1,” then

the DRAM no longer outputs normal read data but outputs MPR

data as deﬁned by MR3[0, 1]. If MR3[0, 1] is equal to “00,” then a

predeﬁned read pattern for system calibration is selected.

NO OPERATION (NOP)

The NOP command (CS# LOW) prevents unwanted commands

from being registered during idle or wait states. Operations already

in progress are not affected.

To enable the MPR, the MRS command is issued to MR3, and

MR3[2] = 1 (see Table 5). Prior to issuing the MRS command, all

banks must be in the idle state (all banks are precharged, and

ZQ CALIBRATION

ZQ CALIBRATION LONG (ZQCL)

The ZQCLcommand is used to perform the initial calibration during

a power-up initialization and reset sequence. This command may

be issued at any time by the controller depending on the system

environment. The ZQCL command triggers the calibration engine

inside the DRAM.After calibration is achieved, the calibrated values

are transferred from the calibration engine to the DRAM I/O, which

are reﬂected as updated RON and ODT values.

t

_RPis met). When the MPR is enabled, any subsequent READ or

RDAP commands are redirected to the multipurpose register. The

resulting operation when either a READ or a RDAP command is

issued, is deﬁned by MR3[1:0] when the MPR is enabled (see Table

6). When the MPR is enabled, only READ or RDAP commands are

allowed until a subsequent MRS command is issued with the MPR

disabled (MR3[2] = 0). Power-down mode, self refresh, and any

other nonREAD/RDAP command is not allowed during MPR enable

mode. The RESET function is supported during MPR enable mode.

The DRAM is allowed a timing window deﬁned by either t_ZQINIT

or t_ZQOPERto perform the full calibration and transfer of values.

When ZQCL is issued during the initialization sequence, the timing

parameter t_ZQINITmust be satisﬁed. When initialization is complete,

subsequent ZQCLcommands require the timing parameter t_ZQOPER

to be satisﬁed.

MPR FUNCTIONAL DESCRIPTION

The MPR JEDEC deﬁnition enables either a prime DQ (DQ0 on a

x4 and a x8; on a x16, DQ0 = lower byte and DQ8 = upper byte)

to output the MPR data with the remaining DQs driven LOW, or for

all DQs to output the MPR data . The MPR readout supports ﬁxed

READ burst and READ burst chop (MRS and OTF via A12/BC#)

with regular READ latencies and AC timings applicable, provided

the DLL is locked as required.

ZQ CALIBRATION SHORT (ZQCS)

The ZQCS command is used to perform periodic calibrations to

account for small voltage and temperature variations. The shorter

timing window is provided to perform the reduced calibration and

transfer of values as deﬁned by timing parameter t_ZQCS. A ZQCS

command can effectively correct a minimum of 0.5 percent RON

and RTT impedance error within 64 clock cycles, assuming the

maximum sensitivities.

MPR addressing for a valid MPR read is as follows:

 A[1:0] must be set to “00” as the burst order is ﬁxed per

nibble

 A2 selects the burst order:

ACTIVATE

• BL8, A2 is set to “0,” and the burst order is ﬁxed to 0, 1,

The ACTIVATE command is used to open (or activate) a row in a

particular bank for a subsequent access. The value on the BA[2:0]

inputs selects the bank, and the address provided on inputsA[n:0]

selects the row. This row remains open (or active) for accesses

until a PRECHARGE command is issued to that bank.

2, 3, 4, 5, 6, 7

 For burst chop 4 cases, the burst order is switched on the

nibble base and:

• A2 = 0; burst order = 0, 1, 2, 3

• A2 = 1; burst order = 4, 5, 6, 7

A PRECHARGE command must be issued before opening a

different row in the same bank.

 Burst order bit 0 (the ﬁrst bit) is assigned to LSB, and burst

order bit 7 (the last bit) is assigned to MSB

READ

 A[9:3] are a “Don’t Care”

 A10 is a “Don’t Care”

 A11 is a “Don’t Care”

The READ command is used to initiate a burst read access to

an active row. The address provided on inputs A[2:0] selects the

starting column address depending on the burst length and burst

type selected. The value on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the READ burst.

If auto precharge is not selected, the row will remain open for

subsequent accesses. The value on input A12 (if enabled in the

mode register) when the READ command is issued determines

whether BC4 (chop) or BL8 is used. After a READ command is

issued, the READ burst may not be interrupted. A summary of

READ commands is shown in Table 9.

 A12: Selects burst chop mode on-the-ﬂy, if enabled within

MR0

 A13 is a “Don’t Care”

 BA[2:0] are a “Don’t Care”

DESELECT (DES)

The DES command (CS# HIGH) prevents new commands from

being executed by the DRAM. Operations already in progress are

not affected.

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 8 – READ LATENCY (AL = 5, CL = 6)

BC4

T2

T11

T0

T1

T6

T12

T13

T14

CK#

CK

Command

ACTIVEn

READn

NOP

t

RCD (MIN)

DQS, DQS#

AL = 5

CL = 6

DO

n

DO

DQ

n + 1

n + 2

n + 3

RL = AL + CL = 11

Indicates A Break in

Time Scale

Transitioning Data

Don’t Care

analogous to CAS#- before-RAS# (CBR) refresh or auto refresh.

This command is nonpersistent, so it must be issued each time

a refresh is required. The addressing is generated by the internal

refresh controller. This makes the address bits a “Don’t Care” during

a REFRESH command. The DRAM requires REFRESH cycles

at an average interval (t_REFI). Refer to “AC Timing Parameters”

table for t_REFI(MAX) which depends of temperature. To allow

for improved efﬁciency in scheduling and switching between

tasks, some ﬂexibility in the absolute refresh interval is provided.

A maximum of eight REFRESH commands can be posted to

any given DRAM, meaning that the maximum absolute interval

between any REFRESH command and the next REFRESH

command is nine times the maximum average interval refresh rate.

The REFRESH period begins when the REFRESH command is

registered and ends t_RFC(MIN) later.

WRITE

The WRITE command is used to initiate a burst write access to

an active row. The value on the BA[2:0] inputs selects the bank.

The value on inputA10 determines whether or not auto precharge

is used. The value on input A12 (if enabled in the MR) when the

WRITE command is issued determines whether BC4 (chop) or

BL8 is used. The WRITE command summary is shown in Table 10.

Input data appearing on the DQ is written to the memory array

subject to the DM input logic level appearing coincident with the

data. If a given DM signal is registered LOW, the corresponding

data will be written to memory. If the DM signal is registered HIGH,

the corresponding data inputs will be ignored and a WRITE will

not be executed to that byte/column location.

PRECHARGE

SELF REFRESH

The PRECHARGE command is used to deactivate the open row

in a particular bank or in all banks. The bank(s) are available

for a subsequent row access a speciﬁed time (t_RP) after the

PRECHARGE command is issued, except in the case of concurrent

auto precharge. A READ or WRITE command to a different bank

is allowed during concurrent auto precharge as long as it does not

interrupt the data transfer in the current bank and does not violate

any other timing parameters. Input A10 determines whether one

or all banks are precharged. In the case where only one bank is

precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0]

are treated as “Don’t Care.” After a bank is precharged, it is in

the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank. A PRECHARGE command

is treated as a NOP if there is no open row in that bank (idle

state) or if the previously open row is already in the process of

precharging. However, the precharge period is determined by the

last PRECHARGE command issued to the bank.

The SELF REFRESH command is used to retain data in the DRAM,

even if the rest of the system is powered down. When in the self

refresh mode, the DRAM retains data without external clocking.

The self refresh mode is also a convenient method used to enable/

disable the DLL (see “DLL Disable Mode”) as well as to change the

clock frequency within the allowed synchronous operating range

(see “Input Clock Frequency Change”). All power supply inputs

(including V_REFCAand V_REFDQ) must be maintained at valid levels

upon entry/exit and during SELF REFRESH operation. For SELF

REFRESH limitations see SRT vs ASR on pg. 14.

DLL DISABLE MODE

If the DLL is disabled by the mode register (MR1[0] can be

switched during initialization or later), the DRAM is targeted, but

not guaranteed, to operate similarly to the normal mode with a

few notable exceptions:

 The DRAM supports only one value of CAS latency (CL =

REFRESH

6) and one value of CAS WRITE latency (CWL = 6).

REFRESH is used during normal operation of the DRAM and is

continued on page 16

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W3J512M32K-XBX

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PRELIMINARY

FIGURE 9 – MODE REGISTER 2 (MR2) DEFINITION

A15 A14 A13

BA2 BA1 BA0

A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address bus

18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

CWL

3

2

1

0

Mode register 2 (MR2)

0¹

1

0

0¹0¹0¹0¹0¹

0¹SRTASR

0¹0¹0¹

R_TT(WR)

M17 M16

Mode Register

M7 Self Refresh Temperature

M5 M4 M3

CAS Write Latency (CWL)

5 CK (t_CK≥ 2.5ns)

0

1

0

1

0

1

Mode register set 0 (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

0

1X refresh rate (+85°C

max temperature)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6 CK (2.5ns > t_CK≥ 1.875ns)

7 CK (1.875ns > t_CK≥ 1.5ns)

8 CK (1.5ns > t_CK≥ 1.25ns)

9 CK (1.25ns > t_CK≥ 1.071ns)

10 CK (1.071ns > t_CK≥ 0.938ns)

Reserved

1

2X refresh rate (+85°C to

95°C temperature)

Auto Self Refresh

Dynamic ODT

(R_TT(WR)

M6

0

(Optional)

)

M10 M9

Reserved

Disabled: Manual

Enabled: Automatic

R_TT(WR)disabled

RZQ/4

0

1

0

1

0

1

RZQ/2

Reserved

NOTE:

1. MR2[18, 15:11, 8, and 2:0] are reserved for future use and must all be programmed to 0.

FIGURE 10 – CAS WRITE LATENCY

BC4

T11

T0

T1

T2

T6

T12

T13

T14

CK#

CK

ACTIVEn

WRITEn

NOP

Command

t

RCD (MIN)

DQS, DQS#

AL = 5

CWL = 6

DI

n

DI

DQ

n + 1

n + 2

n + 3

WL = AL + CWL = 11

Indicates A Break in

Time Scale

Transitioning Data

Don’t Care

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W3J512M32K-XBX

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PRELIMINARY

 DLL disable mode affects the read data clock-to-data strobe

relationship (t_DQSCK), but not the read data-to-data strobe

relationship (t_DQSQ, t_QH). Special attention is needed to line

the read data up with the controller time domain when the

DLL is disabled.

AZQCLcommand should be issued with the appropriate timings

met as well.

The clock frequency range for the DLL disable mode is speciﬁed

by the parameter t_{CKDLL_DIS}. Due to latency counter and timing

restrictions, only CL = 6 and CWL = 6 are supported.

 In normal operation (DLL on), t_DQSCKstarts from the rising

clock edge AL + CL cycles after the READ command. In

DLL disable mode, t_DQSCKstarts AL + CL - 1 cycles after the

READ command. Additionally, with the DLL disabled, the

DLL disable mode will affect the read data clock to data strobe

relationship (t_DQSCK) but not the data strobe to data relationship

(t_DQSQ, t_QH). Special attention is needed to line up read data to the

controller time domain.

value of t_DQSCKcould be larger than t_CK

.

Compared to the DLL on mode where t_DQSCKstarts from the rising

clock edge AL + CL cycles after the READ command, the DLL

disable mode t_DQSCKstarts AL + CL - 1 cycles after the READ

command.

The ODT feature is not supported during DLL disable mode

(including dynamic ODT). The ODT resistors must be disabled

by continuously registering the ODT ball LOW by programming

RTT_NOM MR1[9, 6, 2] and RTT_WR MR2[10, 9] to “0” while in

the DLL disable mode.

WRITE operations function similarly between the DLL enable and

DLL disable modes; however, ODT functionality is not allowed with

DLL disable mode.

Specific steps must be followed to switch between the DLL

enable and DLL disable modes due to a gap in the allowed clock

rates between the two modes (t_{CK [AVG]MAX}and t_{CK [DLL disable] MIN}

,

INPUT CLOCK FREQUENCY CHANGE

respectively). The only time the clock is allowed to cross this clock

rate gap is during self refresh mode. Thus, the required procedure

for switching from the DLL enable mode to the DLL disable mode

is to change frequency during self refresh:

When the DDR3 SDRAM is initialized, it requires the clock to be

stable during most normal states of operation. This means that

after the clock frequency has been set to the stable state, the clock

period is not allowed to deviate except what is allowed for by the

clock jitter and spread spectrum clocking (SSC) speciﬁcations.

1. Starting from the idle state (all banks are precharged, all timings

are fulﬁlled, ODT is turned off, and RTT_NOM and RTT_WR

are High-Z), set MR1[0] to “1” to disable the DLL.

The input clock frequency can be changed from one stable clock

rate to another under two conditions: self refresh mode and

precharge power-down mode. Outside of these two modes, it is

illegal to change the clock frequency. For the self refresh mode

condition, when the DDR3 SDRAM has been successfully placed

into self refresh mode and t_CKSREhas been satisﬁed, the state of

the clock becomes a “Don’t Care.” When the clock becomes a

“Don’t Care,” changing the clock frequency is permissible, provided

the new clock frequency is stable prior to t_CKSRX. When entering

and exiting self refresh mode for the sole purpose of changing

the clock frequency, the self refresh entry and exit speciﬁcations

must still be met.

2. Enter self refresh mode after t_MODhas been satisﬁed.

3. After t_CKSREis satisﬁed, change the frequency to the desired

clock rate.

4. Self refresh may be exited when the clock is stable with the

new frequency for t_CKSRX. After t_XSis satisﬁed, update the mode

registers with appropriate values.

5. The DRAM will be ready for its next command in the DLLdisable

mode after the greater of t_MRDor t_MODhas been satisﬁed.AZQCL

command should be issued with appropriate timings met as well.

A similar procedure is required for switching from the DLL disable

mode back to the DLL enable mode. This also requires changing

the frequency during self refresh mode.

The precharge power-down mode condition is when the DDR3

SDRAM is in precharge power-down mode (either fast exit

mode or slow exit mode). Either ODT must be at a logic LOW or

RTT_NOM and RTT_WR must be disabled via MR1 and MR2.

This ensures RTT_NOM and RTT_WR are in an off state prior

to entering precharge power-down mode, and CKE must be at a

logic LOW. A minimum of t_CKSREmust occur after CKE goes LOW

before the clock frequency can change. The DDR3 SDRAM input

clock frequency is allowed to change only within the minimum and

maximum operating frequency speciﬁed for the particular speed

grade (t_{CK [AVG]MIN}to t_{CK [AVG]MAX}). During the input clock frequency

change, CKE must be held at a stable LOW level. When the input

clock frequency is changed, a stable clock must be provided to

the DRAM t_CKSRXbefore precharge power-down may be exited.

After precharge power-down is exited and t_XPhas been satisﬁed,

the DLL must be reset via the MRS. Depending on the new clock

frequency, additional MRS commands may need to be issued.

During the DLLlock time, RTT_NOM and RTT_WR must remain in

an off state. After the DLL lock time, the DRAM is ready to operate

with a new clock frequency.

1. Starting from the idle state (all banks are precharged, all timings

are fulﬁlled, ODT is turned off, and RTT_NOM and RTT_WR

are High-Z), enter self refresh mode.

2. After t_CKSREis satisﬁed, change the frequency to the new clock

rate.

3. Self refresh may be exited when the clock is stable with the

new frequency for t_CKSRX. After t_XSis satisﬁed, update the mode

registers with the appropriate values.At a minimum, set MR1[0]

to “0” to enable the DLL. Wait t_MRD, then set MR0[8] to “1” to

enable DLL RESET.

4. After another t_MRDdelay is satisﬁed, then update the remaining

mode registers with the appropriate values.

5. The DRAM will be ready for its next command in the DLL

enable mode after the greater of t_MRDor t_MODhas been satisﬁed.

However, before applying any command or function requiring a

locked DLL, a delay of t_DLLKafter DLL RESET must be satisﬁed.

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 11 – MODE REGISTER 3 (MR3) DEFINITION

BA2 BA1 BA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address bus

18 17 16 15 14 13 12 11 10

9

8

1

7

1

6

5

4

1

3

1

2

1

0

Mode register 3 (MR3)

MPR READ Function

1

0

1

0

MPR MPR_RF

0

Mode Register

M2

MPR Enable

M17 M16

M1 M0

2

3

Mode register set (MR0)

Mode register set 1 (MR1)

Mode register set 2 (MR2)

Mode register set 3 (MR3)

0

1

Normal DRAM operations

Dataflow from MPR

0

1

0

1

0

1

0

1

0

1

0

1

Predefined pattern

Reserved

NOTES:

1. MR3[18 and 15:3] are reserved for future use and must all be programmed to 0.

2. When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored.

3. Intended to be used for READ synchronization.

MPR READ PREDEFINED PATTERN

MODE REGISTER SET (MRS)

The predetermined read calibration pattern is a ﬁxed pattern of 0,

1, 0, 1, 0, 1, 0, 1. The following is an example of using the read

out predetermined read calibration pattern. The example is to

perform multiple reads from the multipurpose register in order to

do system level read timing calibration based on the predetermined

and standardized pattern.

The mode registers are loaded via inputs BA[2:0],A[13:0]. BA[2:0]

determine which mode register is programmed:

 BA2 = 0, BA1 = 0, BA0 = 0 for MR0

 BA2 = 0, BA1 = 0, BA0 = 1 for MR1

 BA2 = 0, BA1 = 1, BA0 = 0 for MR2

 BA2 = 0, BA1 = 1, BA0 = 1 for MR3

The following protocol outlines the steps used to perform the read

calibration:

The MRS command can only be issued (or reissued) when all

banks are idle and in the precharged state (t_RPis satisﬁed and no

data bursts are in progress). The controller must wait the speciﬁed

time t_MRDbefore initiating a subsequent operation such as an

ACTIVATE command. There is also a restriction after issuing an

MRS command with regard to when the updated functions become

available. This parameter is speciﬁed by t_MOD. Violating either of

these requirements (t_MOD, T_MRD) will result in unspeciﬁed operation.

 Precharge all banks

 After t_RPis satisﬁed, set MRS, MR3[2] = 1 and MR3[1:0]

= 00. This redirects all subsequent reads and loads the

predeﬁned pattern into the MPR. As soon as t_MRDand t_MOD

are satisﬁed, the MPR is available

 Data WRITE operations are not allowed until the MPR

returns to the normal DRAM state

 Issue a read with burst order information (all other address

pins are “Don’t Care”):

• A[1:0] = 00 (data burst order is ﬁxed starting at nibble)

• A2 = 0 (for BL8, burst order is ﬁxed as 0, 1, 2, 3, 4, 5, 6, 7)

• A12 = 1 (use BL8)

 After RL = AL + CL, the DRAM bursts out the predeﬁned

read calibration pattern (0, 1, 0, 1, 0, 1, 0, 1)

 The memory controller repeats the calibration reads until

read data capture at memory controller is optimized

 After the last MPR READ burst and after t_MPRRhas been

satisﬁed, issue MRS, MR3[2] = 0, and MR3[1:0] = “Don’t

Care” to the normal DRAM state. All subsequent read and

write accesses will be regular reads and writes from/to the

DRAM array

 When t_MRDand t_MODare satisﬁed from the last MRS, the

regular DRAM commands (such as activate a memory bank

for regular read or write access) are permitted

(continued on page 19)

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 12 – MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM

Memory core

MR3[2] = 0 (MPR off)

Multipurpose register

predefined data for READs

MR3[2] = 1 (MPR on)

DQ, DM, DQS, DQS#

NOTES:

1. A predeﬁned data pattern can be read out of the MPR with an external READ command.

2. MR3[2] deﬁnes whether the data ﬂow comes from the memory core or the MPR. When the

data ﬂow is deﬁned, the MPR contents can be read out continuously with a regular READ or

RDAP command.

TABLE 5 – MPR FUNCTIONAL DESCRIPTION OF MR3 BITS

MR3(2)

MPR

MR3(1:0)

Function

MPR Read Function

Normal operation, no MPR transaction

0

1

"Don't Care"

All subsequent READs come from the DRAM memory array

All subsequent WRITEs go to the DRAM memory array

Enable MPR mode, subsequent READ/RDAP commands deﬁned by bits

A(1:0)

1 and 2

TABLE 6 – MPR READOUTS AND BURST ORDER BIT MAPPING

MR3(2)

MR3(1:0)

Functions

Burst Length

Read A[2:0]

Function

Burst order: 0 ,1, 2, 3, 4, 5, 6, 7

Predeﬁned pattern: 0, 1, 0, 1, 0, 1, 0, 1

BL8

000

Read predeﬁned

pattern for

system

Burst order: 0 ,1, 2, 3

Predeﬁned pattern: 0, 1, 0, 1

1

00

BC4

000

100

calibration

Burst order: 4, 5, 6, 7

Predeﬁned pattern: 0, 1, 0, 1

1

01

10

11

RFU

n/a

NOTE:

1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent.

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

still applies. The t_FAW(MIN) parameter applies, regardless of the

number of banks already opened or closed.

ZQ CALIBRATION OPERATION

The ZQ CALIBRATION command is used to calibrate the DRAM

output drivers (RON) and ODT values (RTT) over process, voltage,

and temperature, provided a dedicated 240Ω (±1 percent) external

resistor is connected from the DRAM’s ZQ ball to V_SSQ. DDR3

SDRAM need a longer time to calibrate RON and ODT at power-

up initialization and self refresh exit and a relatively shorter time

to perform periodic calibrations. DDR3 SDRAM deﬁnes two ZQ

CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and

ZQ CALIBRATION SHORT (ZQCS).

READ OPERATION

READ bursts are initiated with a READ command. The starting

column and bank addresses are provided with the READ command

and auto precharge is either enabled or disabled for that burst

access. If auto precharge is enabled, the row being accessed is

automatically precharged at the completion of the burst. If auto

precharge is disabled, the row will be left open after the completion

of the burst.

All banks must be precharged and t_RPmust be met before ZQCLor

ZQCS commands can be issued to the DRAM. No other activities

(other than another ZQCL or ZQCS command may be issued to

another DRAM) can be performed on the DRAM channel by the

controller for the duration of t_ZQINITor t_ZQOPER. The quiet time on

the DRAM channel helps accurately calibrate RON and ODT.After

DRAM calibration is achieved, the DRAM should disable the ZQ

ball’s current consumption path to reduce power.

During READ bursts, the valid data-out element from the starting

column address is available READ latency (RL) clocks later. RL

is deﬁned as the sum of POSTED CAS ADDITIVE latency (AL)

and CAS latency (CL) (RL = AL + CL). The value of AL and CL is

programmable in the mode register via the MRS command. Each

subsequent data-out element will be valid nominally at the next

positive or negative clock edge (that is, at the next crossing of

CK and CK#).

ZQ CALIBRATION commands can be issued in parallel to DLL

RESET and locking time. Upon self refresh exit, an explicit ZQCL

is required if ZQ calibration is desired.

DQS, DQS# is driven by the DRAM along with the output data. The

initial low state on DQS and HIGH state on DQS# is known as the

READ preamble (t_RPRE). The low state on DQS and the HIGH state

on DQS#, coincident with the last data-out element, is known as

the READ postamble (t_RPST). Upon completion of a burst, assuming

no other commands have been initiated, the DQ will go High-Z.

ACTIVATE OPERATION

Before any READ or WRITE commands can be issued to a bank

within the DRAM, a row in that bank must be opened (activated).

This is accomplished via the ACTIVATE command, which selects

both the bank and the row to be activated.

Data from any READ burst may be concatenated with data from a

subsequent READ command to provide a continuous ﬂow of data.

The ﬁrst data element from the new burst follows the last element

of a completed burst. The new READ command should be issued

After a row is opened with an ACTIVATE command, a READ or

WRITE command may be issued to that row, subject to the t_RCD

speciﬁcation. However, if the additive latency is programmed

correctly, a READ or WRITE command may be issued prior to t_RCD

(MIN). In this operation, the DRAM enables a READ or WRITE

command to be issued after theACTIVATE command for that bank,

but prior to t_RCD(MIN) with the requirement that (ACTIVATE-to-

READ/WRITE) + AL ≥ t_RCD(MIN) (see "POSTED CAS ADDITIVE

Latency (AL)"). t_RCD(MIN) should be divided by the clock period

and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVATE command on which a READ or

WRITE command can be entered. The same procedure is used

to convert other speciﬁcation limits from time units to clock cycles.

t_CCDcycles after the ﬁrst READ command. If BC4 is enabled, t_CCD

must still be met which will cause a gap in the data output. DDR3

SDRAM do not allow interrupting or truncating any READ burst.

Data from any READ burst must be completed before a subsequent

WRITE burst is allowed. To ensure the read data is completed

before the write data is on the bus, the minimum READ-to-WRITE

timing is RL + t_CCD- WL + 2t_CK

.

AREAD burst may be followed by a PRECHARGE command to the

same bank provided auto precharge is not activated. The minimum

READ-to-PRECHARGE command spacing to the same bank is

four clocks and must also satisfy a minimum analog time from the

READ command. This time is called t_RTP(READ-to-PRECHARGE).

t_RTPstarts AL cycles later than the READ command. Following

the PRECHARGE command, a subsequent command to the

same bank cannot be issued until t_RPis met. The PRECHARGE

command followed by another PRECHARGE command to the

same bank is allowed. However, the precharge period will be

determined by the last PRECHARGE command issued to the bank.

When at least one bank is open, any READ-to-READ command

delay or WRITE-to-WRITE command delay is restricted to t_CCD

(MIN).

A subsequent ACTIVATE command to a different row in the

same bank can only be issued after the previous active row has

been closed (precharged). The minimum time interval between

successive ACTIVATE commands to the same bank is deﬁned

If A10 is HIGH when a READ command is issued, the READ with

auto precharge function is engaged. The DRAM starts an auto

precharge operation on the rising edge which is AL + t_RTPcycles

after the READ command. DRAM support a t_RASlockout feature. If

by t_RC

.

AsubsequentACTIVATE command to another bank can be issued

while the ﬁrst bank is being accessed, which results in a reduction

of total row-access overhead. The minimum time interval between

successive ACTIVATE commands to different banks is deﬁned

by t_RRD. No more than four bank ACTIVATE commands may be

issued in a given t_FAW(MIN) period, and the t_RRD(MIN) restriction

t

_RAS(MIN) is not satisﬁed at the edge, the starting point of the auto

precharge operation will be delayed until t_RAS(MIN) is satisﬁed. If

_RTP(MIN) is not satisﬁed at the edge, the starting point of the auto

t

precharge operation will be delayed until t_RTP(MIN) is satisﬁed.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 7 – TRUTH TABLE - DDR3 COMMANDS

CKE

BA2

BA1

BA0

A11,

A9-A0

Function

Symbol

CS#

RAS#

CAS#

WE#

An

A12

A10

Notes

MODE REGISTER SET

REFRESH

MRS

REF

SRE

H

L

BA

V

OP Code

H

V

SELF-REFRESH Entry

H

L

H

L

V

H

L

V

H

V

H

L

V

6

SELF-REFRESH Exit

SRX

L

H

V

6, 7

Single bank precharge

All banks PRECHARGE

Bank activate

PRE

PREA

ACT

H

BA

V

L

V

L

H

L

H

BA

Row address (RA)

BL8MRS,

BC4MRS

WR

H

L

H

L

BA

RFU

V

L

CA

8

WRITE

BC4OTF

WRS4

WRS8

H

L

H

L

BA

RFU

L

CA

8

BL8OTF

H

BL8MRS,

WRAP

H

L

H

L

BA

RFU

V

H

CA

8

WRITE

with auto

precharge

BC4MRS

BC4OTF

BL8OTF

WRAPS4

WRAPS8

H

L

H

L

BA

RFU

L

H

CA

8

H

BL8MRS

BC4MRS

RD

H

L

H

L

H

BA

RFU

V

L

CA

8

READ

BC4OTF

BL8OTF

RDS4

RDS8

H

L

H

L

H

BA

RFU

L

CA

8

H

BL8MRS

BC4MRS

RDAP

H

L

H

L

H

BA

RFU

V

H

CA

8

READ

with auto

precharge

BC4OTF

BL8OTF

RDAPS4

RDAPS8

NOP

H

L

H

X

H

V

H

V

H

L

H

X

H

V

H

V

L

BA

V

RFU

V

L

H

V

X

H

V

X

CA

V

8

NO OPERATION

L

H

X

H

V

H

V

H

9

Device DESELECT

DES

H

L

X

10

POWER-DOWN entry

PDE

PDX

H

L

V

6

H

L

POWER-DOWN exit

H

6, 11

12

H

L

ZQ CALIBRATION LONG

ZQ QALIBRATION SHORT

ZQCL

ZQCS

H

X

H

L

X

L

NOTES: (notes 1-5 apply to the entire table)

1.

Commands are deﬁned by states of CAS#, RAS#, CAS#, WE# and CKE at the rising edge of

the clock. The MSB of BA, RA and CA are device-density and conﬁguration-dependent.

commands. A NOP will not terminate an operation that is executing.

The DES and NOP commands perform similarly.

10.

11.

12.

2.

RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be

held HIGH during any normal operation.

The power-down mode does not perform any REFRESH operations.

ZQ CALIBRATION LONG is used for either ZQINIT (ﬁrst ZQCL command during initialization)

or ZQ oper(ZQCL command after initialization)

3.

4.

The state of ODT doesn not affect the states described in this table.

Operations apply to the bank deﬁned by the bank address. For MRS, BA selects one of four

mode registers.

5.

6.

7.

8.

“V” means “H” or “L” (a deﬁned logic level), and “X” means “Don’t Care.”

See Table 8 for additional information on CKE transition.

Self refresh exit is asynchronous.

Burst READs or WRITEs cannot be terminated or interrupted. MRS (ﬁxed) and OTF BL/BC

are deﬁned in MR0.

9.

The purpose of the NOP command is to prevent the DRAM from registering any unwanted

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 8 – TRUTH TABLE - CKE ^{1, 2}

CKE

Current State³

Command⁵

Action⁵

Notes

Previous Cycle⁴(n - 1)

Previous Cycle⁴(n )

L

H

L

"Don't Care"

DES or NOP

"Don't Care"

DES or NOP

Maintain power-down

Power-down exit

Power-down

Maintain self refresh

Self refresh exit

Self Refresh

H

Active power-down

entry

Bank(s) Active

H

L

DES or NOP

Reading

Writing

H

L

DES or NOP

Power-down entry

Precharging

Precharge power-

down entry

Refreshing

H

L

DES or NOP

Precharge power-

down entry

H

L

DES or NOP

REFRESH

All banks idle

6

Self Refresh

NOTES:

1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

2. _CKE(MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks.

Thus, after any CKE transition, CKE may not transition from its valid level during the time period of t_IS+ t_CKE(MIN) + t_IH

t

.

3. Current state = The state of the DRAM immediately prior to clock edge n.

4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge.

5. COMMAND is the command registered at the clock edge (must be a legal command as deﬁned in Table 7). Action is a result of COMMAND. ODT does not affect the states described in this table and is not

listed.

6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisﬁed — All self refresh exit and power-down exit parameters are also satisﬁed.

In case the internal precharge is pushed out by t_RTP, t_RPstarts at

the point at which the internal precharge happens (not at the next

rising clock edge after this event). The time from READ with auto

precharge to the next ACTIVATE command to the same bank is

AL + (t_RTP+ t_RP)*, where “*” means rounded up to the next integer.

In any event, internal precharge does not start earlier than four

clocks after the last 8n-bit prefetch.

During power-down entry, if any bank remains open after all in-

progress commands are complete, the DRAM will be in active

power-down mode. If all banks are closed after all in-progress

commands are complete, the DRAM will be in precharge power-

down mode. Precharge power-down mode must be programmed

to exit with either a slow exit mode or a fast exit mode. When

entering precharge power-down mode, the DLL is turned off in

slow exit mode or kept on in fast exit mode.

POWER-DOWN MODE

The DLL remains on when entering active power-down as well.

ODT has special timing constraints when slow exit mode precharge

power-down is enabled and entered.

Power-down is synchronously entered when CKE is registered

LOW coincident with a NOP or DES command. CKE is not

allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or

WRITE operation is in progress. CKE is allowed to go LOW while

any of the other legal operations (such as ROW ACTIVATION,

PRECHARGE, auto precharge, or REFRESH) are in progress.

However, the power-down I_CCspeciﬁcations are not applicable until

such operations have been completed. Depending on the previous

DRAM state and the command issued prior to CKE going LOW,

certain timing constraints must be satisﬁed.

While in either power-down state, CKE is held LOW, RESET# is

held HIGH, and a stable clock signal must be maintained. ODT

must be in a valid state but all other input signals are a “Don’t Care.”

If RESET# goes LOW during power-down, the DRAM will switch

out of power-down mode and go into the reset state. After CKE is

registered LOW, CKE must remain LOW until t_PD(MIN) has been

satisﬁed. The maximum time allowed for powerdown duration is

t_PD(MAX) (9 × t_REFI).

Entering power-down disables the input and output buffers,

excluding CK, CK#, ODT, CKE, and RESET#. NOP or DES

commands are required until t_CPDEDhas been satisﬁed, at which

time all speciﬁed input/output buffers will be disabled. The DLL

should be in a locked state when power-down is entered for the

fastest power-down exit timing. If the DLL is not locked during

power-down entry, the DLL must be reset after exiting power-down

mode for proper READ operation as well as synchronous ODT

operation.

The power-down states are synchronously exited when CKE is

registered HIGH (with a required NOP or DES command). CKE

must be maintained HIGH until t_CKEhas been satisﬁed. A valid,

executable command may be applied after power-down exit

latency, t_XPt_XPDLLhave been satisﬁed.

For certain CKE-intensive operations, for example, repeating a

power-down exit to refresh to power-down entry sequence, the

number of clock cycles between power-down exit and power-

down entry may not be sufﬁcient enough to keep the DLL properly

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

updated. In addition to meeting t_PDwhen the REFRESH command

is used in between power-down exit and power-down entry, two

other conditions must be met. First, t_XPmust be satisﬁed before

issuing the REFRESH command. Second, t_XPDLLmust be satisﬁed

before the next power-down may be entered.

The memory controller may drive DQS LOW and DQS# HIGH after

t_WLDQSENhas been satisﬁed. The controller may begin to toggle

DQS after t_WLMRD(one DQS toggle is DQS transitioning from a

LOW state to a HIGH state with DQS# transitioning from a HIGH

state to a LOW state, then both transition back to their original

states).At a minimum, ODTL on and t_AONmust be satisﬁed at least

one clock prior to DQS toggling.

WRITE LEVELING

After t_WLMRDand a DQS LOW preamble (t_WPRE) have been satisﬁed,

the memory controller may provide either a single DQS toggle or

multiple DQS toggles to sample CK for a given DQS-to-CK skew.

Each DQS toggle must not violate t_DQSL(MIN) and t_DQSH(MIN)

speciﬁcations. t_DQSL(MAX) and t_DQSH(MAX) speciﬁcations are not

applicable during write leveling mode. The DQS must be able to

distinguish the CK’s rising edge within t_WLSand t_WLH. The prime

DQ will output the CK’s status asynchronously from the associated

DQS rising edge CK capture within tWLO. The remaining DQ that

always drive LOW when DQS is toggling must be LOW within

t_WLOEafter the ﬁrst t_WLOis satisﬁed (the prime DQ going LOW).

As previously noted, DQS is an input and not an output during

this process.

For better signal integrity, DDR3 SDRAM memory modules

adopted ﬂy-by topology for the commands, addresses, control

signals, and clocks. Write leveling is a scheme for the memory

controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK

relationship at the DRAM with a simple feedback feature provided

by the DRAM. Write leveling is generally used as part of the

initialization process, if required. For normal DRAM operation, this

feature must be disabled. This is the only DRAM operation where

the DQS functions as an input (to capture the incoming clock) and

the DQ function as outputs (to report the state of the clock). Note

that nonstandard ODT schemes are required.

The memory controller using the write leveling procedure must

have adjustable delay settings on its DQS strobe to align the rising

edge of DQS to the clock at the DRAM pins. This is accomplished

when the DRAM asynchronously feeds back the CK status via the

DQ bus and samples with the rising edge of DQS. The controller

repeatedly delays the DQS strobe until a CK transition from “0” to

“1” is detected. The DQS delay established through this procedure

helps ensure t_DQSS, t_DSS, and t_DSHspeciﬁcations in systems that

use ﬂy-by topology by deskewing the trace length mismatch.

The memory controller will likely sample each applicable prime DQ

state and determine whether to increment or decrement its DQS

delay setting. After the memory controller performs enough DQS

toggles to detect the CK’s “0-to-1” transition, the memory controller

should lock the DQS delay setting for that DRAM. After locking

the DQS setting, leveling for the rank will have been achieved,

and the write leveling mode for the rank should be disabled or

reprogrammed (if write leveling of another rank follows).

When write leveling is enabled, the rising edge of DQS samples

CK, and the prime DQ outputs the sampled CK’s status. The prime

DQ for a x8 conﬁguration is DQ0 with all other DQ[7:1] driving low.

WRITE LEVELING MODE EXIT PROCEDURE

After the DRAM are leveled, they must exit from write leveling

mode before the normal mode can be used. After the last rising

DQS (capturing a “1” at T0), the memory controller should stop

driving the DQS signals after t_WLO(MAX) delay plus enough delay

to enable the memory controller to capture the applicable prime

DQ state (at ~Tb0). The DQ balls become undeﬁned when DQS

no longer remains LOW, and they remain undeﬁned until t_MODafter

the MRS command (at Te1).

The write leveling mode register interacts with other mode registers

to correctly conﬁgure the write leveling functionality. Besides using

MR1[7] to disable/enable write leveling, MR1[12] must be used to

enable/disable the output buffers. The ODT value, burst length,

and so forth need to be selected as well. It should also be noted

that when the outputs are enabled during write leveling mode,

the DQS buffers are set as inputs, and the DQ are set as outputs.

Additionally, during write leveling mode, only the DQS strobe

terminations are activated and deactivated via the ODT ball. The

DQ remain disabled and are not affected by the ODT ball.

The ODT input should be deasserted LOW such that ODTL off

(MIN) expires after the DQS is no longer driving LOW. When ODT

LOW satisﬁes tIS, ODT must be kept LOW (at ~Tb0) until the

DRAM is ready for either another rank to be leveled or until the

normal mode can be used. After DQS termination is switched off,

write level mode should be disabled via the MRS command (at

Tc2). After t_MODis satisﬁed (at Te1), any valid command may be

registered by the DRAM. Some MRS commands may be issued

after t_MRD(at Td1).

WRITE LEVELING PROCEDURE

A memory controller initiates the DRAM write leveling mode by

setting MR1[7] to a “1,” assuming the other programable features

(MR0, MR1, MR2, and MR3) are ﬁrst set and the DLL is fully reset

and locked. The DQ balls enter the write leveling mode going from

a High-Z state to an undeﬁned driving state, so the DQ bus should

not be driven. During write leveling mode, only the NOP or DES

commands are allowed. The memory controller should attempt

to level only one rank at a time; thus, the outputs of other ranks

should be disabled by setting MR1[12] to a “1” in the other ranks.

The memory controller may assert ODT after a t_MODdelay as the

DRAM will be ready to process the ODT transition. ODT should

be turned on prior to DQS being driven LOW by at least ODTL on

delay (WL - 2 t_CK), provided it does not violate the aforementioned

t

_MODdelay requirement.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 9 – READ COMMAND SUMMARY

CKE

BA

[3:0]

A[11,

9:0]

Function

BL8MRS, BC4MRS

Symbol

RD

CS#

L

RAS#

CAS#

WE#

H

An

A12

V

A10

L

H

L

BA

RFU

CA

Read

BC4OTF

BL8OTF

RDS4

L

H

L

RDS8

L

H

L

BL8MRS, BC4MRS

BC4OTF

RDAP

RDAPS4

RDAPS8

L

H

V

H

Read with auto

precharge

L

H

L

H

BL8OTF

L

H

TABLE 10 – WRITE COMMAND SUMMARY

CKE

BA

[3:0]

A[11,

9:0]

Function

Symbol

WR

CS#

L

RAS#

CAS#

WE#

An

A12

V

A10

L

BL8MRS, BC4MRS

BC4OTF

H

L

BA

RFU

CA

Write

WRS4

L

BL8OTF

WRS8

L

H

L

BL8MRS, BC4MRS

BC4OTF

WRAP

WRAPS4

WRAPS8

L

V

H

Write with auto

precharge

L

H

BL8OTF

L

H

TABLE 11 – READ ELECTRICAL CHARACTERISTICS, DLL DISABLE MODE

Parameter

Access window of DQS from CK, CK#

Symbol

Min

Max

Units

t_DQSCK(DLL_DIS)

1

10

ns

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 12 – ABSOLUTE MAXIMUM RATINGS

Symbol

V_CC

Parameter

MIN

-0.4

-55

MAX

1.85

125

Unit

V

Notes

Voltage on V_CCpin relative to V_SS

Voltage on any pin relative to V_SS

Storage temperature

1

V_CCQ

V

V_IN, V_OUT

T_STG

V

°C

NOTES:

1.

V

_CCand V_CCQmust be within 300mV of each other at all times, and V_REFmust not be greater than 0.6 × V_CCQ.When V_CCand V_CCQare less than 500mV, V_REFmay be ≤300mV.

TABLE 13 – DC OPERATING CONDITIONS

All voltages referenced to V_SS

Parameter

Symbol

V_CC

Typical

1.35

Max

1.45

Unit

V

Notes

1, 2, 3

Min

Supply voltage

1.283

I/O Supply voltage

Input leakage current

V_CCQ

1.35

V

Any input 0V ≤ V_IN≤ V_CC, V_REFpin 0V ≤ V_IN≤ 1.1V (All

other pins not under test = 0V)

I_I

-20

-10

-

20

10

μA

V_REFsupply leakage current

V_REFDQ= V_CC/2 or V_REFCA= V_CC/2

I_VREF

4

-

(All other pins not under test = 0V)

NOTES:

1.

2.

3.

V

_CCand V_CCQmust track one another. V_CCQmust be less than or equal to V_CC. V_SS= V_SSQ.

_CCand V_CCQmay include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0Hz to 250 kHz) speciﬁcations. V_CCand V_CCQmust be at same level for valid AC timing parameters.

_CCand V_CCQare tied.

4. The minimum limit requirement is for testing purposes. The leakage current on the V_REFpin should be minimal.

Table 14 – DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS

All voltages are referenced to V_SS

Parameter/Condition

Symbol

Min

V_SS

Nom

n/a

Max

See table 18

V_CC

Units

Notes

V_INlow; DC/commands/address busses

V_IL

V

_INhigh; DC/commands/address busses

V_IH

See table 18

0.49 X V_CC

0.49 x V_CC

Vss

n/a

Input reference voltage command/address bus

I/O reference voltage DQ bus

V_REFCA(DC)

V_REFDQ(DC)

V_REFDQ(sr)

0.5 X V_CC

0.51 X V_CC

0.51 x V_CC

V_CC

1, 2

2, 3

4

I/O reference voltage DQ bus in SELF REFRESH

Command/address termination voltage

(system level, not direct DRAM input)

NOTES:

V_TT

–

0.5 x V_CC

Q

–

V

5

1.

V

_REFCA(DC)is expected to be approximately 0.5 x V_CCand to track variations in the DC level. Externally generated peak noise (noncommon mode) on V_REFCAmay not exceed

±1 % x V_CCaround the V_REFCA(DC)value. Peak-to-peak AC noise on V_REFCAshould not exceed ±2% of V_REFCA(DC)

2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet speciﬁcations if the DRAM induces a_CCitional AC noise greater than 20 MHz in frequency.

.

3.

V_REFDQ(DC)is expected to be approximately 0.5 x V_CCand to track variations in the DC level. Externally generated peak noise (noncommon mode) on V_REFDQmay not exceed

±1 % x V_CCaround the V_REFDQ(DC)value. Peak-to-peak AC noise on V_REFDQshould not exceed ±2% of _VREFDQ(DC)

.

4.

5.

V

_REFDQ(DC)may transition to V_REFDQ(sr)and back to V_REFDQ(DC)when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section.

_TTis not applied directly to the DRAM component. V_TTis a system supply for signal termination resistors. MIN and MAX values are system-dependent.

TABLE 15 – BGA THERMAL RESISTANCE FOR W3J512M32K-XBX

Description

Symbol

Theta JB

Theta JC

Typical

TBD

Units

°C/W

Notes

Junction to Board

Junction to Case (Top)

1

TBD

The JEDEC JESD51 speciﬁcations are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input

to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board deﬁnition speciﬁcations; therefore, Microsemi PMG recommends a customized

evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

26

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 16 – BGA THERMAL RESISTANCE FOR W3J512M32KT-XB2X

Description

Symbol

Theta JB

Theta JC

Typical

TBD

Units

°C/W

Notes

Junction to Board

Junction to Case (Top)

1

TBD

The JEDEC JESD51 speciﬁcations are used as the default modeling environment and boundary conditions. Using still air, horizontal mounting and the 2s2p board. Published material properties are used as input

to derive the thermal characteristics of the module. Your application conditions will most likely differ from the JESD51 2s2p board deﬁnition speciﬁcations; therefore, Microsemi PMG recommends a customized

evaluation of thermal resistances based on the actual conditions in thermally-challenged situations. Delphi models are available for most products upon request.

TABLE 17 – AC INPUT OPERATING CONDITIONS

DDR3-800

DDR3-1066

Parameter

Symbol

DDR3-1333

Unit

Command and Address

V_IH(AC160)min

V_IH(AC135)min

V_IH(DC90)min

Input high AC voltage: Logic 1

Input high DC voltage: Logic 1

Input low DC voltage: Logic 0

Input low AC voltage: Logic 0

+160

+135

+90

+160

+135

+90

mV

V_IL(DC90)max

V_IL(AC135)max

V_IL(AC160)max

DQ and DM

–90

–135

–160

–135

–160

Input high AC voltage: Logic 1

Input high DC voltage: Logic 1

Input low DC voltage: Logic 0

Input low AC voltage: Logic 0

V_IH(AC160)min

V_IH(AC135)min

V_IH(DC90)min

+160

+135

+90

+160

+135

+90

mV

V_IL(DC90)max

V_IL(AC135)max

V_IL(AC160)max

–90

–135

–160

–135

–160

NOTE

1. All voltages are referenced to V_REF, V_REFis V_REFCAfor control, command, and address. All slew rates and setup/hold times are speciﬁed at the DRAM ball. V_REFis V_REFDQfor DQ and DM inputs.

TABLE 18 – ON-DIE TERMINATION DC ELECTRICAL CHARACTERISICS

Parameter

RTT effective impedance

Deviation of VM with respect to V_CCQ/2

Symbol

RTT_EFF

∆VMM

Min

Nom

Max

Unit

Ω

Notes

1, 2

See Table 20

-10

+5

%

1, 2, 3

NOTES

1. 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (V_CCQ= V_CC, V_SSQ= V_SS).

2. Measurement deﬁnition for RTT: Apply V_IH(AC) to pin under test and measure current I[V_IH(AC)], then apply V_IL(AC) to pin under test and measure current I[V_IL(AC)]:

RTT = V_IH(AC) - V_IL(AC)

I(V_IH(AC)) - I(V_IL(AC)

)

3. Measure voltage (VM) at the tested pin with no load:

∆VM =

(

2 x VM - 1

V_CCQ

)

x 100

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

27

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 19 – AC INPUT OPERATING CONDITIONS

MR1 [9, 6, 2]

R_TT

Resistor

V_OUT

0.2 x V_CCQ

Min

0.6

0.9

0.6

0.8

0.6

0.9

0.6

0.8

0.6

0.9

0.6

0.8

0.6

0.9

0.6

0.8

0.6

0.9

0.6

0.8

Nom

1.0

Max

1.15

1.45

1.15

1.85

1.15

1.45

1.15

1.85

1.15

1.45

1.15

1.85

1.15

1.45

1.15

1.85

1.15

1.45

1.15

1.85

Units

RZQ/1

RZQ/2

RZQ/4

RZQ/3

RZQ/6

RZQ/4

RZQ/8

RZQ/6

RZQ/12

0, 1, 0

120Ω

RTT_120PD240

0.5 x V_CCQ

0.8 x V_CCQ

RTT_120PU240

0.2 x V_CCQ

0.5 x V_CCQ

0.8 x V_CCQ

120Ω

RTT_60PD120

V_IL(AC) to V_IH(AC)

0.2 x V_CCQ

0, 0, 1

0, 1, 1

1, 0, 1

1, 0, 0

60Ω

40Ω

30Ω

20Ω

0.5 x V_CCQ

0.8 x V_CCQ

RTT_60PU120

0.2 x V_CCQ

0.5 x V_CCQ

0.8 x V_CCQ

60Ω

40Ω

30Ω

20Ω

V_IL(AC) to V_IH(AC)

0.2 x V_CCQ

RTT_40PD80

0.5 x V_CCQ

0.8 x V_CCQ

RTT_40PU80

0.2 x V_CCQ

0.5 x V_CCQ

0.8 x V_CCQ

V_IL(AC) to V_IH(AC)

0.2 x V_CCQ

RTT_30PD60

0.5 x V_CCQ

0.8 x V_CCQ

RTT_30PU60

0.2 x V_CCQ

0.5 x V_CCQ

0.8 x V_CCQ

V_IL(AC) to V_IH(AC)

0.2 x V_CCQ

RTT_20PD40

0.5 x V_CCQ

0.8 x V_CCQ

RTT_20PU40

0.2 x V_CCQ

0.5 x V_CCQ

0.8 x V_CCQ

V_IL(AC) to V_IH(AC)

NOTES

1. Values assume an RZQ of 240ꢀ (±1 percent).

2. RTT_XXPU and RTT_XXPD are for reference only. Only RTT for V_OUTfrom V_IL(AC) to V_IH(AC) are tested and guaranteed.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

28

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 20 – DDR3 I_CCSPECIFICATIONS AND CONDITIONS – W3J512M32K(T)

800 CL6

1,066 CL8

Symbol

Proposed Conditions

1,333 CL10

Units

Operating one bank active-precharge current;

t_CK= t_CK(I_CC), t_RC= t_RC(I_CC), t_RAS= t_RASmin(I_CC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

220

188

248

mA (1, 2)

I_CC0

Operating one bank active-read-precharge current;

I_OUT= 0mA; BL = 8, CL = CL(I_CC), AL = 0; t_CK= t_CK(I_CC), t_RC= t_RC(I_CC), t_RAS= t_RASmin(I_CC), t_RCD= t_RCD(I_CC); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are SWITCHING; Data bud inpuyd str plosyinh

264

mA (1, 2)

I_CC1

I_CC2P

I_CC2Q

Fast

128

72

112

72

mA (1, 2)

Precharge power-down current;

All banks idle; t_CK= t_CK(I_CC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

Slow

Precharge quiet standby current;

All banks idle; t_CK= t_CK(I_CC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

128

112

mA (1, 2)

Precharge standby current;

All banks idle; t_CK= t_CK(I_CC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

128

152

116

140

mA (1, 2)

I_CC2N

I_CC3P

I_CC3N

Active power-down current;

All banks open; t_CK= t_CK(I_CC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Active standby current;

All banks open; t_CK= t_CK(I_CC), t_RAS= t_RASMAX(I_CC), t_RP= t_RP(I_CC); CKE is HIGH, CS# is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current;

All banks open, Continuous burst writes; BL = 8, CL = CL(I_CC), AL = 0; t_CK= t_CK(I_CC), t_RAS= t_RASMAX(I_CC), t_RP= t_RP(I_CC); CKE is HIGH, CS#

is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

500

628

940

440

560

912

mA (1, 2)

I_CC4W

I_CC4R

I_CC5B

Operating burst read current;

All banks open, Continuous burst reads, I_OUT= 0mA; BL = 8, CL = CL(I_CC), AL = 0; t_CK= t_CK(I_CC), t_RAS= t_RASMAX(I_CC), t_RP= t_RP(I_CC); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as I_DAD6W

Burst auto refresh current;

t

_CK= t_CK(I_CC); Refresh command at every t_RFC(I_CC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

CK, CK# and CKE are low. Other control and address bus inputs

are FLOATING; Data bus inputs are FLOATING

Normal

80

mA (1, 2, 3)

mA (2, 4)

I_CC6

Self refresh current extended temperature:

CK, CK# and CKE are low; other control and address bus inputs are ﬂoating; data bus inputs are ﬂoating

100

I_CC6ET

Operating bank interleave read current;

All bank interleaving reads, I_OUT= 0mA; BL = 8, CL = CL(I_CC), AL = t_RCD(I_CC)-1*t_CK(I_CC); t_CK= t_CK(I_CC), t_RC= t_RC(I_CC), t_RRD= t_RRD(I_CC), t_RCD

= 1*t_CK(I_CC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is

same as I_DAD6R; Refer to the following page for detailed timing conditions

880

760

mA (1, 2)

I_CC7

NOTES:

1. SRT and ASR are disabled.

2. Enabling ASR could increase I_CCxby up to an additional 8mA

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

29

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 21 – DDR3-800 SPEED BINS

CL-t_RCD-t_RP

6-6-6

Units

Notes

Parameter

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

Symbol

t_RCD

Min

15

Max

–

ns

t_RP

15

–

ACTIVATE-to-ACTIVATE or REFRESH command period

t_RC

52.5

37.5

2.5

ns

ACTIVATE-to-PRECHARGE command period

t_RAS

9 x t_REFI

3.3

ns

1

2

CL = 6

CWL = 5

t_{CK (AVG)}

ns

Supported CL settings

Supported CWL setting

NOTES:

6

5

CK

1. t_REFIdepends on T_OPER

.

2. The CL and CWL settings result in t_CKrequirements. When making a selection of t_CK, both CL and CWL requirement settings need to be fulﬁlled.

TABLE 22 – DDR3-1,066 SPEED BINS ⁽³⁾

CL-t_RCD-t_RP

8-8-8

Units

Notes

Parameter

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

Symbol

t_RCD

Min

15

Max

–

ns

t_RP

15

ACTIVATE-to-ACTIVATE or REFRESH command period

t_RC

52.5

37.5

1.875

–

ns

ACTIVATE-to-PRECHARGE command period

t_RAS

9 x t_REFI

<2.5

ns

1

2

CL = 8

CWL = 6

t_{CK (AVG)}

ns

Supported CL settings

Supported CWL setting

NOTES:

5, 6, 8

5, 6

CK

1. t_REFIdepends on T_OPER

.

2. The CL and CWL settings result in t_CKrequirements. When making a selection of t_CK, both CL and CWL requirement settings need to be fulﬁlled.

3. These devices may not operate correctly under all conditions at 1066Mbs and 1333Mbs speeds. The proposed work around at both speeds is to enable

the auto pre-charge function in the DDR controller and to accommodate the setup and hold time changes on the DQS and DQS# signals.

TABLE 23 – DDR3-1,333 SPEED BINS ⁽³⁾

CL-t_RCD-t_RP

10-10-10

Units

Notes

Parameter

Symbol

t_AA

Min

15

Max

Internal READ command to ﬁst data

–

ACTIVATE to internal READ or WRITE delay time

PRECHARGE command period

t_RCD

15

ns

CK

t_RP

15

–

ACTIVATE-to-ACTIVATE or REFRESH command period

t_RC

51

-

ACTIVATE-to-PRECHARGE command period

t_RAS

36

9 x t_REFI

3.3

1

2

CL = 5

CWL = 5

CWL = 6

CWL = 7

t_{CK (AVG)}

3.0

2.5

1.875

1.5

CL = 6

3.3

CL = 8

<2.5

<1.875

CL = 10

Supported CL settings

Supported CWL setting

NOTES:

5, 6, 8, 10

5, 6, 7

1. t_REFIdepends on T_OPER

.

2. The CL and CWL settings result in t_CKrequirements. When making a selection of t_CK, both CL and CWL requirement settings need to be fulﬁlled.

3. These devices may not operate correctly under all conditions at 1066Mbs and 1333Mbs speeds. The proposed work around at both speeds is to enable

the auto pre-charge function in the DDR controller and to accommodate the setup and hold time changes on the DQS and DQS# signals.

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

30

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 24 – AC TIMING PARAMETERS

DDR3-800

Min Max

Clock Timing

DDR3-1066

DDR3-1333

Parameter

Symbol

Units

Notes

Min

Max

Min

Max

Commercial and Industrial

Military

8

7,800

3,900

8

7,800

3,900

8

7,800

3,900

ns

9, 42

42

Clock period average: DLL

disable mode

t_{CKDLL_DIS}

Clock period average: DLL enable mode

High pulse width average

t_{CK (AVG)}

t_{CH (AVG)}

t_{CL (AVG)}

t_JITPER

See “Speed Bin Tables” on page 35 for t_CKrange allowed

ns

10, 11

12

0.47

–100

–90

0.53

100

90

0.47

–90

–80

0.53

90

0.47

–80

–70

0.53

80

CK

ps

Low pulse width average

12

DLL locked

13

Clock period jitter

DLL locking

t_{JITPER, LCK}

t_CK(ABS)

t_{CH (ABS)}

t_{CL (ABS)}

t_JITCC

80

70

ps

13

Clock absolute period

MIN = t_{CK (AVG)}MIN + t_JITPERMIN; MAX = t_{CK (AVG)}MAX + t_JITPERMAX

ps

Clock absolute high pulse width

Clock absolute low pulse width

0.43

–

0.43

–

0.43

–

t_{CK (AVG)}

ps

14

15

16

17

DLL locked

DLL locking

2 cycles

3 cycles

4 cycles

5 cycles

6 cycles

7 cycles

8 cycles

9 cycles

10 cycles

11 cycles

12 cycles

200

180

160

140

Cycle-to-cycle jitter

t_JITCC

,

ps

LCK

t_ERR2PER

t_ERR3PER

t_ERR4PER

t_ERR5PER

t_ERR6PER

t_ERR7PER

t_ERR8PER

t_ERR9PER

t_ERR10PER

t_ERR11PER

t_ERR12PER

–147

–175

–194

–209

–222

–232

–241

–249

–257

–263

–269

147

175

194

209

222

232

241

249

257

263

269

–132

–157

–175

–188

–200

–209

–217

–224

–231

–237

–242

132

157

175

188

200

209

217

224

231

237

242

–118

–140

–155

–168

–177

–186

–193

–200

–205

–210

–215

118

140

155

168

177

186

193

200

205

210

215

ps

Cumulative error across

ps

t_ERRnPERMIN = (1 + 0.68ln[n]) × t_JITPERMIN

t_ERRnPERMAX = (1 + 0.68ln[n]) × t_JITPERMAX

n = 13, 14 . . . 49, 50 cycles

t_ERRnPER

ps

17

DQ Input Timing

Base (speciﬁcation)

90

–

40

–

ps

18, 19, 44

19, 20

18, 19, 44

19, 20

18,19

Data setup time to DQS, DQS#

t_{DS AC160}

V

_REF@ 1 V/ns

Base (speciﬁcation)

_REF@ 1 V/ns

Base (speciﬁcation)

_REF@ 1 V/ns

250

140

275

160

250

600

200

90

–

90

t_{DS AC135}

V

225

110

200

490

225

110

200

400

Data hold time from DQS,

DQS#

t_{DH DC90}

t_DIPW

V

19, 20

41

Minimum data pulse width

DQ Output Timing

DQS, DQS# to DQ skew, per access

t_DQSQ

t_QH

t_{LZ (DQ)}

t_{HZ (DQ)}

–

0.38

–800

–

200

–

0.38

–600

–

150

–

0.38

–500

–

125

–

ps

t_{CK (AVG)}

ps

DQ output hold time from DQS, DQS#

DQ Low-Z time from CK, CK#

DQ High-Z time from CK, CK#

21

400

300

250

22, 23

ps

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

31

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 24 – AC TIMING PARAMETERS (continued)

DDR3-800

Min Max

DQ Strobe Input Timing

DDR3-1066

DDR3-1333

Parameter

Symbol

Units

Notes

Min

Max

Min

Max

DQS, DQS# rising to CK, CK# rising

t_DQSS

t_DQSL

t_DQSH

t_DSS

–0.25

0.45

0.2

0.25

0.55

–

–0.25

0.45

0.2

0.25

0.55

–

–0.25

0.45

0.2

0.25

0.55

–

CK

25

DQS, DQS# differential input low pulse width

DQS, DQS# differential input high pulse width

DQS, DQS# falling setup to CK, CK# rising

DQS, DQS# falling hold from CK, CK# rising

DQS, DQS# differential WRITE preamble

DQS, DQS# differential WRITE postamble

25

t_DSH

0.2

–

0.2

–

0.2

–

t_WPRE

t_WPST

0.9

–

0.9

–

0.9

–

0.3

–

0.3

–

0.3

–

DQ Strobe Output Timing

DQS, DQS# rising to/from rising CK, CK#

t_DQSCK

–400

1

400

10

–300

1

300

10

–255

1

255

10

ps

ns

23

26

DQS, DQS# rising to/from rising CK, CK# when DLL is disabled t_{DQSCK DLL_DIS}

DQS, DQS# differential output high time

DQS, DQS# differential output low time

DQS, DQS# Low-Z time (RL - 1)

t_QSH

t_QSL

0.38

–800

–

0.38

–600

–

0.40

–500

–

CK

ps

21

–

21

t_{LZ (DQS)}

t_{HZ (DQS)}

t_RPRE

400

300

250

22, 23

23, 24

23, 27

DQS, DQS# High-Z time (RL + BL/2)

DQS, DQS# differential READ preamble

DQS, DQS# differential READ postamble

400

300

250

ps

0.9

0.3

Note 24

Note 27

0.9

0.3

Note 24

Note 27

0.9

0.3

Note 24

Note 27

CK

t_RPST

Command and Address Timing

DLL locking time

t_DLLK

512

215

375

365

500

285

375

900

–

512

140

300

290

425

210

300

780

–

512

80

–

CK

ps

ns

28

29, 30

20, 30

29, 30, 44

20, 30

29, 30

20, 30

41

Base (speciﬁcation)

V_REF@ 1 V/ns

CTRL, CMD, ADDR setup to CK,CK#

t_{IS AC160}

240

205

340

150

240

620

Base (speciﬁcation)

V_REF@ 1 V/ns

CTRL, CMD, ADDR hold from CK,CK#

t_{IH (AC135)}

t_{IH DC90}

Base (speciﬁcation)

V_REF@ 1 V/ns

CTRL, CMD, ADDR setup to CK,CK#

Minimum CTRL, CMD, ADDR pulse width

t_IPW

t_RCD

t_RP

ACTIVATE to internal READ or WRITE delay

PRECHARGE command period

See “Speed Bin Tables” on page 30 for t_RCD

See “Speed Bin Tables” on page 30 for t_RP

See “Speed Bin Tables” on page 30 for t_RAS

See “Speed Bin Tables” on page 30 for t_RC

31

ACTIVATE-to-PRECHARGE command period

ACTIVATE-to-ACTIVATE command period

t_RAS

t_RC

31, 32

31, 43

MIN = greater of 4CK

or 10ns

MIN = greater of 4CK

or 7.5ns

MIN = greater of 4CK

or 6ns

1KB page size

2KB page size

CK

31

ACTIVATE-to-ACTIVATE minimum

command period

t_RRD

MIN = greater of 4CK

or 7.5ns

MIN = greater of 4CK or 10ns

Four ACTIVATE windows for 1KB page size

Four ACTIVATE windows for 2KB page size

40

50

–

37.5

50

–

30

45

–

ns

31

t_FAW

–

31, 32,

33, 34

Write recovery time

t_WR

MIN = 15ns; MAX = n/a

ns

Delay from start of internal WRITE transaction to internal

READ command

t_WTR

MIN = greater of 4CK or 7.5ns; MAX = n/a

CK

31, 34

31, 32

READ-to-PRECHARGE time

t_RTP

t_CCD

t_DAL

t_MRD

t_MOD

MIN = greater of 4CK or 7.5ns; MAX = n/a

MIN = 4CK; MAX = n/a

CK

CAS#-to-CAS# command delay

Auto precharge write recovery + precharge time

MODE REGISTER SET command cycle time

MODE REGISTER SET command update delay

MIN = WR + t_RP/t_CK(AVG); MAX = n/a

MIN = 4CK; MAX = n/a

MIN = greater of 12CK or 15ns; MAX = n/a

MULTIPURPOSE REGISTER READ burst end to mode

register set for multipurpose register exit

t_MPRR

MIN = 1CK; MAX = n/a

CK

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

32

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 24 – AC TIMING PARAMETERS (continued)

DDR3-800

Min Max

Calibration Timing

DDR3-1066

DDR3-1333

Parameter

Symbol

Units

Notes

Min

Max

Min

Max

POWER-UP and RESET

operation

t_ZQINIT

512

–

512

–

512

–

CK

ZQCL command: Long

calibration time

Normal operation

t_ZQOPER

t_ZQCS

256

64

–

256

64

–

256

64

–

CK

ZQCS command: Short calibration time

Initialization and Reset Timing

Exit reset from CKE HIGH to a valid command

Begin power supply ramp to power supplies stable

RESET# LOW to power supplies stable

t_XPR

t_VDDPR

t_RPS

MIN = greater of 5CK or t_RFC+ 10ns; MAX = n/a

MIN = n/a; MAX = 200

CK

ms

ns

MIN = 0; MAX = 200

RESET# LOW to I/O and RTT High-Z

t_IOz

MIN = n/a; MAX = 20

35

Refresh Timing

REFRESH-to-ACTIVATE or REFRESH command period

Com, Ind (1X)

t_RFC

MIN = 260; MAX = 70,200

7.8 (64ms/8,192)

ns

ꢁs

36

Military, 85°C to 95°C

Maximum average periodic

temperature (2X)

refresh

3.9 (32ms/8,192)

1.95 (16ms/8,192)

ꢁs

t_REFI

Military, 95°C to 125°C

temperature (4X)

36

Self Refresh Timing

Exit self refresh to commands not requiring a locked DLL

Exit self refresh to commands requiring a locked DLL

t_XS

MIN = greater of 5CK or t_RFC+ 10ns; MAX = n/a

MIN = t_DLLK(MIN); MAX = n/a

CK

t_XSDLL

28

Minimum CKE low pulse width for self refresh entry to self refresh

exit timing

t_CKESR

MIN = t_CKE(MIN) + CK; MAX = n/a

CK

Valid clocks after self refresh entry or powerdown entry

t_CKSRE

t_CKSRX

MIN = greater of 5CK or 10ns; MAX = n/a

CK

Valid clocks before self refresh exit, powerdown exit, or reset exit

Power-Down Timing

Greater of 3CK or

7.5ns

Greater of 3CK or

5.625ns

Greater of 3CK or

5.625ns

CKE MIN pulse width

t_{CKE (MIN)}

CK

Command pass disable delay

t_CPDED

t_PD

MIN = 1; MAX = n/a

MIN = t_CKE(MIN); MAX = 9 × t_REFI

WL - 1CK

CK

Power-down entry to power-down exit timing

Begin power-down period prior to CKE registered HIGH

t_ANPD

Power-down entry period: ODT either synchronous or

asynchronous

PDE

PDX

Greater of t_ANPDor t_RFC- REFRESH command to CKE LOW time

CK

Power-down exit period: ODT either synchronous or

asynchronous

t

_ANPD+ t_XPDLL

Power-Down Entry Minimum Timing

t_ACTPDEN

ACTIVATE command to power-down entry

MIN = 1

CK

PRECHARGE/PRECHARGE ALL command to power-down entry t_PRPDEN

REFRESH command to power-down entry

MRS command to power-down entry

t_REFPDEN

t_MRSPDEN

37

MIN = t_MOD(MIN)

MIN = RL + 4 + 1

READ/READ with auto precharge command to power-down entry t_RDPDEN

BL8 (OTF, MRS) BC4OTF

BC4MRS

t_WRPDEN

t_WRAPDEN

MIN = WL + 4 + t_WR/t_CK(AVG)

MIN = WL + 2 + t_WR/t_CK(AVG)

MIN = WL + 4 + WR + 1

MIN = WL + 2 + WR + 1

WRITE command to power-

down entry

BL8 (OTF, MRS) BC4OTF

BC4MRS

WRITE with auto precharge

command to power-down entry

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

33

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

TABLE 24 – AC TIMING PARAMETERS (continued)

DDR3-800

Min Max

Power-Down Exit Timing

DDR3-1066

Min Max

DDR3-1333

Parameter

Symbol

Units

Notes

Min

Max

DLL on, any valid command, or DLL off to commands not

requiring locked DLL

MIN = greater of 3CK or

6ns; MAX = n/a

t_XP

MIN = greater of 3CK or 7.5ns; MAX = n/a

CK

Precharge power-down with DLL off to commands requiring a

locked DLL

t_XPDLL

MIN = greater of 10CK or 24ns; MAX = n/a

28

ODT Timing

R

_TTsynchronous turn-on delay

_TTsynchronous turn-off delay

ODTL on

ODTL off

t_AON

CWL + AL - 2CK

CK

ps

38

40

R

R_TTturn-on from ODTL on reference

–400

0.3

400

0.7

–300

0.3

300

0.7

–250

0.3

250

0.7

23, 38

39, 40

38

R_TTturn-off from ODTL off reference

t_AOF

CK

ns

Asynchronous R_TTturn-on delay (power-down with DLL off)

Asynchronous R_TTturn-off delay (power-down with DLL off)

ODT HIGH time with WRITE command and BL8

t_AONPD

t_AOFPD

ODTH8

MIN = 2; MAX = 8.5

MIN = 6; MAX = n/a

ns

40

CK

ODT HIGH time without WRITE command or with WRITE

command and BC4

ODTH4

MIN = 4; MAX = n/a

CK

Dynamic ODT Timing

R_TT_NOM-to-R_TT_WR change skew

ODTL_CNW

ODTL_CNW4

ODTL_CNW8

t_ADC

WL - 2CK

CK

R_TT_WR-to-R_TT_NOM change skew - BC4

R_TT_WR-to-R_TT_NOM change skew - BL8

4CK + ODTL off

6CK + ODTL off

R_TTdynamic change skew

0.3

0.7

0.3

0.7

0.3

0.7

39

Write Leveling Timing

First DQS, DQS# rising edge

DQS, DQS# delay

t

_WLMR_D

40

25

–

40

25

–

40

25

–

CK

t_WLDQSEN

Write leveling setup from rising CK, CK# crossing to rising

DQS, DQS# crossing

t_WLS

325

–

245

–

195

–

ps

Write leveling hold from rising DQS, DQS# crossing to rising

CK, CK# crossing

t_WLH

Write leveling output delay

Write leveling output error

t_WLO

0

9

2

0

9

2

0

9

2

ns

t_WLOE

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

34

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

AC Overshoot/Undershoot Speciﬁcation

Table 25 – Control and Address Pins

Parameter

DDR3-800

0.4V

DDR3-1066

DDR3-1333

0.4V

Maximum peak amplitude allowed for overshoot area (see Figure 14)

Maximum peak amplitude allowed for undershoot area (see Figure 15)

Maximum overshoot area above V_CC(see Figure 14)

Maximum undershoot area below V_SS(see Figure 15)

0.4V

0.67 Vns

0.5 Vns

0.4 Vns

Table 26 – Clock, Data, Strobe, and Mask Pins

Parameter

DDR3-800

DDR3-1066

0.4V

DDR3-1333

0.4V

Maximum peak amplitude allowed for overshoot area (see Figure 14)

Maximum peak amplitude allowed for undershoot area (see Figure 15)

Maximum overshoot area above V_CC/V_CCQ(see Figure 14)

0.4V

0.25 Vns

0.19 Vns

0.15 Vns

Maximum undershoot area below V_SS/V_SSQ(see Figure 15)

FIGURE 13 – OVERSHOOT

Maximum amplitude

Overshoot area

Volts (V)

V_CC/V_CCQ

Time (ns)

FIGURE 14 – UNDERSHOOT

V_SS/V_SSQ

Volts (V)

Undershoot area

Maximum amplitude

Time (ns)

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

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W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

NOTES:

1. Parameters are applicable with V_CC/V_CCQ= +1.35V ±0.075V.

24. The maximum preamble is bound by t_LZDQS(MAX).

2. All voltages are referenced to VSS.

25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its

respective clock signal (CK, CK#) crossing. The speciﬁcation values are not affected by

the amount of clock jitter applied, as these are relative to the clock signal crossing. These

parameters should be met whether clock jitter is present.

26. The t_DQSCK(DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.

27. The maximum postamble is bound by t_HZDQS(MAX).

3. Output timings are only valid for RON34 output buffer selection.

4. Unit “t_CK(AVG)” represents the actual t_CK(AVG) of the input clock under operation. Unit “CK”

represents one clock cycle of the input clock, counting the actual clock edges.

5. AC timing and I_CCtests may use a V_IL-to-V_IHswing of up to 900mV in the test environment,

but input timing is still referenced to V_REF(except t_IS, t_IH, t_DS, and t_DHuse the AC/DC trip points

and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input

signals used to test the device is 1 V/ns for single ended inputs and 2 V/ns for differential inputs

28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands.

In addition, after any change of latency t_XPDLL, timing must be met.

in the range between V_IL(AC)and V_IH(AC)

.

29.

t

_IS(base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew

6. All timings that use time-based values (ns, ꢁs, ms) should use t_CK(AVG) to determine the

correct number of clocks (AC Operation Table). In the case of non integer results, all minimum

limits are to be rounded up to the nearest whole integer, and all maximum limits are to be

rounded down to the nearest whole integer.

7. The use of “strobe” or “DQSDIFF” refers to the DQS and DQS# differential crossing point when

DQS is the rising edge. The use of “clock” or “CK” refers to the CK and CK# differential crossing

point when CK is the rising edge.

8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The

actual test load may be different. The output signal voltage reference point is V_CCQ/2for single-

ended signals and the crossing point for differential signals.

rate and 2 V/ns CK, CK# differential slew rate.

30. These parameters are measured from a command/address signal transition edge to its

respective clock (CK, CK#) signal crossing. The speciﬁcation values are not affected by the

amount of clock jitter applied as the setup and hold times are relative to the clock signal

crossing that latches the command/address. These parameters should be met whether clock

jitter is present.

31. For these parameters, the DDR3 SDRAM device supports _{tnPARAM (nCK) = RU(}t_{PARAM [ns]/ CK[AVG] [ns])}

assuming all input clock jitter speciﬁcations are satisﬁed. For example, the device will support

_{nRP (nCK) = RU(}t_{RP/ CK[AVG])}if all input clock jitter speciﬁcations are met. This means for DDR3-800

6-6-6, of which t_RP= 15ns, the device will support t_{nRP = RU( RP/ CK[AVG])}= 6 as long as the input

t

,

t

9. When operating in DLL disable mode, Microsemi does not warrant compliance with normal

mode timings or functionality.

10. The clock’s t_{CK (AVG)}is the average clock over any 200 consecutive clocks and t_CK(AVG)MIN is

the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock

jitter is allowed provided it does not exceed values speciﬁed and must be of a random Gaussian

distribution in nature.

clock jitter speciﬁcations are met. That is, the PRECHARGE command at T0 and the ACTIVATE

command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter.

32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal

PRECHARGE command until t_RAS(MIN) has been satisﬁed.

33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisﬁed for t_WR

34. The start of the write recovery time is deﬁned as follows:

.

11. Spread spectrum is not included in the jitter speciﬁcation values. However, the input clock can

accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with an additional

1 percent of t_CK(AVG) as a long-term jitter component; however, the spread-spectrum may not

use a clock rate below t_CK(AVG) MIN.

12. The clock’s t_{CH (AVG)}and t_{CL (AVG)}are the average half clock period over any 200 consecutive

clocks and is the smallest clock half period allowed, with the exception of a deviation due to

clock jitter. Input clock jitter is allowed provided it does not exceed values speciﬁed and must be

of a random Gaussian distribution in nature.

13. The period jitter (t_JITPER) is the maximum deviation in the clock period from the average or

nominal clock. It is allowed in either the positive or negative direction.

14. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising

edge to the following falling edge.

– For BL8 (ﬁxed by MRS and OTF): Rising clock edge four clock cycles after WL

– For BC4 (OTF): Rising clock edge four clock cycles after WL

– For BC4 (ﬁxed by MRS): Rising clock edge two clock cycles after WL

35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z.

Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current,

depending on bus activity.

36. The refresh period is 64ms up to +85°C. This equates to an average refresh rate of 7.8125ꢁs.

However, nine REFRESH commands must be asserted at least once every 70.3ꢁs.

37. Although CKE is allowed to be registered LOW after a REFRESH command when t_REFPDEN

(MIN) is satisﬁed, there are cases where additional time such as t_XPDLL(MIN) is required.

38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on.

ODT turn-on time maximum is when the ODT resistance is fully on.

15. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling

edge to the following rising edge.

39. Half-clock output parameters must be derated by the actual t_ERR10PERand t_JITDTYwhen input

clock jitter is present. This results in each parameter becoming larger. The parameters t_ADC

(MIN) and t_AOF(MIN) are each required to be derated by subtracting both t_ERR10PER(MAX)

and t_JITDTY(MAX). The parameters t_ADC(MAX) and t_AOF(MAX) are required to be derated by

subtracting both t_ERR10PER(MAX) and t_JITDTY(MAX).

40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off

time maximum is when the DRAM buffer is in High-Z. This output load is used for ODT timings.

41. Pulse width of a input signal is deﬁned as the width between the ﬁrst crossing of V_REF(DC)and

16. The cycle-to-cycle jitter (t_JITCC) is the amount the clock period can deviate from one cycle to the

next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time.

17. The cumulative jitter error (t_ERRnPER), where n is the number of clocks between 2 and 50, is the

amount of clock time allowed to accumulate consecutively away from the average clock over n

number of clock cycles.

18.

t

_DS(base) and t_DH(base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns

differential DQS, DQS# slew rate.

the consecutive crossing of V_REF(DC)

.

19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition

edge to its respective data strobe signal (DQS, DQS#) crossing.

20. The setup and hold times are listed converting the base speciﬁcation values (to which derating

tables apply) to V_REFwhen the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are

for reference only.

21. When the device is operated with input clock jitter, this parameter needs to be derated by the

actual tJITPER of the input clock (output deratings are relative to the SDRAM input clock).

22. Single-ended signal parameter.

23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters

must be derated by the actual jitter error when input clock jitter is present, even when within

speciﬁcation. This results in each parameter becoming larger. The following parameters are

required to be derated by subtracting t_ERR10PER(MAX): t_DQSCK(MIN), t_LZ(DQS)MIN, t_LZ(DQ)

MIN, and t_AON(MIN). The following parameters are required to be derated by subtracting

42. Should the clock rate be larger than t_RFC(MIN), an AUTO REFRESH command should have at

least one NOP command between it and another AUTO REFRESH command. Additionally, if

the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a

PRECHARGE ALL command.

43. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses

to a particular row address may result in reduction of the product lifetime.

44. When two V_IH(AC)values (and two corresponding V_IL(AC)values) are listed for a speciﬁc speed

bin, the user may choose either value for the input AC level. Whichever value is used, the

associated setup time for that AC level must also be used. Additionally, one V_IH(AC)value may be

used for address/command inputs and the other V_IH(AC)value may be used for data inputs.

For example, for DDR3-800, two input AC levels are deﬁned: VIH_(AC175),minand V_{IH(AC150),min}

(corresponding V_{IL(AC175),min}and V_{IL(AC150),min}). For DDR3-800, the address/ command inputs

must use either V_{IH(AC175),min}with t_IS(AC175)of 200ps or V_{IH(AC150),min}with t_IS(AC150)of 350ps;

independently, the data inputs must use either V_{IH(AC175),min}with t_DS(AC175)of 75ps or V_{IH(AC150),min}

with t_DS(AC150)of 125ps.

t_ERR10PER(MIN): t_DQSCK(MAX), t_HZ(MAX), t_LZ(DQS)MAX, t_LZ(DQ) MAX, and t_AON(MAX). The

parameter t_RPRE(MIN) is derated by subtracting t_JITPER(MAX), while t_RPRE(MAX) is derated by

subtracting t_JITPER(MIN).

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

36

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 15 – PACKAGE DIMENSION: 136 PLASTIC BALL GRID ARRAY (PBGA) for W3J512M32KT-XBX

BOTTOM VIEW

12 11 10

9

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

0.8 (0.031) NOM

0.3

(0.012)

NOM

8.8 (0.346) NOM

10.1 (0.398) MAX

3.540

(0.139)

MAX

• Pads are Solder Mask Deﬁned (SMD), pads openings: 0.4mm

• Solder balls composition: Eutectic Sn63 Pb37

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

37

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

FIGURE 15A – PACKAGE DIMENSION: 204 PBGA, for W3J512M32T-XB2X

BOTTOM VIEW

12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

0.8 (0.031) NOM

0.3

(0.012)

NOM

8.8 (0.346) NOM

10.1 (0.398) MAX

3.540

(0.139)

MAX

• Pads are Solder Mask Deﬁned (SMD), pads openings: 0.4mm

• Solder balls composition: Eutectic Sn63 Pb37

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

38

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

ORDERING INFORMATION

W 3J 512M 32 K T - XXXX XX X

MICROSEMI CORPORATION:

DDR3 SDRAM:

CONFIGURATION, 512M x32:

1.35V POWER SUPPLY:

OPTIONAL:

T = Address/Control Termination resistors included. B2 package only.

DATA RATE (Mb/s):

800 = 800Mb/s

1066 = 1,066Mb/s

1333 = 1,333Mb/s

PACKAGE:

B = 136 Plastic Ball Grid Array (PBGA) – No address/control termination, no clock

termination, with calibration resistors.

B2 = 204 PBGA, x32 with clock termination, with calibration resistors with address/

control termination. Only option available is 512M32KT.

DEVICE GRADE:

M = Military

-55°C to +125°C

-40°C to +85°C

0°C to +70°C

I

= Industrial

C

= Commercial

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

39

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp

W3J512M32K-XBX

W3J512M32KT-XB2X

PRELIMINARY

Document Title

2GB – 512M x 32/40 DDR3 SDRAM 1.35V – 136/204 PBGA Multi-Chip Package

Revision History

Rev #

History

Release Date Status

Rev 0

Initial Release

April 2014

Preliminary

Rev 1

Rev 2

Change (Pg. 1)

June 2014

Preliminary

1.1 Change W3J512M36K(T)-XB2X to W3J512M32K(T)-XB2X “B2” package is

for X32 with termination.

Changes (Pg. 1, 3, 4, 40, 41, 42, 43)

September 2014

Preliminary

2.1 Remove all reference to x36 package

2.2 Remove functional block diagram for x36 conﬁguration

2.3 “B2” package only available in x32 bit data conﬁguration with address/control

terminations

Rev 3

Rev 4

Changes (Pg. 23)

December 2014

April 2015

Preliminary

3.1 Correct Table 7 “Bank Activate” values for RAS#, CAS# and WE#

Changes (Pgs. 1-40)

4.1 Remove x40 data width option including block diagram and package drawing

4.2 Change DQ timing for DDR3 - 1333

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

40

Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp


型号：	W3J512M32K-1066B2C
厂家：	MERCURY UNITED ELECTRONICS INC
描述：	DDR DRAM, 512MX32, CMOS, PBGA204, BGA-204 动态存储器双倍数据速率
文件：	总40页 (文件大小：1655K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W3J512M32K-1066B2C [MERCURY]

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