DSC400-0121Q0001KE1T [MICREL]
Configurable Four Output, Low Jitter Crystal-less⢠Clock Generator;
| 型号： | DSC400-0121Q0001KE1T |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Configurable Four Output, Low Jitter Crystal-less⢠Clock Generator |
| 文件： | 总15页 (文件大小：456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC400
Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Features
General Description
Low RMS Phase Jitter: <1 ps (typ)
The DSC400 is a four output crystal-less™
High Stability: ±25ppm, ±50ppm
clock generator. It utilizes Micrel’s proven
PureSilicon™ MEMS technology to provide
Wide Temperature Range
o Ext. commercial: -20°C to 70°C
o Industrial: -40°C to 85°C
excellent
jitter
and
stability
while
incorporating additional device functionality.
The frequencies of the outputs can be
identical or independently derived from
common PLLs.
High Supply Noise Rejection: -50 dBc
Four format configurable outputs:
o LVPECL, LVDS, HCSL, LVCMOS
Each
output
may
be
configured
independently to support a single ended
LVCMOS interface or a differential interface.
Differential options include LVPECL, LVDS, or
HCSL.
The DSC400 provides two independent select
lines for choosing between two sets of pre-
configured frequencies per bank. It also has
two OE pins to allow for enabling and
disabling outputs.
Available Pin-Selectable frequency table
o 1 pin per bank for 2 frequency sets
Wide Freq. Range:
o 2.3 MHz – 460 MHz
20 QFN Footprint (5mm x 3.2mm)
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
The DSC400 is packaged in a 20-pin QFN
(5mm x 3.2mm) and is available in extended
High Reliability
o 20x better MTF than quartz based devices
commercial and
industrial
temperature
Wide Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
grades.
AEC-Q100 Automotive Qualified
Block Diagram
Applications
Communications and Networks
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
HD/SD/SDI Video & Surveillance
Automotive
Media and Video
Embedded and Industrial
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DSC400 Page 1
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Pin Description
Pin
No.
Pin
Name
Pin
Type
Description
1
2
OE1
NC
I
NA
Output Enable for Bank1 (CLK0 and CLK3); active high – See Table 1
Leave unconnected or connect to ground
Ground
Ground
3
4
5
6
7
8
9
10
11
12
13
14
15
VSS
VSS
Power
Power
O
Complement output of differential pair 0 (off when in LVCMOS format)
CLK0-
CLK0+
CLK1-
CLK1+
VDD2
FSB2
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD1
FSB1
O
O
O
True output of differential pair 0 or LVCMOS output 0
Complement output of differential pair 1 (off when in LVCMOS format)
True output of differential pair 1 or LVCMOS output 1
Power Supply for Bank2 (CLK1 and CLK2)
Power
I
I
NA
Input for selecting pre-configured frequencies on Bank2 (CLK1 and CLK2)
Output Enable for Bank2 (CLK1 and CLK2); active high – See Table 1
Leave unconnected or connect to ground
Ground
Power
Power Ground
O
O
O
O
Complement output of differential pair 2 (off when in LVCMOS format)
True output of differential pair 2 or LVCMOS output 2
Complement output of differential pair 3 (off when in LVCMOS format)
True output of differential pair 3 or LVCMOS output 3
17
18
19
20
Power Power Supply for Bank1 (CLK0 and CLK3)
I
Input for selecting pre-configured frequencies on Bank1 (CLK0 and CLK3)
Pin Diagram
20 QFN 5.0 × 3.2mm
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DSC400 Page 2
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Operational Description
The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it
does not require an external crystal to operate; it relies on the integrated MEMS resonator that
interfaces with internal PLLs. This technology enhances performance and reliability by allowing
tighter frequency stability over a far wider temperature range. In addition, the higher resistance to
shock and vibration decreases the aging rate to allow for much improved product life in the system.
Inputs
There are 4 input signals in the device. Each has an internal (40kΩ) pull up to default the selection
to a high (1). Inputs can be controlled through hardware strapping method with a resistor to
ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs
In case more than one frequency set is desired, FSB1 and FSB2 are used for independently
selecting one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3)
and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in table 2.
If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to
disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.
Table 1: Output Enable (OE) Selection Table
OE1 OE2 Bank1 (CLK0 & CLK3) Bank2 (CLK1 & CLK2)
0
0
1
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Running
Hi-Z
Running
Running
Running
Outputs
The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to
allow for optimized noise isolation between the two banks. Each bank provides two synchronous
outputs generated by a common PLL:
Bank1 is composed of outputs CLK0 and CLK3
Bank2 is composed of outputs CLK1 and CLK2
Each output maybe pre-configured independently to be one of the following formats: LVCMOS,
LVDS, LVPECL or HCSL. In case the output is configured to be the single ended LVCMOS, the
frequency is generated on the true output (CLKx+) and the complement output (CLKx-) is shut off
in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential outputs and from
2.3MHz to 170MHz on LVCMOS outputs.
Power
VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different
supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should
have a 0.1µF capacitor to filter high frequency noise. VSS is common to the entire device.
______________________________________________________________________________________________________________________________________________
DSC400
Page 3
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Ordering Information
(Example shown in red font)
Q
DSC400- 4 3 2 1 x x x x K E 1 T
CLK3 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
Packing
T: Tape & Reel
Stability
1: ±50ppm
2: ±25ppm
4: HCSL
CLK2 Output Format
1: LVCMOS
2: LVPECL
Temp Range
E: -20ºC to 70ºC
I: -40ºC to 85º
3: LVDS
4: HCSL
Package
K: 20 QFN
CLK1 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
Frequency Code
Qxxxx is assigned
by factory; see
Table2
4: HCSL
CLK0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Factory configuration code assignment of Qxxxx
The DSC400 is meant for customers to define their own frequency requirements at the four
available outputs. The Qxxxx number identifies these specific customer requirements and is
assigned by the factory.
Table 2: Example of how FSB1 and FSB2 are applied and the Qxxxx code assignment
Bank1
FSB1
Qxxxx number
Outputs
CLK0
1 (default)
125 MHz
50 MHz
0
150 MHz
25 MHz
CLK3
Bank2
FSB2
Q0001
Outputs
CLK1
1 (default)
0
156.25 MHz
156.25 MHz
100 MHz
100 MHz
CLK2
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DSC400 Page 4
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Absolute Maximum Ratings
Item
Min
Max
Unit Condition
Supply Voltage
-0.3
+4.0
V
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3 VDD+0.3
V
°C
°C
°C
V
-
-55
-
+150
+150
+260
40sec max.
ESD
HBM
MM
-
4000
400
CDM
1500
Note: 1000+ years of data retention on internal memory
Specifications (Unless specified otherwise: Ta =25° C, VDD = 3.3V)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Supply Voltage1
VDD
2.25
3.6
V
OE(1:2) = 0
All outputs are disabled
Supply Current – Core2
IDDcore
40
44
mA
±25
±50
Frequency Stability
Δf
All temp and VDD ranges
ppm
Aging – first year
ΔfY1
ΔfY2
tSU
1 year @25°C
Year 2 and beyond @25°C
T=25°C
±5
<±1/yr
5
ppm
ppm
ms
+
Aging – after first year
Startup Time3
Input Logic Levels
Input logic high
Input logic low
VIH
VIL
0.75xVDD
-
-
V
0.25xVDD
Output Disable Time4
Output Enable Time4
tDA
OE(1:2) transition from 1 to 0
OE(1:2) transition from 0 to 1
5
ns
ns
tEN
20
All input pins have an internal pull-
up
Pull-Up Resistor
RPU
40
kΩ
Notes:
1. VDD pins should be filtered with a 0.1µF capacitor connected between VDD and VSS.
2. The addition of IDDcore and IDDio provides total current consumption of the device
3. tsu is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform figures below the parameters. See Output Waveform section
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DSC400 Page 5
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVPECL Outputs6
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
VDD-1.08
-
-
V
VDD-1.55
Pk to Pk Output Swing
Output Transition time4
Rise Time
Single-Ended
800
250
mV
ps
20% to 80%
tR
tF
RL=50Ω
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
SYM
Supply Current – IO2
IDDio
JPER
Per output at 125MHz
35
38
mA
Period Jitter5
CLK(0:3) = 156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.5
0.25
0.38
1.7
psRMS
Integrated Phase Noise
JPH
psRMS
2
Notes:
5.
6.
Period Jitter includes crosstalk from adjacent output
LVPECL applicable to ext. commercial temperature only
LVPECL: Typical Termination Scheme
______________________________________________________________________________________________________________________________________________
DSC400 Page 6
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVDS Outputs
Output offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time3
Rise Time
VOS
∆VOS
VPP
R=100Ω Differential
1.125
1.4
50
V
mV
mV
Single-Ended
350
200
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
ps
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Supply Current – IO2
Period Jitter
SYM
IDDio
JPER
Per output at 125MHz
9
12
mA
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
Integrated Phase Noise
JPH
psRMS
2
LVDS: Typical Termination Scheme
If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the
PCB and placed as close as possible to the receiver.
______________________________________________________________________________________________________________________________________________
DSC400
Page 7
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
HCSL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
0.725
-
-
0.1
V
Pk to Pk Output Swing
Output Transition time3
Rise Time
Single-Ended
750
mV
ps
20% to 80%
RL=50Ω, CL= 2pF
tR
tF
200
400
Fall Time
Frequency
f0
Single Frequency
Differential
2.3
48
460
52
MHz
%
Output Duty Cycle
Supply Current – IO2
Period Jitter
SYM
IDDio
JPER
Per output at 125MHz
20
22
mA
2.5
psRMS
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.37
1.7
Integrated Phase Noise
JPH
psRMS
2
HCSL: Typical Termination Scheme
RS is a series resistor implemented to match the trace impedance. Depending on the board
layout, the value may range from 0 to 30Ω
______________________________________________________________________________________________________________________________________________
DSC400
Page 8
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVCMOS Outputs
Output Logic Levels
Output logic high
Output logic low
Output Transition time3
Rise Time
VOH
VOL
I=±6mA
0.9xVDD
-
-
V
0.1xVDD
20% to 80%
CL=15pF
tR
tF
1.1
1.3
2
2
ns
Fall Time
All temp range except Auto
Auto temp range
2.3
45
170
100
Frequency
f0
MHz
%
Output Duty Cycle
Supply Current – IO2
Period Jitter
SYM
55
14
IDDio
JPER
Per output at 125MHz, CL=15pF
CLK(0:3) =125MHz
11
3
mA
psRMS
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
0.3
0.38
1.7
Integrated Phase Noise
JPH
psRMS
2
LVCMOS: Typical Termination Scheme
RS is a series resistor implemented to match the trace impedance to that of the clock
output. Depending on the board layout, the value may range from 0 to 27Ω
______________________________________________________________________________________________________________________________________________
DSC400 Page 9
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Connection Diagram:
The connection Diagram below includes recommended capacitors to be placed on each VDD
for noise filtering.
______________________________________________________________________________________________________________________________________________
DSC400
Page 10
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Output Waveform
Differential Output (LVDS, LVPECL, HCSL)
LVCMOS Output
______________________________________________________________________________________________________________________________________________
DSC400
Page 11
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Solder Reflow Profile
MSL 1 @ 260°C refer to JSTD-020C
Ramp-up rate (200°C to peak temp)
Preheat time 150°C to 200°C
Time maintained above 217°C
Peak temperature
3°C/sec max.
60-180 sec
60-150 sec
255-260°C
20-40 sec
Time within 5°C of actual peak
Ramp-down rate
6°C/sec max.
8 min max.
Time 25°C to peak temperature
______________________________________________________________________________________________________________________________________________
DSC400 Page 12
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Package Dimensions
20 QFN, 5.0mm x 3.2 mm
______________________________________________________________________________________________________________________________________________
DSC400 Page 13
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Recommended Solder Pad Layout
units: mm[inches]
Connect the center pad to ground plane for best thermal performance
______________________________________________________________________________________________________________________________________________
DSC400
Page 14
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a
warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license,
whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of
sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including
liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to
result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose
failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or
systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
●
●
USA
●
Email: hbwhelp@micrel.com
www.micrel.com
______________________________________________________________________________________________________________________________________________
DSC400 Page 15
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