DSC558-03 [MICREL]
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator;
| 型号： | DSC558-03 |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Crystal-less Two Output PCIe Gen1/2/3 Clock Generator PC |
| 文件： | 总9页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSC558-03
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
Features
General Description
Meets PCIe Gen1, Gen2 & Gen3 specs.
The DSC557-03 is a crystal-less, two output
PCI express clock generator meeting Gen1,
Gen2, and Gen3 specifications. The clock
generator uses proven silicon MEMS
technology to provide 100MHz and 60 MHz
differential output clocks with excellent jitter
and stability over a wide range of supply
voltages and temperatures. By eliminating
the external quartz crystal, the DSSC558-03
Available Output Formats:
o HCSL, LVPECL, or LVDS
o HCSL/LVPECL, HCSL/LVDS, LVPECL/LVDS
Wide Temperature Range
o Ext. Industrial: -40° to 105° C
o Industrial: -40° to 85° C
significantly
enhances
reliability
and
o Ext. commercial: -20° to 70° C
Supply Range of 2.25 to 3.6 V
accelerates product development, while
meeting stringent clock performance criteria
for a variety of communications, storage,
and networking applications.
Low Power Consumption
o 30% lower than competing devices
DSC557-03 has an Output Enable / Disable
feature allowing it to disable the outputs
when OE is low. The device is available in
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
two
different
packages;
a
“drop-in”
Available Footprints:
o 16 TSSOP
o 14 QFN
replacement 16 pin TSSOP or a space
saving 14 pin QFN (77% less board space).
Additional output formats are also available
in any combination of LVPECL, LVDS, and
HCSL.
Lead Free & RoHS Compliant
Short Lead Time: 2 Weeks
Block Diagram
Applications
Control Circuitry
Communications/Networking
o Ethernet
CLK0+
Output
Control
and
MEMS
PLL
CLK0-
o 1G, 10GBASE-T/KR/LR/SR, and FcoE
o Routers and Switches
o Gateways, VoIP, Wireless AP’s
o Passive Optical Networks
Storage
Divider
CLK1-
CLK1+
OE
o SAN, NAS, SSD, JBOD
Embedded Applications
o Industrial, Medical, and Avionics
o Security Systems and Office
Automation
* Clk0+/- is 100MHz and Clk1+/- is 60 MHz per
PCIe standards. For other frequencies, please
contact the factory.
o Digital Sinage, POS and others
Consumer Electronics
o Smart TV, Bluray, STB
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 1 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
Specifications (Unless specified otherwise: T=25° C, VDD =3.3V)
Parameter
Condition
Min.
Typ.
Max.
Unit
Supply Voltage1
VDD
IDD
2.25
3.6
V
EN pin low – outputs are
disabled
EN pin high – outputs are
enabled. RL=100 Ω,
FO1=100 MHz, FO2= 60MHz
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
Supply Current
21
38
23
mA
Supply Current2
(Two HCSL Outputs)
IDD
mA
±100
Frequency Stability
Δf
ppm
ms
V
±50
5
Startup Time3
Input Logic Levels
Input logic high
Input logic low
tSU
VIH
VIL
0.75xVDD
-
-
0.25xVDD
Output Disable Time4
Output Enable Time
Pull-Up Resistor2
tDA
5
ns
ns
tEN
20
Pull-up on OE pin
40
kΩ
LVDS Outputs6
Condition
Parameter
Min.
Typ.
Max.
1.4
Unit
V
Output Offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time4
Rise Time
R=100Ω Differential
1.125
50
mV
mV
Single-Ended
350
200
20% to 80%
RL=100Ω, CL= 2pF (to GND)
tR
tF
350
ps
Fall Time
FO1
FO2
2.3
2.3
1007
607
Frequency
f0
460
52
MHz
Output Duty Cycle
Period Jitter5
SYM
JPER
Differential
48
%
FO1=100 MHz, FO2=60 MHz
2.5
psRMS
PCIe Gen 1.1
TJ=DJ + 14.069 x RJ (BER 10-12)
RJ
0.540
PsRMS
DJ
TJ
PCIe Gen 1.1
TJ=DJ + 14.069 x RJ (BER 10-12)
0.832
8.536
41.98
86.08
Jitter, Phase
(Common Clock
Architecture)
psp-p
PCIe Gen 2.1, 1.5 MHz to
Nyquist
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
JRMS-CCHF
0.458
3.18
psRMS
JRMS-CCLF
JRMS-CC
0.030
0.165
3.08
1.08
psRMS
psRMS
PCIe Gen 2.1, 1.5 MHz to
Nyquist
JRMS-DCHF
0.561
4.08
psRMS
Integrated Phase Noise
(Data Clock
Architecture)
JRMS-DCLF
JRMS-DC
PCIe Gen 2.1, 10 kHz to 1.5 MHz
PCIe Gen 3.0
1.778
0.147
7.58
1.08
psRMS
psRMS
Notes:
1. VDD should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact Sales@Discera.com for alternate output options (LVPECL, HCSL, LVCMOS).
7. Contact Sales@Discera.com for alternative frequency options
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 2 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
Absolute Maximum Ratings
Item
Min
-0.3
-0.3
-
Max
+4.0
Unit
V
Condition
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
VDD+0.3
+150
V
°C
°C
°C
V
-55
-
+150
+260
40sec max.
ESD
HBM
MM
-
4000
400
CDM
1500
Solder Reflow Profile
20-40
Sec
260°C
217°C
200°C
60-150
Sec
Reflow
60-180
Sec
150°C
Cool
Pre heat
25°C
Time
8 min max
14 QFN
MSL 1 @ 260°C refer to JSTD-020C
16 TSSOP MSL 3 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
60-180 Sec
60-150 Sec
255-260°C
20-40 Sec
Preheat Time 150°C to 200°C
Time maintained above 217°C
Peak Temperature
Time within 5°C of actual Peak
Ramp-Down Rate
6°C/Sec Max.
8 min Max.
Time 25°C to Peak Temperature
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 3 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
Pin Diagram (16 TSSOP)
Connection Diagram
(16 TSSOP Two LVDS Outputs)
+
VDD
-
NC
NC
NC
NC
NC
OE
VSS
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
CLK0+
CLK0-
NC
0.01 uF
16
15
14
13
12
11
1
2
3
4
5
6
7
CLK0+
100 W
NC
CLK0-
CLK1-
CLK1-
CLK1+
NC
+
Enable
-
10
9
100 W
8
16-TSSOP (173 mil)
(5.1 x 6.8 mm)
CLK1+
Pin Description (16 TSSOP)
Pin No. Pin Name9
Pin Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
NC
NC
NC
NC
OE
VSS
NC
NA
NA
NA
NA
NA
I
Power
NA
NA
O
No connect
No connect
No connect
No connect
No connect
Output Enable; active high
Ground
No connect
No connect
NC
CLK1+
CLK1-
NC
True output of differential pair
Complement output of differential pair
No connect
O
NA
NA
O
O
Power
No connect
NC
CLK0-
CLK0+
VDD
Complement output of differential pair
True output of differential pair
Power Supply
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 4 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
Pin Diagram (14 QFN)
Connection Diagram
(14 QFN Two LVDS Outputs)
14 13 12
+
VDD
-
0.01 uF
0.01 uF
OE
NC
1
2
3
4
11
10
9
CLK0+
CLK0-
CLK1-
CLK1+
14 13 12
CLK0+
NC
1
2
3
4
11
10
9
100 W
100 W
VSS
8
CLK0-
CLK1-
+
Enable
-
5
6
7
8
CLK1+
5
6
7
14 QFN 3.2x2.5mm
Pin Description (14 QFN)
Pin
Type
I
NA
NA
Power
NA
NA
Pin No.
Pin Name
Description
Output Enable; active high
Ground recommended or leave as a NC
Ground recommended or leave as a NC
Ground
Ground recommended or leave as a NC
Ground recommended or leave as a NC
Ground recommended or leave as a NC
1
2
3
4
5
OE
NC
NC
VSS
NC
6
7
NC
NC
NA
8
9
CLK1+
CLK1-
CLK0-
CLK0+
VDD1
VDD0
NC
O
O
O
O
True output of differential pair
Complement output of differential pair
Complement output of differential pair
True output of differential pair
Power Supply for Core and Output 1 (CLK0+/-)
Power Supply for Output 0 (CLK1+/-)
10
11
12
13
14
Power
Power
NA
Ground recommended or leave as a NC
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 5 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
OE Function and Output Waveform: LVDS
tR
tF
Output
Output
80%
50%
20%
350 mV
tEN
1/fo
tDA
VIH
Enable
VIL
Ordering Information9
DSC557-03 3 3 F I 0 - T
Packing
T: Tape & Reel
CLK 1 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Stability
0: ±100ppm
1: ±50ppm
Temp Range
E: -20 to 70
I: -40 to 85
L: -40 to 105
CLK 0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Package
F: 14 QFN
S: 16 TSSOP
Note 9. CLK0 and CLK1 are configured at the factory to 100 MHz and 60 MHz respectively. (For other frequencies, contact the
factory at sales@discera.com.)
______________________________________________________________________________________________________________________________________________
DSC558-03
Page 6
MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
Package Dimensions
F: 14 QFN, 3.2 x 2.5 mm
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 7 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
S: 16 TSSOP (173 mil body width)
Recommended Solder
Pad Layout
Units mm [in]
1.1[0.043]
0.65 [0.256]
6.8[0.268]
4.6 [0.181]
0.3 [0.012]
4.85 [0.191]
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 8 MK-QB-P-D-130612
Crystal-less Two Output PCIe Gen1/2/3 Clock Generator
DSC558-03
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information
is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims
any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the
body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or
sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any
damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
●
●
USA
●
Email: hbwhelp@micrel.com
www.micrel.com
______________________________________________________________________________________________________________________________________________
DSC558-03 Page 9 MK-QB-P-D-130612
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