KSZ8081RNAIA_技术文档

KSZ8081RNA/KSZ8081RND

10Base-T/100Base-TX PHY

with RMII Support

Revision 1.1

General Description

Features

The KSZ8081RNA is a single-supply 10Base-T/100Base-

TX Ethernet physical-layer transceiver for transmission

and reception of data over standard CAT-5 unshielded

twisted pair (UTP) cable.

• Single-chip 10Base-T/100Base-TX IEEE 802.3

compliant Ethernet transceiver

• RMII v1.2 Interface support with a 50MHz reference

clock output to MAC, and an option to input a 50MHz

reference clock

The KSZ8081RNA is a highly-integrated PHY solution. It

reduces board cost and simplifies board layout by using on-

chip termination resistors for the differential pairs and by

integrating a low-noise regulator to supply the 1.2V core, and

by offering 1.8/2.5/3.3V digital I/O interface support.

• RMII back-to-back mode support for a 100Mbps copper

repeater

• MDC/MDIO management interface for PHY register

configuration

The KSZ8081RNA offers the Reduced Media Independent

Interface (RMII) for direct connection to RMII-compliant

MACs in Ethernet processors and switches.

• Programmable interrupt output

• LED outputs for link and activity status indication

• On-chip termination resistors for the differential pairs

• Baseline wander correction

• HP Auto MDI/MDI-X to reliably detect and correct

straight-through and crossover cable connections with

disable and enable option

As the power-up default, the KSZ8081RNA uses a 25MHz

crystal to generate all required clocks, including the

50MHz RMII reference clock output for the MAC. The

KSZ8081RND is the version that takes in the 50MHz RMII

reference clock as the power-up default.

To facilitate system bring-up and debugging in production

testing and in product deployment, parametric NAND tree

support enables fault detection between KSZ8081RNA

I/Os and the board. Micrel’s LinkMD^®TDR-based cable

diagnostics identify faulty copper cabling.

• Auto-negotiation to automatically select the highest link-

up speed (10/100Mbps) and duplex (half/full)

• Power-down and power-saving modes

• LinkMD TDR-based cable diagnostics to identify faulty

copper cabling

The KSZ8081RNA and KSZ8081RND are available in 24-

pin, lead-free QFN packages (see “Ordering Information”).

• Parametric NAND Tree support for fault detection

between chip I/Os and the board

Data sheets and support documentation are available on

Micrel’s web site at: www.micrel.com.

Functional Diagram

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

Revision 1.1

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KSZ8081RNA/KSZ8081RND

Features (Continued)

Applications

• Loopback modes for diagnostics

• Game console

• IP phone

• IP set-top box

• IP TV

• Single 3.3V power supply with VDD I/O options for

1.8V, 2.5V, or 3.3V

• Built-in 1.2V regulator for core

• Available in 24-pin (4mm x 4mm) QFN package

• LOM

• Printer

Ordering Information

Temperature

Lead

Finish

Wire

Bonding

Part Number

Package

Description

Range

RMII with 25MHz crystal/clock input and 50MHz

RMII REF_CLK output (power-up default),

Commercial Temperature, Gold Wire Bonding

KSZ8081RNACA

0°C to 70°C

24-Pin QFN

Pb-Free

Gold

RMII with 25MHz crystal/clock input and 50MHz

RMII REF_CLK output (power-up default),

Industrial Temperature, Gold Wire Bonding

KSZ8081RNAIA⁽¹⁾

KSZ8081RNDCA

24-Pin QFN

Pb-Free

Gold

−40°C to 85°C

RMII with 50MHz clock input (power-up default),

Commercial Temperature, Gold Wire Bonding

0°C to 70°C

KSZ8081RNA Evaluation Board

KSZ8081RNA-EVAL

KSZ8081RND-EVAL

0°C to 70°C

24-Pin QFN

Pb-Free

(Mounted with KSZ8081RNA device in

commercial temperature)

KSZ8081RND Evaluation Board

(Mounted with KSZ8081RND device in

commercial temperature)

Note:

1. Contact factory for availability.

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KSZ8081RNA/KSZ8081RND

Revision History

Date

Summary of Changes

Revision

11/5/12

Initial release of datasheet.

1.0

Removed copper wire bonding part numbers from Ordering Information.

Added note for RXER (Pin 17) and Register 16h, Bit [15] regarding a Reserved Factory Mode.

2/6/14

1.1

Added series resistance and load capacitance for the 25MHz crystal selection criteria.

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Contents

List of Figures.......................................................................................................................................................................... 6

List of Tables........................................................................................................................................................................... 7

Pin Configuration..................................................................................................................................................................... 8

Pin Description ........................................................................................................................................................................ 9

Strapping Options .................................................................................................................................................................11

Functional Description: 10Base-T/100Base-TX Transceiver................................................................................................12

100Base-TX Transmit..........................................................................................................................................................................12

100Base-TX Receive...........................................................................................................................................................................12

Scrambler/De-Scrambler (100Base-TX Only)......................................................................................................................................12

10Base-T Transmit..............................................................................................................................................................................12

10Base-T Receive...............................................................................................................................................................................13

PLL Clock Synthesizer ........................................................................................................................................................................13

Auto-Negotiation..................................................................................................................................................................................13

RMII Interface........................................................................................................................................................................15

RMII Signal Definition..........................................................................................................................................................................15

RMII Signal Diagram – 25/50MHz Clock Mode ...................................................................................................................................16

Back-to-Back Mode – 100Mbps Copper Repeater ...............................................................................................................18

RMII Back-to-Back Mode.....................................................................................................................................................................18

MII Management (MIIM) Interface.........................................................................................................................................19

Interrupt (INTRP)...................................................................................................................................................................19

HP Auto MDI/MDI-X..............................................................................................................................................................19

Straight Cable......................................................................................................................................................................................20

Crossover Cable..................................................................................................................................................................................20

Loopback Mode.....................................................................................................................................................................21

Local (Digital) Loopback......................................................................................................................................................................21

Remote (Analog) Loopback.................................................................................................................................................................22

LinkMD^®Cable Diagnostic....................................................................................................................................................23

NAND Tree Support..............................................................................................................................................................23

NAND Tree I/O Testing .......................................................................................................................................................................24

Power Management..............................................................................................................................................................24

Power-Saving Mode ............................................................................................................................................................................24

Energy-Detect Power-Down Mode ......................................................................................................................................................24

Power-Down Mode..............................................................................................................................................................................24

Slow-Oscillator Mode...........................................................................................................................................................................25

Reference Circuit for Power and Ground Connections.........................................................................................................26

Typical Current/Power Consumption ....................................................................................................................................27

Transceiver (3.3V), Digital I/Os (3.3V).................................................................................................................................................27

Transceiver (3.3V), Digital I/Os (2.5V).................................................................................................................................................27

Transceiver (3.3V), Digital I/Os (1.8V).................................................................................................................................................28

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KSZ8081RNA/KSZ8081RND

Register Map.........................................................................................................................................................................29

Register Description..............................................................................................................................................................30

Absolute Maximum Ratings ..................................................................................................................................................39

Operating Ratings .................................................................................................................................................................39

Electrical Characteristics.......................................................................................................................................................39

Timing Diagrams...................................................................................................................................................................41

RMII Timing.........................................................................................................................................................................................41

Auto-Negotiation Timing......................................................................................................................................................................42

MDC/MDIO Timing ..............................................................................................................................................................................43

Power-Up/Reset Timing ......................................................................................................................................................................44

Reset Circuit..........................................................................................................................................................................45

Reference Circuits – LED Strap-In Pins................................................................................................................................46

Reference Clock – Connection and Selection ......................................................................................................................47

Magnetic – Connection and Selection ..................................................................................................................................48

Recommended Land Pattern ................................................................................................................................................50

Package Information .............................................................................................................................................................51

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List of Figures

Figure 1. Auto-Negotiation Flow Chart.................................................................................................................................14

Figure 2. KSZ8081RNA/RND RMII Interface (RMII – 25MHz Clock Mode) ........................................................................17

Figure 3. KSZ8081RNA/RND RMII Interface (RMII – 50MHz Clock Mode) ........................................................................17

Figure 4. KSZ8081RNA/RND and KSZ8081RNA/RND RMII Back-to-Back Copper Repeater...........................................18

Figure 5. Typical Straight Cable Connection .......................................................................................................................20

Figure 6. Typical Crossover Cable Connection ...................................................................................................................21

Figure 7. Local (Digital) Loopback .......................................................................................................................................21

Figure 8. Remote (Analog) Loopback ..................................................................................................................................22

Figure 9. KSZ8081RNA/RND Power and Ground Connections..........................................................................................26

Figure 10. RMII Timing – Data Received from RMII............................................................................................................41

Figure 11. RMII Timing – Data Input to RMII .......................................................................................................................41

Figure 12. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................42

Figure 13. MDC/MDIO Timing..............................................................................................................................................43

Figure 14. Power-Up/Reset Timing......................................................................................................................................44

Figure 15. Recommended Reset Circuit..............................................................................................................................45

Figure 16. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output .....................................................45

Figure 17. Reference Circuits for LED Strapping Pins.........................................................................................................46

Figure 18. 25MHz Crystal/Oscillator Reference Clock Connection .....................................................................................47

Figure 19. 50MHz Oscillator Reference Clock Connection .................................................................................................47

Figure 20. Typical Magnetic Interface Circuit.......................................................................................................................48

Figure 21. Recommended Land Pattern, 24-Pin (4mm × 4mm) QFN.................................................................................50

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KSZ8081RNA/KSZ8081RND

List of Tables

Table 1. RMII Signal Definition.............................................................................................................................................15

Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ......................................18

Table 3. MII Management Frame Format for the KSZ8081RNA/RND ................................................................................19

Table 4. MDI/MDI-X Pin Definition .......................................................................................................................................20

Table 5. NAND Tree Test Pin Order for KSZ8081RNA/RND ..............................................................................................23

Table 6. KSZ8081RNA/RND Power Pin Description ...........................................................................................................26

Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)............................................................27

Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)............................................................27

Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)............................................................28

Table 10. RMII Timing Parameters – KSZ8081RNA/RND (25MHz input to XI pin, 50MHz output from REF_CLK pin) ....41

Table 11. RMII Timing Parameters – KSZ8081RNA/RND (50MHz input to XI pin) ............................................................41

Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters...............................................................................42

Table 13. MDC/MDIO Timing Parameters...........................................................................................................................43

Table 14. Power-Up/Reset Timing Parameters ...................................................................................................................44

Table 15. 25MHz Crystal / Reference Clock Selection Criteria ...........................................................................................47

Table 16. 50MHz Oscillator / Reference Clock Selection Criteria .......................................................................................47

Table 17. Magnetics Selection Criteria ................................................................................................................................49

Table 18. Compatible Single-Port 10/100 Magnetics...........................................................................................................49

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KSZ8081RNA/KSZ8081RND

Pin Configuration

24-Pin (4mm × 4mm) QFN

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KSZ8081RNA/KSZ8081RND

Pin Description

Pin Number

Pin Name

Type⁽¹⁾

Pin Function

1.2V core V_DD(power supplied by KSZ8081RNA/KSZ8081RND)

Decouple with 2.2µF and 0.1µF capacitors to ground.

3.3V analog V_DD

1

VDD_1.2

P

2

3

4

5

6

VDDA_3.3

RXM

P

I/O

Physical receive or transmit signal (− differential)

Physical receive or transmit signal (+ differential)

Physical transmit or receive signal (− differential)

Physical transmit or receive signal (+ differential)

Crystal feedback for 25MHz crystal

RXP

TXM

TXP

7

XO

XI

O

This pin is a no connect if an oscillator or external clock source is used.

RMII – 25MHz Mode:

RMII – 50MHz Mode:

25MHz ±50ppm Crystal / Oscillator / External Clock Input

50MHz ±50ppm Oscillator / External Clock Input

For unmanaged mode (power-up default setting),

KSZ8081RNA takes in the 25MHz crystal/clock on this pin.

KSZ8081RND takes in the 50MHz clock/on this pin.

8

I

After power-up, both the KSZ8081RNA and KSZ8081RND can be programmed to

either the 25MHz mode or 50MHz mode using PHY register 1Fh bit [7].

See also XI (pin 8).

RMII Receive Error output

17

18

RXER

INTRP

Ipd/O

At the de-assertion of reset, this pin needs to latch in a pull-down value for normal

operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution.

Interrupt output: Programmable interrupt output

Ipu/Opu

This pin has a weak pull-up, is open drain, and requires an external 1.0kΩ pull-up

resistor.

19

20

TXEN

TXD0

I

RMII Transmit Enable input

RMII Transmit Data Input[0]⁽³⁾

RMII Transmit Data Input[1]⁽³⁾

21

22

TXD1

GND

I/O

NAND Tree mode:

Ground

NAND Tree output pin

Gnd

LED output:

Programmable LED0 output

Config mode:

Latched as auto-negotiation enable (register 0h, bit [12]) and

Speed (register 0h, bit [13]) at the de-assertion of reset.

See the “Strapping Options” section for details.

The LED0 pin is programmable using register 1Fh bits

[5:4], and is defined as follows.LED mode = [00]

Link/Activity

No link

Pin State

High

LED Definition

OFF

LED0 /

Link

Low

ON

23

Ipu/O

ANEN_SPEED

Activity

Toggle

Blinking

LED mode = [01]

Link

Pin State

High

LED Definition

No link

Link

OFF

ON

Low

LED mode = [10], [11]

Chip reset (active low)

Ground

Reserved

24

RST#

GND

Ipu

PADDLE

Gnd

Notes:

2. RMII RX Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted,

two bits of recovered data are sent by the PHY to the MAC.

3. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two

bits of data are received by the PHY from the MAC.

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KSZ8081RNA/KSZ8081RND

Strapping Options

Type⁽¹⁾

Pin Number

Pin Name

Pin Function

The PHY Address is latched at the de-assertion of reset and is configurable to either

one of the following two values:

Pull-up = PHY Address is set to 00011b (0x3h)

Pull-down (default) = PHY Address is set to 00000b (0x0h)

PHY Address bits [4:2] are set to 000 by default.

15

PHYAD[1:0]

Ipd/O

Auto-Negotiation Enable and SPEED mode

Pull-up (default) = Enable Auto-Negotiation and set 100Mbps Speed

Pull-down = Disable Auto-Negotiation and set 10Mbps Speed

23

ANEN_SPEED

Ipu/O

At the de-assertion of reset, this pin value is latched into register 0h bit [12] for Auto-

negotiation enable/disable, register 0h bit [13] for the Speed select, and register 4h

(Auto-Negotiation Advertisement) for the Speed capability support.

Note:

1. Ipu/O = Input with internal pull-up (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see “Electrical Characteristics” for value) during power-up/reset; output pin otherwise.

The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins

may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with the

RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7kΩ) or pull-down

(1.0kΩ) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.

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KSZ8081RNA/KSZ8081RND

Functional Description: 10Base-T/100Base-TX Transceiver

The KSZ8081RNA is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3

Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two

differential pairs and by integrating the regulator to supply the 1.2V core.

On the copper media side, the KSZ8081RNA supports 10Base-T and 100Base-TX for transmission and reception of data

over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and

correction for straight-through and crossover cables.

On the MAC processor side, the KSZ8081RNA offers the Reduced Media Independent Interface (RMII) for direct

connection with RMII-compliant Ethernet MAC processors and switches

The MII management bus option gives the MAC processor complete access to the KSZ8081RNA control and status

registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.

As the power-up default, the KSZ8081RNA uses a 25MHz crystal to generate all required clocks, including the 50MHz

RMII reference clock output for the MAC. The KSZ8081RND version uses the 50MHz RMII reference clock as the power-

up default.

The KSZ8081RNA/RND is used to refer to both KSZ8081RNA and KSZ8081RND versions in this data sheet.

100Base-TX Transmit

The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI

conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit

stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data

is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by

an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX

transmitter.

100Base-TX Receive

The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair

cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its

characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. This

is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit

compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit

converts MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used

to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder. Finally,

the NRZ serial data is converted to MII format and provided as the input data to the MAC.

Scrambler/De-Scrambler (100Base-TX Only)

The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and

baseline wander. The de-scrambler recovers the scrambled signal.

10Base-T Transmit

The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.

The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of

2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency when

driven by an all-ones Manchester-encoded signal.

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KSZ8081RNA/KSZ8081RND

10Base-T Receive

On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent

noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL

locks onto the incoming signal and the KSZ8081RNA/RND decodes a data frame. The receive clock is kept active during

idle periods between data receptions.

PLL Clock Synthesizer

The KSZ8081RNA/RND in RMII – 25MHz Clock mode generates all internal clocks and all external clocks for system

timing from an external 25MHz crystal, oscillator, or reference clock. For the KSZ8081RNA/RND in RMII – 50MHz clock

mode, these clocks are generated from an external 50MHz oscillator or system clock.

Auto-Negotiation

The KSZ8081RNA/RND conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.

Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.

During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their own

capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the

two link partners is selected as the mode of operation.

The following list shows the speed and duplex operation mode from highest to lowest priority.

•

Priority 1: 100Base-TX, full-duplex

Priority 2: 100Base-TX, half-duplex

Priority 3: 10Base-T, full-duplex

Priority 4: 10Base-T, half-duplex

If auto-negotiation is not supported or the KSZ8081RNA/RND link partner is forced to bypass auto-negotiation, then the

KSZ8081RNA/RND sets its operating mode by observing the signal at its receiver. This is known as parallel detection,

which allows the KSZ8081RNA/RND to establish a link by listening for a fixed signal protocol in the absence of the auto-

negotiation advertisement protocol.

Auto-negotiation is enabled by either hardware pin strapping (ANEN_SPEED, pin 23) or software (register 0h, bit [12]).

By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or

disabled by register 0h, bit [12]. If auto-negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is

set by register 0h, bit [8].

The auto-negotiation link-up process is shown in Figure 1.

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KSZ8081RNA/KSZ8081RND

Figure 1. Auto-Negotiation Flow Chart

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KSZ8081RNA/KSZ8081RND

RMII Interface

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides

a common interface between physical layer and MAC layer devices, and has the following key characteristics:

•

Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock).

10Mbps and 100Mbps data rates are supported at both half- and full-duplex.

Data transmission and reception are independent and belong to separate signal groups.

Transmit data and receive data are each 2 bits wide, a dibit.

RMII Signal Definition

Table 1 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.

RMII

Signal

Name

Direction

(with respect to PHY,

KSZ8081RNA/RND signal)

Direction

(with respect to MAC)

Description

REF_CLK

Output (25MHz clock mode) /

Input/

Synchronous 50MHz reference clock for receive,

transmit, and control interface

<no connect> (50MHz clock

mode)

Input or <no connect>

TXEN

Input

Output

Transmit Enable

TXD[1:0]

CRS_DV

RXD[1:0]

RXER

Input

Output

Transmit Data[1:0]

Carrier Sense/Receive Data Valid

Receive Data[1:0]

Output

Input

Input, or (not required)

Receive Error

Table 1. RMII Signal Definition

Reference Clock (REF_CLK)

REF_CLK is a continuous 50MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0], and

RX_ER.

For RMII – 25MHz Clock Mode, the KSZ8081RNA/RND generates and outputs the 50MHz RMII REF_CLK to the MAC at

REF_CLK (pin 16).

For RMII – 50MHz Clock Mode, the KSZ8081RNA/RND takes in the 50MHz RMII REF_CLK from the MAC or system

board at XI (pin 8) and leaves the REF_CLK (pin 16) as no connect.

Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first

dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated

before the first REF_CLK following the final dibit of a frame.

TXEN transitions synchronously with respect to REF_CLK.

Transmit Data[1:0] (TXD[1:0])

TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for

transmission.

TXD[1:0] is 00 to indicate idle when TXEN is de-asserted. The PHY ignores values other than 00 on TXD[1:0] while TXEN

is de-asserted.

Carrier Sense / Receive Data Valid (CRS_DV)

The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is detected.

This happens when squelch is passed in 10Mbps mode, and when two non-contiguous 0s in 10 bits are detected in

100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.

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While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the frame

through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on RXD[1:0] is

considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous relative to

REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.

Receive Data[1:0] (RXD[1:0])

RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,

RXD[1:0] transfers two bits of recovered data from the PHY.

RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while

CRS_DV is de-asserted.

Receive Error (RXER)

RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a

PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being

transferred from the PHY.

RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RXER has no effect on the

MAC.

Collision Detection (COL)

The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.

RMII Signal Diagram – 25/50MHz Clock Mode

The KSZ8081RNA/RND RMII pin connections to the MAC for 25MHz clock mode are shown in Figure 2. The connections

for 50MHz clock mode are shown in Figure 3 .

RMII – 25MHz Clock Mode

The KSZ8081RNA is configured to RMII – 25MHz clock mode after it is powered up or hardware reset with the following:

•

A 25MHz crystal connected to XI, XO (pins 8, 7), or an external 25MHz clock source (oscillator) connected to XI

The KSZ8081RND can optionally be configured to RMII – 25MHz clock mode after it is powered up or hardware reset and

software programmed with the following:

•

A 25MHz crystal connected to XI, XO (pins 8, 7), or an external 25MHz clock source (oscillator) connected to XI

Register 1Fh, bit [7] programmed to ‘1’ to select RMII – 25MHz clock mode

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Figure 2. KSZ8081RNA/RND RMII Interface (RMII – 25MHz Clock Mode)

RMII – 50MHz Clock Mode

The KSZ8081RND is configured to RMII – 50MHz clock mode after it is powered up or hardware reset with the following:

An external 50MHz clock source (oscillator) connected to XI (pin 8)

•

The KSZ8081RNA can optionally be configured to RMII – 50MHz clock mode after it is powered up or hardware reset and

software programmed with the following:

•

An external 50MHz clock source (oscillator) connected to XI (pin 8)

Register 1Fh, bit [7] programmed to ‘1’ to select RMII – 50MHz clock mode

Figure 3. KSZ8081RNA/RND RMII Interface (RMII – 50MHz Clock Mode)

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Back-to-Back Mode – 100Mbps Copper Repeater

Two KSZ8081RNA/RND devices can be connected back-to-back to form a managed 100Base-TX copper repeater.

Figure 4. KSZ8081RNA/RND and KSZ8081RNA/RND RMII Back-to-Back Copper Repeater

RMII Back-to-Back Mode

In RMII back-to-back mode, a KSZ8081RNA/RND interfaces with another KSZ8081RNA/RND to provide a 100Mbps

copper repeater solution.

The KSZ8081RNA/RND devices are configured to RMII back-to-back mode after power-up or reset, and software

programming, with the following:

•

A common 50MHz reference clock connected to XI (pin 8)

Register 1Fh, bit [7] programmed to ‘1’ to select RMII – 50MHz clock mode for KSZ8081RNA

(KSZ8081RND is set to RMII – 50MHz clock mode as the default after power up or hardware reset)

Register 16h, bits [6] and [1] programmed to ‘1’ and ‘1’, respectively, to enable RMII back-to-back mode.

RMII signals connected as shown in Table 2

•

KSZ8081RNA/RND (100Base-TX copper)

[Device 1]

KSZ8081RNA/RND (100Base-TX copper)

[Device 2]

Pin Name

CRS_DV

RXD1

Pin Number

Pin Type

Output

Input

Pin Name

TXEN

Pin Number

Pin Type

Input

15

12

13

19

21

20

19

21

20

15

12

13

TXD1

Input

RXD0

TXD0

Input

TXEN

CRS_DV

RXD1

Output

TXD1

Input

TXD0

Input

RXD0

Table 2. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)

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MII Management (MIIM) Interface

The KSZ8081RNA/RND supports the IEEE 802.3 MII management interface, also known as the Management Data

Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and

control the state of the KSZ8081RNA/RND. An external device with MIIM capability is used to read the PHY status and/or

configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3

Specification.

The MIIM interface consists of the following:

•

A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

A specific protocol that operates across the physical connection mentioned earlier, which allows the external

controller to communicate with one or more PHY devices.

•

A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE

802.3 Specification. The additional registers are provided for expanded functionality. See the “Register Map” section

for details.

The KSZ8081RNA/RND supports only two unique PHY addresses. The PHYAD[1:0] strapping pin is used to select either

0h or 3h as the unique PHY address for the KSZ8081RNA/RND device.

PHY address 0h is defined as the broadcast PHY address according to the IEEE 802.3 Specification, and can be used to

read/write to a single PHY device, or write to multiple PHY devices simultaneously. For the KSZ8081RNA/RND, PHY

address 0h defaults to the broadcast PHY address after power-up, but PHY address 0h can be disabled as the broadcast

PHY address using software to assign it as a unique PHY address.

For applications that require two KSZ8081RNA/RND PHYs to share the same MDIO interface with one PHY set to

address 0h and the other PHY set to address 3h, use PHY address 0h (defaults to broadcast after power-up) to set both

PHYs’ register 16h, bit [9] to ‘1’ to assign PHY address 0h as a unique (non-broadcast) PHY address.

Table 3 shows the MII management frame format for the KSZ8081RNA/RND.

Start of Read/Write PHY Address

REG Address

Bits [4:0]

Data

Bits [15:0]

Preamble

TA

Idle

Frame

OP Code

Bits [4:0]

Read

Write

32 1’s

01

10

01

000AA

RRRRR

Z0

10

DDDDDDDD_DDDDDDDD

Z

01

000AA

Table 3. MII Management Frame Format for the KSZ8081RNA/RND

Interrupt (INTRP)

INTRP (pin 18) is an optional interrupt signal that is used to inform the external controller that there has been a status

update to the KSZ8081RNA/RND PHY register. Bits [15:8] of register 1Bh are the interrupt control bits to enable and

disable the conditions for asserting the INTRP signal. Bits [7:0] of register 1Bh are the interrupt status bits to indicate

which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.

Bit [9] of register 1Fh sets the interrupt level to active high or active low. The default is active low.

The MII management bus option gives the MAC processor complete access to the KSZ8081RNA/RND control and status

registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.

HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable

between the KSZ8081RNA/RND and its link partner. This feature allows the KSZ8081RNA/RND to use either type of

cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and

receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8081RNA/RND accordingly.

HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to register 1Fh, bit [13]. MDI and MDI-X mode is

selected by register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.

An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.

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Table 4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.

MDI

MDI-X

RJ-45 Pin

Signal

TX+

RJ-45 Pin

Signal

RX+

RX−

TX+

1

2

3

6

1

2

3

6

TX−

RX+

RX−

TX−

Table 4. MDI/MDI-X Pin Definition

Straight Cable

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 5 shows a

typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).

Figure 5. Typical Straight Cable Connection

Crossover Cable

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 6

shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

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Figure 6. Typical Crossover Cable Connection

Loopback Mode

The KSZ8081RNA/RND supports the following loopback operations to verify analog and/or digital data paths.

•

Local (digital) loopback

Remote (analog) loopback

Local (Digital) Loopback

This loopback mode checks the RMII transmit and receive data paths between the KSZ8081RNA/RND and the external

MAC, and is supported for both speeds (10/100Mbps) at full-duplex.

The loopback data path is shown in Figure 7.

1. The RMII MAC transmits frames to the KSZ8081RNA/RND.

2. Frames are wrapped around inside the KSZ8081RNA/RND.

3. The KSZ8081RNA/RND transmits frames back to the RMII MAC.

Figure 7. Local (Digital) Loopback

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The following programming action and register settings are used for local loopback mode.

For 10/100Mbps loopback,

Set register 0h,

•

Bit [14] = 1

Bit [13] = 0/1

Bit [12] = 0

Bit [8] = 1

// Enable local loopback mode

// Select 10Mbps/100Mbps speed

// Disable auto-negotiation

// Select full-duplex mode

Remote (Analog) Loopback

This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive

data paths between the KSZ8081RNA/RND and its link partner, and is supported for 100Base-TX full-duplex mode only.

The loopback data path is shown in Figure 8.

1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8081RNA/RND.

2. Frames are wrapped around inside the KSZ8081RNA/RND.

3. The KSZ8081RNA/RND transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.

Figure 8. Remote (Analog) Loopback

The following programming steps and register settings are used for remote loopback mode.

1. Set Register 0h,

•

Bits [13] = 1

Bit [12] = 0

Bit [8] = 1

// Select 100Mbps speed

// Disable auto-negotiation

// Select full-duplex mode

Or just auto-negotiate and link up at 100Base-TX full-duplex mode with the link partner.

2. Set Register 1Fh,

Bit [2] = 1

•

// Enable remote loopback mode

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LinkMD^®Cable Diagnostic

The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.

These include open circuits, short circuits, and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape

of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the

approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a

numerical value that can be translated to a cable distance.

LinkMD is initiated by accessing register 1Dh, the LinkMD Control/Status register, in conjunction with register 1Fh, the

PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the

cable differential pair for testing.

NAND Tree Support

The KSZ8081RNA/RND provides parametric NAND tree support for fault detection between chip I/Os and board. The

NAND tree is a chain of nested NAND gates in which each KSZ8081RNA/RND digital I/O (NAND tree input) pin is an

input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND

gates.

The NAND tree test process includes:

•

Enabling NAND tree mode

Pulling all NAND tree input pins high

Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order

Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input

driven low

Table 5 lists the NAND tree pin order.

Pin Number

Pin Name

MDIO

NAND Tree Description

10

11

12

13

15

16

18

19

23

20

21

Input

Output

MDC

RXD1

RXD0

CRS_DV

REF_CLK

INTRP

TXEN

LED0

TXD0

TXD1

Table 5. NAND Tree Test Pin Order for KSZ8081RNA/RND

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NAND Tree I/O Testing

Use the following procedure to check for faults on the KSZ8081RNA/RND digital I/O pin connections to the board:

1. Enable NAND tree mode by setting register 16h, bit [5] to ‘1’.

2. Use board logic to drive all KSZ8081RNA/RND NAND tree input pins high.

3. Use board logic to drive each NAND tree input pin, in KSZ8081RNA/RND tree pin order, as follows:

a. Toggle the first pin (MDIO) from high to low, and verify that the TDX1 pin switches from high to low to

indicate that the first pin is connected properly.

b. Leave the first pin (MDIO) low.

c. Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to

indicate that the second pin is connected properly.

d. Leave the first pin (MDIO) and the second pin (MDC) low.

e. Toggle the third pin from high to low, and verify that the TXD1 pin switches from high to low to indicate

that the third pin is connected properly.

f. Continue with this sequence until all KSZ8081RNA/RND NAND tree input pins have been toggled.

Each KSZ8081RNA/RND NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to

indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8081RNA/RND input pin toggles from high to low,

the input pin has a fault.

Power Management

The KSZ8081RNA/RND incorporates a number of power-management modes and features that provide methods to

consume less energy. These are discussed in the following sections.

Power-Saving Mode

Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by

writing a ‘1’ to register 1Fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected

(no link).

In this mode, the KSZ8081RNA/RND shuts down all transceiver blocks except the transmitter, energy detect, and PLL

circuits.

By default, power-saving mode is disabled after power-up.

Energy-Detect Power-Down Mode

Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is

unplugged. It is enabled by writing a ‘0’ to register 18h, bit [11], and is in effect when auto-negotiation mode is enabled

and the cable is disconnected (no link).

EDPD mode works with the PLL off (set by writing a ‘1’ to register 10h, bit [4] to automatically turn the PLL off in EDPD

mode) to turn off all KSZ8081RNA/RND transceiver blocks except the transmitter and energy-detect circuits.

Power can be reduced further by extending the time interval between transmissions of link pulses to check for the

presence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same low

power state and with auto MDI/MDI-X disabled can wake up when the cable is connected between them.

By default, energy-detect power-down mode is disabled after power-up.

Power-Down Mode

Power-down mode is used to power down the KSZ8081RNA/RND device when it is not in use after power-up. It is

enabled by writing a ‘1’ to register 0h, bit [11].

In this mode, the KSZ8081RNA/RND disables all internal functions except the MII management interface. The

KSZ8081RNA/RND exits (disables) power-down mode after register 0h, bit [11] is set back to ‘0’.

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Slow-Oscillator Mode

Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (pin 8) and select the on-chip slow

oscillator when the KSZ8081RNA/RND device is not in use after power-up. It is enabled by writing a ‘1’ to register 11h,

bit [5].

Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081RNA/RND device in the lowest

power state, with all internal functions disabled except the MII management interface. To properly exit this mode and

return to normal PHY operation, use the following programming sequence:

1. Disable slow-oscillator mode by writing a ‘0’ to register 11h, bit [5].

2. Disable power-down mode by writing a ‘0’ to register 0h, bit [11].

3. Initiate software reset by writing a ‘1’ to register 0h, bit [15].

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Reference Circuit for Power and Ground Connections

The KSZ8081RNA/RND is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and

ground connections are shown in Figure 9 and Table 6 for 3.3V VDDIO.

Figure 9. KSZ8081RNA/RND Power and Ground Connections

Power Pin

Pin Number Description

VDD_1.2

1

Decouple with 2.2µF and 0.1µF capacitors to ground.

Connect to board’s 3.3V supply through a ferrite bead.

Decouple with 22µF and 0.1µF capacitors to ground.

Connect to board’s 3.3V supply for 3.3V VDDIO.

Decouple with 22µF and 0.1µF capacitors to ground.

VDDA_3.3

VDDIO

2

14

Table 6. KSZ8081RNA/RND Power Pin Description

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Typical Current/Power Consumption

Table 7 through Table 9 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O

(VDDIO) power pins and typical values for power consumption by the KSZ8081RNA/RND device for the indicated nominal

operating voltage combinations. These current and power consumption values include the transmit driver current and on-

chip regulator current for the 1.2V core.

Transceiver (3.3V), Digital I/Os (3.3V)

3.3V Transceiver 3.3V Digital I/Os

Total Chip Power

(VDDA_3.3)

(VDDIO)

mA

12

Condition

mA

34

14

30

14

10

mW

152

155

82.5

135

79.2

66.0

100Base-TX Link-up (no traffic)

100Base-TX Full-duplex @ 100% utilization

10Base-T Link-up (no traffic)

13

11

10Base-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, bit [10] = 1)

EDPD mode (Reg. 18h, bit [11] = 0)

11

10

EDPD mode (Reg. 18h, bit [11] = 0) and

PLL off (Reg. 10h, bit [4] = 1)

3.77

2.59

1.36

1.54

1.51

0.45

17.5

13.5

5.97

Software power-down mode (Reg. 0h, bit [11] =1)

and slow-oscillator mode (Reg. 11h, bit [5] =1)

Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)

Transceiver (3.3V), Digital I/Os (2.5V)

3.3V Transceiver 2.5V Digital I/Os

Total Chip Power

(VDDA_3.3)

(VDDIO)

mA

12

Condition

mA

34

15

27

15

11

mW

142

145

77.0

117

74.5

61.3

100Base-TX Link-up (no traffic)

100Base-TX Full-duplex @ 100% utilization

10Base-T Link-up (no traffic)

13

11

10Base-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, bit [10] = 1)

EDPD mode (Reg. 18h, bit [11] = 0)

11

10

EDPD mode (Reg. 18h, bit [11] = 0) and

PLL off (Reg. 10h, bit [4] = 1)

3.55

2.29

1.15

1.35

1.34

0.29

15.1

10.9

4.52

Software power-down mode (Reg. 0h, bit [11] =1)

and slow-oscillator mode (Reg. 11h, bit [5] =1)

Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)

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Transceiver (3.3V), Digital I/Os (1.8V)

3.3V Transceiver 1.8V Digital I/Os

Total Chip Power

(VDDA_3.3)

(VDDIO)

mA

11

Condition

mA

34

15

27

15

11

mW

132

134

67.5

107

65.7

52.5

100Base-TX Link-up (no traffic)

100Base-TX Full-duplex @ 100% utilization

10Base-T Link-up (no traffic)

12

10

10Base-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, bit [10] = 1)

EDPD mode (Reg. 18h, bit [11] = 0)

10

9.0

EDPD mode (Reg. 18h, bit [11] = 0) and

PLL off (Reg. 10h, bit [4] = 1)

4.05

2.79

1.65

1.21

0.19

15.5

11.4

5.79

Software power-down mode (Reg. 0h, bit [11] =1)

and slow-oscillator mode (Reg. 11h, bit [5] =1)

Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)

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Register Map

Register Number (Hex)

Description

0h

1h

Basic Control

Basic Status

2h

PHY Identifier 1

3h

PHY Identifier 2

4h

Auto-Negotiation Advertisement

Auto-Negotiation Link Partner Ability

Auto-Negotiation Expansion

Auto-Negotiation Next Page

Link Partner Next Page Ability

Reserved

5h

6h

7h

8h

9h

10h

11h

12h – 14h

15h

16h

17h

18h

19h – 1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Digital Reserved Control

AFE Control 1

Reserved

RXER Counter

Operation Mode Strap Override

Operation Mode Strap Status

Expanded Control

Reserved

Interrupt Control/Status

Reserved

LinkMD Control/Status

PHY Control 1

PHY Control 2

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Register Description

Mode⁽¹⁾

Address

Name

Description

Default

Register 0h – Basic Control

1 = Software reset

0.15

0.14

Reset

0 = Normal operation

This bit is self-cleared after a ‘1’ is written to it.

1 = Loopback mode

0 = Normal operation

1 = 100Mbps

RW/SC

RW

0

Loopback

Set by the ANEN_SPEED

strapping pin.

0 = 10Mbps

0.13

0.12

Speed Select

RW

See the “Strapping Options”

section for details.

This bit is ignored if auto-negotiation is enabled

(register 0.12 = 1).

1 = Enable auto-negotiation process

0 = Disable auto-negotiation process

Set by the ANEN_SPEED

strapping pin.

Auto-

Negotiation

Enable

See the “Strapping Options”

section for details.

If enabled, the auto-negotiation result overrides

the settings in registers 0.13 and 0.8.

1 = Power-down mode

0 = Normal operation

If software reset (register 0.15) is used to exit

power-down mode (register 0.11 = 1), two

software reset writes (register 0.15 = 1) are

required. The first write clears power-down

mode; the second write resets the chip and re-

latches the pin strapping pin values.

0.11

Power-Down

Isolate

RW

0

1 = Electrical isolation of PHY from MII

0 = Normal operation

0.10

0.9

RW

RW/SC

RW

0

1

1 = Restart auto-negotiation process

0 = Normal operation.

Restart Auto-

Negotiation

This bit is self-cleared after a ‘1’ is written to it.

1 = Full-duplex

0.8

Duplex Mode

0 = Half-duplex

1 = Enable COL test

0.7

Collision Test

Reserved

RW

RO

0

0 = Disable COL test

0.6:0

Reserved

000_0000

Register 1h – Basic Status

1 = T4 capable

1.15

1.14

1.13

100Base-T4

RO

0

1

0 = Not T4 capable

1 = Capable of 100Mbps full-duplex

0 = Not capable of 100Mbps full-duplex

1 = Capable of 100Mbps half-duplex

0 = Not capable of 100Mbps half-duplex

100Base-TX

Full-Duplex

100Base-TX

Half-Duplex

Note:

1. RW = Read/Write.

RO = Read only.

SC = Self-cleared.

LH = Latch high.LL = Latch low.

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Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 1h – Basic Status

1 = Capable of 10Mbps full-duplex

0 = Not capable of 10Mbps full-duplex

1 = Capable of 10Mbps half-duplex

0 = Not capable of 10Mbps half-duplex

Reserved

10Base-T

1.12

RO

1

Full-Duplex

10Base-T

1.11

RO

1

Half-Duplex

1.10:7

1.6

Reserved

000_0

1

1 = Preamble suppression

No Preamble

0 = Normal preamble

Auto-

Negotiation

Complete

1 = Auto-negotiation process completed

0 = Auto-negotiation process not completed

1.5

1.4

1.3

1.2

RO

RO/LH

RO

0

1

0

1 = Remote fault

Remote Fault

0 = No remote fault

Auto-

Negotiation

Ability

1 = Can perform auto-negotiation

0 = Cannot perform auto-negotiation

1 = Link is up

Link Status

RO/LL

0 = Link is down

1 = Jabber detected

1.1

1.0

Jabber Detect

RO/LH

RO

0

1

0 = Jabber not detected (default is low)

Extended

Capability

1 = Supports extended capability registers

Register 2h – PHY Identifier 1

Assigned to the 3rd through 18th bits of the

Organizationally Unique Identifier (OUI).

KENDIN Communication’s OUI is 0010A1

(hex).

PHY ID

2.15:0

RO

0022h

Number

Register 3h – PHY Identifier 2

Assigned to the 19th through 24th bits of the

Organizationally Unique Identifier (OUI).

KENDIN Communication’s OUI is 0010A1

(hex).

PHY ID

3.15:10

RO

0001_01

Number

3.9:4

3.3:0

Model Number Six-bit manufacturer’s model number

RO

01_0110

Revision

Four-bit manufacturer’s revision number

Number

Indicates silicon revision

Register 4h – Auto-Negotiation Advertisement

1 = Next page capable

0 = No next page capability

Reserved

4.15

4.14

4.13

4.12

RW

RO

RW

RO

0

1 = Remote fault supported

0 = No remote fault

Reserved

Remote Fault

Reserved

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Revision 1.1

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KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 4h – Auto-Negotiation Advertisement

[00] = No pause

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

1 = T4 capable

4.11:10

Pause

RW

00

0

4.9

4.8

100Base-T4

RO

RW

0 = No T4 capability

Set by the ANEN_SPEED

strapping pin.

1 = 100Mbps full-duplex capable

100Base-TX

Full-Duplex

0 = No 100Mbps full-duplex capability

See the “Strapping Options”

section for details.

Set by the ANEN_SPEED

strapping pin.

1 = 100Mbps half-duplex capable

100Base-TX

Half-Duplex

4.7

4.6

RW

0 = No 100Mbps half-duplex capability

See the “Strapping Options”

section for details.

1 = 10Mbps full-duplex capable

0 = No 10Mbps full-duplex capability

1 = 10Mbps half-duplex capable

0 = No 10Mbps half-duplex capability

[00001] = IEEE 802.3

10Base-T

Full-Duplex

1

10Base-T

Half-Duplex

4.5

RW

1

4.4:0

Selector Field

0_0001

Register 5h – Auto-Negotiation Link Partner Ability

1 = Next page capable

5.15

5.14

RO

0

0 = No next page capability

1 = Link code word received from partner

0 = Link code word not yet received

1 = Remote fault detected

Acknowledge

5.13

5.12

Remote Fault

Reserved

RO

0

0 = No remote fault

Reserved

[00] = No pause

[10] = Asymmetric pause

5.11:10

Pause

RO

00

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

1 = T4 capable

5.9

5.8

5.7

5.6

100Base-T4

RO

0

0 = No T4 capability

1 = 100Mbps full-duplex capable

0 = No 100Mbps full-duplex capability

1 = 100Mbps half-duplex capable

0 = No 100Mbps half-duplex capability

1 = 10Mbps full-duplex capable

0 = No 10Mbps full-duplex capability

1 = 10Mbps half-duplex capable

0 = No 10Mbps half-duplex capability

[00001] = IEEE 802.3

100Base-TX

Full-Duplex

100Base-TX

Half-Duplex

10Base-T

Full-Duplex

10Base-T

Half-Duplex

5.5

RO

0

5.4:0

Selector Field

0_0001

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 6h – Auto-Negotiation Expansion

6.15:5

6.4

Reserved

RO

0000_0000_000

0

1 = Fault detected by parallel detection

0 = No fault detected by parallel detection

1 = Link partner has next page capability

Parallel

Detection Fault

RO/LH

RO

Link Partner

6.3

0

0 = Link partner does not have next page

capability

1 = Local device has next page capability

6.2

6.1

RO

1

0

0 = Local device does not have next page

capability

1 = New page received

Page Received

RO/LH

0 = New page not received yet

Link Partner

Auto-

Negotiation

Able

1 = Link partner has auto-negotiation capability

6.0

RO

0

0 = Link partner does not have auto-negotiation

capability

Register 7h – Auto-Negotiation Next Page

1 = Additional next pages will follow

0 = Last page

7.15

7.14

7.13

RO

RW

0

1

Reserved

1 = Message page

Message Page

0 = Unformatted page

1 = Will comply with message

0 = Cannot comply with message

7.12

Acknowledge2

Toggle

RW

0

1 = Previous value of the transmitted link code

word equaled logic 1

7.11

RO

RW

0

0 = Logic 0

7.10:0

Message Field 11-bit wide field to encode 2048 messages

000_0000_0001

Register 8h – Link Partner Next Page Ability

1 = Additional next pages will follow

0 = Last page

8.15

8.14

8.13

8.12

RO

0

1 = Successful receipt of link word

0 = No successful receipt of link word

1 = Message page

Acknowledge

Message Page

Acknowledge2

0 = Unformatted page

1 = Can act on the information

0 = Cannot act on the information

1 = Previous value of transmitted link code

word equal to logic 0

8.11

Toggle

RO

0

0 = Previous value of transmitted link code

word equal to logic 1

8.10:0

Message Field 11-bit wide field to encode 2048 messages

000_0000_0000

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33

Revision 1.1

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KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 10h – Digital Reserved Control

10.15:5

10.4

Reserved

PLL Off

Reserved

RW

0000_0000_000

1 = Turn PLL off automatically in EDPD mode

0 = Keep PLL on in EDPD mode.

See also register 18h, bit [11] for EDPD mode

Reserved

0

10.3:0

Reserved

0000

Register 11h – AFE Control 1

11.15:6

Reserved

RW

0000_0000_00

Slow-oscillator mode is used to disconnect the

input reference crystal/clock on the XI pin and

select the on-chip slow oscillator when the

KSZ8081RNA/RND device is not in use after

power-up.

Slow-Oscillator

Mode Enable

11.5

RW

0

1 = Enable

0 = Disable

This bit automatically sets software power-down

to the analog side when enabled.

11.4:0

Reserved

RW

0_0000

0000h

Register 15h – RXER Counter

15.15:0 RXER Counter Receive error counter for symbol error frames

Register 16h – Operation Mode Strap Override

RO/SC

If RXER (Pin 17) latches in a pull-up value at

the de-assertion of reset, write a ‘0’ to this bit to

clear Reserved Factory Mode.

Reserved

Factory Mode

Set by the pull-up / pull-down

value of RXER (Pin 17).

16.15

RW

16.14:11

16.10

Reserved

RW

RO

000_0

0

Reserved

1 = Override strap-in for B-CAST_OFF

If bit is ‘1’, PHY Address 0 is non-broadcast.

Reserved

B-CAST_OFF

Override

16.9

RW

0

16.8:7

16.6

Reserved

RW

0_0

0

RMII B-to-B

Override

1 = Override strap-in for RMII back-to-back

mode (also set bit 1 of this register to ‘1’)

NAND Tree

Override

16.5

1 = Override strap-in for NAND tree mode

Reserved

RW

0

16.4:2

16.1

Reserved

RW

0_00

RMII Override 1 = Override strap-in for RMII mode

Reserved Reserved

1

0

16.0

Register 17h – Operation Mode Strap Status

[000] = Strap to PHY Address 0

PHYAD[2:0]

Strap-In Status

[011] = Strap to PHY Address 3

17.15:13

RO

The KSZ8081RNA/RND supports only PHY

addresses 0h and 3h.

17.12:2

17.1

Reserved

RO

RMII Strap-In

Status

1 = Strap to RMII mode

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Revision 1.1

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KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

RO

Address

Register 17h – Operation Mode Strap Status

17.0 Reserved Reserved

Register 18h – Expanded Control

Name

Description

Default

18.15:12

Reserved

RW

0000

Energy-detect power-down mode

1 = Disable

EDPD

Disabled

18.11

RW

1

0 = Enable

See also register 10h, bit [4] for PLL off.

Reserved

18.10:0

Reserved

000_0000_0000

Register 1Bh – Interrupt Control/Status

Jabber

Interrupt

Enable

1 = Enable jabber interrupt

0 = Disable jabber interrupt

1B.15

1B.14

1B.13

1B.12

RW

0

Receive Error

Interrupt

1 = Enable receive error interrupt

0 = Disable receive error interrupt

Enable

Page Received

Interrupt

1 = Enable page received interrupt

0 = Disable page received interrupt

Enable

Parallel Detect

Fault Interrupt

Enable

1 = Enable parallel detect fault interrupt

0 = Disable parallel detect fault interrupt

Link Partner

Acknowledge

Interrupt

1 = Enable link partner acknowledge interrupt

1B.11

RW

0

0 = Disable link partner acknowledge

interrupt

Enable

Link-Down

Interrupt

Enable

1= Enable link-down interrupt

0 = Disable link-down interrupt

1B.10

1B.9

1B.8

RW

0

Remote Fault

Interrupt

1 = Enable remote fault interrupt

0 = Disable remote fault interrupt

Enable

Link-Up

Interrupt

Enable

1 = Enable link-up interrupt

0 = Disable link-up interrupt

1 = Jabber occurred

Jabber

Interrupt

1B.7

1B.6

1B.5

1B.4

RO/SC

0

0 = Jabber did not occur

1 = Receive error occurred

0 = Receive error did not occur

1 = Page receive occurred

0 = Page receive did not occur

1 = Parallel detect fault occurred

0 = Parallel detect fault did not occur

Receive Error

Interrupt

Page Receive

Interrupt

Parallel Detect

Fault Interrupt

Link Partner

Acknowledge

Interrupt

1 = Link partner acknowledge occurred

1B.3

RO/SC

0

0 = Link partner acknowledge did not occur

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 1Bh – Interrupt Control/Status

1 = Link-down occurred

Link-Down

Interrupt

1B.2

1B.1

1B.0

RO/SC

0

0 = Link-down did not occur

1 = Remote fault occurred

0 = Remote fault did not occur

1 = Link-up occurred

Remote Fault

Interrupt

Link-Up

Interrupt

0 = Link-up did not occur

Register 1Dh – LinkMD Control/Status

1 = Enable cable diagnostic test. After test

has completed, this bit is self-cleared.

Cable

1D.15

Diagnostic

Test Enable

RW/SC

0

0 = Indicates cable diagnostic test (if enabled)

has completed and the status information

is valid for read.

[00] = Normal condition

[01] = Open condition has been detected in

cable

Cable

Diagnostic

Test Result

1D.14:13

RO

00

[10] = Short condition has been detected in

cable

[11] = Cable diagnostic test has failed

Short Cable

Indicator

1 = Short cable (<10 meter) has been detected

by LinkMD

1D.12

1D.11:9

1D.8:0

RO

RW

RO

0

Reserved

000

Cable Fault

Counter

Distance to fault

0_0000_0000

Register 1Eh – PHY Control 1

1E.15:10

Reserved

RO

0000_00

0

1 = Flow control capable

0 = No flow control capability

1 = Link is up

Enable Pause

(Flow Control)

1E.9

1E.8

Link Status

RO

0

0 = Link is down

1 = Polarity is reversed

0 = Polarity is not reversed

Reserved

1E.7

1E.6

1E.5

Polarity Status

Reserved

RO

0

1 = MDI-X

MDI/MDI-X

State

0 = MDI

1 = Signal present on receive differential

pair

1E.4

1E.3

Energy Detect

PHY Isolate

RO

RW

0

0 = No signal detected on receive differential

pair

1 = PHY in isolate mode

0 = PHY in normal operation

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Revision 1.1

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KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 1Eh – PHY Control 1

[000] = Still in auto-negotiation

[001] = 10Base-T half-duplex

[010] = 100Base-TX half-duplex

[011] = Reserved

Operation

Mode

Indication

1E.2:0

RO

000

[100] = Reserved

[101] = 10Base-T full-duplex

[110] = 100Base-TX full-duplex

[111] = Reserved

Register 1Fh – PHY Control 2

1 = HP Auto MDI/MDI-X mode

0 = Micrel Auto MDI/MDI-X mode

When Auto MDI/MDI-X is disabled,

1 = MDI-X mode

1F.15

HP_MDIX

RW

1

0

Transmit on RXP,RXM (pins 4, 3) and

Receive on TXP,TXM (pins 6, 5)

MDI/MDI-X

Select

1F.14

0 = MDI mode

Transmit on TXP,TXM (pins 6, 5) and

Receive on RXP,RXM (pins 4, 3)

1 = Disable Auto MDI/MDI-X

0 = Enable Auto MDI/MDI-X

Pair Swap

Disable

1F.13

1F.12

RW

0

Reserved

1 = Force link pass

0 = Normal link operation

1F.11

Force Link

RW

0

This bit bypasses the control logic and allows

the transmitter to send a pattern even if there is

no link.

1 = Enable power saving

0 = Disable power saving

1 = Interrupt pin active high

0 = Interrupt pin active low

1 = Enable jabber counter

0 = Disable jabber counter

1F.10

1F.9

1F.8

Power Saving

Interrupt Level

Enable Jabber

RW

0

1

1 = For KSZ8081RNA, clock input to XI (pin 8)

is 50MHz for RMII – 50MHz clock mode.

For KSZ8081RND, clock input to XI (pin 8)

is 25MHz for RMII – 25MHz clock code.

RMII

Reference

Clock Select

1F.7

RW

0

0 = For KSZ8081RNA, clock input to XI (pin 8)

is 25MHz for RMII – 25MHz clock code.

For KSZ8081RND, clock input to XI (pin 8)

is 50MHz for RMII – 50MHz clock mode.

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Register Description (Continued)

Mode⁽¹⁾

Address

Name

Description

Default

Register 1Fh – PHY Control 2

1F.6

Reserved

LED Mode

Reserved

RW

0

[00] =

[01] =

LED0: Link/Activity

LED0: Link

1F.5:4

00

[10], [11] = Reserved

1 = Disable transmitter

0 = Enable transmitter

Disable

Transmitter

1F.3

RW

0

1 = Remote (analog) loopback is enabled

0 = Normal mode

Remote

Loopback

1F.2

1F.1

1F.0

RW

0

Reserved

1 = Disable scrambler

0 = Enable scrambler

Disable Data

Scrambling

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Absolute Maximum Ratings⁽¹⁾

Operating Ratings⁽²⁾

Supply Voltage (V_IN)

Supply Voltage

(V_{DDIO_3.3,}V_{DDA_3.3}) .......................... +3.135V to +3.465V

(V_{DDIO_2.5})........................................ +2.375V to +2.625V

(V_{DDIO_1.8})........................................ +1.710V to +1.890V

Ambient Temperature

(T_A, Commercial) ......................................0°C to +70°C

(T_A, Industrial).......................................–40°C to +85°C

Maximum Junction Temperature (T_Jmax.)................ 125°C

Thermal Resistance (θ_JA) ....................................49.22°C/W

Thermal Resistance (θ_JC)....................................25.65°C/W

(V_{DD_1.2}) .................................................. −0.5V to +1.8V

(V_DDIO,V_{DDA_3.3})....................................... −0.5V to +5.0V

Input Voltage (all inputs) .............................. −0.5V to +5.0V

Output Voltage (all outputs) ......................... −0.5V to +5.0V

Lead Temperature (soldering, 10sec.)....................... 260°C

Storage Temperature (T_s) .........................–55°C to +150°C

Electrical Characteristics⁽³⁾

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Supply Current (V_DDIO, V_{DDA_3.3}= 3.3V)⁽⁴⁾

I_{DD1_3.3V}

I_{DD2_3.3V}

I_{DD3_3.3V}

I_{DD4_3.3V}

10Base-T

Full-duplex traffic @ 100% utilization

Ethernet cable disconnected (reg. 18h.11 = 0)

Software power-down (reg. 0h.11 = 1)

41

47

20

4

mA

100Base-TX

EDPD Mode

Power-Down Mode

CMOS Level Inputs

V_DDIO= 3.3V

V_DDIO= 2.5V

V_DDIO= 1.8V

V_DDIO= 3.3V

V_DDIO= 2.5V

V_DDIO= 1.8V

V_IN= GND ~ VDDIO

2.0

1.8

1.3

V

V_IH

Input High Voltage

V

0.8

0.7

0.5

10

V

V_IL

Input Low Voltage

Input Current

V

|I_IN|

µA

CMOS Level Outputs

V_DDIO= 3.3V

V_DDIO= 2.5V

V_DDIO= 1.8V

V_DDIO= 3.3V

V_DDIO= 2.5V

V_DDIO= 1.8V

2.4

2.0

1.5

V

V_OH

Output High Voltage

V

0.4

0.3

10

V

V_OL

|I_oz|

Output Low Voltage

V

Output Tri-State Leakage

µA

LED Output

I_LED

Output Drive Current

LED0 pin

8

mA

Notes:

1. Exceeding the absolute maximum rating can damage the device. Stresses greater than the absolute maximum rating can cause permanent

damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification

is not implied. Maximum conditions for extended periods may affect reliability.

2. The device is not guaranteed to function outside its operating rating.

3. T_A= 25°C. Specification is for packaged product only.

4. Current consumption is for the single 3.3V supply KSZ8081RNA/RND device only, and includes the transmit driver current and the 1.2V supply

voltage (V_{DD_1.2}) that are supplied by the KSZ8081RNA/RND.

February 6, 2014

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Electrical Characteristics⁽³⁾

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

All Pull-Up/Pull-Down Pins (including Strapping Pins)

V_DDIO= 3.3V

30

39

48

26

34

53

45

61

99

43

59

99

73

kΩ

pu

pd

Internal Pull-Up Resistance

V_DDIO= 2.5V

V_DDIO= 1.8V

V_DDIO= 3.3V

V_DDIO= 2.5V

V_DDIO= 1.8V

102

178

79

Internal Pull-Down Resistance

113

200

100Base-TX Transmit (measured differentially after 1:1 transformer)

V_O

Peak Differential Output Voltage 100Ω termination across differential output

0.95

1.05

2

V

V_IMB

t_r, t_f

Output Voltage Imbalance

Rise/Fall Time

100Ω termination across differential output

%

3

0

5

ns

%

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

0.5

±0.25

5

Output Jitter

Peak-to-peak

0.7

ns

10Base-T Transmit (measured differentially after 1:1 transformer)

V_P

Peak Differential Output Voltage 100Ω termination across differential output

2.2

2.8

3.5

V

Jitter Added

Peak-to-peak

ns

t_r, t_f

Rise/Fall Time

25

10Base-T Receive

V_SQ

Squelch Threshold

5MHz square wave

400

0.65

mV

V

Transmitter – Drive Setting

V_SET

Reference Voltage of I_SET

R(I_SET) = 6.49kΩ

REF_CLK Output

Peak-to-peak

50MHz RMII Clock Output Jitter

300

ps

(Applies only to RMII – 25MHz clock mode)

100Mbps Mode – Industrial Applications Parameters

Link loss detected at receive differential inputs

to PHY signal indication time for each of the

following:

Link Loss Reaction (Indication)

Time

t_llr

1. For LED mode 01, Link LED output changes

from low (link-up) to high (link-down).

4.4

µs

2. INTRP pin asserts for link-down status

change.

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Timing Diagrams

RMII Timing

Figure 10. RMII Timing – Data Received from RMII

Figure 11. RMII Timing – Data Input to RMII

Timing Parameter

t_CYC

t₁

Description

Clock cycle

Setup time

Hold time

Min.

Typ.

Max.

Unit

ns

20

4

2

7

ns

t₂

ns

t_OD

Output delay

10

13

ns

Table 10. RMII Timing Parameters – KSZ8081RNA/RND (25MHz input to XI pin, 50MHz output from REF_CLK pin)

Timing Parameter

Description

Clock cycle

Setup time

Hold time

Min.

Typ.

Max.

Unit

ns

t_CYC

t₁

20

4

2

8

ns

t₂

ns

t_OD

Output delay

11

13

ns

Table 11. RMII Timing Parameters – KSZ8081RNA/RND (50MHz input to XI pin)

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Auto-Negotiation Timing

Figure 12. Auto-Negotiation Fast Link Pulse (FLP) Timing

Timing Parameter

Description

Min.

Typ.

16

Max.

Units

ms

ns

t_BTB

t_FLPW

t_PW

FLP burst to FLP burst

FLP burst width

8

24

2

Clock/Data pulse width

Clock pulse to data pulse

Clock pulse to clock pulse

100

64

t_CTD

t_CTC

55.5

111

69.5

139

µs

128

µs

Number of clock/data pulses per

FLP burst

17

33

Table 12. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

MDC/MDIO Timing

Figure 13. MDC/MDIO Timing

Timing Parameter

Description

Min.

Typ.

Max.

Unit

ns

t_P

MDC period

400

t_MD1

t_MD2

t_MD3

MDIO (PHY input) setup to rising edge of MDC

MDIO (PHY input) hold from rising edge of MDC

MDIO (PHY output) delay from rising edge of MDC

10

4

ns

5

ns

Table 13. MDC/MDIO Timing Parameters

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Power-Up/Reset Timing

The KSZ8081RNA/RND reset timing requirement is summarized in Figure 14 and Table 14.

Figure 14. Power-Up/Reset Timing

Parameter

Description

Min.

300

10

5

Max.

Units

µs

t_VR

t_SR

t_CS

t_CH

t_RC

Supply voltage (V_DDIO,V_{DDA_3.3}) rise time

Stable supply voltage (V_DDIO,V_{DDA_3.3}) to reset high

Configuration setup time

ms

ns

Configuration hold time

5

ns

Reset to strap-in pin output

6

ns

Table 14. Power-Up/Reset Timing Parameters

The supply voltage (V_DDIOand V_{DDA_3.3}) power-up waveform should be monotonic. The 300µs minimum rise time is from

10% to 90%.

For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read

and updated at the de-assertion of reset.

After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Reset Circuit

Figure 15 shows a reset circuit recommended for powering up the KSZ8081RNA/RND if reset is triggered by the power

supply.

Figure 15. Recommended Reset Circuit

Figure 16 shows a reset circuit recommended for applications where reset is driven by another device (for example, the

CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8081RNA/RND

device. The RST_OUT_n from the CPU/FPGA provides the warm reset after power-up.

Figure 16. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output

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KSZ8081RNA/KSZ8081RND

Reference Circuits – LED Strap-In Pins

The pull-up, float, and pull-down reference circuits for the LED0/ANEN_SPEED strapping pin are shown in Figure 17 for

3.3V and 2.5V VDDIO.

Figure 17. Reference Circuits for LED Strapping Pins

For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the

ANEN_SPEED strapping pin is functional with a 4.7kΩ pull-up to 1.8V VDDIO or float for a value of ‘1’, and with a 1.0kΩ

pull-down to ground for a value of ‘0’.

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KSZ8081RNA/KSZ8081RND

Reference Clock – Connection and Selection

A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081RNA/RND.

For the KSZ8081RNA/RND in RMII – 25MHz clock mode, the reference clock is 25 MHz. The reference clock connections

to XI (pin 8) and XO (pin 7), and the reference clock selection criteria, are provided in Figure 18 and Table 15.

Figure 18. 25MHz Crystal/Oscillator Reference Clock Connection

Characteristics

Value

25

Units

MHz

ppm

Ω

Frequency

Frequency tolerance (max.)

Crystal series resistance (typ.)

Crystal load capacitance (typ.)

±50

40

16

pF

Table 15. 25MHz Crystal / Reference Clock Selection Criteria

For the KSZ8081RNA/RND in RMII – 50MHz clock mode, the reference clock is 50MHz. The reference clock connection

to XI (pin 8), and the reference clock selection criteria are provided in Figure 19 and Table 16.

Figure 19. 50MHz Oscillator Reference Clock Connection

Characteristics

Value

50

Units

MHz

ppm

Frequency

Frequency tolerance (max)

±50

Table 16. 50MHz Oscillator / Reference Clock Selection Criteria

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Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Magnetic – Connection and Selection

A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs

exceeding FCC requirements.

The KSZ8081RNA/RND design incorporates voltage-mode transmit drivers and on-chip terminations.

With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential

pairs. Therefore, the two transformer center tap pins on the KSZ8081RNA/RND side should not be connected to any

power supply source on the board; instead, the center tap pins should be separated from one another and connected

through separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage

is different between transmitting and receiving differential pairs.

Figure 20 shows the typical magnetic interface circuit for the KSZ8081RNA/RND.

Figure 20. Typical Magnetic Interface Circuit

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KSZ8081RNA/KSZ8081RND

Table 17 lists recommended magnetic characteristics.

Parameter

Value

Test Condition

Turns ratio

1 CT : 1 CT

350µH

Open-circuit inductance (min.)

Insertion loss (typ.)

HIPOT (min.)

100mV, 100kHz, 8mA

100kHz to 100MHz

–1.1dB

1500Vrms

Table 17. Magnetics Selection Criteria

Table 18 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that

can be used with the KSZ8081RNA/RND.

Temperature

Range

Magnetic +

RJ-45

Manufacturer

Part Number

Bel Fuse

Delta

S558-5999-U7

SI-46001-F

SI-50170-F

LF8505

0°C to 70°C

No

Yes

No

HALO

HFJ11-2450E

TG110-E055N5

LF-H41S-1

H1102

Yes

HALO

–40°C to 85°C No

LANKom

Pulse

0°C to 70°C

No

Pulse

H1260

Pulse

HX1188

–40°C to 85°C No

Pulse

J00-0014

0°C to 70°C

Yes

Pulse

JX0011D21NL

TLA-6T718A

HB726

–40°C to 85°C Yes

TDK

0°C to 70°C

Yes

No

Transpower

Wurth/Midcom

000-7090-37R-LF1

–40°C to 85°C No

Table 18. Compatible Single-Port 10/100 Magnetics

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KSZ8081RNA/KSZ8081RND

Recommended Land Pattern

Figure 21. Recommended Land Pattern, 24-Pin (4mm × 4mm) QFN

Red circles indicate thermal vias. They should be 0.350mm in diameter and be connected to the GND plane for maximum

thermal performance.

Green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. They should be 1.00 x

1.00mm in size, 1.20mm pitch.

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Revision 1.1

Micrel, Inc.

KSZ8081RNA/KSZ8081RND

Package Information⁽¹⁾

24-Pin (4mm × 4mm) QFN

Note:

1. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. (Micrel note body)

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This

information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,

specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability

whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties

relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant

into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

February 6, 2014

51

Revision 1.1


型号：	KSZ8081RNAIA
厂家：	MICREL SEMICONDUCTOR
描述：	10Base-T/100Base-TX PHY with RMII Support
文件：	总51页 (文件大小：861K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KSZ8081RNAIA [MICREL]

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