MIC2310-1ZTS_技术文档

MIC2310

Single-FET, Constant Power-Limit Hot

Swap Controller

General Description

Features

The MIC2310 is a single-channel, positive voltage,

constant power-limit hot swap controller designed to

provide for the safe insertion and removal of pc boards into

fixed, rack, and pedestal mid- or back-planes using few

external components. In addition, the MIC2310 employs a

patent-pending, output load power-limiting technique

where the current limit is inversely proportional to the

output load voltage, such that the power product will not

exceed the programmed power limit any longer than the

externally programmed primary overcurrent period. The

MIC2310 is ideally suited to address the power-limiting

and timing requirements per the UL60950 specification for

240-VA applications. The MIC2310 incorporates high-side

controller circuitry for an external N-channel MOSFET for

which the MOSFET drain current rate of change is user-

programmable via an external capacitor. The MIC2310

employs dual-speed, dual-level overcurrent fault

protection. The primary overcurrent detector response time

is programmable via an external current sense resistor and

the secondary overcurrent detector is 2-bit user-

programmable and exhibits a very fast (default) response

to faults to ensure that the system power supplies are

protected against catastrophic load current and short-

circuit faults. Additionally, an analog output (voltage) signal

is provided that is proportional to the steady-state load

current to allow monitoring of the system’s power. A

PWRGD signal is provided to indicate a valid output

voltage that can be used to enable a DC-DC power

module.

•

Provides safe PCB insertion and removal from live

+12V backplanes

•

Patent-pending, adaptive circuit breaker threshold

control

–

Maintains constant power product at output

Power-limit product (VA) is externally

programmable for various power applications

•

Dual-level, dual-speed overcurrent detection/protection

–

Programmable primary detector response time

Fast (< 1 µs) secondary detector response time to

short circuit conditions

User-programmable threshold settings via (2)

digital inputs

•

Steady-state load current monitoring

Programmable inrush current slew-rate control

Electronic circuit breaker functions after fault

–

Latch off

Automatic retry

•

Programmable input undervoltage lockout and

overvoltage protection

Fault reporting:

–

Open-drain ‘Power-is-Good’ output

Open-drain ‘I_FLT’ output signaling for all current

faults

–

Shorted R_SENSEand Damaged MOSFET detection

(D-G and D-S shorts)

Data sheets and support documentation can be found on

Micrel’s web site at www.micrel.com.

Applications

• UL60950, EN60950, and CSA1950 systems (240-VA)

• General Power-limiting Applications

• Base stations

• Enterprise servers

• High-reliability servers

• Enterprise switch networks

• +12V backplanes

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-070108-A

July 2008

Micrel, Inc.

MIC2310

Typical Application

R_SENSE

0.5%

Q1

V_OUT

12V@20A

IRL3713S

V_IN

D²Pak

1

2

12V

C2*

3

4

R1

R2

C3

0.68µF

C4

0.47µF

C7

0.01µF

C1

1.5µF

24

23

22

11

10

21

19

R3

VCC

VCCSENSE SENSE

CSLEW CPRIMARY

GATE

SOURCE

1%

6

18

17

16

ENABLE

UVLO

LOADSENSE

R9

1

2

C_LOAD

R4

GNDSENSE

DISCH

3

1%

R5

OVP

S0

Q2

ZUMT618

SOT-323

MIC2310

7

8

1%

C_DISCH

4

VREG

S[1,0]=X,X

C6

S1

0.1µF

VISS

CRETRY

CPGND

AGND

HW_FLT

PWRGD

I_FLT

TO SYSTEM

MANAGEMENT

CONTROLLER

3

9

20

12

13

14

15

R8

V_LOGIC

C5

0.068µF

R7

R6

Overcurrent

Fault Output

* The value of C2 is flexible and dependant upon the

parasitic inductance, which should be minimzed as much

as possible. A

Power-Good

Output

Hardware

Fault Output

inductance) for C2 is 56µF, minimum

M9999-070108-A

July 2008

2

Micrel, Inc.

MIC2310

Ordering Information

Part Number

MIC2310-1ZTS

MIC2310-2ZTS

Note:

PWRGD State

I_FLT State

Active-HIGH

Active-LOW

Fault Condition Status

Latched/Auto-retry

Package

Lead Finish

Active-HIGH

Active-LOW

24-pin TSSOP

Pb-Free

1. Other Voltage available. Contact Micrel for details.

Pin Configuration

UVLO

OVP

1

24 VCC

UVLO

OVP

1

2

3

4

5

6

7

8

9

24 VCC

2

23 VCCSENSE

22 SENSE

21 GATE

23 VCCSENSE

22 SENSE

VISS

VREG

NC

3

4

5

6

7

8

9

VISS

VREG

NC

21 GATE

20 CPGND

19 SOURCE

18 LOADSENSE

17 GNDSENSE

16 DISCH

20 CPGND

19 SOURCE

18 LOADSENSE

17 GNDSENSE

16 DISCH

ENABLE

S0

ENABLE

S0

S1

CRETRY

CPRIMARY 10

CSLEW 11

AGND 12

15 I_FLT

CPRIMARY 10

CSLEW 11

AGND 12

15 /I_FLT

14 PWRGD

13 HW_FLT

14 /PWRGD

13 HW_FLT

24-pin TSSOP (TS)

MIC2310-1ZTS

24-pin TSSOP (TS)

MIC2310-2ZTS

M9999-070108-A

July 2008

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Micrel, Inc.

MIC2310

Pin Description

Pin Number

Pin Name

Pin Function

1

UVLO

Undervoltage Lockout Input. When the applied voltage at the UVLO pin is higher

than the controller’s V_UVLOHthreshold voltage, the GATE drive circuits are active

when ENABLE= HIGH. If the applied voltage at the UVLO pin falls below the

controller’s V_UVLOLthreshold voltage, the GATE drive circuits are disabled to turn

the external MOSFET OFF. In addition, the DISCH circuit is activated to drive an

optional, external discharge transistor alone (illustrated in the Typical Application

circuit) or in combination with an SCR for a very fast discharge circuit

configuration.

2

OVP

Overvoltage Protection Input. When the applied voltage at the OVP pin is higher

than the controller’s V_OVPHthreshold voltage, the GATE drive circuit is disabled

to turn the external MOSFET OFF. In addition, the DISCH circuit is activated to

drive an optional, external discharge transistor alone (illustrated in the Typical

Application circuit) or in combination with an SCR for a very fast discharge circuit

configuration. Using an external resistor divider, the UVLO and the OVP pins

form a window comparator that defines the supply voltage range within which the

load may be safely powered.

3

4

VISS

Steady-state Output Current Monitor. This output signal provides an analog

voltage that is proportional to the steady-state load current. This signal is

provided as an input to the system supervisor/processor to monitor the dc

current/power level of the application circuit.

VREG

Internal +5V Regulator Bypass. Connect a 0.1-µF, 16V ceramic capacitor from

this pin to AGND.

5

6

NC

No connection

ENABLE

ENABLE Input. An active asserted-HIGH digital input that controls the operation

of the MIC2310. Activated after the internal POR timer has terminated, a LOW-

to-HIGH transition on this pin commences a start-up sequence if the applied V_CC

is above the V_UVLOHand below the V_OVPHthreshold voltages. While ENABLE =

LOW, the GATE pin is held to 0V and the DISCH output is activated. The

ENABLE input can be used to reset the internal circuit breaker by applying a

HIGH-to-LOW-to-HIGH transition as defined by t_ENLPWfollowing either a load

current fault, an open LOADSENSE fault, an open GNDSENSE fault, or a

shorted RSENSE fault.

7

8

S0

S1

Secondary OC Detector Current Threshold Digital Inputs – S1 is the MSB and

S0 is the LSB. When used together, S[1:0] sets the overcurrent threshold for the

secondary overcurrent detection circuit to one of four levels relative to the

primary overcurrent detector nominal threshold. For example, S[1:0] = L, L sets

the secondary overcurrent threshold at 1.3X; S[1:0] = L, H sets a 1.5X threshold;

S[1:0] = H, L sets a 2X threshold, and S[1:0] = H, H sets a 1.75X threshold. If the

S[1:0] pins are not connected or left NC, the default setting is S[1:0] = L, L or

1.3X. The permissible voltage range on these inputs is AGND ≤ S[1:0] ≤ V_CC

.

9

CRETRY

Auto-retry Timing Capacitor. A capacitor connected from the CRETRY pin to

AGND configures the MIC2310 to re-start automatically with ENABLE = HIGH

after the circuit breaker trips and latches off. It also sets the “cool-off” time delay

before a new load current start-up sequence is initiated. To configure the

MIC2310’s circuit breaker to latch off after fault, connect this pin to AGND. The

circuit breaker latches OFF and remains latched OFF unless the ENABLE input

is toggled HIGH-to-LOW-to-HIGH as defined by t_ENLPWor the V_CCsupply voltage

is turned OFF then ON.

10

CPRIMARY

Primary Overcurrent Detector Timing Capacitor. Connecting a capacitor from the

CPRIMARY pin to AGND sets the response time of the controller’s primary

overcurrent detection circuit to GATE OFF in the event of an overcurrent

condition. If the CPRIMARY pin is not connected, the primary overcurrent

detection response time defaults to t_POCSENSE, typically 250µs as specified in the

Electrical Characteristics Table. The controller incorporates a patent-pending

built-in test for a faulty CPRIMARY capacitor.

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July 2008

4

Micrel, Inc.

MIC2310

Pin Description (continued)

Pin Number

Pin Name

Pin Function

11

CSLEW

Inrush Current Slew Rate Control Input. To adjust the inrush load current profile

(controlled dI_DRAIN/dt), connect a capacitor from this pin to VCC. To adjust the

MOSFET GATE voltage profile (controlled dV_GATE/dt), leave this pin OPEN

(floating) and connect a capacitor from GATE to AGND. For additional

information on the operation of this function, please refer to the Functional

Description section.

12

13

AGND

Analog Ground. Connect this pin to the system analog ground plane.

HW_FLT

External MOSFET Hardware Fault Digital Output. This output is an open-drain,

active-HIGH signal that should be connected to a +3.3V logic supply by a 10kΩ

resistor. This digital output is active after the internal POR timer has terminated

and becomes asserted (HIGH) due to a fault under the following conditions: a) a

shorted DG MOSFET with ENABLE = LOW; b) a shorted DS MOSFET with

ENABLE = LOW; c) a shorted R_SENSE; d) a shorted DS MOSFET after steady-

state operation with ENABLE = HIGH-to-LOW; or e) a shorted DG or DS while

EN = HIGH and DISCH = HIGH; or f) a shorted C_PRIMARYto AGND. The

HW_FLT output is latched and is reset when VCC is brought low such that

V

_REG< V_VREG(UVLO).

14

15

PWRGD

/PWRGD

Power Good Digital Output. This output is an open-drain, active-HIGH (PWRGD)

or active-LOW (/PWRGD) signal that should be connected to a +3.3-V logic

supply by a 10kΩ resistor. This digital output is active after the internal POR

timer has terminated and becomes asserted when the voltage between the

LOADSENSE and the GNDSENSE pins is higher than the controller’s V_PGH

threshold voltage. It is de-asserted when the voltage between the LOADSENSE

and the GNDSENSE pins is less than the controller’s V_PGLthreshold voltage.

I_FLT

Load Current Fault Digital Output. This output is an open-drain, active-HIGH

(I_FLT) or active-LOW (/I_FLT) signal that should be connected to a +3.3V logic

supply by a 10kΩ resistor. This digital output is active after the internal POR

timer has terminated and becomes asserted whenever the primary or secondary

overcurrent detection circuits cause the internal circuit breaker to latch OFF. The

digital output remains asserted unless the ENABLE input is toggled HIGH-to-

LOW-to-HIGH as defined by t_ENLPWor the V_CCsupply voltage is turned OFF then

ON or if the auto-retry mode is enabled.

/I_FLT

16

DISCH

Discharge External Transistor Drive Output. When ENABLE = LOW or after a

fault condition (either an overcurrent fault or hardware fault such as a shorted

MOSFET) that causes either the primary and secondary overcurrent detectors to

trip the internal circuit breaker, the DISCH circuit is activated to provide gate

drive to optional, external transistors (and SCR, for very fast load discharge).

These transistors serve as auxiliary gate pull-down or load voltage pull-down

switches. A load voltage pull-down is illustrated in the Typical Application circuit.

17

18

GNDSENSE

LOADSENSE

These input pins (when used together) sense the load voltage and provide

feedback to the controller’s adaptive VA limit and Power-Good circuits. The

voltage across these two pins also sets the controller’s Power-Is-Good status

output as defined by the specified V_PGHor the V_PGLthreshold voltages. Internal

circuit monitors are included if either or both LOADSENSE and GNDSENSE

connections are severed or not connected to the load.

19

SOURCE

External Power MOSFET Source Pin Monitor. To protect external circuits

downstream of the controller, internal monitor circuits are included to sense a

shorted drain-source condition of the external power MOSFETs.

20

21

CPGND

GATE

Internal charge pump power ground. Connect this pin directly to the system’s

analog ground plane.

External N-channel MOSFET GATE Drive Output. The GATE output signal uses

an internal charge pump to charge the gate of an external N-channel MOSFET

pass transistor.

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July 2008

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Micrel, Inc.

MIC2310

Pin Description (continued)

Pin Number

Pin Name

SENSE

Pin Function

22

23

By connecting a very low value (mΩ) current sense resistor between these two

pins, the MIC2310’s internal primary and secondary overcurrent detection

circuits monitor the load current. The VCCSENSE pin is the positive (+) input

terminal and the SENSE pin is the negative (-) input terminal of the overcurrent

detection circuits. If the voltage across the sense resistor exceeds either the

primary overcurrent threshold for a time (t_POC) or the secondary primary

overcurrent threshold for any duration, the MIC2310 electronic circuit breaker is

tripped, the GATE is turned OFF, the DISCH circuit is activated, and the I_FLT

VCCSENSE

digital output is asserted. The controller also incorporates a patent-pending built-

in test for shorted current-sense resistors. Because of this built-in self test, the

MIC2310’s electronic circuit breaker cannot be disabled by connecting together

the VCCSENSE and SENSE pins.

24

VCC

Positive supply input to the MIC2310. The MIC2310 is specified to operate from

+10.8V ≤ V_CC≤ +13.2V and the supply current with ENABLE = HIGH is less than

10mA.

M9999-070108-A

July 2008

6

Micrel, Inc.

MIC2310

Absolute Maximum Ratings⁽¹⁾

Operating Ratings⁽²⁾

VCC, VCCSENSE, SENSE, LOADSENSE, ENABLE,

CSLEW, S1, S0, SOURCE..................... –0.3V to +18V

GATE............................................................. –0.3V to +30V

UVLO, OVP, VISS, CRETRY, CPRIMARY, HW_FLT,

PWRGD, I_FLT, DISCH, GNDSENSE.... –0.3V to +6V

Output Current

Supply Voltage (V_CC)................................ +10.8V to +13.2V

Ambient Temperature Range (T_A) ................0 °C to +70 °C

Junction Temperature (T_J) ...................................... +125 °C

Package Thermal Resistance (θ_JA)

24-pin TSSOP................................................83.8 °C/W

HW_FLT, PWRGD, I_FLT pins...................................10mA

ESD Rating (All pins)

Human Body Model.............................................. 2kV⁽³⁾

Machine Model ......................................................200V

Lead Temperature (Soldering) Pb-free package

IR Reflow ..........................................+260°C +0°C/-5°C

Storage Temperature..........................–65°C to +150°C

DC Electrical Characteristics⁽⁴⁾

V_CC= +12V, C_REG= 0.1µF, T_A= +25 ºC unless otherwise noted. Bold indicates specification applies over the full

operating temperature range of 0 ºC to +70 ºC. All voltages are measured with respect to AGND unless otherwise

noted.

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_CC

Operating Supply Voltage

(Constant Output Power)

10.8

13.2

V

I_CC

Supply Current

ENABLE = LOW,HIGH

10

mA

V

V_VREG(UVLOH)

Internal VREG Undervoltage V_REGLow-to-High Transition

Lockout High Threshold

Voltage

3.95

3.70

0.96

4.25

4.5

V_VREG(UVLOL)

Internal V_REGUndervoltage

Lockout Low Threshold

Voltage

4.25

V

V_UVLOH

V_UVLOL

UVLO High Threshold

Voltage

Low-to-High Transition

High-to-Low Transition

UVLO = 6V

1.00

1.04

0.97

V

UVLO Low Threshold

Voltage

0.91 0.941

I_UVLO

UVLO Pin Input Current

5

µA

V

V_OVPH

V_OVPL

I_OVP

OVP High Threshold Voltage Low-to-High Transition

OVP Low Threshold Voltage High-to-Low Transition

1.35 1.407

1.45

1.295 1.339 1.395

V

OVP Pin Input Current

OVP = 6V

5

µA

V

V_GSPGH

“Power-is-Good” GATE-

SOURCE Threshold

(V_GATE– V_SOURCE

)

4.25

9.3

5

V_PGH

“Power-is-Good” High

Threshold

Low-to-High Transition,

(V_GATE– V_SOURCE) ≥ V_GSPGH

9.7

10.1

V

(V_LOADSENSE– V_GNDSENSE

)

Measured with respect to

GNDSENSE = AGND

V_PGL

“Power-not-Good” Low

Threshold

(V_LOADSENSE– V_GNDSENSE

High-to-Low Transition,

(V_GATE– V_SOURCE) ≥ V_GSPGHMeasured

with respect to GNDSENSE = AGND

8.4

4.5

9

5

9.6

5.5

V

V_REG

V_REGOutput Voltage

R_REG> 1 MΩ

M9999-070108-A

July 2008

7

Micrel, Inc.

MIC2310

Symbol

Parameter

Condition

Min

54.7

60.7

49.6

64

Typ

57.2

63.5

51.9

75.5

87.5

116.6

102

Max

59.7

66.3

54.2

87

Units

mV

V_CBP

Primary OC Circuit Breaker

Threshold Voltage

(V_LOADSENSE– V_GNDSENSE) = +12V

(V_LOADSENSE– V_GNDSENSE) = +10.8V

(V_LOADSENSE– V_GNDSENSE) = +13.2V

V_VCCSENSE– V_SENSE

V_CBS

Secondary OC SENSE

Voltage

Secondary OC

Detector Circuit

Breaker Trips,

V_LOADSENSE

V_GNDSENSE

S[1:0] = L, L

S[1:0] = L, H

S[1:0] = H, L

S[1:0] = H,H

75

99

V_VCCSENSE- V_SENSE

100

85

130

116

–

=

10.8V to 13.2V

I_VCCSENSE

VCCSENSE Pin Input

Current

V_VCCSENSE= V_CC

1

µA

I_SENSE

SENSE Pin Input Current

V_SENSE= V_CC

3

µA

V

V_RETRYH

CRETRY Pin High

Threshold Voltage

1.21

0.25

-4.25

1.25

0.3

-3

1.28

V_RETRYL

I_RETRYUP

I_RETRYDN

V_PRIL

CRETRY Pin Low Threshold

Voltage

0.35

V

µA

mA

V

CRETRY Pin Charging

Current

TIMER ON,

V_RETRY= 0V

-1.65

CRETRY Pin Pull-down

Current

TIMER OFF,

V_RETRY= 1.5V

3

CPRIMARY Pin Low

Threshold Voltage

During OC response;

ENABLE = HIGH;

-1.3

-1.25

-1.2

V_CC(SENSE)– V_SENSE> V_CBP

Measured relative to V_REG

V_PRIL

CPRIMARY Pin Low

Threshold Voltage

During shorted

C_PRIMARY

detection;

Measured

relative to V_REG

ENABLE = HIGH;

_CC(SENSE)– V_SENSE

< V_CBP

-1.25

V

ENABLE = LOW

I_PRI

CPRIMARY Pin Charging

Current

During Primary OC Fault

V_CPRIMARY= V_REG

ENABLE = HIGH

_CC(SENSE)– V_SENSE> V_CBP

During nominal and reset operation

_PRIMARY= V_REG– 1.25V;

ENABLE = HIGH

_CC(SENSE)– V_SENSE< V_CBP

During disable;

_CPRIMARY= V_REG– 1.25V

2.4

3

3.6

µA

;

V

-4.5

-3

-1.5

mA

V

-4.5

8

-1.5

15

mA

V

ENABLE = LOW

GATE Output Voltage

(V_GATE-V_CC): V_CC> 10.5V

Internally clamped

∆V_GATE

V_CSLEW– V_SENSEDifferential

Charge pump to OFF

V_CSLEW= V_CC– 50mV

50

10

mV

µA

∆V_CP

I_SLEW

Inrush Current slew

Charging current

5

15

M9999-070108-A

July 2008

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Micrel, Inc.

MIC2310

Symbol

Parameter

Condition

Min

-60

Typ

Max

-15

Units

I_GATEUP

GATE Pin Pull-up Current

Charge pump ON,

-30

µA

V_GATE= V_SOURCE= +13.2V

I_GATEDN

Normal GATE Pin Pull-down ENABLE = LOW,

Current

1.0

45

2.7

4.5

mA

V_GATE= 2V

Fault-mode GATE Pin Pull-

down current

I_FLT Latched and OC Detector Trip

or in UVLO, V_GATE= 2V

120

5

mA

V

V_GATEFT(EXT)

GATE-to-AGND Fault

Threshold

ENABLE = LOW

V_SRCFT(EXT)

SOURCE-to-AGND Fault

Threshold

5

V

ENABLE = LOW

V_THLOADSENSEOpen LOADSENSE

Threshold

V_SOURCE- V_LOADSENSE

V_GNDSENSE

4

V

V_THGNDSENSE

Open GNDSENSE

Threshold

I_SOURCE

SOURCE Pin Input Current

EN = LOW, 0V ≤ SOURCE ≤ V_CC

EN = HIGH, SOURCE = V_CC

EN = HIGH, /FAULT Condition

0V ≤ SOURCE ≤ V_CC

18

1.5

18

µA

I_LOADSENSE

LOADSENSE Pin Input

Current

+10.8V ≤ V_LOADSENSE≤ +13.2V

300

µA

V_LOADSENSE= 0V

DISCH = HIGH

V_GNDSENSE= 0V

I_GNDSENSE

GNDSENSE Pin Input

Current

-400

µA

Shorted R_SENSEThreshold

Voltage at SOURCE

V_CC(SENSE)– V_SENSE= 0V,

V_GATE– V_SOURCE> V_GSPGH

7

mV

∆V_DS(FET)

(V_SENSE– V_SOURCE

)

Shorted R_SENSEThreshold

Voltage

V_SENSE– V_SOURCE= 30mV,

V_GATE– V_SOURCE> V_GSPGH

12

mV

∆V_RSENSE

(V_VCCSENSE– V_SENSE

)

V_DISCH

I_DISCH

V_ISS(LIN)

V_ISS(Q)

DISCH Pin Drive Voltage

DISCH Pin Drive Current

Linear Sensing Range

I_DISCH= 12mA

0.4

-400

90

V

V_DISCH= 2.5V

µA

mV

V_VCC(SENSE)- V_SENSE

V_VCC(SENSE)- V_SENSE= 0mV

0

7

Zero Voltage VISS Output

Voltage

55

103

R_VISS

VISS DC Output Resistance

100

30

[VISS_(20µA)-VISS_(10µA)]/10µA

∆V_VISS/∆( V_VCC(SENSE)- V_SENSE

kΩ

V_ISS(SENS)

VISS Analog Signal

Sensitivity

28

32

V/V

)

E_TOT

VISS Total Error % (240 VA) V_VCC(SENSE)- V_SENSE= 60mV

%

±10

M9999-070108-A

July 2008

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Micrel, Inc.

MIC2310

Symbol

Parameter

Condition

Min

Typ

Max

±6.5

0.4

Units

E_LIN

VISS Analog Nonlinearity

V_VCC(SENSE)- V_SENSE= 0mV to 90mV

%

V_OL

LOW-Level Output Voltage

I_FLT, PWRGD, HW_FLT

I_OUT= 1.6mA

V

V_IL

LOW-Level Input Voltage

ENABLE, S1, S0

0.8

V

V_IH

HIGH-Level Input Voltage

ENABLE, S1, S0

2

V

I_IH

Input Pull-down Current

ENABLE, S1, S0

V_IH= +0.8V

55

80

120

µA

Notes:

1. Exceeding the absolute maximum rating may damage the device.

2. The device is not guaranteed to function outside its operating rating.

3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.

4. Specification for packaged product only.

AC Electrical Characteristics⁽⁴⁾

V_CC= +12V, C_REG= 0.1µF, T_A= +25 ºC unless otherwise noted. Bold indicates specification applies over the full

operating temperature range of 0 ºC to +70 ºC.

Symbol

Parameter

Condition

Min

Typ

Max

6.5

Units

t_POR

Power-on-Reset Delay

ms

V_VREG≥ V_VREG(UVLOH)

t_POCSENSE

Primary OC Detector Default (V_VCCSENSE-V_SENSE) = 70-mV step;

200

300

420

µs

Response Time to GATE pin PRIMARY Pin Floating; and

S[1:0] = H,L

Discharge

C

_GATE= 100pF

t_SOCSENSE

Secondary OC Detector

Response Time to GATE Pin

Discharge

(V_VCCSENSE-V_SENSE) = 200-mV step

0.25

0.5

5

µs

t_CBRESET

Circuit Breaker Reset Delay

Time

ENABLE Low to I_FLT Low

t_ENLPW

ENABLE Low Pulse Width

200

µs

t_SCPDETECT

Shorted C_PRIMARYDetection

Time to HW_FLT Latched

ENABLE = LOW or HIGH;

0.25

10

t_SCPDETPOR

Shorted C_PRIMARYDetection

Delay after Primary OC

Detection

V_VCCSENSE-V_SENSE≤ V_CBP

6.5

ms

µs

t_DG(FET)

MOSFET DG Short to

HW_FLT Latched

ENABLE = LOW;

GATEFT(EXT) Asserts HW_FLT

t_DS(FET)

MOSFET DS Short to

HW_FLT Latched

ENABLE = LOW;

SRCFT(EXT) Asserts HW_FLT

10

µs

2

t_DS-SSFAULT

MOSFET DS Short to

HW_FLT Latched

ENABLE = HIGH-to-LOW after

steady-state operation

250

ENABLE = HIGH

DISCH = LOW-to-HIGH

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Symbol

Parameter

Condition

Min

Typ

Max

Units

t_GLITCH(UVLO)

UVLO & OVP Glitch Filter

Delay Time

Overdrive = 50mV

10

µs

t_VISS(PROP)

VISS Propagation Delay

Time

V_VCCSENSE- V_SENSE= 0mV to 60mV

7

µs

Capacitance from VISS to GND is

100pF

t_VISS(RISE)

VISS Rise Time

V_VCCSENSE- V_SENSE= 0mV to 60mV

25

Capacitance from VISS to GND is

100pF

V_VISS10% to 90%

t_{GLITCH(PWRGD)}PWRGD Glitch Filter Delay

Time

Overdrive = 250mV

30

µs

t_DLY(DISCH)

GATE OFF to DISCH Delay

Time

0.25

Notes:

1. Exceeding the absolute maximum rating may damage the device.

2. The device is not guaranteed to function outside its operating rating.

3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.

4. Specification for packaged product only.

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Block Diagram

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there is sufficient charge stored on the load capacitor

Functional Description

as evidenced by the output load voltage profile. Note

that the secondary overcurrent detection threshold

(I_SOC) is set externally at the controller’s S[1:0] pins.

Once the inrush current exceeds the I_SOCthreshold,

the circuit breaker trips without delay and the

MIC2310 controller shuts down the output. If the

inrush current profile does not cause either of the OC

detection circuits to trip the circuit breaker and assert

the I_FLT digital output, the controller will assert the

PWRGD digital output when the output load voltage is

higher than the controller’s V_PGHthreshold voltage and

the V_GSof the external MOSFET is higher than the

controller’s V_GSPGHthreshold voltage. Due to the low

R_DS(ON)of the external MOSFET, the output load

voltage rises with the GATE voltage as the V_GSof the

MOSFET reaches its threshold voltage. Once the

output load voltage stabilizes near the V_CCsupply

voltage, the V_GSof the external MOSFET increases

above its threshold voltage and eventually exceeds

Basic Startup Cycle

The basic operation of the MIC2310 is illustrated

below in Figure 2 from a cold-start condition. With the

applied V_CCsupply low such that the internal V_REG

voltage is less than the MIC2310’s internal

V_VREG(UVLOH)threshold voltage, all state machines are

reset, all voltage and current monitor subcircuits are

OFF, and the GATE drive circuit is disabled. Digital

inputs and all open-drain digital outputs are inactive.

When the applied V_CCsupply rises such that the

internal V_REGvoltage is above the controller’s

V_VREG(UVLOH)threshold voltage, the t_PORcounter circuit

commences. Once the timer terminates, all internal

state machines are activated, the CPRIMARY short

detection circuit is ON and the DG & DS MOSFET

short detection circuits are ON if ENABLE is LOW.

The I_FLT, PWRGD, and HW_FLT outputs are valid.

Upon the application of an ENABLE LOW-to-HIGH

transition after the t_PORdelay, or at the end of the t_POR

delay if ENABLE is already HIGH, a nominal start-up

commences where the dI_D/dt-controlled inrush current

(by dI_D/dt = 17.6x10^-3× I_SLEW/ (R_SENSE×C_SLEW)) is

permitted to exceed the I_POCthreshold for t_POC, until

V_GSPGH. The PWRGD output asserts to signal that the

external MOSFET is fully enhanced and ready for the

application of the full load.

+12V, nominal

V_REG= 5V, nominal

V_CC

V_VREGUVLOH

Primary & Secondary

OC Detector Armed

ENABLE

V_GSPGH

Power

Not Good

GATE

Power

Good

I_SOC= V_CBS/R_SENSE

set by S[1:0]

V_PGL

V_OUT

t_POC

I_POC= V_CBP/R_SENSE

dI_D/dt

Control

by C_SLEW

I_SOC

I_POC

Peak inrush current = f(C_SLEW, C_LOAD

)

I_LOAD

t

_POC= f(C_PRIMARY)

∆t = f(C_GATE,V_TH(FET)

)

0A

t_POR

PWRGD

I_FLT

Figure 2. Basic Startup Cycle

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OC detector has been triggered, the 3mA current

Primary Overcurrent (OC) Detector Trips Circuit

Breaker and Asserts I_FLT

source is first disabled and a 3µA current sink is

enabled to discharge the external C_PRIMARY. When

C_PRIMARYhas discharged below V_PRIL, a default timer is

enabled. Once the default timer (t_POCSENSE) times out,

the circuit breaker is tripped, the 3µA current sink is

disabled, and the 3mA current source is enabled to

discharge C_PRIMARYback to V_REGquickly. Concurrently,

the GATE drive circuit is disabled and a higher

current, fault-mode pull-down current sink is enabled

at the GATE pin. The DISCH output goes high to

(optionally) drive external pull-down circuitry.

Figure 3 below illustrates the behavior of the controller

to an OC event after the primary and secondary OC

detection circuits have been armed (upon the

application of an ENABLE LOW-to-HIGH transition

and after t_POR) and steady-state operation has been

achieved. Note that the assertion of the controller’s

PWRGD digital output occurs when the output load

voltage profile is higher than the controller’s V_PGH

threshold voltage and the V_GSof the external

MOSFET is higher than the controller’s V_GSPGH

threshold voltage.

In the event that the CPRIMARY pin is left NC

(intentionally or otherwise), the overcurrent timer

default value is t_POCSENSE(250µs typical), as specified

in the ac specification table. Once the circuit breaker

is latched, the I_FLT digital output is asserted and the

PWRGD digital output becomes de-asserted when the

output voltage profile falls below the controller’s V_PGL

threshold voltage or the V_GSof the external MOSFET

falls below the controller’s V_GSPGHthreshold voltage.

The use of an external C_PRIMARYcapacitor sets the

response time, t_POC, of the primary OC detector

according to the internal V_PRILthreshold voltage and

the CPRIMARY pin discharging current, I_PRI, where

t_POC= t_POCSENSE+ C_PRIMARY∗ (V_PRIL/I_PRI). Prior to

triggering the primary OC detector (i.e., when

V_VCCSENSE-V_SENSE< V_CBP), a 3mA current source is

enabled to hold the CPRIMARY pin voltage to the

internally-generated V_REGvoltage. When the primary

+12V, nominal

V_REG= 5V, nominal

V_CC

V_VREG(UVLOH)= +4.25V

Primary &

ENABLE

Secondary OC

Detectors Armed

V_GSPGH

Power

Not Good

V_GSPGH

GATE

V_OUT

Power

Good

V_PGL

V_CBS

t_POC

V_CBP

V_VCCSENSE–V_SENSE

0V

t_POR

PWRGD

I_FLT

I_FLT is asserted by Primary OC

Dtector CB Trip after t_POC

t_POC= f(C_PRIMARY

)

Figure 3. Primary OC Detector Trips Circuit Breaker

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MIC2310

the ac specification table. When the secondary OC

detector has sensed a very large current surge

(V_CCSENSE– V_SENSE≥ V_CBS), the circuit breaker is

tripped within t_SOCSENSE. Concurrently, the GATE drive

circuit is disabled and a higher current, fault-mode

pull-down current sink is enabled at the GATE pin.

The DISCH output goes high to (optionally) drive

external pull-down circuitry.

Secondary OC Detector Trips Circuit Breaker and

Asserts I_FLT

Figure 4 illustrates the behavior of the controller to an

OC event after the primary and secondary OC

detection circuits have been armed (upon the

application of an ENABLE LOW-to-HIGH transition

and after t_POR) and steady-state operation has been

achieved. Note that the assertion of the controller’s

PWRGD digital output occurs when the output load

voltage profile is higher than the controller’s V_PGH

threshold voltage and the V_GSof the external

MOSFET is higher than the controller’s V_GSPGH

threshold voltage.

Once the circuit breaker is latched, the I_FLT digital

output is asserted and the PWRGD digital output

becomes de-asserted when the output voltage profile

falls below the controller’s V_PGLthreshold voltage or

the V_GSof the external MOSFET falls below the

controller’s V_GSPGHthreshold voltage.

The controller’s secondary OC detection threshold is

set by the status of the controller’s S[1:0] pins and its

response time is internally set at t_SOCSENSEas shown in

V_CC= 12V, nominal

V_REG= 5V, nominal

V

_VREG(UVLOH)= +4.25V

Figure 4. Secondary OC Detector Trips Circuit Breaker

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voltage profile at no time rises higher than the

controller’s V_PGHthreshold voltage and the V_GSof the

external MOSFET does not rise higher than the

controller’s V_GSPGHthreshold voltage.

Charging Load by dI_D/dt – Primary OC Trips CB

after t_POCand CB Reset by Toggling ENABLE

HIGH-to-LOW

Figure 5 illustrates the behavior of the controller to an

OC event after the primary and secondary OC

detection circuits have been armed (upon the

application of an ENABLE LOW-to-HIGH transition

and after t_POR). In this example, the load capacitor is

charged at a controlled dI_D/dt rate. Steady-state

operation is not achieved as the controlled inrush

profile causes the primary OC detector to trigger at

I_POCand continues charging when the t_POCSENSEtimer

terminates. Note that the controller’s PWRGD digital

output does not assert because the output load

Once the circuit breaker has latched, the I_FLT digital

output is asserted. When the circuit breaker is tripped

by either the primary OC or secondary OC detectors),

applying a HIGH-to-LOW transition on the ENABLE

pin will reset the circuit breaker. At a delay defined by

t_CBRESET, the internal circuit breaker is reset and is

indicated when the I_FLT digital output becomes de-

asserted. The earliest a LOW-to-HIGH transition at

ENABLE is permitted to initiate a new start-up

sequence is defined by the t_ENLPWtiming specification.

V_CC= 12V, nominal

V_REG= 5V, nominal

V

_VREG(UVLOH)= +4.25V

Figure 5. dI_D/dt Load Charge Profile w/ Primary OC Circuit Breaker (CB) Trip w/ CB Reset

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The use of an external C_RETRYcapacitor sets the auto-

Primary OC Trips Circuit Breaker (CB) and CB

Resets with C_RETRY(Auto-Retry Timing Capacitor)

retry time, t_RETRY, according to the internal V_RETRYH

threshold voltage and the CRETRY pin charging

current, I_RETRYUP[t_RETRY= C_RETRY* (V_RETRYH/I_RETRYUP)].

Prior to the tripping of the OC circuit breaker, a 3mA

current sink is enabled holding the CRETRY pin

voltage at 0V. When the OC circuit breaker has been

tripped, the 3mA current sink is disabled and a 3µA

current source is enabled to charge the external

C_RETRYcapacitor. When C_RETRYhas charged above

V_RETRYH, the circuit breaker is reset such that the

I_FLT digital output is de-asserted. Additionally, the

3µA current source is disabled and the 3mA current

sink is enabled to discharge the CRETRY pin voltage

back to 0V. When C_RETRYhas discharged below

V_RETRYL, the GATE drive circuit is re-enabled and the

DISCH output returns low. For the case of a persistent

overcurrent load, the controller will continuously cycle

between starting up into an OC condition that trips the

circuit breaker and the auto-retry time before the

circuit breaker is reset.

Figure 6 illustrates the behavior of the controller to a

primary OC event when a C_RETRYcapacitor is used to

automatically reset the circuit breaker. The automatic

reset operation is the same for the case of a

secondary OC event. In this example, the primary and

secondary OC detection circuits have been armed

(upon the application of an ENABLE LOW-to-HIGH

transition and after t_POR) and the load capacitor is

charged at a controlled dI_D/dt rate. Note that in this

diagram, ENABLE is tied to V_CCand rises with V_CC.

Steady-state operation is achieved as the controller’s

PWRGD digital output is asserted when the output

load voltage profile is higher than the controller’s V_PGH

threshold voltage and the V_GSof the external

MOSFET is higher than the controller’s V_GSPGH

threshold voltage.

When the primary OC detector has been triggered by

an output current exceeding I_POCfor a time t_POC, the

circuit breaker is tripped, the GATE drive circuit is

disabled, the fault-mode pull-down current sink is

enabled at the GATE pin, the DISCH output goes

high, and the I_FLT digital output becomes asserted.

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MIC2310

V_CC= 12V, nominal

V_REG= 5V, nominal

VCC & VREG

ENABLE

V_VREG(UVLOH)

V_GSPGH

GATE

V_OUT

V_PGL

V_PGH

t_POC

I_POC

I_LOAD

t_RETRY

CRETRY

t_POR

PWRGD

I_FLT

DISCH

Figure 6. Primary Overcurrent Fault with Auto-Retry to Reset the Circuit Breaker

current sink is not capable of holding the voltage at 0V

HW_FLT Digital Output Asserted by a MOSFET DG

Short with ENABLE = LOW

as the GATE voltage tracks the MOSFET’s DRAIN

voltage. The voltage monitor circuit at the controller’s

GATE pin will be triggered once the GATE voltage

crosses the V_GATEFT(EXT)threshold voltage. The

HW_FLT digital output is subsequently asserted within

a delay approximately equal to the delay in the logic

circuits – no additional timing circuit is required. To

clear the latched GATE voltage monitor circuit and to

reset the HW_FLT digital output, the applied V_CC

supply voltage must fall such that V_REGis below the

controller’s V_VREG(UVLOL)threshold voltage.

In order to protect the system from the result of the

installation of a damaged MOSFET on the PCB, the

controller incorporates

a MOSFET shorted DG

detection scheme whose operation is described in

Figure 7. With the applied V_CCsupply high such that

the internal V_REGvoltage is above the controller’s

V_VREG(UVLOH)threshold voltage, an elapsed POR timer,

and with the ENABLE input LOW, a weak current sink

at the GATE pin attempts to hold the GATE voltage at

0V. If there is a DG short on the MOSFET, the weak

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Figure 7. Hardware Fault Detection of a MOSFET DG Short with ENABLE = LOW

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at 0V as the SOURCE voltage tracks the MOSFET’s

HW_FLT Digital Output Asserted by MOSFET DS

Short with ENABLE = LOW

DRAIN voltage. The voltage monitor circuit at the

controller’s SOURCE pin will be triggered once the

SOURCE voltage crosses the V_SRCFT(EXT)threshold

voltage. The HW_FLT digital output is subsequently

asserted within a delay approximately equal to the

delay in the logic circuits – no additional timing circuit

is required. To clear the latched source voltage

monitor circuit and to reset the HW_FLT digital output,

the applied V_CCsupply voltage must fall such that

V_REGis below the controller’s V_VREG(UVLOL)threshold

voltage.

In order to protect the system from the result of the

installation of a damaged MOSFET on the PCB, the

controller incorporates

a

MOSFET shorted DS

detection scheme whose operation is described in

Figure 8. With the applied V_CCsupply high such that

the internal V_REGvoltage is above the controller’s

V_VREG(UVLOH)threshold voltage, an elapsed POR timer,

and with the ENABLE input LOW, a voltage monitor

circuit for the controller’s SOURCE pin is enabled. If

there is a DS short on the MOSFET, the external load

on the MOSFET is not capable of holding the voltage

Figure 8. Hardware Fault Detection of a MOSFET DS Short with ENABLE = LOW

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MIC2310

current sink is enabled, the DISCH output goes high,

and the t_DS-SSFAULTtimer is started. With the ENABLE

input LOW, a voltage monitor circuit for the controller’s

SOURCE pin (i.e., V_OUT) is enabled. If there is a DS

short, the voltage at the source will not drop to 0V

even though the GATE is OFF. If the output voltage at

the SOURCE pin remains higher than the controller’s

HW_FLT Asserted by MOSFET DS Short after

Steady-state Operation then ENABLE = HIGH-to-

LOW

Figure 9 illustrates the behavior of the controller to a

shorted DS MOSFET condition after steady-state

operation is achieved via a nominal start-up. Note that

the load capacitor at start-up was charged in a

controlled dI_D/dt mode and assertion of the controller’s

PWRGD digital output occurs when the output load

voltage profile is higher than the controller’s V_PGH

threshold voltage and the V_GSof the external

MOSFET is higher than the controller’s V_GSPGH

threshold voltage. Upon the application of a HIGH-to-

LOW transition on ENABLE by the service processor,

the GATE drive circuit is disabled, the weak GATE

V_SRCFT(EXT)threshold voltage when the t_DS-SSFAULTtimer

terminates, the HW_FLT digital output is asserted. To

repair the damaged MOSFET and to reset the

HW_FLT digital output and the controller, the service

processor instructs the main supply to turn off the V_CC

supply voltage to the controller such that V_REGfalls

below the controller’s V_VREG(UVLOL)threshold voltage.

Figure 9. Hardware Fault by a MOSFET DS Short after Steady-State Operation

(ENABLE = HIGH-to-LOW)

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MIC2310

voltage monitor circuit for the controller’s SOURCE

HW_FLT Asserted by MOSFET DS Short after

Steady-state Operation then a Fault Condition

pin is also enabled. If there is a DS short, the voltage

at the source will not drop to 0V even though the

GATE is OFF. If the output voltage at the SOURCE

pin remains higher than the controller’s V_SRCFT(EXT)

threshold voltage when the t_DS-SSFAULTtimer

terminates, the HW_FLT digital output is asserted. To

repair the damaged MOSFET and to reset the

HW_FLT digital output and the controller, the service

processor instructs the main supply to turn off the V_CC

supply voltage to the controller such that V_REGfalls

below the controller’s V_VREG(UVLOL)threshold voltage.

Figure 10 illustrates the behavior of the controller to a

shorted DS MOSFET condition after steady-state

operation is achieved via a nominal start-up. With the

occurrence of one of the following fault conditions –

UVLO, OVP, primary OC, secondary OC, open

LOADSENSE, or open GNDSENSE - the GATE drive

circuit is disabled, the GATE fault-mode pull-down

current sink is enabled, the DISCH output goes high,

and the t_DS-SSFAULTtimer is started. The occurrence of

a primary OC fault condition is shown here. The

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

V_GSPGH

GATE

DG Short

V_PGL

V_PGH

V_SRCFT(EXT)

V_OUT

t_POC

I_LOAD

t_POR

PWRGD

I_FLT

t_DS-SSFAULT

HW_FLT

DISCH

Figure 10. HW_FLT Asserted by a MOSFET DS Short after Steady-State Operation then a Fault Condition

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R_SENSEshort detection at low current, a minimum V_DS

Shorted R_SENSEDetector Trips CB and Asserts

HW_FLT

of ∆V_DS(FET)must exist across the external MOSFET

for a shorted sense resistor to be detected. For larger

values of V_DSacross the external MOSFET generated

by higher load currents, the ∆V_RSENSEthreshold

voltage for the detection of an R_SENSEshort follows the

equation ∆V_RSENSE= 0.5 * (V_DS- ∆V_DS(FET)). If there

exists a short across the sense resistor such that V_RS

drops below the ∆V_RSENSEthreshold voltage, then an

internal circuit breaker is tripped, the GATE drive

circuit is disabled, the GATE fault-mode pull-down

current sink is enabled, the DISCH output goes high,

and the HW_FLT digital output is asserted. To repair

the damaged sense resistor and reset the HW_FLT

digital output, the service processor instructs the main

supply to turn off the V_CCsupply voltage to the

controller such that V_REGfalls below the controller’s

In order to protect the system from the result of the

installation of a shorted sense resistor on the PCB,

which would increase the effective OC detection

thresholds to unsafe levels, the controller incorporates

a shorted R_SENSEdetection scheme whose operation is

described in Figure 11. The R_SENSEdetection circuitry

is enabled upon the application of an ENABLE LOW-

to-HIGH transition, an elapsed POR timer, and the

V_GSof the external MOSFET being higher than the

controller’s V_GSPGHthreshold voltage. Note that for the

case of a shorted sense resistor, dI_D/dt control of the

inrush current is disabled and the controller defaults to

dV_GATE/dt control of the GATE voltage.

An R_SENSEshort is detected by comparing the V_RS

voltage drop across the sense resistor

V_VREG(UVLOL)threshold voltage.

(V_CCSENSE-V_SENSE) to the V_DSvoltage drop across the

external MOSFET (V_SENSE-V_SOURCE). To avoid a false

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V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

V_GSPGH

GATE

V_OUT

V_PGH

VDS(FET)

DS(FET)

RSENSE

VRS

t_POR

PWRGD

HW_FLT

DISCH

Figure 11. Shorted R_SENSETrips Circuit Breaker and Asserts HW_FLT

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capacitor value, one which keeps the primary OC

Shorted C_PRIMARYDetector Asserts HW_FLT at

Start-up

response time, t_POC, less than 0.5s, C_PRIMARYcharges

above V_PRIHbefore the POR timer terminates and

normal operation commences. However, if the

CPRIMARY pin is shorted to GND or C_PRIMARYis too

large, as in this timing diagram, the POR timer

terminates before C_PRIMARYcharges above V_PRIHand a

shorted C_PRIMARYis detected. When a C_PRIMARYshort is

detected, the GATE drive circuit and the DISCH

output are not affected, however, the HW_FLT digital

output is asserted. To repair the damaged C_PRIMARY

capacitor and reset the HW_FLT digital output, the

service processor instructs the main supply to turn off

the V_CCsupply voltage to the controller such that V_REG

falls below the controller’s V_VREG(UVLOL)threshold

voltage.

In order to protect the system from the result of the

installation of a shorted or excessively large C_PRIMARY

capacitor on the PCB, the controller incorporates a

shorted C_PRIMARYdetection scheme.

A

shorted

CPRIMARY pin or an excessively large C_PRIMARY

capacitor will impact the primary OC detection time,

t_POC.The operation of the shorted C_PRIMARYdetection

scheme at start-up is described in Figure 12. Prior to

power-up, the CPRIMARY pin is discharged to 0V. As

the applied V_CCsupply and the internal V_REGvoltage

rise, a 3mA current source is applied to the

CPRIMARY pin to charge C_PRIMARYto V_REG. When the

internal V_REGvoltage is above the controller’s

V_VREG(UVLOH)threshold voltage, the t_PORtimer is

initiated. For the case of a reasonable C_PRIMARY

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

V_GSPGH

GATE

V_PGH

V_PGL

V_OUT

I_LOAD

SMALLER CPRIMARY

V_PRIH

CPRIMARY

PWRGD

CPRIMARY TOO LARGE

t_POR

HW_FLT

DISCH

Figure 12. Shorted C_PRIMARYDetector Asserts HW_FLT at Start-up

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circuit remains enabled and the DISCH output

remains low such that the external MOSFET remains

ON, however, the HW_FLT digital output is asserted.

To repair the damaged C_PRIMARYcapacitor and reset

the HW_FLT digital output, the service processor

instructs the main supply to turn off the V_CCsupply

voltage to the controller such that V_REGfalls below the

controller’s V_VREG(UVLOL)threshold voltage.

Shorted C_PRIMARYDetector Asserts HW_FLT during

Steady-state

Figure 13 illustrates the behavior of the controller to a

shorted C_PRIMARYcapacitor condition after steady-state

operation is achieved via a nominal start-up. If a

C_PRIMARYshort occurs during steady-state operation,

the CPRIMARY pin voltage will drop below the V_PRIL

threshold voltage and a shorted C_PRIMARYis detected.

When a C_PRIMARYshort is detected, the GATE drive

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

V_GSPGH

GATE

V_PGH

V_PGL

V_OUT

I_LOAD

SHORTED CPRIMARY

CPRIMARY REPAIRED

V_PRIH

CPRIMARY

V_PRIL

t_POR

PWRGD

HW_FLT

DISCH

Figure 13. Shorted C_PRIMARYDetector Asserts HW_FLT During Steady-State

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when the C_PRIMARYshort detection circuitry is re-

Shorted C_PRIMARYDetector Asserts HW_FLT After

Primary OC Event

enabled.

The diagram in Figure 14 illustrates the behavior of

the controller to a shorted C_PRIMARYcapacitor condition

after steady-state operation is achieved via a nominal

start-up and after a primary OC event has occurred.

As described previously, during a primary OC event,

the C_PRIMARYcapacitor is discharged as part of setting

the primary OC detector response time, t_POC. In order

to prevent a false C_PRIMARYshort detection from

occurring while the CPRIMARY pin is being

intentionally discharged, the C_PRIMARYshort detection

circuit is disabled when the primary OC detector

detects an overcurrent. In addition, the C_PRIMARYshort

detection circuit is not re-enabled until after a time

delay, t_SCPDETPOR, once the primary OC detector no

longer detects an overcurrent. This delay time should

allow a capacitor of reasonable size to be charged

back up above V_PRIH, even if it has been discharged to

0V, such that a false C_PRIMARYshort is not indicated

In the timing diagram, C_PRIMARYbecomes shorted

during the primary OC event. When the CPRIMARY

pin voltage falls below V_PRIL, the t_POCSENSEtimer is

enabled. Once this timer times out, the circuit breaker

is tripped, I_FLT is asserted, the GATE drive circuitry

is disabled, the GATE fault-mode pull-down current

sink is enabled, and the DISCH output goes high. As

the external MOSFET is turned OFF, the output

current drops and an overcurrent condition is no

longer detected. This initiates the t_SCPDETPORtimer.

Since C_PRIMARYdoes not charge back up above V_PRIH

before this timer expires, HW_FLT is asserted after

the t_SCPDETPORtime. To repair the damaged C_PRIMARY

capacitor and reset the HW_FLT digital output, the

service processor instructs the main supply to turn off

the V_CCsupply voltage to the controller such that V_REG

falls below the controller’s V_VREG(UVLOL)threshold

voltage.

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Micrel, Inc.

MIC2310

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

V_GSPGH

GATE

V_OUT

V_PGH

t_POCSENSE

t_POC

I_POC

I_LOAD

SHORTED CPRIMARY

V_PRIL

CPRIMARY REPAIRED

V_PRIH

CPRIMARY

t_POR

t_SCPDETPOR

PWRGD

I_FLT

HW_FLT

DISCH

Figure 14. Shorted C_PRIMARYDetector Asserts HW_FLT after Primary OC Event

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MIC2310

LOADSENSE pin is open, the LOADSENSE voltage

Open LOADSENSE Detector Trips CB

will remain at a lower voltage due to the load of other

internal circuitry. An open LOADSENSE pin is

detected by comparing the voltage at the SOURCE

pin to the voltage at the LOADSENSE pin. Once the

voltage at the SOURCE pin differs from the voltage at

the LOADSENSE pin by V_THLOADSENSE, a circuit

breaker is tripped, the GATE drive circuitry is

disabled, the GATE fault-mode pull-down current sink

is enabled, and the DISCH output goes high. This

circuit breaker can be reset, such that the GATE drive

circuitry can be re-enabled, by either a HIGH-to-LOW

transition on ENABLE or turning off the V_CCsupply

voltage to the controller such that V_REGfalls below the

controller’s V_VREG(UVLOL)threshold voltage.

In order to protect the system from the result of an

open LOADSENSE pin, the controller incorporates an

open LOADSENSE detection scheme. An open

LOADSENSE pin could result in the effective primary

OC detection threshold being at an unsafe level. The

timing diagram in Figure 15 describes the operation of

this function. With the applied V_CCsupply high such

that the internal V_REGvoltage is above the controller’s

V_VREG(UVLOH)threshold voltage, an elapsed POR timer,

and with the application of an ENABLE LOW-to-HIGH

transition, the GATE drive circuitry is enabled and the

GATE voltage begins to rise. As the external

MOSFET turns ON, the SOURCE voltage begins to

rise also. Normally, the LOADSENSE voltage would

rise with the SOURCE voltage. However, if the

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

GATE

V_GSPGH

V_PGH

V_THLOADSENSE

V_OUT

I_LOAD

LOADSENSE CONNECTED

LOADSENSE OPEN

LOADSENSE

t_POR

PWRGD

DISCH

Figure 15. Open LOADSENSE Detector Trips CB

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Micrel, Inc.

MIC2310

would remain at 0V. However, if the GNDSENSE pin

Open GNDSENSE Detector Trips CB

is open, the GNDSENSE voltage will rise due to the

load of other internal circuitry. An open GNDSENSE

pin is detected by comparing the voltage at the

GNDSENSE pin to the voltage at the AGND pin. Once

the voltage at the GNDSENSE pin differs from the

voltage at the AGND pin by V_THGNDSENSE, a circuit

breaker is tripped, the GATE drive circuitry is

disabled, the GATE fault-mode pull-down current sink

is enabled, and the DISCH output goes high. This

circuit breaker can be reset, such that the GATE drive

circuitry can be re-enabled, by either a HIGH-to-LOW

transition on ENABLE or turning off the V_CCsupply

voltage to the controller such that V_REGfalls below the

controller’s V_VREG(UVLOL)threshold voltage.

In order to protect the system from the result of an

open GNDSENSE pin, the controller incorporates an

open GNDSENSE detection scheme. An open

GNDSENSE pin could result in the effective primary

OC detection threshold being at an unsafe level. The

timing diagram in Figure 16 describes the operation of

this function. With the applied V_CCsupply high such

that the internal V_REGvoltage is above the controller’s

V_VREG(UVLOH)threshold voltage, an elapsed POR timer,

and with the application of an ENABLE LOW-to-HIGH

transition, the GATE drive circuitry is enabled and the

GATE voltage begins to rise. As the external

MOSFET turns ON, the SOURCE voltage begins to

rise also and the LOADSENSE voltage follows the

SOURCE voltage. Normally, the GNDSENSE pin

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

GATE

V_GSPGH

V_PGH

V_OUT

I_LOAD

GNDSENSE OPEN

V_THGNDSENSE

GNDSENSE CONNECTED

GNDSENSE

t_POR

PWRGD

DISCH

Figure 16. Open GNDSENSE Detector Trips CB

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Micrel, Inc.

MIC2310

V_OVPHthreshold voltage, the GATE drive circuitry is

UVLO and OVP Operation

disabled, the GATE fault-mode pull-down current sink

is enabled, and the DISCH output goes high.

Increasing V_CCsuch that the voltage applied to the

UVLO pin increases above V_UVLOHor decreasing V_CC

such that the voltage applied to the OVP decreases

below V_OVPLre-enables the GATE drive circuit and

forces the DISCH output low, allowing the controller to

return to normal operation.

The system can be protected against an under-

voltage condition or an over-voltage condition on the

V_CCsupply by using an external resistor divider and

the UVLO and OVP pins, respectively. Figure 17

illustrates the timing of the GATE and digital pin

outputs when the input supply crosses the UVLO and

OVP thresholds. When the voltage applied to the

UVLO pin is less than the V_UVLOLthreshold voltage or

the voltage applied to the OVP pin is greater than the

V_CC& V_REG

V_VREG(UVLOH)

ENABLE

V_GSPGH

GATE

V_PGH

V_PGL

V_PGH

V_PGL

V_PGH

V_OUT

I_LOAD

UVLOL

UVLOH

UVLO

OVPH

OVPL

OVP

t_POR

PWRGD

DISCH

Figure 17. UVLO and OVP Operation

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Micrel, Inc.

MIC2310

digital output is asserted and the VISS output

VISS Output Operation

becomes active. The current flowing in the external

sense resistor is determined by sensing the voltage

across the sense resistor (V_CCSENSE-V_SENSE). As the

output current varies under changing load conditions,

The VISS output provides a voltage which is

proportional to the output current flowing in the

external sense resistor. Figure 18 illustrates the

operation of this output. With the applied V_CCsupply

high such that the internal V_REGvoltage is above the

controller’s V_VREG(UVLOH)threshold voltage, an elapsed

POR timer, and with the application of an ENABLE

LOW-to-HIGH transition, the GATE drive circuitry is

enabled. When the output load voltage profile is

higher than the controller’s V_PGHthreshold voltage and

the V_GSof the external MOSFET is higher than the

controller’s V_GSPGHthreshold voltage, the PWRGD

V_CCSENSE-V_SENSEalso varies and the VISS output

voltage changes proportionally according to V_ISS(SENS)

.

When the external MOSFET is disabled, either by a

HIGH-to-LOW transition on ENABLE or due to a fault

condition, the V_GSof the external MOSFET falls below

the controller’s V_GSPGHthreshold voltage. This causes

the PWRGD digital output to be de-asserted and the

VISS output to be disabled.

V_CC& V_REG

V_VREG(UVLOH)

V_VREG(UVLOL)

ENABLE

GATE

V_GSPGH

V_PGH

V_PGL

V_OUT

I_LOAD

VISS

t_POR

PWRGD

DISCH

Figure 18. VISS Operation

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MIC2310

components are vital with regards to the shorted

_SENSEdetection scheme such that the values of each

Applications Information

R

The MIC2310 can be configured to address power-

limiting applications other than the 240-VA power

control (UL60950 Safe Power Handling Systems).

There are two key requirements to consider in

selecting the external components for use in various

power-limit applications: 1) The value (and tolerance)

of the R_SENSEcurrent sensing resistor; and 2) The

R_DS(ON)of the external Power MOSFET. These two

need to be chosen such that variations in R_DS(ON)and

R_SENSEover process, supply, and temperature does

not result in a false R_SENSEshort detection. In short,

the value of R_DS(ON)of the external MOSFET should

be selected to not exceed twice the value of R_SENSE

over process, supply, and temperature, to avoid the

generation of

a

false R_SENSEshort detection.

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MIC2310

Package Information

24-Pin TSSOP (TS)

MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com

The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its

use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product

can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant

into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A

Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully

indemnify Micrel for any damages resulting from such use or sale.

M9999-070108-A

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34


型号：	MIC2310-1ZTS
厂家：	MICREL SEMICONDUCTOR
描述：	Single-FET, Constant Power-Limit Hot Swap Controller 单场效应管，恒功率，限制热插拔控制器光电二极管控制器
文件：	总34页 (文件大小：483K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MIC2310-1ZTS [MICREL]

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