MIC502BM [MICREL]
Fan Management IC Advance Information; 范管理IC超前信息
| 型号： | MIC502BM |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Fan Management IC Advance Information |
| 文件： | 总11页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MIC502
Fan Management IC
Advance Information
General Description
Features
The MIC502 is a thermal and fan management IC which
supports the features for NLX/ATX power supplies and other
control applications.
• Temperature-proportional fan speed control
• Low-cost, efficient PWM fan drive
• 4.5V to 13.2V IC supply range
• Controls any voltage fan
• Overtemperature detection with fault output
• Integrated fan startup timer
• Automatic user-specified sleep mode
• Supports low-cost NTC/PTC thermistors
• 8-pin DIP and SOIC packages
Fan speed is determined by an external temperature sensor,
typically a thermistor-resistor divider, and (optionally) a sec-
ond signal, such as the NLX “FanC” signal. The MIC502
produces a low-frequency pulse-width modulated output for
driving an external motor drive transistor. Low-frequency
PWM speed control allows operation of standard brushless
dc fans at low duty cycle for reduced acoustic noise and
permits the use of a very small power transistor. The PWM
time base is determined by an external capacitor.
Applications
• NLX and ATX power supplies
• Personal computers
An open-collector overtemperature fault output is asserted if
the primary control input is driven above the normal control
range.
• File servers
• Telecom and networking hardware
• Printers, copiers, and office equipment
• Instrumentation
• Uninterruptable power supplies
• Power amplifiers
The MIC502 features a low-power sleep mode with a user-
determined threshold. Sleep mode completely turns off the
fan and occurs when the system is asleep or off (both control
inputs very low). A complete shutdown or reset can also be
initiated by external circuitry as desired.
Ordering Information
Part Number
MIC502BN
MIC502BM
Temperature Range
–40°C to +85°C
Package
The MIC502 is available as 8-pin plastic DIP and SOIC
packages in the –40°C to +85°C industrial temperature
range.
8-pin Plastic DIP
8-pin SOIC
–40°C to +85°C
Typical Application
12V
Fan
Q1
T1 R1
R2
MIC502
1
2
3
4
8
7
6
5
VT1
CF
VDD
OUT
RBASE
R3
R4
VSLP OTF
GND VT2
Overtemperature
Fault Output
CF
Secondary
Fan-control
Input
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Pin Configuration
VT1
CF
1
2
3
4
8
7
6
5
VDD
OUT
OTF
VT2
VSLP
GND
8-Pin SOIC (M)
8-Pin DIP (N)
Pin Description
Pin Number
Pin Name
Pin Function
Thermistor 1 (Input): Analog input of approximately 30% to 70% of VDD
1
VT1
produces active duty cycle of 0% to 100% at driver output (OUT). Connect to
external thermistor network (or other temperature sensor). Pull low for
shutdown.
2
3
CF
PWM Timing Capacitor (External Component): Positive terminal for the
PWM triangle-wave generator timing capacitor. The recommended CF is
0.1µF for 30Hz PWM operation.
VSLP
Sleep Threshold (Input): The voltage on this pin is compared to VT1 and VT2
When VT1 < VSLP and VT2 < VSLP the MIC502 enters sleep mode until VT1 or
T2 rises above VWAKE. (VWAKE = VSLP + VHYST.) Grounding VSLP
.
V
disables the sleep-mode function.
4
5
GND
VT2
Ground
Thermistor 2 (Input): Analog input of approximately 30% to 70% of VDD
produces active duty cycle of 0% to 100% at driver output (OUT). Connect to
motherboard fan control signal or second temperature sensor.
6
7
8
/OTF
OUT
VDD
Overtemperature Fault (Output): Open-collector output (active low).
Indicates overtemperature fault condition (VT1 > VOT) when active.
Driver Output: Asymmetical-drive active-high complimentary PWM output.
Typically connect to base of external NPN motor control transistor.
Power Supply (Input): IC supply input; may be independent of fan power
supply.
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Supply Voltage (V ) ..................................................+14V
Supply Voltage (V ) ................................ +4.5V to +13.2V
DD
DD
Output Sink Current (I
) ..................................10mA
) ..........................25mA
Sleep Voltage (V
)........................................GND to V
OUT(sink)
SLP DD
Output Source Current (I
Temperature Range (T ) ........................... –40°C to +85°C
OUT(source)
A
Input Voltage (any pin) .........................–0.3V to V +0.3V
Power Dissipation at 25°C
DD
SOIC ...................................................................800mW
DIP ......................................................................740mW
Junction Temperature (T ) ...................................... +125°C
J
Storage Temperature (T ) ....................... –65°C to +150°C
A
Derating Factors
Lead Temperature (Soldering, 5 sec.) ...................... 260°C
ESD, Note 3
SOIC ...............................................................8.3mW/°C
Plastic DIP.......................................................7.7mW/°C
Electrical Characteristics
4.5V ≤ VDD ≤ 13.2V, Note 4; TA = 25, bold values indicate –40°C ≤ TA ≤ +85°C; unless noted
Symbol
Parameter
Condition
Min
Typ
Max
Units
IDD
Supply Current, Operating
VSLP = grounded, OTF, OUT = open,
CF = 0.1µF, VT1 = VT2 = 0.7 VDD
0.5
1.2
mA
IDD(slp)
Supply Current, Sleep
VT1 = grounded,
VSLP, OTF, OUT = open, CF = 0.1µF
240
400
µA
Driver Output
tR
Output Rise Time, Note 5
Output Fall Time, Note 5
Output Sink Current
IOH = 10mA
TBD
TBD
50
50
µs
µs
tF
IOL = 1mA
IOL
IOH
VOL = 0.5V
0.9
10
10
mA
mA
mA
µA
Output Source Current
4.5V ≤ VDD ≤ 5.5V, VOH = 2.4V
10.8V ≤ VDD ≤ 13.2V, VOH = 3.2V
VOUT = 0V
IOS
Sleep-Mode Output Leakage
1
Thermistor and Sleep Inputs
VPWM(max)
100% PWM Duty Cycle
Input Voltage
67
70
73
%VDD
VPWM(span)
VHYST
VIL
VPWM(max) – VPWM(min)
Sleep Comparator Hysteresis
VT1 Shutdown Threshold
VT1 Startup Threshold
37
8
40
11
43
14
%VDD
%VDD
V
0.7
VIH
1.1
74
V
VOT
VT1 Overtemperature Fault
Threshold
Note 6
77
80
%VDD
IVT, IVSLP
tRESET
VT1, VT2, VSLP Input Current
Reset Setup Time
–2.5
1
µA
µs
minimum time VT1 < VIL, to guarantee reset,
Note 5
30
Oscillator
f
Oscillator Frequency, Note 7
4.5V ≤ VDD ≤ 5.5V, CF = 0.1µF
10.8V ≤ VDD ≤ 13.2V, CF = 0.1µF
Note 7
24
27
15
27
30
30
33
90
Hz
Hz
Hz
s
fMIN, fMAX
tSTARTUP
Oscillator Frequency Range
Startup Interval
64/f
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Symbol
Parameter
Condition
Min
Typ
Max
0.3
Units
Overtemperature Fault Output
VOL
IOH
Active (Low) Output Voltage
Off-State Leakage
IOL = 2mA
V
V/OTF = VDD
1
µA
Note 1. Exceeding the absolute maximum rating may damage the device.
Note 2. The device is not guaranteed to function outside its operating rating.
Note 3. Devices are ESD sensitive. Handling precautions recommended.
Note 4: Part is functional over this V range; however, it is characterized for operation at 4.5V ≤ V ≤ 5.5V and 10.8V ≤ V ≤ 13.2V ranges. These
DD
DD
DD
ranges correspond to nominal V of 5V and 12V, respectively.
DD
Note 5. Guaranteed by design.
Note 6. is guaranteed by design to always be higher than V
V
.
PWM(max)
OT
0.1µF
Note 7. Logic time base and PWM frequency. For other values of C , f(Hz) = 30Hz
, where C is in µF.
F
C
Timing Diagrams
VOT
100%
0.7VDD
80%
VT1
VT2
Input
Signal
Range
70%
40%
50%
40%
30%
0%
VSLP
0.3VDD
VIH
VIL
0V
VOH
VOTF
VOL
0V
F
tPWM
tSTARTUP
A
B
C
D
E
G
VOH
VOUT
VOL
0V
Output
Duty Cycle
50%
80%
40%
70%
0%
100%
40%
Figure 1. Typical System Behavior
Note A. Output duty-cycle is initially determined by V , as it is greater than V
.
T1
T2
Note B. PWM duty-cycle follows V as it increases.
T1
Note C.
V
drops below V . V now determines the output duty-cycle.
T1 T2 T2
Note D. The PWM duty-cycle follows V as it increases.
T2
Note E. Both V and V decrease below V
but above V . The device enters sleep mode.
IL
T1
T2
SLP
Note F. The PWM ‘wakes up’ because one of the control inputs (V in this case) has risen above V
. The startup timer is triggered, forcing OUT
T1
WAKE
high for 64 clock periods. (V
= V
+ V
. See “Electrical Characteristics.”)
WAKE
SLP
HYST
Note G. Following the startup interval, the PWM duty-cycle is the higher of V and V
.
T2
T1
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VOT
100%
0.7VDD
VT1
VT2
PWM
Range
60%
30%
40%
VSLP
20%
0%
0.3VDD
VIH
VIL
0V
L
M
VOH
VOTF
VOL
0V
H
I
tSTARTUP
tPWM
J
K
N
O
VOH
VOUT
VOL
0V
Output
Duty Cycle
100%
40%
60%
100%
30%
0%
VDD
0V
VDD
Figure 2. MIC502 Typical Power-Up System Behavior
Note H. At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (t
). This insures that the fan will start from a
PWM
dead stop.
Note I. The PWM duty-cycle follows the higher of V and V in the case, V .
T1
T1
T2,
Note J. The PWM duty-cycle follows V as it increases.
T1
Note K. PWM duty-cycle is 100% (OUT constantly on) anytime V > V
.
T1
PWM(max)
Note L. /OTF is asserted anytime V > V . (The fan continues to run at 100% duty-cycle.)
T1
OT
Note M. /OTF is deasserted when V falls below V ; duty-cycle once again follows V .
T1
T1
OT
Note N. Duty-cycle follows V until V < V , at which time V becomes the controlling input signal. Note that V is below V
but above V ; so
IH
T1
T1
T2
T2
T1
SLP
normal operation continues. (Both V and V must be below V to active sleep mode.)
T1
T2
SLP
Note O. All functions cease when V < V ; this occurs regardless of the state of V .
T2
T1
IL
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Typical Characteristics
PWM Frequency vs.
Timing Capacitor Value
3000
1000
100
10
1
0.001
0.01
0.1
1
CAPACITANCE (µF)
Functional Diagram
VT2
PWM
5
Driver
OUT
7
VT1
1
CLK
Start-Up
Timer
OUT
RESET
CF
Oscillator
2
Sleep
VSLP
Sleep
Control
3
VDD
Power-On
Reset
8
Bias
Reset
ENABLE
VIL
OTF
6
Overtemperature
4
GND
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Once in sleep mode, all device functions cease (/OTF in-
Functional Description
Oscillator
active, PWM output off) unless V or V rise above V .
T1
T2
WAKE
(V
= V
+ V
.) V
is a fixed amount of hyster-
WAKE
SLP
HYST
HYST
A capacitor connected to CF determines the frequency of the
internal time base which drives the state-machine logic and
determines the PWM frequency. This operating frequency
esis added to the sleep comparator which prevents erratic
operation around the V operating point. The result is
SLP
stable and predictable thermostatic action: whenever pos-
sible the fan is shut down to reduce energy consumption and
acoustic noise, but will always be activated if the system
temperature rises.
will be typically 30Hz to 60Hz. (C = 0.1µF for 30Hz.)
F
Pulse-Width Modulator
A triangle-wave generator and threshold detector comprise
the internal pulse-width modulator (PWM). The PWM’s out-
put duty-cycle is determined by the higher of V or V . A
If the device powers-up or exits its reset state, the fan will not
start unless V or V rises above V .
T1
T2
WAKE
T1
T2
typicalvoltagerangeof30%to70%ofV appliedtotheVT1
DD
and VT2 pins corresponds to 0% to 100% duty-cycle. Since
at least one of the control voltage inputs is generally from a
System Operation
thermistor-resistor divider connected to V , the PWM out-
DD
Power Up
put duty cycle will not be affected by changes in the supply
voltage.
•
•
•
•
A complete reset occurs when power is applied.
OUT is off (low) and /OTF is inactive (high/floating).
If V < V , the MIC502 remains in shutdown.
Driver Output
OUT is a complementary push-pull digital output with asym-
metric drive (approximately 10mA source, 1mA sink—see
“Electrical Characteristics”). It is optimized for directly driving
an NPN transistor switch in the fan’s ground-return. See
“Applications Information” for circuit details.
T1
IL
The startup interval begins. OUT will be on (high) for 64
clock cycles (64 × t ).
PWM
•
Following the startup interval, normal operation begins.
Shutdown/Reset
InternalcircuitryautomaticallyperformsaresetoftheMIC502
whenpowerisapplied. TheMIC502maybeshutdownatany
time by forcing V below its V threshold. This is typically
POWER ON
T1
IL
accomplished by connecting the VT1 pin to open-drain or
open-collector logic and results in an immediate and asyn-
chronous shutdown of the MIC502. The OUT and /OTF pins
will float while V is below V .
Reset Startup Timer;
Deassert /OTF;
OUT Off (Low).
YES
T1
IL
If V then rises above V , a device reset occurs. Reset is
T1
IH
VT1 < VIL
?
equivalent to a power-up condition: the state of /OTF is
cleared, a startup interval is triggered, and normal fan opera-
tion begins.
NO
Startup Interval
VT1 > VOT
?
Assert /OTF While
T1 > VOT
Any time the fan is started from the off state (power-on or
coming out of sleep mode or shutdown mode), the PWM
output is automatically forced high for a startup interval of 64
YES
V
NO
NO
×t
.Oncethestartupintervaliscomplete,PWMoperation
PWM
will commence and the duty-cycle of the output will be
determined by the higher of V or V .
OUT Held On (High)
During Startup
Interval.
T1
T2
Overtemperature Fault Output
/OTF is an active-low, open-collector logic output. An over-
temperature condition will cause /OTF to be asserted. An
overtemperature condition is determined by V exceeding
Startup Interval
T1
Finished
?
the normal operating range of 30% to 70% of V by > 7% of
DD
V
. Note that V is guaranteed by design to always be
YES
DD
OT
PWM(max)
higher than V
.
Sleep Mode
Deassert OUT
(OUT = Low)
NORMAL
OPERATION
When V and V fall below V , the system is deemed
SLP
T1
T2
capable of operating without fan cooling and the MIC502
enters sleep mode and discontinues fan operation. The
threshold where the MIC502 enters sleep mode is deter-
Figure 3. Power-Up Behavior
mined by V
. Connecting the VSLP pin to ground disables
SLP
sleep mode.
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, the
Normal Operation
Sleep Mode
Normal operation consists of the PWM operating to control
the speed of the fan according to V and V . Exceptions to
this otherwise indefinite behavior can be caused by any of
three conditions: V exceeding V , an overtemperature
During normal operation, if V and V fall below V
T1
T2
SLP
devicewillgointosleepmodeandfanoperationwillstop. The
MIC502willexitsleepmodewhenV orV riseaboveV
T1
T2
T1
T2
SLP
by the hysteresis voltage, V . When this occurs, normal
T1
OT
HYST
condition; V being pulled below V initiating a device
operation will resume. The resumption of normal operation
uponexitingsleepisindistinguishablefromapower-onreset.
(See “Sleep: Normal Operation,” above.)
T1
IL
shutdown and reset; or both V and V falling below V ,
T1
T2
SLP
activatingsleepmode. Eachoftheseexceptionsistreatedas
follows:
NORMAL
OPERATION
SLEEP
Reset?
POWER ON
YES
YES
V
T1 < VIL
Disable PWM
?
NO
VT1 and VT2
< VSLEEP
?
SLEEP
Reset Initiated
NO
NO
V
T1 < VIL
?
YES
Overtemp?
VT1 > VOT
?
Assert /OTF while
YES
V
T1 > VOT
NO
NO
Reset Released
V
T1 > VIH
?
OUT Duty Cycle
Proportional to
Greater of VT1, VT2
YES
Wake Up?
V
T1 or VT2
VSLP+VHYST
?
>
NO
Figure 4. Normal System Behavior
YES
• Overtemperature: If the system temperature rises
typically 7% above the 100% duty-cycle operating point,
/OTF will be activated to indicate an overtemperature
fault. (V > V ) Overtemperature detection is essen-
POWER ON
T1
OT
tially independent of other operations—the PWM
continues its normal behavior; with V > V
Figure 5. Sleep-Mode Behavior
, the
,
T1
PWM(max)
output duty-cycle will be 100%. If V falls below V
T1
OT
the overtemperature condition is cleared and /OTF is no
longer asserted. It is assumed that in most systems, the
/OTF output will initiate power supply shutdown.
• Shutdown/Reset: If V is driven below V an immedi-
T1
IL
ate, asynchronous shutdown occurs. While in shutdown
mode, OUT is off (low), and /OTF is unconditionally
inactive (high/floating). If V subsequently rises above
T1
V , a device reset will occur. Reset is indistinguishable
IH
from a power-up condition. The state of /OTF is cleared,
a startup interval is triggered, and normal fan operation
begins.
• Sleep: If V and V fall below V , the device enters
T1
T2
SLP
sleep mode. All internal functions cease unless V or
T1
.) The
V
rise above V
. (V
= V
+ V
T2
WAKE
WAKE
SLP
HYST
/OTF output is unconditionally inactive (high/floating)
and the PWM is disabled during sleep. (OUT will float.)
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since
and
Applications Information
TheTypicalApplicationdrawingonpage1illustratesatypical
application circuit for the MIC502. Interfacing the MIC502
with a system consists of the following steps:
V
V
V
= 70% of V
= 30% of V
100% RPM
0% RPM
PWM(max)
PWM(min)
PWM(span)
DD
DD
1. Selecting a temperature sensor
then
2. Interfacing the temperature sensor to the VT1 input
= 40% of V
100% RPM range.
DD
3 Selecting a fan-drive transistor, and base-drive current
limit resistor
Figure 6 shows the following linear relationship between the
voltage applied to the VT1 input, motor drive duty cycle, and
approximate motor speed.
4. Deciding what to do with the Secondary
Fan-Control Input
since
5. Making use of the Overtemperature Fault Output.
V
V
V
V
= 0.7V
= 0.6V
= 0.5V
= 0.4V
100% PWM
75% PWM
50% PWM
25% PWM.
T1
T1
T1
T1
DD
DD
DD
DD
Temperature Sensor Selection
then
and
and
Temperature sensor T1 is a negative temperature coefficient
(NTC) thermistor. The MIC502 can be interfaced with either
a negative or positive tempco thermistor; however, a nega-
tive temperature coefficient thermistor typically costs less
than its equivalent positive tempco counterpart. While a
variety of thermistors can be used in this application, the
following paragraphs reveal that those with an R25 rating
(resistance at 25°C) of from about 50kΩ to 100kΩ lend
themselves nicely to an interface network that requires only
a modest current drain. Keeping the thermistor bias current
low not only indicates prudent design; it also prevents self-
heating of the sensor from becoming an additional design
consideration.Itisassumedthatthethermistorwillbelocated
within the system power supply, which most likely also
houses the speed-controlled fan.
In addition to the R25 thermistor rating, sometimes a data
sheet will provide the ratio of R25/R50 (resistance at 25°C
divided by resistance at 50°C) is given. Sometimes this is
given as an R0/R50 ratio. Other data sheet contents either
specify or help the user determine device resistance at
arbitrarytemperatures.ThethermistorinterfacetotheMIC502
usually consists of the thermistor and two resistors.
100
80
60
40
20
0
Temperature Sensor Interface
As shown by the Electrical Characteristics table, the working
voltageforinputVT1isspecifiedasapercentageofV .This
DD
conveniently frees the designer from having to be concerned
with interactions resulting from variations in the supply volt-
age. Bydesign, theoperatingrangeofVT1isfromabout30%
of V to about 70% of V
.
DD
DD
0
20
40
60
80
100
V
= V
– V
PWM(max) PWM(span)
PWM(min)
V
/SUPPLY VOLTAGE (%)
T1
When V = V
≈ 0.7V , a 100% duty-cycle motor
DD
T1
PWM(max)
Figure 6. Control Voltage vs. Fan Speed
Design Example
drive signal is generated. Conversely, when V = V
T1
PWM(min)
≈ 0.3V , the motor-drive signal has a 0% duty cycle.
DD
ResistorvoltagedividerR1||T1,R2intheTypicalApplication
The thermistor-resistor interface network is shown in the
TypicalApplicationdrawing.Thefollowingexampledescribes
the design process: A thermistor data sheet specifies a
thermistorthatisacandidateforthisdesignashavinganR25
resistance of 100kΩ. The data sheet also supports calcula-
tionofresistanceatarbitrarytemperatures,anditwasdiscov-
ered the candidate thermistor has a resistance of 13.6k at
70°C (R70). Accuracy is more important at the higher tem-
peratureendoftheoperatingrange(70°C)thanthelowerend
because we wish the overtemperature fault output (/OTF) to
be reasonably accurate—it may be critical to operating a
power supply crowbar or other shutdown mechanism, for
example. The lower temperature end of the range is less
important because it simply establishes minimum fan speed,
which is when less cooling is required.
diagram is designed to preset V to a value of V
corresponds to the slowest desired fan speed when the
resistance of thermistor T1 is at its highest (cold) value. As
temperature rises the resistance of T1 decreases and V
increases because of the parallel connection of R1 and T1.
that
T1
PWM
T1
Since V = V
represents a stopped fan (0% duty-
PWM(min)
T1
cycledrive), andsinceitisforeseenthatatleastsomecooling
will almost always be required, the lowest voltage applied to
the VT1 input will normally be somewhat higher than 0.3V
DD
(or >V
). It is assumed that the system will be in sleep
PWM(min)
mode rather than operate the fan at a very low duty cycle
(<< 25%).Operationatverylowdutycycleresultsinrelatively
little airflow. Sleep mode should be used to reduce acoustic
noise when the system is cool. For a given minimum desired
fan speed, a corresponding V
the following observation:
can be determined via
T1(min)
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Referring to the “Typical Application,” the following approach
can be used to design the required thermistor interface
network:
R
= 100k
T1
and
let
RT1 || R1 = 49.5k ≈ 50k
Let
R1 = ∞
R1 = 100k
R
= 13.6k
(at 70°C)
T1
While that solves the low temperature end of the range, there
is a small effect on the other end of the scale. The new value
of V for 70°C is 0.734, or about 73% of V . This represents
and
V = 0.7V
(70% of V
)
T
DD
DD
T
DD
only a 3% shift from the design goal of 70% of V . In
Since
DD
summary,R1=100k,andR2=33k.Thecandidatethermistor
used in this design example is the RL2010-54.1K-138-D1,
manufactured by Keystone Thermometrics.
V
×R2
DD
V =
T
R
||R1+R2
(
)
T1
The R25 resistance (100kΩ) of the chosen thermistor is
probably on the high side of the range of potential thermistor
resistances. The result is a moderately high-impedance
network for connecting to the V and/or V input(s). Be-
R2
+R2
0.7 =
R
(
)
T1
T1
T2
0.7R + 0.7R2 = R2
T1
cause these inputs can have up to 1µA of leakage current,
care must be taken if the input network impedance becomes
higher than the example. Leakage current and resistor accu-
racy could require consideration in such designs. Note that
0.7R = 0.3R2
T1
and
R2 = 2.33R = 2.33 × 13.6k = 31.7k ≈ 33k
T1
the V
input has this same leakage current specification.
SLP
Let’s continue by determining what the temperature-propor-
tional voltage is at 25°C.
Secondary Fan-Control Input
The above discussions also apply to the secondary fan-
control input, VT2, pin 5. It is possible that a second ther-
mistor, mounted at another temperature-critical location out-
side the power supply, may be appropriate. There is also the
possibility of accommodating the NLX “FanC” signal via this
input. If a second thermistor is the desired solution, the VT2
input may be treated exactly like the VT1 input. The above
discussions then apply directly. If, however, the NLX FanC
signal is to be incorporated into the design then the operating
voltage (V = 5V vs. V = 12V) becomes a concern. The
Let
R1 = ∞
and
R
= 100k
(at 25°C).
T1
From
V
×R2
DD
V =
T
R
(
+R2
)
T1
DD
DD
FanC signal is derived from a 12V supply and is specified to
swing at least to 10.5V. A minimum implementation of the
FanC signal would provide the capability of asserting full-
speed operation of the fan; this is the case when 10.5V ≤
FanC ≤ 12V. This FanC signal can be applied directly to the
V
DD × 33k
VT =
100k +33k
(
)
V = 0.248V
T
DD
Recalling from above discussion that the desired V for 25°C
should be about 40% of V , the above value of 24.8% is far
too low. This would produce a voltage that would stop the fan
(recall from the above that this occurs when V is about 30%
of V . To choose an appropriate value for R1 we need to
learn what the parallel combination of R and R1 should be
T
VT2 input of the MIC502, but only when its V is 12V. If this
DD
DD
signal is required when the MIC502 V
= 5V a resistor
DD
divider is necessary to reduce this input voltage so it does not
T
exceed the MIC502 V
voltage. A good number is 4V
DD
DD
(80%V ).
DD
T1
at 25°C:
Because of input leakage considerations, the impedance of
the resistive divider should be kept at ≤ 100kΩ. A series
resistor of 120kΩ driven by the Fan C signal and a 100kΩ
shunt resistor to ground make a good divider for driving the
Again
V
×R2
DD
V =
T
V
input.
R
||R1+R2
(
)
T2
T1
Transistor and Base-Drive Resistor Selection
R2
The OUT motor-drive output, pin 7, is intended for driving a
medium-power device, such as an NPN transistor. A rather
ubiquitous transistor, the 2N2222A, is capable of switching
up to about 400mA. It is also available as the PN2222A in a
plastic TO-92 package. Since 400mA is about the maximum
current for most popular computer power supply fans (with
manydrawingsubstantiallylesscurrent)andsincetheMIC502
provides a minimum of 10mA output current, the PN2222A,
with its minimum β of 40, is the chosen motor-drive transistor.
0.4 =
R
(
||R1+R2
)
T1
0.4(R || R1) + 0.4R2 = R2
T1
0.4(R || R1) = 0.6R2
T1
and
R
|| R1 = 1.5R2 = 1.5 × 33k = 49.5k
T1
Since
MIC502
172
May 1999
MIC502
Micrel
The design consists soley of choosing the value R
in
alerting a system about an overtemperature condition or
BASE
Figures 7 and 8. To minimize on-chip power dissipation in the
triggering a power supply crowbar circuit. If V
for the
DD
MIC502, the value of R should be determined by the
power supply voltage. The Electrical Characteristics table
specifies a minimum output current of 10mA. However,
MIC502 is 5V the output should not be pulled to a higher
voltage. This output can sink up to 2mA and remain compat-
ible with the TTL logic-low level.
BASE
different output voltage drops (V – V
) exist for 5V vs.
Timing Capacitors vs. PWM Frequency
DD
OUT
12V operation. The value R
should be as high as
BASE
The recommended C (see first page) is 0.1µF for opertaion
F
possible for a given required transistor base-drive current in
order to reduce on-chip power dissipation.
at a PWM frequency of 30Hz. This frequency is factory
trimmed within ±3Hz using a 0.1% accurate capacitor. If it is
desired to operate at a different frequency, the new value for
Referring to the “Typical Application” and to the “Electrical
Characteristics” table, the value for R
is calculated as
of OUT (pin 7) is
C is calculated as follows:
BASE
F
follows. For V
= 5V systems, I
DD
OH
3
guaranteed to be a minimum of 10mA with a V
of 2.4V.
OH
C =
, where C is in µF and f is in Hz.
f
R
then equals (2.4V – V ) ÷ 10mA = 170Ω.
BASE
BE
Thecomposition, voltagerating, ESR, etc., parametersofthe
capacitorarenotcritical.However,iftightcontroloffrequency
vs. temperature is an issue, the temperature coefficient may
become a consideration.
For V = 12V systems, R
= (3.4 – 0.7) ÷ 0.01 = 250Ω.
DD
BASE
Overtemperature Fault Output
The /OTF output, pin 6, is an open-collector NPN output. It is
compatible with CMOS and TTL logic and is intended for
Keystone Thermonics
RL2010-54.1K-138-D1
or similar
5V
12V
Keystone Thermonics
12V 5V
RL2010-54.1K-138-D1
or similar
Yate Loon
YD80SM-12
or similar fan
Yate Loon
R1
T1
47k
R1
100k
MIC502
47k
YD80SM-12
or similar fan
100k
T1
MIC502
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
VT1
CF
VDD
OUT
RBASE
180Ω
VT1
CF
VDD
OUT
R3 R2
56k 33k
RBASE
280Ω
Q1
R3 R2
56k 33k
Q1
VSLP OTF
GND VT2
VSLP OTF
GND VT2
R4
56k
R4
56k
Overtemperature
Fault Output
CF
0.1µF
Overtemperature
Fault Output
CF
0.1µF
4.7k
120k 100k
NLX FanC
Signal Input
NLX FanC
Signal Input
Figure 7. Typical 5V V Application Circuit
DD
Figure 8. Typical 12V V Application Circuit
DD
May 1999
173
MIC502
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