MIC706RMTR [MICREL]

Power Supply Management Circuit, Fixed, 2 Channel, PDSO8, PLASTIC, SOIC-8;


型号：	MIC706RMTR
厂家：	MICREL SEMICONDUCTOR
描述：	Power Supply Management Circuit, Fixed, 2 Channel, PDSO8, PLASTIC, SOIC-8 监控
文件：	总7页 (文件大小：178K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MIC705/06/07/08

Micrel, Inc.

MIC705/706/707/708

µP Supervisory Circuit

General Description

Features

TheMIC705, MIC706, MIC707, andMIC708areinexpensive

mircoprocessor supervisory circuit that monitors power sup-

plies in microprocessor based systems. The circuit functions

include a watchdog timer, microprocessor reset, backup

battery switchover, power failure warning and a debounced

manual reset input.

• Debounced manual reset input is TTL/CMOS

Compatible

• Watchdog timer, 1.6s (MIC705/706)

• 4.65V or 4.40V Precision Voltage Monitor

• Early power fail warning or low battery detect

Applications

• Automotive systems

• Intelligent systems

• Critical microprocessor power monitoring

• Battery powered computers

• Computers

The MIC705 and MIC706 offer a watchdog timer function

while the MIC707 and MIC708 have an active high reset

output in addition to the active low reset output.

Supplyvoltagemonitorlevelsof4.65Vand4.4Vareavailable.

TheMIC705andMIC707haveanominalresetthresholdlevel

of 4.65V while the MIC706 and MIC708 have a 4.4V nominal

threshold level. When the supply voltage drops below the

respective reset threshold level, /RESET is asserted.

• Controllers

Ordering Information

Part Number

Pb-Free

Temperature Range

Package

Standard

MIC70_N

MIC70_M

MIC70_NY

MIC70_MY

–40ºC to +85ºC

8-Pin PDIP

8-Pin SOIC

Typical Application

+5V (Regulated)

Manual

Reset

RESET

MIC705

MIC706

µP

DC Voltage

(Unregulated)

WDI

I/O Line

WDO

PFO

NMI

PFI

Interrupt

Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

January 2006

MIC705/06/07/08

Micrel, Inc.

Pin Conﬁguration

WDO

RESET

WDI

GND

PFI

MIC705

MIC706

PPFO

RESET

MIC707

MIC708

GND

PFI

PPFO

8-Pin PDIP Package

8-Pin SOIC Package

Pin Description

Pin Number

Pin Name

Pin Function

MIC705/06

MIC707/08

/MR

Manual Reset Input forces /RESET to assert when pulled below 0.8V. An

internal pull-up current of 250µA on this input forces it high when left ﬂoating.

this input can also be driven from TTL or CMOS logic.

VCC

GND

PFI

Primary supply input, +5V

IC ground pin, 0V reference

Power Fail Input. Internally connected to the power fail comparator which

is referenced to 1.25V. The Power Fail Output (/PFO) remains high if PFI

is above 1.25V. PFI should be connected to GND or V_OUTif the power fail

comparator is not used.

/PFO

WDI

Power Fail Output. The power fail comparator is independent of all other

function on this device.

N/A

Watch Dog Input. The WDI input monitors microprcessor activity, an internal

watchdog timer resets itself with each transition on the watchdog input. If the

WDIpin is held high or low for longer than the watchog timeout period, /WDO

is forced to active low. the watchdog function can be diabled by ﬂoating the

WDI pin.

N/A

N/C

Not Internally Connected

/RESET

/RESET is asserted if either V_CCgoes below the reset threshold voltage or

by low signal on the manual reset input (/MR). /RESET remains asserted for

one reset timeout period (200ms) after V_CCexceeds the reset threshold volt-

age or after the manual reset pin transition from low to high. The watchdog

timer will not assert /RESET unless /WDO is connected to /MR

N/A

/WDO

Output for the Watchdog Timer. The watchdog timer resets itself with each

transition o the watchdog input. If the WDI pin is held high or low for longer

than the watchdog timeout period, /WDO is forced low. /WDO will also be

forced low id V_CCis below the reset threshold voltageand will remain low

until V_CCreturns to a valid level.

N/A

RESET

RESET is the compliment of /RESET and is asserted if either V_CCgoes be-

low the reset threshold voltage or by a low signal on the manual reset input

(/MR). RESET is suitable for microprocessor systems that use active high

reset.

MIC705/06/07/08

January 2006

MIC705/06/07/08

Micrel, Inc.

Absolute Maximum Ratings⁽¹⁾

Operating Ratings⁽²⁾

Terminal Voltage

Operating Temperature Range

MIC70_N ................................................ –40°C to +85°C

MIC70_M................................................ –40°C to +85°C

..........................................................–0.3V to +6.0V

All other inputs.............................–0.3V to (V

+ 0.3V)

OUT

Power Dissipation (PDIP)........................................475mW

Power Dissipation (SOP).........................................400mW

Input Current

, Gnd ................................................................ 25mA

Output Current (all outputs)........................................ 20mA

Lead Temperature (soldering, 10 sec.)...................... 300°C

Storage Temperature................................ –65°C to +150°C

Electrical Characteristics⁽³⁾

V_CC= 4.75V to 5.5V for MIC705/07; V_CC= 4.5V to 5.5V for MIC706/08; T_A= Operating Temperature Range, bold values indicate

–40°C ≤ T_A≤ +85°C; unless noted

Parameter

Conditions

MIC70_

Min.

Typ.

Max

5.5

Units

Operating Voltage Range, V_CC

Supply Current

1.4

MIC70_

µA

Reset Voltage Threshold

MIC705, MIC707

MIC706, MIC708

4.50

4.25

4.65

4.4

4.75

4.5

Reset Threshold Hysteresis

Reset Pulse Width, t_RS

/RESET Output Voltage

140

200

280

I_Source= 80µA

I_Sink= 3.2mA

MIC70_C, I_Sink= 50µA, V_CC= 1.4V

V_CC- 1.5V

0.4

0.3

RESET Output Voltage

I_Source= 80µA

I_Sink= 3.2mA

V_CC- 1.5V

0.4

Watchdog Timeout Period, t_WD

WDI Minimum Input Pulse, t_WP

WDI Threshold Voltage

1.0

1.6

2.25

sec

V_IL= 0.4V, V_IH= 80% of V_CC

V_IH, V_CC= 5V

V_IL, V_CC= 5V

3.5

0.8

WDI Input Current

WDI = 0V

WDI = V_CC

-150

-50

µA

150

WDO Output Voltage

I_Source= 800µA

I_Sink= 1.2mA

V_CC- 1.5V

0.4

/MR Pull-Up Current

/MR Pulse Width, t_MR

/MR Input Threshold

/MR = 0V

100

150

250

600

µA

V_IL

V_IH

0.8

2.0

/MR to Reset Output Delay, t_MD

PFI Input Threshold

250

1.3

V_CC= 5V

1.2

-25

1.25

0.01

PFI Input Current

+25

0.4

/PFO Output Voltage

I_Sink= 3.2mA

V_CC= 5V, I_Source= 800µA

V_CC- 1.5V

Note 1. Exceeding the absolute maximum rating may damage the device.

Note 2. The device is not guaranteed to function outside its operating rating.

Note 3. Speciﬁcation for packaged product only.

January 2006

MIC705/06/07/08

Micrel, Inc.

Timing Diagram

Timing Diagram for Reset

MIC705/06/07/08

January 2006

MIC705/06/07/08

Micrel, Inc.

Block Diagrams

* 4.4V for MIC706

MIC705/MIC706 Block diagram

* 4.4V for MIC708

MIC707/MIC708 Block diagram

January 2006

MIC705/06/07/08

Micrel, Inc.

Applications Information

Power Fail Warning

Battery Switchover Section

An additional comparator which is independent of the other

functions on the MIC691/693 is provided for early warning

of power failure. An external voltage divider can be used to

compare unregulated DC to an internal 1.25V reference. The

voltage divider ratio on the input of the power-fail comparator

(PFI) can be chosen so as to trip the power fail comparator a

The MIC691/693 monitors the supply voltage applied to the

pin.WheneverV fallsbelowtheresetthresholdvoltage

andV

,thedeviceentersbattery-backupmode.Whenthis

BATT

happens, the auxiliary supply on V

is routed through a

BATT

low impedance PMOS switch to the VOUT pin. The V

OUT

is capable of sourcing up to 25mAwhen in the backup mode.

is routed to V through a large PMOS switch during

few milliseconds before V falls below the maximum reset

OUT

threshold voltage. The output of the power-fail comparator

(/PFO) can be used to interrupt the microprocessor when

used in this mode and execute shut-down procedures prior

to power loss. Hysteresis can be added to this comparator

with external resistors, as is commonly done with any com-

parator. When VCC < VBATT - 1.2V (typ.), the power-fail

comparator is turned off and /PFO is pulled low in order to

conserve power.

normal operation (V > V

currents of up to 250mA. V

RAM. The BATT ON Pin can be used to indicate the status

of battery backup mode or as the base drive for an external

) and can source continuous

can be used to drive CMOS

BATT

OUT

pass transistor when V

has to source more than 25mA

OUT

in battery-backup mode. V is connected to V

and the

OUT

substrate whenever V

exceeds the reset threshold. If

is connected to a voltage source that is greater than

BATT

0.6V above V , the parasitic diode of the V

switch will

Unregulated DC

BATT

conduct from the V

to the substrate.

BATT

Microprocessor Reset

PFI

The /RESET pin is asserted whenever V falls below the

reset threshold voltage. The reset pin remains asserted for a

period of 200ms after VCC has risen above the reset thresh-

old voltage. The reset timeout period can also be selected

by the end user, see Table 1. The reset function ensures the

microprocessor is properly reset and powers up into a known

condition after a power failure. /RESET will remain valid with

VCC as low as 1.4V and when auxiliary power is connected

to VBATT (VBATT > 2.0V), the reset pin will remain valid with

VCC from 0V to 5.5V.

PFO

1.25V

Power Fail Comparator

Watchdog Timer

The microprocessor can be monitored by connecting the

WDI pin (watchdog input) to a bus line or an I/O line. If a

transition doesn't occur on the WDI pin with in the watchdog

timeout (Table 1.), the microprocessor is reset. /RESET will

remain asserted for 200ms when this occurs. A minimum

pulse of 100ns or any transition low-to-high or high-to-low

on the WDI pin will reset the watchdog timer. The output of

the watchdog timer (WDO) will remain high, if WDI sees a

valid transition within the watchdog period or if VCC falls

below the reset threshold as the watchdog timer is disabled

when this happens.

Chip Enable Gating

The MIC691/693 also include memory protection circuitry

which inhibits the writing of memory during a power fail con-

dition. During normal operation, chip enable transitions are

gated througha series transmission gate from /CE IN to /CE

OUT. The typical propagation delay through the chip enable

gating circuitry is 2ns. /CE OUT follows /CE IN unless V

dropsbelowtheresetthresholdvoltage,atwhichtime/CEOUT

will remain high until V returns to a valid level. EEPROMs

can be write protected in a similar manner by connecting the

/CE OUT pin to the store or write input.

MIC705/06/07/08

January 2006

MIC705/06/07/08

Micrel, Inc.

Package Information

0.400

0.370

0.260

0.240

0.310

0.290

0.150

0.120

0.035

0.015

0.150

0.125

0.110

0.090

0.370

0.300

0.023

0.015

8-Pin PDIP (N)

8-Pin SOIC (M)

MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA

TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com

This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.

Micrel reserves the right to change circuitry and speciﬁcations at any time without notiﬁcation to the customer.

Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can

reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into

the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signiﬁcant injury to the user. A Purchaser's

use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify

Micrel for any damages resulting from such use or sale.

January 2006

MIC705/06/07/08

MIC706RMTR [MICREL]

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