MICRF620TR_技术文档

MICRF620

434MHz ISM Band Transceiver Module

General Description

The MICRF620 is a self-contained frequency shift keying

(FSK) transceiver module, intended for use in half-duplex,

bidirectional RF links. The multi-channeled FSK

transceiver module is intended for UHF radio equipment in

compliance with the European Telecommunication

Standard Institute (ETSI) specification, EN300 220.

RadioWire^®Module

Features

• “Drop in” RF solution

• Small size: 11.5x14.1mm

• RF tested

• Low Power

• Surface Mountable

The transmitter consists of a fully programmable PLL

frequency synthesizer and power amplifier. The frequency

synthesizer consists of a voltage-controlled oscillator

(VCO), a crystal oscillator, dual modulus prescaler,

programmable frequency dividers, and a phase-detector.

The output power of the power amplifier can be

programmed to seven levels. A lock-detect circuit detects

when the PLL is in lock.

• Tape & Reel

• Digital Bit Synchronizer

• Received Signal Strength Indicator (RSSI)

• RX and TX power management

• Power down function

• Register read back function

In receive mode, the PLL synthesizer generates the local

oscillator (LO) signal. The N, M, and A values that give the

LO frequency are stored in the N0, M0, and A0 registers.

The receiver is a zero intermediate frequency (IF) type that

makes channel filtering possible with low-power, integrated

low-pass filters. The receiver consists of a low noise

amplifier (LNA) that drives a quadrature mix pair. The

mixer outputs feed two identical signal channels in phase

quadrature. Each channel includes a pre-amplifier, a third

order Sallen-Key RC low-pass filter that protects the

following switched-capacitor filter from strong adjacent

channel signals, and a limiter. The main channel filter is a

switched-capacitor implementation of a six-pole elliptic low

pass filter. The cut-off frequency of the Sallen-Key RC filter

can be programmed to four different frequencies: 100kHz,

150kHz, 230kHz, and 350kHz. The I and Q channel

outputs are demodulated and produce a digital data

output. The demodulator detects the relative phase of the I

and the Q channel signal. If the I channel signal lags

behind the Q channel, the FSK tone frequency is above

the LO frequency (data “1”). If the I channel leads the Q

channel, then the FSK tone is below the LO frequency

(data “0”). The output of the receiver is available on the

DataIXO pin. A receive signal strength indicator (RSSI)

circuit indicates the received signal level. All support

documentation can be found on Micrel’s web site at:

www.micrel.com.

Applications

• Telemetry

• Remote metering

• Wireless controller

• Remote data repeater

• Remote control systems

• Wireless modem

• Wireless security system

RadioWire® is a trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

M9999-120205

December 2005

Micrel, Inc.

MICRF620

Contents

General Description ................................................................................................................................................................1

Features ..................................................................................................................................................................................1

Applications.............................................................................................................................................................................1

Contents..................................................................................................................................................................................2

RadioWire^®RF Module Selection Guide.................................................................................................................................3

Ordering Information ...............................................................................................................................................................3

Block Diagram.........................................................................................................................................................................3

Pin Configuration.....................................................................................................................................................................4

Pin Description........................................................................................................................................................................4

Absolute Maximum Ratings⁽¹⁾.................................................................................................................................................5

Operating Ratings⁽²⁾................................................................................................................................................................5

Electrical Characteristics.........................................................................................................................................................5

Programming...........................................................................................................................................................................7

General ...............................................................................................................................................................................7

Writing to the Control Registers in MICRF620 ...................................................................................................................8

Writing to a Single Register ................................................................................................................................................8

Writing to All Registers .......................................................................................................................................................8

Writing to n Registers Having Incremental Addresses .......................................................................................................9

Reading from the Control Registers in MICRF620.............................................................................................................9

Reading n Registers from MICRF620.................................................................................................................................9

Programming Interface Timing..............................................................................................................................................10

Programming Summary....................................................................................................................................................11

Frequency Synthesizer .........................................................................................................................................................11

Crystal Oscillator (XCO) ...................................................................................................................................................11

VCO ..................................................................................................................................................................................12

Lock Detect.......................................................................................................................................................................12

Modes of Operation...............................................................................................................................................................12

Transceiver Sync/Non-Synchronous Mode......................................................................................................................13

Data Interface ...................................................................................................................................................................13

Receiver ................................................................................................................................................................................13

Front End ..........................................................................................................................................................................14

Sallen-Key Filters..............................................................................................................................................................14

Switched Capacitor Filter..................................................................................................................................................14

RSSI..................................................................................................................................................................................14

FEE...................................................................................................................................................................................15

Bit Synchronizer................................................................................................................................................................15

Transmitter ............................................................................................................................................................................16

Power Amplifier.................................................................................................................................................................16

Frequency Modulation ......................................................................................................................................................16

Using the XCO-tune Bits.......................................................................................................................................................16

Application Circuit Illustration................................................................................................................................................17

Assembling the MICRF620 ...................................................................................................................................................17

Recommended Reflow Temperature Profile ....................................................................................................................17

Shock/Vibration during Reflow..........................................................................................................................................17

Handassembling the MICRF620.......................................................................................................................................17

Layout....................................................................................................................................................................................18

Recommended Land Pattern............................................................................................................................................18

Layout Considerations......................................................................................................................................................18

Package Dimensions ............................................................................................................................................................19

Tape Dimensions ..................................................................................................................................................................19

2

M9999-120205

December 2005

Micrel, Inc.

MICRF620

RadioWire^®RF Module Selection Guide

Frequency

Range

Supply

Voltage

Modulation

Type

Device

Data Rate

<20 kbps

Receive

13.5 mA

12.0 mA

8 mA

Transmit

28 mA

26 mA

23 mA

42 mA

50 mA

Package

MICRF600

MICRF610

MICRF620

RFB433B

RFB868B

RFB915B

902-928 MHz

868-870 MHz

410-450 MHz

430-440 MHz

868-870 MHz

902-928 MHz

2.0-2.5 v

2.5-3.4 V

FSK

11.5x14.1 mm

1”x1”

<15 kbps

<20 kbps

19.2 kbaud

10 mA

1”x1”

10 mA

1”x1”

Ordering Information

Part Number

MICRF620 TR

Junction Temp. Range⁽¹⁾

Package

–20° to +75°C

11.5 x 14.1mm

Block Diagram

SCLK

IO

Main

Sallen-key

filter

CS

Main

Sallen-key

filter

DataIXO

ANT

DataClk

RSSI

LO-Buffer

DIV 2

RSSI

LDout

Frequency

Synthesiser

VCO

XCO

Bias

MICRF620

3

M9999-120205

December 2005

Micrel, Inc.

MICRF620

Pin Configuration

MICRF620 TR

11.5 x 14.1 mm

(Top view)

Pin Description

Pin Number

Pin Name

NC

Type

Pin Function

Not connected

1

2

NC

3

CS

I

Chip select, three wire programming interface

4

SClk

IO

Clock, three wire programming interface

5

I/O

O

Data, three wire programming interface

6

DataIXO

DataClk

LD

Data receive/transmit, bi-directional

7

Data clock receive/transmit

Lock detect

8

O

9

RSSI

GND

ANT

O

Receive signal strength indicator

Ground

10

11

12

13

14

15

16

Ground

I/O

RF In/Out

GND

VDD

GND

Ground

VDD (2.0-2.5V)

Ground

4

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December 2005

Micrel, Inc.

MICRF620

Absolute Maximum Ratings⁽¹⁾

Operating Ratings⁽²⁾

Supply Voltage (V_DD)...................................................+2.8V

Voltage on any pin (GND = 0V). .....................-0.3V to 2.8V

Lead Temperature (soldering, 5 sec.)......................+225°C

Storage Temperature (T_s) ............................-30°C to +85°C

ESD Rating⁽³⁾..................................................................2kV

Supply voltage (V_IN) ..................................+2.0V to +2.5V

RF Frequencies.................................410MHz to 450MHz

Data Rate (NRZ) ................................................ <20 kbps

Ambient Temperature (T_A) .......................–20°C to +75°C

Electrical Characteristics

f_RF= 434MHz, Data rate = 20kbps, V_DD= 2.5V; T_A= 25°C, bold values indicate –20°C< T_A< +75°C, unless noted.

Parameter

Condition

Min

2.0

Typ

Max

2.5

Units

V

Power Supply

Power Down Current

Standby Current

VCO and PLL Section

0.3

µA

280

µA

Tunable with on-chip cap bank

Tuning range

16

MHz

ppm

µs

Crystal Oscillator Frequency

-30

-10

+40

+10

Crystal Initial Tolerance

Crystal Temperature Tolerance

Rx 433.4MHz – Rx 434MHz

300

200

Rx – Tx, same frequency, measured @

frequency offset < 10kHz

µs

Switch Time

Tx – Rx, same frequency, time to good

data

350

Standby – Rx,

Standby – Tx

XCO_tune=13

1.1

750

ms

µs

Crystal Oscillator Start-Up Time

Transmit Section

10

-8

dBm

dB

R_LOAD= 50Ω, Pa2_0: 111

R_LOAD= 50Ω, Pa2_0: 001

Over temperature range

Over power supply range

R_LOAD= 50Ω, PA2_0: 111

R_LOAD= 50Ω, PA2_0: 001

Output Power

3

Output Power Tolerance

Tx Current Consumption

3

dB

23

10

2.5

mA

Tx Current Consumption Variation

Binary FSK Frequency Separation ⁽⁵⁾

Data Rate

mA

R

_LOAD= 50Ω, PA2_0: 111

Limited by receiver BW

NRZ

20

0

400

20

kHz

kbps

19.2kbps, β = 9 (±85kHz), -36dBm

Occupied bandwidth

kHz

dBm

(RBW=10kHz)

Harmonics 434

-36

-54

Spurious Emission in Restricted

bands < 1GHz

ETSI EN300 220

Spurious Emission < 1GHz

Spurious Emission > 1GHz

-36

-30

dBm

5

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December 2005

Micrel, Inc.

MICRF620

Parameter

Condition

Min

Typ

Max

Units

Receive Section

All functions on

12

10.3

9.6

3

mA

Rx Current Consumption

LNA bypass

Switch cap filter bypass with LNA

Over temperature

mA

Rx Current Consumption Variation

mA

-110

-109

-108

-107

-105

+10

3

dBm

dB

2.4 kbps, β = 16, SC=50 kHz

4.8 kbps, β = 16, SC=50 kHz

4.8 kbps, β = 4, SC=31 kHz

19.2 kbps, β =8, SC=200 kHz

19.2 kbps, β =2, SC=67 kHz

19.2 kbps, β = 8

Receiver Sensitivity

Receiver Maximum Input Power

Receiver Sensitivity Tolerance

Over temperature

Over power supply range

1

dB

Receiver Bandwidth

50

350

kHz

dB

Co-Channel Rejection

-8

TBD

61

19.2 kbps, β = 6, SC=133 kHz

200 kHz spacing

Adjacent Channel Rejection

500 kHz spacing

1 MHz spacing

Offset ±1MHz

dB

Desired signal:

19.2 kbps, β =6,

3dB above sens,

SC=133 kHz

Offset ±2MHz

Offset ±5MHz

Offset ±10MHz

Offset ±30MHz

58

Blocking

46

dB

62

dB

75

dB

1dB Compression

Input IP3

-35

-25

TBD

dB

2 tones with 1MHz separation

ETSI 300-220

dBm

Ω

Input IP2

LO Leakage

-90

-57

-47

Spurious Emission < 1GHz

Spurious Emission > 1GHz

Input Impedance

RSSI Dynamic Range

37+j18

50

dB

Pin = -100 dBm

Pin = -60 dBm

1.1

V

RSSI Output Range

2.0

V

Digital Inputs/Outputs

Logic Input High

0.7V_DD

0

V_DD

0.3V_DD

10

V

Logic Input Low

Clock/Data Frequency⁽⁴⁾

Clock/Data Duty Cycle⁽⁴⁾

MHz

%

45

55

Notes:

1. Exceeding the absolute maximum rating may damage the device.

2. The device is not guaranteed to function outside its operating rating.

3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF.

4. Guaranteed by design.

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December 2005

Micrel, Inc.

MICRF620

Programming

General

The MICRF620 functions are enabled through a number of

programming bits. The programming bits are organized as

a set of addressable control registers, each register

holding 8 bits.

shown in the table.

The control registers in MICRF620 are accessed through a

3-wire interface; clock, data and chip select. These lines

are referred to as SCLK, IO, and CS, respectively. This 3-

wire interface is dedicated to control register access and is

referred to as the control interface. Received data (via RF)

and data to transmit (via RF) are handled by the DataIXO

and DataClk (if enabled) lines; this is referred to as the

data interface.

There are 23 control registers in total in the MICRF620,

and they have addresses ranging from 0 to 22. The user

can read all the control registers. The user can write to the

first 22 registers (0 to 21); the register 22 is a read-only

register.

All control registers hold 8 bits and all 8 bits must be

written to when accessing a control register, or they will be

read. Some of the registers do not utilize all 8 bits. The

value of an unused bit is “don’t care.”

The SCLK line is applied externally; access to the control

registers are carried out at a rate determined by the user.

The MICRF620 will ignore transitions on the SCLK line if

the CS line is inactive. The MICRF620 can be put on a

bus, sharing clock and data lines with other devices.

The control register with address 0 is referred to as

ControlRegister0, the control register with address 1 is

ControlRegister1 and so on. A summary of the control

registers is given in the table below. In addition to the

unused bits (marked with”-“) there are a number of fixed

bits (marked with “0” or “1”). Always maintain these as

All control registers should be written to after a battery

reset. During operation, it is sufficient to write to one

register only. The MICRF620 will automatically enter

power down mode after a battery reset.

Address

Data

A6…A0

0000000

0000001

0000010

0000011

0000100

0000101

0000110

D7

LNA_by

‘1’

D6

PA2

‘0’

D5

PA1

‘0’

D4

PA0

D3

D2

Mode1

LD_en

‘0’

D1

Mode0

PF_FC1

‘0’

D0

‘1’

Sync_en

RSSI_en

‘0’

PF_FC0

‘0’

‘SC_by’

‘1’

‘0’

‘PA_by’

VCO_IB2

‘1’

‘0’

VCO_IB1

VCO_IB0

VCO_freq1

VCO_freq0

‘0’

-

‘0’

-

‘0’

‘1’

‘0’

-

BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

‘0’

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4

RefClk_K3

ScClk3

XCOtune3

A0_3

RefClk_K2

ScClk2

XCOtune2

A0_2

RefClk_K1

ScClk1

XCOtune1

A0_1

RefClk_K0

ScClk0

XCOtune0

A0_0

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

‘1’

ScClk5

ScClk4

‘0’

‘1’

A0_5

-

XCOtune4

-

A0_4

-

N0_4

-

N0_11

N0_3

N0_10

N0_2

N0_9

N0_8

N0_7

N0_6

N0_5

-

N0_1

N0_0

-

M0_11

M0_3

M0_10

M0_2

M0_9

M0_8

M0_7

M0_6

M0_5

A1_5

-

M0_4

A1_4

-

M0_1

M0_0

-

A1_3

A1_2

A1_1

A1_0

-

N1_7

-

N1_6

-

N1_11

N1_3

N1_10

N1_2

N1_9

N1_8

N1_5

-

N1_4

-

N1_1

N1_0

M1_11

M1_3

M1_10

M1_2

M1_9

M1_8

M1_7

‘1’

M1_6

‘0’

M1_5

‘1’

M1_4

‘1’

M1_1

M1_0

‘0’

‘1’

‘0’

‘1’

-

FEEC_3

FEE_3

FEEC_2

FEE_2

FEEC_1

FEE_1

FEEC_0

FEE_0

FEE_7

FEE_6

FEE_5

FEE_4

Table 1. Control Registers in MICRF620

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December 2005

Micrel, Inc.

MICRF620

Field

Comments

Writing to the Control Registers in MICRF620

Address:

R/W bit:

Values:

7 bit = A6, A5, …A0 (A6 = msb. A0 = lsb)

“0” for writing

Writing: A number of octets are entered into MICRF620,

followed by a load-signal to activate the new setting.

Making these events is referred to as a “write sequence.” It

is possible to update all, 1, or n control registers in a write

sequence. The address to write to (or the first address to

write to) can be any valid address (0-21). The IO line is

always an input to the MICRF620 (output from user) when

writing.

8 bits = D7, D6, …D0 (D7 = msb, D0 = lsb)

Table 3. “Address” and “R/W bit” together make 1 octet.

In addition, 1 octet with programming bits is entered. Totally, 2

octets are clocked into the MICRF620.

How to write:

•

Bring CS high

What to write:

Use SCLK and IO to clock in the 2 octets

Bring CS low

•

The address of the control register to write to (or if

more than 1 control register should be written to,

the address of the 1^stcontrol register to write to).

CS

•

A bit to enable reading or writing of the control

registers. This bit is called the R/W bit.

SCLK

IO

The values to write into the control register(s).

A6

A5

A0

D7

D6

D2

D1

D0

RW

Field

Comments

Address of register i

RW

Data to write into register i

Internal load pulse made here

Address:

R/W bit:

Values:

A 7-bit field, ranging from 0 to 21. MSB is written first.

A 1-bit field, = “0” for writing

A number of octets (1-22 octets). MSB in every octet is written

first. The first octet is written to the control register with the

specified address (=”Address”). The next octet (if there is one) is

written to the control register with address = “Address + 1” and so

on.

Figure 1. How to write to a single Control Register

In Figure 1, IO is changed at positive edges of SCLK. The

MICRF620 samples the IO line at negative edges. The

value of the R/W bits is always “0” for writing.

Table 2. Writing to the Control Registers

Writing to All Registers

How to write:

After a power-on, all writable registers must be written.

This is described here.

Bring CS active to start a write sequence. The active state

of the CS line is “high.” Use the SCLK/IO serial interface to

clock “Address” and “R/W” bit and “Values” into the

MICRF620. MICRF620 will sample the IO line at negative

edges of SCLK. Make sure to change the state of the IO

line before the negative edge. Refer to figures below.

Writing to all register can be done at any time. To get the

simplest firmware, always write to all registers. The price

to pay for the simplicity is increased write-time, which

leads to increased time for changing the way the

MICRF620 works.

Bring CS inactive to make an internal load-signal and

complete the write-sequence.

What to write

Field

Comments

The two different ways to “program the chip” are:

Address:

R/W bit:

Values:

‘000000’ (address of the first register to write to, which is 0)

•

Write to a number of control registers (0-22) when

the registers have incremental addresses (write to

1, all or n registers)

“0” for writing

1^stOctet: wanted values for ControlRegister0. 2^ndOctet: wanted

values for ControlRegister1 and so on for all of the octets. So the

22^ndoctet: wanted values for ControlRegister21. Refer to the

specific sections of this document for actual values.

•

Write to a number of control registers when the

registers have non-incremental addresses.

Table 4. “Address” and “R/W bit” together make 1 octet.

Writing to a Single Register

In total, 23 octets are clocked into the MICRF620.

Writing to a control register with address “A6. A5, …A0” is

described here. During operation, writing to 1 register is

sufficient to change the way the transceiver works. Typical

example: Change from receive mode to power-down.

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December 2005

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MICRF620

How to write:

Reading from the Control Registers in MICRF620

•

Bring CS high

The “read-sequence” is:

Use SCLK and IO to clock in the 23 octets

Bring CS low

1. Enter address and R/W bit

2. Change direction of IO line

Refer to the figure in the next section, “Writing to n

registers having incremental addresses”.

3. Read out a number of octets and change IO

direction back again.

Writing to n Registers Having Incremental Addresses

It is possible to read all, 1 or n registers. The address to

read from (or the first address to read from) can be any

valid address (0-22). Reading is not destructive, i.e. values

are not changed. The IO line is output from the MICRF620

(input to user) for a part of the read-sequence. Refer to

procedure description below.

In addition to entering all bytes, it is also possible to enter

a set of n bytes, starting from address i = “A6, A5, … A0”.

Typical example: Clock in a new set of frequency dividers

(i.e. change the RF frequency). “Incremental addresses”.

Registers to be written are located in i, i+1, i+2.

A read-sequence is described for reading n registers,

where n is number 1-23.

What to write:

Field

Comments

Address:

7 bit = A6, A5, …A0 (A6 = msb. A0 = lsb) (address of first byte to

write to)

Reading n Registers from MICRF620

R/W bit:

Values:

“0” for writing

n* 8 bits =

CS

D7, D6, …D0 (D7 = msb, D0 = lsb) (written to control reg. with

address ”i”)

SCLK

D7, D6, …D0 (D7 = msb, D0 = lsb) (written to control reg. with

address ”i+1”)

A6

A5

A0

D7

D6

D0

RW

IO

D7, D6, …D0 (D7 = msb, D0 = lsb) (written to control reg. with

address ”i+n-1”)

Address of register i

RWData read from reg. i

Simple time

Table 5. “Address” and “R/W bit” together make 1 octet.

IO Input

IO Output

In addition, n octets with programming bits are entered.

Totally. 1 +n octets are clocked into the MICRF620.

Figure 3. How to read from many Control Registers

How to write:

•

Bring CS high

In Figure 3, 1 register is read. The address is A6, A5, …

A0. A6 = msb. The data read out is D7, D6, …D0. The

value of the R/W bit is always “1” for reading.

Use SCLK and IO to clock in the 1 + n octets

Bring CS low

SCLK and IO together form a serial interface. SCLK is

applied externally for reading as well as for writing.

In Figure 1, IO is changed at positive edges of SCLK. The

MICRF620 samples the IO line at negative edges. The

value of the R/W bits is always “0” for writing.

•

Bring CS active

Enter address to read from (or the first address to

read from) (7 bits) and

CS

•

The R/W bit = 1 to enable reading

SCLK

Make the IO line an input to the user (set pin in

tristate)

A6

A5

A0

D7

D6

D2

D1

D0

RW

IO

•

Read n octets. The first rising edge of SCLK will

set the IO as an output from the MICRF620.

MICRF will change the IO line at positive edges.

The user should read the IO line at the negative

edges.

Address of first

RW Data to write

Data to write

register to write to,

register i

into register i into register i+1

Internal load pulse made here

•

Make the IO line an output from the user again.

Figure 2. How to write to many Control Registers

9

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December 2005

Micrel, Inc.

MICRF620

Programming Interface Timing

Figure 4 and Table 6 show the timing specification for the 3-wire serial programming interface.

Tcsr

Tper

Thigh Tread

Tlow

Tscl

traise

tfall

Twrite

SCLK

CS

A6

A5

A0

D7

D6

D2

D1

D0

RW

IO

Address Register

Data Register

LOAD

Figure 4. Programming Interface Timing

Values

Symbol

Parameter

Units

Min. Typ.

Max.

Tper

Min. period of SCLK (Voltage dividers on IO lines will slow down the

write/read frequency)

50

ns

Thigh

Tlow

tfall

Min. high time of SCLK

20

ns

µs

ns

Min. low time of SCLK

Max. time of falling edge of SCLK

1

trise

Max. time of rising edge of SCLK

Tcsr

Max. time of rising edge of CS to falling edge of SCLK

Min. delay from rising edge of CS to rising edge of SCLK

Min. delay from valid IO to falling edge of SCLK during a write operation

0

5

Tcsf

Twrite

Tread

0

Min. delay from rising edge of SCLK to valid IO during a read operation

(assuming load capacitance of IO is 25pF)

75

Time from power up to first rising edge of CS

3.4

ms

(Assuming Vdd rail rise time of 100 µsec)

Table 6. Timing Specification for the 3-wire Programming Interface

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MICRF620

Frequency Synthesizer

Programming Summary

A6…A0

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

D7

D6

D5

A0_5

-

D4

A0_4

-

D3

D2

D1

D0

•

Use CS, SCLK, and IO to get access to the control

registers in MICRF620.

-

A0_3

A0_2

A0_1

N0_9

N0_1

M0_9

M0_1

A1_1

N1_9

N1_1

M1_9

M1_1

A0_0

N0_8

N0_0

M0_8

M0_0

A1_0

N1_8

N1_0

M1_8

M1_0

-

N0_11

N0_3

M0_11

M0_3

A1_3

N0_10

N0_2

M0_10

M0_2

A1_2

•

SCLK is user-controlled.

N0_7

N0_6

N0_5

-

N0_4

-

Write to the MICRF620 at positive edges

(MICRF620 reads at negative edges).

M0_7

M0_6

M0_5

A1_5

-

M0_4

A1_4

-

N1_11

N1_3

M1_11

M1_3

N1_10

N1_2

M1_10

M1_2

•

Read from the MICRF620 at negative edges

(MICRF620 writes at positive edges)

N1_7

-

N1_6

-

N1_5

-

N1_4

-

After power-on: Write to the complete set of

control registers.

M1_7

M1_6

M1_5

M1_4

The frequency synthesizer consists of a voltage-controlled

oscillator (VCO), crystal oscillator, phase select

prescaler, programmable frequency dividers and a phase-

detector. The length of the N, M, and A registers are 12,

12 and 6 respectively. The N, M, and A values can be

calculated from the formula:

•

Address field is 7 bits long. Enter msb first.

R/W bit is 1 bit long (“1” for read, “0” for write)

Address and R/W bit together make 1 octet

a

All control registers are 8 bits long. Enter/read msb

in every octet first.

f_XCO

M

f_VCO

31×N + A

f_RF× 4

31×N + A

•

Always write 8 bits to/read 8 bits from a control

register. This is the case for registers with less

than 8 used programming bits as well.

f_PhD

=

,

(

)

(

)

1 ≤ A < N

PhD: Phase detector comparison frequency

Writing: Bring CS high, write address and R/W bit

followed by the new values to fill into the

addressed control register(s) and bring CS low for

loading, i.e., activation of the new control register

values.

f

_XCO: Crystal oscillator frequency

f

_VCO: Voltage controlled oscillator frequency

•

Reading: Bring CS high, write address and R/W

bit, set IO as an input, read present contents of the

addressed control register(s), bring CS low and

set IO an output.

f_RF: Input/output RF frequency

There are two sets of each of the divide factors (i.e. A0

and A1). Storing the ‘0’ and the ‘1’ frequency in the 0- and

the 1 registers respectively, does the 2-FSK. The receive

frequency must be stored in the ‘0’ registers.

Crystal Oscillator (XCO)

Adr

D7

D6

D5

D4

D3

D2

D1

D0

0001001

‘0’

‘1’

XCOtune4

XCOtune3

XCOtune2

XCOtune1

XCOtune0

The crystal oscillator is a reference for the RF output

frequency and the LO frequency in the receiver. It is

possible to tune the internal crystal oscillator by switching

in internal capacitance using 5 tune bits XCOtune4 –

XCOtun0. The benefit of tuning the crystal oscillator is to

eliminate the initial tolerance and the tolerance over

temperature and aging. By using the crystal tuning feature

the noise bandwidth of the receiver can be reduced and a

higher sensitivity is achieved.

When XCOtune4 –

XCOtune0 = 0 no internal capacitors are connected to the

crystal pins. When XCOtune4 – XCOtune0 = 1 all of the

internal capacitors are connected to the crystal pins.

Figure 5 shows the tuning range.

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MICRF620

VCO frequency gain, Vdd=2.5V

55.0

480

460

440

420

400

380

45.0

35.0

25.0

15.0

5.0

11

10

01

00

-5.0

-15.0

-25.0

-35.0

-45.0

0

4

8

12 16 20 24 28 32

0

0,4

0,8

1,2

1,6

2

2,4

[XCO_tune value]

V_varactor [V]

Figure 5. XCO Tuning

Figure 6. RF Frequency vs. Varactor Voltage

and VCO Frequency bit (V_DD= 2.5V)

The typical start up time for the crystal oscillator (default

XCO_tune=13) is ~750us. If more capacitance is added

(higher XCO_tune value), then the start-up time will be

longer.

Lock Detect

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000001

‘1’

‘0’

RSSI_en

LD_en

PF_FC1

PF_FC0

To save current in the crystal oscillator start-up period, the

XCO is turned on before any other circuit block. When the

XCO has settled, rest of the circuit will be turned on. No

programming should be made during this period.

A lock detector can be enabled by setting LD_en = 1.

When pin LD is high, it indicates that the PLL is in lock.

When entering TX, the procedure is first to load the TX

word and then turn on the PA stage. During the PA ramp

up time, the LD signal may indicate out of lock. It is first

when the PA stage is fully on that the LD signal will

indicate in “Lock”. During transmission, the Lock Detect

signal will have transitions and the user should therefore,

ignore the Lock detect signal.

The current consumption during the prestart period is

approximately 280µA.

VCO

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000011

‘1’

‘0’

VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0

Modes of Operation

The VCO has no external components. It has three bit to

set the bias current and two bit to set the VCO frequency.

These five bits are set by the RF frequency, as follows:

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

’1’

RF freq.

410MHz

434MHz

450MHz

VCO_IB2 VCO_IB1 VCO_IB0 VCO_freq1 VCO_freq0

Mode1

Mode0

State

Comments

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Power down

Standby

Keeps register configuration

Only crystal oscillator running

Full receive

Receive

Transmit

Full transmit ex PA state

Table 7. VCO Bit Setting

The bias bit will optimize the phase noise, and the

frequency bit will control a capacitor bank in the VCO. The

tuning range the RF frequency versus varactor voltage is

dependent on the VCO frequency setting, and can be

shown in Figure 6.

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MICRF620

Transceiver Sync/Non-Synchronous Mode

A6..A0

0000000

0000110

D7

LNA_by

-

D6

PA2

‘0’

D5

PA1

‘0’

D4

PA0

‘0’

D3

Sync_en

D2

Mode1

D1

Mode0

D0

’1’

BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

RefClk_K3 RefClk_K2 RefClk_K1 RefClk_K0

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4

Sync_en

State

Comments

The data interface is defined in such a way that all user

actions should take place on falling edge and is illustrated

Figures 7 and 8. The two figures illustrate the relationship

between DATACLK and DATAIXO in receive mode and

transmit mode.

Rx: Bit

synchronization off

0

Transparent reception of data

Transparent transmission of

data

0

1

Tx: DataClk pin off

Rx: Bit

synchronization on

Bit-clock is generated by

transceiver

MICRF620 will present data on rising edge and the

“USER” sample data on falling edge in receive mode.

Bit-clock is generated by

transceiver

Tx: DataClk pin on

When Sync_en = 1, it will enable the bit synchronizer in

receive mode. The bit synchronizer clock needs to be

programmed, see chapter Bit synchronizer. The

synchronized clock will be set out on pit DataClk.

DATAIXO

DATACLK

In transmit mode, when Sync_en = 1, the clock signal on

pin DataClk is a programmed bit rate clock. Now the

transceiver controls the actual data rate. The data to be

transmitted will be sampled on rising edge of DataClk. The

micro controller can therefore use the negative edge to

change the data to be transmitted. The clock used for this

purpose, BitRate-clock, is programmed in the same way

as the modulator clock and the bit synchronizer clock:

Figure 7. Data interface in Receive Mode

The User presents data on falling edge and MICRF620 samples

on rising edge in transmit mode.

DATAIXO

DATACLK

f_XCO

Figure 8. Data interface in Transmit Mode

f_{BITRATE_CLK}

=

Refclk_K × 2^{(7-BITRATE_clkS)}

Receiver

where

The receiver is a zero intermediate frequency (IF) type in

order to make channel filtering possible with low-power

integrated low-pass filters. The receiver consists of a low

noise amplifier (LNA) that drives a quadrature mixer pair.

The mixer outputs feed two identical signal channels in

phase quadrature. Each channel includes a pre-amplifier,

a third order Sallen-Key RC lowpass filter from strong

adjacent channel signals and finally a limiter. The main

channel filter is a switched-capacitor implementation of a

six-pole elliptic lowpass filter. The elliptic filter minimizes

the total capacitance required for a given selectivity and

dynamic range. The cut-off frequency of the Sallen-Key

RC filter can be programmed to four different frequencies:

100kHz, 150kHz, 230kHz and 340kHz. The demodulator

demodulates the I and Q channel outputs and produces a

digital data output. If detects the relative phase of the I and

Q channel signal. If the I channel signal lags the Q

channel, the FSK tone frequency lies above the LO

frequency (data ‘1’). If the I channel leads the Q channel,

the FSK tone lies below the LO frequency (data ‘0’). The

output of the receiver is available on the DataIXO pin. A

RSSI circuit (receive signal strength indicator) indicates

the received signal level.

f

_{BITRATE_CLK}: The clock frequency used to control the

bit rate, should be equal to the bit rate (bit rate of 20

kbit/sec requires a clock frequency of 20kHz)

f_XCO: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1 and 63

BitRate_clkS: Bit rate setting, values between 0 and

6

Data Interface

The MICRF620 interface can be divided in to two separate

interfaces,

interface”. The “programming interface” has a three wire

serial programmable interface and is described in chapter

Programming.

a “programming interface” and a “Data

The “data interface” can be programmed to sync-/non-

synchronous mode. In synchronous mode the MICRF620

is defined as “Master” and provides a data clock that

allows users to utilize low cost micro controller reference

frequency.

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MICRF620

Front End

f_CUT: Filter cutoff frequency

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

f_XCO: Crystal oscillator frequency

0000000 LNA_by PA2

PA1

PA0

Sync_en Mode1 Mode0

’1’

ScCLK: Switched capacitor filter clock, bits ScClk5-0

1^storder RC lowpass filters are connected to the output of

the SC filter to filter the clock frequency.

A low noise amplifier in RF receivers is used to boost the

incoming signal prior to the frequency conversion process.

This is important in order to prevent mixer noise from

dominating the overall front-end noise performance. The

LNA is a two-stage amplifier and has a nominal gain of

approximately 23dB at 434MHz. The front end has a gain

of about 33dB to 35dB. The gain varies by 1-1.5dB over a

2.0V to 2.5V variation in power supply.

The lowest cutoff frequency in the pre- and the main

channel filter must be set so that the received signal is

passed with no attenuation, that is frequency deviation

plus modulation. If there are any frequency offset between

the transmitter and the receiver, this must also be taken

into consideration. A formula for the receiver bandwidth

can be summarized as follows:

The LNA can be bypassed by setting bit LNA_by to ‘1’.

This can be useful for very strong input signal levels. The

front-end gain with the LNA bypassed is about 9-10dB.

The mixers have a gain of about 10dB at 434MHz.

f

BW = + fOFFSET + fDEV + Baudrate / 2

where

Sallen-Key Filters

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

f_BW: Needed receiver bandwidth, fcut above should

not be smaller than f_BW(Hz)

0000001

‘1’

‘0’

RSSI_en

LD_en

PF_FC1

PF_FC0

Each channel includes a pre-amplifier and a prefilter,

which is a three-pole Sallen-Key lowpass filter. It protects

the following switched-capacitor filter from strong adjacent

channel signals, and it also works as an anti-aliasing filter.

The preamplifier has a gain of 22.23dB. The maximum

output voltage swing is about 1.4Vpp for a 2.25V power

supply. In addition, the IF amplifier also performs offset

cancellation. Gain varies by less than 0.5dB over a 2.0 –

2.5V variation in power supply. The third order Sallen-Key

lowpass filter is programmable to four different cut-off

frequencies according to the table below:

f_offset: Total frequency offset between receiver and

transmitter (Hz)

f_DEV: Single-sided frequency deviation

Baudrate: The baud rate given is bit/sec

RSSI

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000001

‘1’

‘0’

RSSI_en

LD_en

PF_FC1

PF_FC0

RSSI

PF_FC1

PF_FC0

Cut-off Freq. (kHz)

2,5

2

0

1

0

1

0

1

100

150

230

340

1,5

1

Switched Capacitor Filter

0,5

0

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0001000

‘1’

ScClk5

ScClk4

ScClk3

ScClk2

ScClk1

ScClk0

-110

-100

-90

-80

-70

-60

-50

-40

Pin (dBm)

The main channel filter is

a

switched-capacitor

implementation of a six-pole elliptic low pass filter. The

elliptic filter minimized the total capacitance required for a

given selectivity and dynamic range. The cut-off frequency

of the switched-capacitor filter is adjustable by changing

the clock frequency.

Figure 9. RSSI Voltage

A Typical plot of the RSSI voltage as function of input

power is shown in Figure 9. The RSSI has a dynamic

range of about 50dB from about -110dBm to -60dBm input

power.

The clock frequency is designed to be 20 times the cut-off

frequency. The clock frequency is derived from the

reference crystal oscillator. A programmable 6-bit divider

divides the frequency of the crystal oscillator. The cut-off

frequency of the filter is given by:

The RSSI can be used as a signal presence indicator.

When a RF signal is received, the RSSI output increases.

This could be used to wake up circuitry that is normally in

a sleep mode configuration to conserve battery life.

f

XCO

f

CUT

=

40 ⋅ ScClk

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MICRF620

Another application for which the RSSI could be used is to

determine if transmit power can be reduced in a system. If

the RSSI detects a strong signal, it could tell the

transmitter to reduce the transmit power to reduce current

consumption.

The result of the measurement is the FEE value, this can

be read from register with address 0010110b. Negative

values are stored as a binary no between 0000000 and

1111111. To calculate the negative value, a two’s

complement of this value must be performed. Only FEE

modes where DN-pulses are counted (10 and 11) will give

a negative value.

FEE

A6..A0

0010101

0010110

D7

-

D6

-

D5

-

D4

-

D3

D2

D1

D0

FEEC_3

FEE_3

FEEC_2

FEE_2

FEEC_1

FEE_1

FEEC_0

FEE_0

When the FEE value has been read, the frequency offset

can be calculated as follows:

FEE_7

FEE_6

FEE_5

FEE_4

The Frequency Error Estimator (FEE) uses information

from the demodulator to calculate the frequency offset

between the receive frequency and the transmitter

frequency. The output of the FEE can be used to tune the

XCO frequency, both for production calibration and for

compensation for crystal temperature drift and aging.

Mode UP:

Mode DN:

Foffset = R/(2P)x(FEE-∆Fp)

Foffset = R/(2P)x(FEE+∆Fp)

Mode UP+DN: Foffset = R/(4P)x(FEE)

where FEE is the value stored in the FEE register, (Fp is

the single sided frequency deviation, P is the number. of

symbols/data bit counted and R is the symbol/data rate. A

positive Foffset means that the received signal has a

higher frequency than the receiver frequency. To

compensate for this, the receivers XCO frequency should

be increased.

The input to the FEE circuit are the up and down pulses

from the demodulator. Every time a ‘1’ is updated, an UP-

pulse is coming out of the demodulator and the same with

the DN-pulse every time the ‘0’ is updated. The expected

no. of pulses for every received symbol is 2 times the

modulation index (∆).

It is recommended to use Mode UP+DN for two reasons,

you do not need to know the actual frequency deviation

and this mode gives the best accuracy.

The FEE can operate in three different modes; counting

only UP-pulses, only DN-pulses or counting UP+DN

pulses. The no. of received symbols to be counted is either

8, 16, 32 or 64. This is set by the FEEC_0…FEEC_3

control bit, as follows:

FEEC_1 FEEC_0 FEE Mode

0

1

0

1

0

1

Off

Counting UP pulses

Counting DN pulses

Counting UP and DN pulses. UP

increments the counter, DN

decrements it.

FEEC_3 FEEC_2 No. of symbols used for the

measurement

0

1

0

1

0

1

8

16

32

65

Table 8. FEEC Control Bit

Bit Synchronizer

A6..A0

D7

D6

D5

D4

D3

D2

D1

D0

0000110

-

‘0’

BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2

0000111 BitRate_clkS1 BitRate_clkS0 RefClk_K5 RefClk_K4

RefClk_K3

RefClk_K2

RefClk_K1

RefClk_K0

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MICRF620

A bit synchronizer can be enabled in receive mode by

selecting the synchronous mode (Sync_en=1). The

DataClk pin will output a clock with twice the frequency of

the bit rate (a bit rate of 20 kbit/sec gives a DataClk of 20

kHz). A received symbol/bit on DataIXO will be output on

rising edge of DataClk. The micro controller should

therefore sample the symbol/bit on falling edge of DataClk.

The divider values stored in the M0-, N0-, and A0-

registers will be used when transmitting a ‘0’ and the M1-,

N1-, and A1-registers will be used to transmit a ‘1’. The

difference between the two carrier frequencies

corresponds to the double sided frequency deviation. The

data to be transmitted shall be applied to pin DataIXO (see

chapter Transceiver sync-/non-synchronous mode on how

to use the pin DataClk). The DataIXO pin is set as input in

transmit mode and output in receive mode.

The bit synchronizer uses a clock that needs to be

programmed according to the bit rate. The clock frequency

should be 16 times the actual bit rate (a bit rate of 20

kbit/sec needs a bit synchronizer clock with frequency of

320 kHz). The clock frequency is set by the following

formula:

Using the XCO-tune Bits

The module has a built-in mechanism for tuning the

frequency of the crystal oscillator and is often used in

combination with the Frequency Error Estimator (FEE).

The XCO tuning is designed to eliminate or reduce initial

frequency tolerance of the crystal and/or the frequency

stability over temperature.

f

XCO

f

BITSYNC_CLK

=

Refclk_K × 2^{(7-BITSYNC_clkS)}

where

A procedure for using the XCO tuning feature in

combination with the FEE is given below. The MICRF620

measures the frequency offset between the receivers LO

frequency and the frequency of the transmitter. The

receiver XCO frequency can be tuned until the receiver

and transmitter frequencies are equal.

f

_{BITSYNC_CLK}: The bit synchronizer clock frequency

(16 times higher than the bit rate)

f_XCO: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1 and 63

BitSync_clkS: Bit synchronizer setting, values

between 0 and 7

A procedure like this can be called during production

(storing the calibrated XCO_tune value), at regular

intervals or implemented in the communication protocol

when the frequency has changed. The MICRF620

development system can test this feature.

Refclk_K is also used to derive the modulator clock and

the bit rate clock.

At the beginning of a received data package, the bit

synchronizer clock frequency is not synchronized to the bit

rate. When these two are maximum offset to each other, it

takes 22 bit/symbols before synchronization is achieved.

Example: In FEE, count up+down pulses, counting 8 bits:

A perfect case ==> FEE = 0

If FEE > 0: LO is too low, increase LO by decreasing

XCO_tune value

Transmitter

v.v. for FEE < 0

Power Amplifier

A6..A0

0000000

0000001

D7

LNA_by

‘1’

D6

PA2

‘0’

D5

PA1

‘0’

D4

PA0

‘0’

D3

D2

D1

D0

’1’

FEE field holds a number in the range -128, … , 127.

However, it keeps counting above/below the range, which

is:

Sync_en

RSSI_en

Mode1

LD_en

Mode0

PF_FC1

PF_FC0

The maximum output power is approximately 10dBm for a

50Ω load. The output power is programmable in seven

steps, with approximately 3dB between each step. Bits

PA2 – PA0, control this. PA2 – PA0 = 1 give the maximum

output power.

If FEE = -128 and still counting dwn-pulses:

1) =>-129 = +127

2) 126

3) 125

The power amplifier can be turned off by setting PA2 –

PA0 = 0.

To avoid this situation, always make sure max count is

between limits.

For all other combinations the PA is on and has maximum

power when PA2 – PA0 = 1.

Frequency Modulation

FSK modulation is applied by switching between two sets

of dividers (M,N,A). The formula for calculating the M, N

and A values is given in chapter Frequency synthesizer.

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MICRF620

Application Circuit Illustration

Assembling the MICRF620

Recommended Reflow Temperature Profile

When the MICRF620 module is being automatically

assembled to a PCB, care must be taken not to expose

the module for temperature above the maximum specified.

Figure 12 shows the recommended reflow temperature

profile.

Figure 10. Circuit illustration of MICRF620, LDO and MCU

Figure 10. shows a typical set-up with the MICRF620, a

Low-Drop-Out voltage regulator (LDO) and a micro-

controller (MCU). When the MICRF620 and the MCU runs

on the same power supply (min 2.0, max. 2.5V), the IO

can be connected directly to the MCU. If the MCU needs a

higher VDD than the max. specified VDD of the MICRF620

(2.5V), voltage dividers need to be added on the IO lines

not to override the max. input voltage.

Figure 12. Recommended Reflow Temperature Reflow

Shock/Vibration during Reflow

Figure 11 shows a recommended voltage divider circuit for

a MCU running at 3.0V and the MICRF620 at 2.5V.

The module has several components inside which are

assembled in a reflow process. These components may

reflow again when the module is assembled onto a PCB. It

is therefore important that the module is not subjected to

any mechanical shock or vibration during this process.

MICRF6xx

MCU

3k3

15k

CS

SCLK

IO

CS

18k

Handassembling the MICRF620

SCLK

It is recommended to use solder paste also during hand

assembling of the module. Because of the module ground

pad on the bottom side, the module will be assembled

most efficient if the heat is being subjected to the bottom

side of the PCB. The heat will be transferred trough the

PCB due the ground vias under the module (see Layout

Considerations). In addition, it is recommended to use a

solder tip on the signal and power pads, to make sure the

solder points are properly melted.

IO

DATAIXO

DATACLK

LD

DATAIXO

DATACLK

LD

RSSI

Figure 11. How to connect MICRF620 (2.5V) and MCU (3.0V)

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MICRF620

Layout

Layout Considerations

Except for the antenna input/output signal, only digital and

low frequency signals need to interface with the module.

There is therefore no need of years of RF expertise to do a

successful layout, as long as the following few points are

being followed:

Recommended Land Pattern

Figure 12 shows a recommended land pattern that

facilitates both automatic and hand assembling.

•

Proper ground is needed. If the PCB is 2-layer, the

bottom layer should be kept only for ground. Avoid

signal traces that split the ground plane. For a 4-

layer PCB, it is recommended to keep the second

layer only for ground.

•

A ground via should be placed close to all the

ground pins. The bottom ground pad should be

penetrated with 4-16 ground vias.

The antenna has an impedance of ~50 ohm. The

antenna trace should be kept to 50 ohm to avoid

signal reflection and loss of performance. Any

transmission line calculator can be used to find the

needed trace width given a board build up. Ex: A

trace width of 44 mil (1.12 mm) gives 50

impedance on a FR4 board (dielectric cons=4.4)

with copper thickness of 35µm and height (layer 1-

layer 2 spacing) of 0.61 mm.

Figure 13. Recommended Land Pattern (TOP VIEW)

18

M9999-120205

December 2005


型号：	MICRF620TR
厂家：	MICREL SEMICONDUCTOR
描述：	434MHz ISM Band Transceiver Module 434MHz的ISM频段收发器模块电信集成电路电信电路 ISM频段
文件：	总18页 (文件大小：257K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MICRF620TR [MICREL]

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