SY100E143JZTR [MICREL]

9-BIT HOLD REGISTER; 9位保持寄存器
SY100E143JZTR
型号: SY100E143JZTR
厂家: MICREL SEMICONDUCTOR    MICREL SEMICONDUCTOR
描述:

9-BIT HOLD REGISTER
9位保持寄存器

触发器 锁存器 逻辑集成电路
文件: 总4页 (文件大小:63K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
9-BIT HOLD  
REGISTER  
SY10E143  
SY100E143  
DESCRIPTION  
FEATURES  
The SY10/100E143 are high-speed 9-bit hold registers  
designed for use in new, high-performance ECL systems.  
The E143 can hold current data or load new data. The nine  
inputs, D0-D8, accept parallel input data.  
The SEL (Select) control pin serves to determine the  
mode of operation; either HOLD or LOAD. The input data  
has to meet the set-up time before being clocked into the  
nine input registers on the rising edge of CLK1 or CLK2.  
The MR (Master Reset) control signal asynchronously  
resets all nine registers to a logic LOW when a logic HIGH  
is applied to MR.  
700MHz min. operating frequency  
Extended 100E VEE range of –4.2V to –5.5V  
9 bits wide for byte-parity applications  
Asynchronous Master Reset  
Dual clocks  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E143  
Available in 28-pin PLCC package  
The E143 is designed for applications requiring high-  
speed registers, pipeline registers, synchronous operation,  
and is also suitable for byte-wide parity.  
BLOCK DIAGRAM  
PIN NAMES  
D
D
Q0  
MUX  
D0  
D1  
D2  
R
R
Pin  
D0-D8  
SEL  
Function  
Parallel Data Inputs  
Mode Select Input  
Clock Inputs  
Q1  
Q2  
MUX  
MUX  
CLK1, CLK2  
MR  
Master Reset  
D
D
R
R
Q0-Q8  
NC  
Data Outputs  
No Connection  
VCC to Output  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
VCCO  
MUX  
D3  
D4  
D5  
D6  
D7  
D8  
D
D
MUX  
MUX  
R
R
D
D
MUX  
MUX  
MUX  
R
R
D
R
SEL  
CLK1  
CLK2  
MR  
Rev.: F  
Amendment: /0  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  
SY10E143  
SY100E143  
Micrel, Inc.  
PACKAGE/ORDERING INFORMATION  
Ordering Information(1)  
Package  
Type  
Operating  
Range  
Package  
Marking  
Lead  
Finish  
Part Number  
25 24 23 22 21 20 19  
SY10E143JC  
SY10E143JCTR(2)  
J28-1  
J28-1  
J28-1  
Commercial  
Commercial  
Commercial  
SY10E143JC  
SY10E143JC  
SY100E143JC  
Sn-Pb  
Sn-Pb  
Sn-Pb  
MR  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q7  
CLK  
1
Q
6
SY100E143JC  
CLK  
2
V
CC  
PLCC  
TOP VIEW  
J28-1  
SY100E143JCTR(2)  
SY10E143JZ(3)  
J28-1  
J28-1  
Commercial  
Commercial  
SY100E143JC  
Sn-Pb  
V
EE  
Q
5
NC  
2
VCCO  
SY10E143JZ with  
Pb-Free bar-line indicator  
Matte-Sn  
D
D
0
1
3
Q
Q
4
3
4
SY10E143JZTR(2, 3)  
SY100E143JZ(3)  
J28-1  
J28-1  
Commercial  
Commercial  
SY10E143JZ with  
Pb-Free bar-line indicator  
Matte-Sn  
Matte-Sn  
5
6
7
8
9
10 11  
SY100E143JZ with  
Pb-Free bar-line indicator  
SY100E143JZTR(2, 3)  
J28-1  
Commercial  
SY100E143JZ with  
Pb-Free bar-line indicator  
Matte-Sn  
28-Pin PLCC (J28-1)  
Notes:  
1. Contact factory for die availability. Dice are guaranteed at T = 25°C, DC Electricals only.  
A
2. Tape and Reel.  
3. Pb-Free package is recommended for new designs.  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
2
SY10E143  
SY100E143  
Micrel, Inc.  
TRUTH TABLE  
SEL  
L
MODE  
LOAD  
HOLD  
H
DC ELECTRICAL CHARACTERISTICS  
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND  
TA = 0°C  
TA = +25°C  
TA = +85°C  
Symbol  
IIH  
Parameter  
Input HIGH Current  
Power Supply Current  
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit  
Condition  
150  
150  
150  
µA  
IEE  
mA  
10E  
100E  
120 145  
120 145  
120  
120  
145  
145  
120  
138  
145  
165  
AC ELECTRICAL CHARACTERISTICS  
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND  
TA = 0°C  
TA = +25°C  
TA = +85°C  
Symbol  
fMAX  
Parameter  
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit  
Condition  
Max. Toggle Frequency  
700 900  
700 900  
700 900  
MHz  
ps  
tPD  
Propagation Delay to Output  
CLK  
MR  
600 800 1000 600 800 1000 600 800 1000  
600 800 1000 600 800 1000 600 800 1000  
tS  
tH  
Set-up Time  
D
SEL  
ps  
ps  
50 –100  
300 150  
50 –100  
300 150  
50 –100  
300 150  
Hold Time  
D
SEL  
300 100  
75 –150  
300 100  
75 –150  
300 100  
75 –150  
tRR  
tPW  
Reset Recovery Time  
900 700  
900 700  
900 700  
ps  
ps  
Minimum Pulse Width  
CLK, MR  
400  
400  
400  
tskew  
Within-Device Skew  
75  
75  
75  
ps  
ps  
1
tr  
tf  
Rise/Fall Time  
20% to 80%  
300 525 800 300 525  
800 300 525  
800  
Note:  
1. Within-device skew is defined as identical transitions on similar paths through a device.  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
3
SY10E143  
SY100E143  
Micrel, Inc.  
28-PIN PLCC (J28-1)  
Rev. 03  
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA  
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com  
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.  
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.  
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can  
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into  
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchasers  
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchasers own risk and Purchaser agrees to fully indemnify  
Micrel for any damages resulting from such use or sale.  
© 2006 Micrel, Incorporated.  
M9999-032006  
hbwhelp@micrel.com or (408) 955-1690  
4

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