SY100EL34ZC [MICREL]
5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP; 5V / 3.3V ÷ 2 ÷ 4 ÷ 8时钟发生器芯片
| 型号： | SY100EL34ZC |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 5V/3.3V ±2, ±4, ±8 CLOCK GENERATION CHIP |
| 文件： | 总4页 (文件大小：60K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ClockWorks™
SY10EL34/L
SY100EL34/L
5V/3.3V ÷2, ÷4, ÷8 CLOCK
GENERATION CHIP
FEATURES
DESCRIPTION
■ 3.3V and 5V power supply options
■ 50ps output-to-output skew
The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor.
The VBB output is designed to act as the switching
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
■ Synchronous enable/disable
■ Master Reset for synchronization
■ Internal 75KΩ input pull-down resistors
■ Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
VCC
16
15
Q0
1
2
Q
Q
Q
÷2
EN
Q0
R
Q
D
VCC
3
4
14 NC
13
R
Q1
CLK
÷4
5
6
12
11
CLK
VBB
R
Q1
VCC
Q2
Q2
7
8
10 MR
÷8
9
VEE
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
R
SOIC
TOP VIEW
PIN NAMES
Pin
CLK
EN
MR
VBB
Q0
Function
Differential Clock Inputs
Synchronous Enable
Master Reset
Reference Output
Differential ÷2 Outputs
Differential ÷4 Outputs
Differential ÷8 Outputs
Q1
Q2
Rev.: F
Amendment:/0
Issue Date: August, 1998
1
ClockWorks™
SY10EL34/L
SY100EL34/L
Micrel
TRUTH TABLE
CLK
EN
L
MR
L
Function
Divide
Z
ZZ
X
H
L
Hold Q0–2
X
H
Reset Q0–2
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
(1)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Power Supply
Current
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
IEE
10EL
100EL
—
—
—
—
49
49
—
—
—
—
49
49
—
—
—
—
49
49
—
—
—
—
49
54
mA
VBB
Output Reference 10EL –1.43
—
—
–1.30 –1.38
–1.26 –1.38
—
—
–1.27 –1.35
–1.26 –1.38
—
—
–1.25 –1.31
–1.26 –1.38
—
—
–1.19
–1.26
V
Voltage
100EL –1.38
IIH
Input High Current
—
—
150
—
—
150
—
—
150
—
—
150
µA
NOTE:
1. Parametric values specified at:
5 volt Power Supply Range 100EL34 Series:
10EL34 Series
-4.2V to -5.5V.
-4.75V to -5.5V.
3 volt Power Supply Range 10/100EL34L Series: -3.0V to -3.8V.
(1)
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
tPLH
tPHL
Propagation Delay to
ps
Output
CLK
MR
960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200
650
800 1010 650 800
1010 650
800 1010 650
800 1010
tskew
tS
Within-Device Skew(2)
Set-up Time EN
—
—
—
50
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
50
—
ps
ps
ps
mV
V
400
200
250
400
200
250
400
200
250
400
200
250
tH
Hold Time EN
—
—
—
VPP
VCMR
Minimum Input Swing(3)
—
—
—
Common Mode Range(4) –1.3
—
–0.4 –1.4
525
–0.4 –1.4
525 275
—
–0.4 –1.4
525 275
–0.4
tr
tf
Output Rise/Fall Times
Q (20% – 80%)
275
400
275 400
400
400 525
ps
NOTES:
1. Parametric values specified at:
5 volt Power Supply Range 100EL34 Series:
10EL34 Series
-4.2V to -5.5V.
-4.75V to -5.5V.
3 volt Power Supply Range 10/100EL34L Series: -3.0V to -3.8V.
2. Skew is measured between outputs under identical transitions.
3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV.
4. TheCMRrangeisreferencedtothemostpositivesideofthedifferentialinputsignal. NormaloperationisobtainediftheHIGHlevelfallswithinthespecified
range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I.
2
ClockWorks™
SY10EL34/L
SY100EL34/L
Micrel
TIMING DIAGRAM
Internal Clock
Disabled
Internal Clock
Enabled
CLK
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers
will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs
will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
PRODUCT ORDERING CODE
5V
3.3V
Ordering
Code
Package
Type
Operating
Range
VEE Range
(V)
Ordering
Code
Package
Type
Operating
Range
VEE Range
(V)
SY10EL34LZC
Z16-2
Z16-2
Z16-2
Z16-2
Commercial
Commercial
Commercial
Commercial
-3.0 to -3.8
-3.0 to -3.8
-3.0 to -3.8
-3.0 to -3.8
SY10EL34ZC
Z16-2
Z16-2
Z16-2
Z16-2
Commercial -4.75 to -5.5
Commercial -4.75 to -5.5
SY10EL34LZCTR
SY100EL34LZC
SY100EL34LZCTR
SY10EL34ZCTR
SY100EL34ZC
SY100EL34ZCTR
Commercial
Commercial
-4.2 to -5.5
-4.2 to -5.5
3
ClockWorks™
SY10EL34/L
SY100EL34/L
Micrel
16 LEAD SOIC .150" WIDE (Z16-2)
Rev. 02
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
相关型号：
SY100EL34ZG
100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MICROCHIP
SY100EL34ZG-TR
100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MICROCHIP
SY100EL35LZI-TR
100EL SERIES, POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
MICROCHIP
©2020 ICPDF网 联系我们和版权申明