SY100S891JC [MICREL]
5-BIT REGISTERED TRANSCEIVER; 5位寄存收发器型号: | SY100S891JC |
厂家: | MICREL SEMICONDUCTOR |
描述: | 5-BIT REGISTERED TRANSCEIVER |
文件: | 总5页 (文件大小:83K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
5-BIT REGISTERED
TRANSCEIVER
SY100S891
FEATURES
DESCRIPTION
■ 25Ω cut-off bus outputs
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS0 – BUS4) are
specified for driving a 25 ohm bus and the receive outputs
(Q0 – Q4) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN0 – BUSEN4) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK1) which is common to all five bus driver
registers; and a separate clock (CLK2) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK1 and
data on the bus is clocked into the Receiver register by
a positive transition of CLK2. A high on the Master Reset
clears all registers.
■ 50Ω receiver outputs
■ Transmit and receive registers with separate clocks
■ 1500ps max. delay from CLK1 to Bus Outputs (BUS)
■ 1500ps max. delay from CLK2 to Receiver Outputs (Q)
■ Individual bus enable pins
■ Internal 75KΩ input pull-down resistors
■ Voltage and temperature compensation for improved
noise immunity
■ Industry standard 100K ECL levels
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Available in 28-pin PLCC package
PIN CONFIGURATION
PIN NAMES
Pin
BUSEN0–4
D0 – D4
CLK1
Function
Bus Enable Inputs
Data Inputs
Bus Driver Clock Input
Receive Register Clock
Master Reset
25 24 23 22 21 20 19
CLK2
MR
26
27
28
1
18
17
16
15
14
13
12
Q
3
MR
CLK
2
1
BUS
3
2
Q0 – Q4
BUS0–4
Bus Receive Outputs
Bus Outputs
CLK
V
CC
TOP VIEW
PLCC
V
EE
Q
2
J28-1
2
D2
BUS
BUSEN
D
2
3
VCCA
4
1
Q1
5
6
7
8
9
10 11
Rev.: E
Amendment:/0
Issue Date: August, 1998
1
Micrel
SY100S891
BLOCK DIAGRAM
25Ω CUTOFF
50Ω
D Q
R C
D0
BUS
0
D Q
R C
Q
0
BUSEN
0
25Ω CUTOFF
50Ω
D Q
R C
D1
BUS
1
D Q
R C
Q
1
BUSEN
1
25Ω CUTOFF
50Ω
D Q
R C
D
2
BUS
2
3
D Q
R C
Q
2
BUSEN
2
25Ω CUTOFF
50Ω
D Q
R C
D3
BUS
D Q
R C
Q
3
BUSEN
3
25Ω CUTOFF
50Ω
D Q
R C
D
4
BUS
4
D Q
R C
Q
4
BUSEN
4
MR
CLK
CLK
1
2
2
Micrel
SY100S891
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
Symbol
Parameter
Min.
Typ.
Max.
Unit
Condition
VCUT
Cut-off Bus Output Voltage
–2200 –2160 –2100
mV
VIN = VIH (Max.) or VIL (Min.)
Loading with
25Ω to –2.20V
VOH
VOL
Output HIGH Voltage Bus
Output LOW Voltage Bus
Output HIGH Voltage Bus
Output LOW Voltage Bus
–1025
–955
–880
mV
mV
mV
mV
mV
mV
VIN = VIH (Max.) or VIL (Min.)
VIN = VIH (Min.) or VIL (Max.)
Loading with
–1810 –1705 –1620
25Ω to –2.0V
VOHA
VOLA
–1035
—
—
—
—
–1610
–880
VOH
VOL
Output HIGH Voltage Receiver –1025
–955
VIN = VIH (Max.) or VIL (Min.)
VIN = VIH (Min.) or VIL (Max.)
Loading with
Output LOW Voltage Receiver –1810 –1705 –1620
50Ω to –2.0V
VOHA
VOLA
Output HIGH Voltage Receiver –1035
Output LOW Voltage Receiver
—
—
—
–1610
mV
mV
—
–1165
–1810
0.5
VIH
VIL
IIL
Input HIGH Voltage
—
—
—
—
—
4
–880
–1475
—
mV
mV
µA
µA
mA
pF
Guaranteed HIGH Signal for All Inputs
Guaranteed LOW Signal for All Inputs
VIN = VIL (Min.)
Input LOW Voltage
Input LOW Current
IIH
Input High Current
—
150
—
VIN = VIH (Max.)
IEE
CIN
COUT
Power Supply Current
Input Pin Capacitance
Output Pin Capacitance
–216
—
Inputs Open
—
—
5
—
pF
3
Micrel
SY100S891
AC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified; VCC = VCCA = GND
TA = 0°C TA = +25°C
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
TA = +85°C
Symbol
Parameter
Condition
tPLH
tPHL
Propagation Delay(1)
CLK1 to Bus
600 1000 1500 600 1000 1500 600 1000 1500
ps
ps
ps
ps
ps
ps
tPLH
tPHL
Propagation Delay(2)
CLK2 to Q
500
500
800 1200 500
800 1200 500
800 1200 500
800 1200 500
800 1200
800 1200
tPLH
tPHL
Propagation Delay(1)
BUSEN to Bus
tPLH
tPHL
Propagation Delay(1)
Master Reset to Bus
600 1000 1500 600 1000 1500 600 1000 1500
tPLH
tPHL
Propagation Delay(2)
Master Reset to Q
500
800 1200 500
800 1200 500
800 1200
tS
Set-up Time
Bus Wrt CLK2
D Wrt CLK1
—
—
—
—
400
400
—
—
—
—
400
400
—
—
—
—
400
400
tREL
tH
Master Reset
Release Time
—
—
1000
—
—
1000
—
—
1000
ps
ps
Hold Time
Bus Wrt CLK2
D Wrt CLK1
—
—
—
—
400
400
—
—
—
—
400
400
—
—
—
—
400
400
tr
Output Rise Time
ps
ps
ps
Bus(3)
Q(4)
500
300
—
—
1000 500
900 300
—
—
1000 500
900 300
—
—
1000
900
tf
Output Fall Time
Bus(3)
Q(4)
500
300
—
—
1000 500
—
—
1000 500
—
—
1000
900
900
300
900
300
tskew
Skew (Maximum
—
100
—
—
100
—
—
100
—
difference between
slowest and fastest path)
NOTES:
1. Loaded with 25Ω to –2.0V
2. Loaded with 50Ω to –2.0V
3. 25Ω Load
4. 50Ω Load
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY100S891JC
J28-1
J28-1
Commercial
Commercial
SY100S891JCTR
4
Micrel
SY100S891
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
5
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