SY10E131JI [MICREL]
4-BIT D FLIP-FLOP; 4位D触发器
| 型号： | SY10E131JI |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 4-BIT D FLIP-FLOP |
| 文件： | 总4页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-BIT D
FLIP-FLOP
SY10E131
SY100E131
DESCRIPTION
FEATURES
■ 1100MHz min. toggle frequency
■ Extended 100E VEE range of –4.2V to –5.5V
■ Differential output
The SY10/100E131 are high-speed quad master slave
D-type flip-flops with differential outputs designed for use
in new, high-performance ECL systems. The flip-flops may
be individually clocked by holding CC (Common Clock) at
a logic LOW and then using the four individual CE (Clock
Enable CE0–CE3) inputs to accomplish such clocking.
Alternatively, all four flip-flops can be clocked in common
by holding the CE inputs LOW and then using CC to clock
the data. In the common clock mode, the CE input acts as
a control that passes the CC signal to the flip-flop. Data is
clocked into the flip-flop on the rising edge of the output of
the logical OR operation between CE and CC (data enters
the master when both CC and CE are LOW and data
transfers to the slave when either CE or CC, or both, go
HIGH).
■ Individual and common clocks
■ Indivldual asynchronous reset
■ Paired asynchronous sets
■ Fully compatible with Industry standard 10KH,
100K ECL levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E131
■ Available in 28-pin PLCC package
Asynchronous set and reset controls are provided. The
reset controls are individual and the set controls are
pairwise.
PIN NAMES
PIN CONFIGURATION
Pin
Function
Data Inputs
D0-D3
CE0-CE3
R0-R3
CC
Clock Enables (Individual)
Resets
25 24 23 22 21 20 19
18
26
27
28
1
Q
2
CE
3
Common Clock
Sets (paired)
D
3
17
16
15
14
13
12
Q
2
S03, S12
Q0-Q3
Q0-Q3
VCCO
S
12
EE
V
CC
1
PLCC
TOP VIEW
J28-1
True Outputs
V
Q
Q
C
C
2
1
Inverting Outputs
VCC to Output
Q
0
S
03
3
4
D
0
Q
0
5
6
7
8
9
10 11
Rev.: E
Amendment: /0
Issue Date: November, 1998
1
SY10E131
SY100E131
Micrel
BLOCK DIAGRAM
TRUTH TABLE
Pin
CC
CE
State
Mode
S
L
L
Individual clocking with CEn
Common clocking with CC
Q3
Q3
D
Q
Q
D
3
CE
3
R
S
R
3
Q
Q
D
Q2
Q2
D2
CE
2
R
R2
S
03
12
S
CC
R1
R
Q1
Q1
Q
Q
CE1
D1
D
S
R
R
0
Q0
Q0
Q
Q
CE
0
D
D0
S
2
SY10E131
SY100E131
Micrel
DC ELECTRICAL CHARACTERISTICS
VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max. Unit
IIH
Input HIGH Current
µA
CC
S
R
CE
D
—
—
—
—
—
—
—
—
—
—
350
450
300
300
150
—
—
—
—
—
—
—
—
—
—
350
450
300
300
150
—
—
—
—
—
—
—
—
—
—
350
450
300
300
150
—
—
—
—
—
—
—
—
—
—
350
450
300
300
150
IEE
Power Supply Current
10E
100E
mA
—
—
58
58
70
70
—
—
58
58
70
70
—
—
58
58
70
70
—
—
58
67
70
81
AC ELECTRICAL CHARACTERISTICS
VEE = VEE(Min.) to VEE(Max.); VCC = VCCO = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Min. Typ. Max. Unit
Symbol
Parameter
Min. Typ. Max. Min.
Typ. Max. Min. Typ. Max.
fMAX
Max. Toggle Frequency 1100 1400
—
1100 1400
—
1100 1400
—
1100 1400
—
MHz
ps
tPLH
tPHL
Propagation Delay to
Output
CE 310
CC 275
600
600
625
550
750
725
775
775
360
325
350
350
500
500
550
550
700
675
725
725
360
325
350
350
500
500
550
550
700
675
725
725
360
325
350
350
500
500
550
550
700
675
725
725
R
S
300
300
ts
Set-up Time, D(2)
200
225
450
20
—
—
—
150
175
400
20
—
—
—
150
175
400
20
—
—
—
150
175
400
20
—
—
—
ps
ps
ps
ps
th
Hold Time, D(2)
–20
150
–20
150
–20
150
–20
150
tRR
tPW
Reset Recovery Time
Minimum Pulse Width
Clk 400
R, S 400
—
—
—
—
400
400
—
—
—
—
400
400
—
—
—
—
400
400
—
—
—
—
tskew
Within-Device Skew(1)
—
60
—
—
60
—
—
60
—
—
60
—
ps
ps
tr
tf
Rise/Fall Time
20% to 80%
275
460
725
300
480
675
300
480
675
300
480
675
NOTES:
1. Within-device skew is defined as identical transitions on similar paths through a device.
2. Set-up/hold times guaranteed for both CC and CE.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
Ordering
Code
Package
Type
Operating
Range
SY10E131JC
J28-1
J28-1
J28-1
J28-1
Commercial
Commercial
Commercial
Commercial
SY10E131JI
J28-1
J28-1
J28-1
J28-1
Industrial
Industrial
Industrial
Industrial
SY10E131JCTR
SY100E131JC
SY100E131JCTR
SY10E131JITR
SY100E131JI
SY100E131JITR
3
SY10E131
SY100E131
Micrel
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
相关型号：
SY10E131JY
10E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
MICROCHIP
SY10E131JY-TR
10E SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28
MICROCHIP
©2020 ICPDF网 联系我们和版权申明