SY10E136 [MICREL]
6-BIT UNIVERSAL UP/DOWN COUNTER; 6位通用加/减计数器型号: | SY10E136 |
厂家: | MICREL SEMICONDUCTOR |
描述: | 6-BIT UNIVERSAL UP/DOWN COUNTER |
文件: | 总8页 (文件大小:122K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
6-BIT UNIVERSAL
SY10E136
UP/DOWN COUNTER
SY100E136
DESCRIPTION
FEATURES
■ 550MHz count frequency
The SY10/100E136 are 6-bit synchronous, presettable,
cascadable universal counters. These devices generate
a look-ahead-carry output and accept a look-ahead-carry
input. These two features allow for the cascading of
multiple E136s for wider bit width counters that operate
at very nearly the same frequency as the stand-alone
counter.
The CLOUT output will pulse LOW for one clock cycle
one count before the E136 reaches terminal count. The
COUT output will pulse LOW for one clock cycle when
the counter reaches terminal count. For more information
on utilizing the look-ahead-carry features of the device,
please refer to the applications section of this data sheet.
The differential COUT output facilitates the E136's use in
programmable divider and self-stopping counter
applications.
■ Extended 100E VEE range of –4.2V to –5.5V
■ Look-ahead-carry input and output
■ Fully synchronous up and down counting
■ Asynchronous Master Reset
■ Internal 75KΩ input pull-down resistors
■ Available in 28-pin PLCC package
PIN CONFIGURATION
Unlike the H136 and other similar universal counter
designs, the E136 carry-out and look-ahead-carry-out
signals are registered on chip. This design alleviates the
glitch problem seen on many counters where the carry-
out signals are merely gated. Because of this architecture,
there are some minor functional differences between the
E136 and H136 counters. The user, regardless of
familiarity with the H136, should read this data sheet
carefully. Note specifically (see block diagram) the
operation of the carry-out outputs and the look-ahead-
carry-in input when utilizing the Master Reset.
25 24 23 22 21 20 19
26
27
28
1
18
17
16
15
14
13
12
Q3
D2
S2
S1
Q2
VCC
PLCC
TOP VIEW
J28-1
VEE
VCCO
COUT
COUT
CLK
2
CIN
3
CLIN
4
CLOUT
5
6
7
8
9
10 11
When left open, all of the input pins will be pulled
LOW via an input pulldown resistor. The Master Reset is
an asynchronous signal which, when asserted, will force
the Q outputs LOW.
The Q outputs need not be terminated for the E136 to
function properly. In fact, if these outputs will not be
used in a system, it is recommended that they be left
open to save power and minimize noise. This practice
will minimize switching noise which can reduce the
maximum count frequency of the device, or significantly
reduce margins against other noise in the system.
PIN NAMES
Pin
D0–D5
Q0–Q5
S1, S2
MR
Function
Preset Data Inputs
Differential Data Outputs
Mode Control Pins
Master Reset
CLK
Clock Input
COUT, COUT
CLOUT
CIN
Carry Out Output (Active LOW)
Look-Ahead-Carry Output
Carry-In Input (Active LOW)
Look-Ahead-Carry Input
VCC to Output
CLIN
VCCO
Rev.: C
Amendment:/1
Issue Date: February, 1998
1
SY10E136
Micrel
SY100E136
(1)
BLOCK DIAGRAM
Q5
D5
Q
2
2
– Q5
BITS 2 – 4
D
– D4
Q1
D1
Q0
D0
E136 Universal Up/Down Counter Logic Diagram
NOTE:
1. This diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved
internally without incurring a full gate delay.
2
SY10E136
Micrel
SY100E136
(1)
TRUTH TABLE
S1
L
S2
L
CIN
X
MR
L
CLK
Z
Function
Preset Parallel Data Inputs
L
H
H
L
L
L
Z
Increment (Count Up)
Hold Count
L
H
L
L
Z
H
H
H
X
L
Z
Decrement (Count Down)
Hold Count
L
H
X
L
Z
H
X
L
Z
Hold Count
X
H
X
Reset (Qn = LOW; COUT = HIGH)
NOTE:
1. Expanded truth table included on following pages.
(1)
EXPANDEDTRUTH TABLE
Function S1
S2 MR CIN CLIN CLK D5
D4
D3
D2
D1
D0
Q5
Q4 Q3 Q2
Q1
Q0 COUT CLOUT
Preset
Down
L
L
L
X
X
Z
L
L
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Preset
Up
L
L
L
X
X
Z
H
H
H
H
L
L
H
H
H
H
L
L
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
H
L
H
H
H
H
L
H
H
H
H
Hold
H
H
H
H
L
L
X
X
X
X
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
H
H
L
L
H
H
H
H
Down
Hold
Down
Hold
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
H
L
L
L
L
L
L
H
H
L
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
H
H
H
L
L
H
H
H
H
H
H
H
Hold
L
L
Hold
Preset
Up
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
L
H
H
L
L
X
L
L
L
L
L
H
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hold
Up
Hold
L
H
H
H
H
Hold
Up
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
Reset
X
X
H
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
NOTE:
1. Z = LOW-to-HIGH transition
3
SY10E136
Micrel
SY100E136
DCELECTRICALCHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IIH
Parameter
Input HIGH Current
Power Supply Current
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
Condition
—
—
150
—
—
150
—
—
150
µA
—
—
IEE
mA
10E
100E
—
—
125 150
125 150
—
—
125
125
150
150
—
—
125
140
150
170
ACELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ.
550 650 550 650 550 650
Max. Unit
Condition
fCOUNT
Maximum Count Frequency
—
—
—
MHz
ps
—
—
tPLH
tPHL
Propagation Delay to Output
CLK to Q
MR to Q
CLK to COUT
CLK to CLOUT
850 1150 1450 850 1150 1450 850 1150 1450
850 1150 1450 850 1150 1450 850 1150 1450
800 1150 1300 800 1150 1300 800 1150 1300
825 1150 1400 825 1150 1400 825 1150 1400
tS
tH
Set-up Time
S1, S2
D
CLIN
CIN
ps
ps
—
—
1500 650
—
—
—
—
1500 650
—
—
—
—
1500 650
—
—
—
—
800
150
800
400
0
400
800
150
800
400
0
400
800
150
800
400
0
400
Hold Time
S1, S2
D
CLIN
CIN
150 –200
150 –250
—
—
—
—
150 –200
150 –250
—
—
—
—
150 –200
150 –250
—
—
—
—
300
0
300
0
300
0
150 –250
150 –250
150 –250
tRR
tPW
Reset Recovery Time
1000 700
—
—
1000 700
—
—
1000 700
—
—
ps
ps
—
—
Minimum Pulse Width
CLK, MR
700
400
700
400
700
400
tr
tf
Rise/Fall Times
20% to 80%
COUT
ps
—
275
300
—
—
600
700
275
300
—
—
600
700
275
300
—
—
600
700
Other
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY10E136JC
J28-1
J28-1
J28-1
J28-1
Commercial
Commercial
Commercial
Commercial
SY10E136JCTR
SY100E136JC
SY100E136JCTR
4
SY10E136
Micrel
SY100E136
APPLICATIONSINFORMATION
Overview
having to ripple through the entire counter chain. As a
The SY10E/100E136 are 6-bit synchronous, presettable, result, past counters of this type were not widely used in
cascadable universal counters. Using the S1 and S2 control large bit counter applications.
pins, the user can select between preset, count up, count
An alternative counter architecture similar to the E016
down and hold count. The Master Reset pin will reset the binary counter was implemented to alleviate the need to
internal counter and set the COUT, CLOUT and CLIN flip- ripple propagate the terminal count signal. Unfortunately,
flops. Unlike previous 136-type counters, the carry-out these types of counters require external gating for cascading
outputs will go to a high state during the preset operation. designs of more than two devices. In addition to requiring
In addition, since the carry-out outputs are registered, they additional components, these external gates limit the
will not go low if terminal count is loaded into the register. cascaded count frequency to a value less than the free
The look-ahead-carry-out output functions similarly.
running count frequency of a single counter. Although there
Note from the schematic the use of the master information is a performance impact with this type of architecture, it is
from the least significant bits for control of the two carry-out minor compared to the impact of the ripple propagate
functions. This architecture not only reduces the carry-out designs. As a result, the E016-type counters have been
delay, but is essential to incorporate the registered carry- used extensively in applications requiring very high speed,
out functions. In addition to being faster, the resulting carry- wide bit width synchronous counters.
out signals are stable and glitch free because these functions
are registered.
Several improvements have been incorporated to past
universal counter designs in the E136 universal counter.
These enhancements make the E136 the unparalleled leader
in its class. With the addition of look-ahead-carry features
Cascading Multiple E136 Devices
Many applications require counters significantly larger than on the terminal count signal, very large counter chains can
the 6 bits available with the E136. For these applications, be designed which function at very nearly the same clock
several E136 devices can be cascaded to increase the bit frequency as a single free running device. More importantly,
width of the counter to meet the needs of the application.
these counter chains require no external gating. Figure 1
In the past, cascading several 136-type universal counters below illustrates the interconnect scheme for using the look-
necessarily impacted the maximum count frequency of the ahead-carry features of the E136 counter.
resulting counter chain. This performance impact was the
result of the terminal count signal of the lower order counters
Q0
– Q
5
Q0
– Q
5
Q0
– Q
5
Q0 – Q5
CLOCK
CLK
LSB
CLK
CLK
CLK
MSB
"LO"
"LO"
"LO"
C
IN
C
OUT
C
IN
C
OUT
C
IN
C
OUT
C
IN
COUT
CLIN CLOUT
CLIN CLOUT
CLIN CLOUT
CLIN CLOUT
D0
– D5
D0
– D5
D0
– D5
D0 – D5
111101
111110
111111
000000
000001
CLK
CLOUT
COUT
Figure 1. 24-bit Cascaded E136 Counter
5
SY10E136
Micrel
SY100E136
count status for the next occurrence of terminal count on
the LSC. This ripple propagation will not affect the count
frequency as it has 2 -1 or 63 clock pulses to ripple through
C
IN
ACTIVE
LOW
6
CLIN
CLK
D
Q
without affecting the count operation of the chain.
The only limiting factor which could reduce the count
frequency of the chain as compared to a free running single
device will be the set-up time of the CLIN input. This limit
will consist of the CLK to CLOUT delay of the E136, plus the
CLIN set-up time, plus any path length differences between
Figure 2. Look-Ahead-Carry Input Structure
Note from the waveforms that the look-ahead-carry output the CLOUT output and the clock.
(CLOUT) pulses low one clock pulse before the counter
reaches terminal count. Also note that both CLOUT and the Programmable Divider
carry-out pin (COUT) of the device pulse low for only one
Using external feedback of the COUT pin, the E136 can
clock period. The input structure for look-ahead-carry-in be configured as a programmable divider. Figure 3 illustrates
(CLIN) and carry-in (CIN) is pictured in Figure 2.
the configuration for a 6-bit count-down programmable
The CLIN input is registered and then OR'ed with the CIN divider. If for some reason a count-up divider is preferred,
input. From the truth table one can see that both the CIN the COUT signal is simply fed back to S2 rather than S1.
and the CLIN inputs must be in a LOW state for the E136 to Examination of the truth table for the E136 shows that when
be enabled to count (either count up or count down). The both S1 and S2 are LOW, the counter will parallel load on
CLIN inputs are driven by the CLOUT output of the lower the next positive transition of the clock. If the S2 input is
order E136 and, therefore, are only asserted for a single low and the S1 input is high, the counter will be in the
clock period. Since the CLIN input is registered, it must be count-down mode and will count towards an all zero state
asserted one clock period prior to the CIN input.
upon successive clock pulses. Knowing this and the
If the counter previous to a given counter is at terminal operation of the COUT output, it becomes a trivial matter to
count, its COUT output, and thus the CIN input of the given build programmable dividers.
counter will be in the "LOW" state. This signals the given
For a programmable divider, one must to load a
counter that it will need to count one upon the next terminal predesignated number into the counter and count to terminal
count of the least significant counter (LSC). The CLOUT count. Upon terminal count, the counter should automatically
output of the LSC will pulse low one clock period before it reload the divide number. With the architecture shown in
reaches terminal count. This CLOUT signal will be clocked Figure 3, when the counter reaches terminal count, the
into the CLIN input of the higher order counters on the COUT output, and thus the S1 input, will go LOW. This,
following positive clock transition. Since both CIN and CLIN combined with the low on S2 will cause the counter to load
are in the LOW state, the next clock pulse will cause the the inputs present on D0–D5. Upon loading the divide value
least significant counter to roll over and all higher order into the counter, COUT will go HIGH as the counter is no
counters, if signaled by the CIN inputs, to count by one.
longer at terminal count, thereby placing the counter back
During the clock pulse in which the higher order counter into the count mode.
is counting by one, the CLIN is clocking in the high signal
presented by the CLOUT of the LSC. The CINs in the higher
order counter will ripple through the chain to update the
Divide
Ratio
Preset Data Inputs
D5
D4
D3
D2
D1
D0
2
3
L
L
L
L
*
L
L
L
L
*
L
L
L
L
*
L
L
L
H
*
L
H
H
L
*
H
L
H
L
*
Q
0 – Q5
4
5
S
0
1
"LO"
*
*
*
*
*
*
*
*
CLOCK
CLK
S
36
37
38
*
H
H
H
*
L
L
L
*
L
L
L
*
L
H
H
*
H
L
L
*
H
L
H
*
C
C
OUT
OUT
*
*
*
*
*
*
*
62
63
64
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
H
D
0 – D5
Figure 3. 6-bit Programmable Divider
Table 1. Preset Inputs Versus Divide Ratio
6
SY10E136
Micrel
SY100E136
LOAD
100100
100011
000011
000010
000001
000000
LOAD
CLOCK
S1
COUT
DIVIDE BY 37
Figure 4. Programmable Divider Waveforms
The exercise of building a programmable divider then benefits of the E016 diminishes and, in fact, for very wide
becomes simply determining what value to load into the dividers, the E136 will provide the capability of a faster
counter to accomplish the desired division. Since the load count frequency. Figure 5 shows the architecture of a 24-
operation requires a clock pulse, to divide by N, N-1 must bit programmable divider implemented using E136 counters.
be loaded into the counter. A single E136 device is capable Note the need for one external gate to control the loading of
of divide ratios of 2 to 64, inclusive. Table 1 outlines the the entire counter chain. An ideal device for the external
load values for the various divide ratios. Figure 4 presents gating of this architecture would be the 4-input OR function
the waveforms resulting from a divide by 37 operation. Note in the 8-lead SOIC ECLinPS Lite™ family. However, the
that the availability of the COUT complimentary output (COUT) final decision as to what device to use for external gating
allows the user to choose the polarity of the divide by output. requires a balancing of performance needs, cost and
For single device programmable counters, the E016 available board space. Note that because of the need for
counter is probably a better choice than the E136. The external gating, the maximum count frequency of a given
E016 has an internal feedback to control the reloading of sized programmable divider will be less than that of a single
the counter. This not only simplifies board design, but also cascaded counter.
will result in a faster maximum count frequency.
For programmable dividers of larger than 8 bits, the
Q
0
– Q
5
Q
0
– Q
5
Q
0
– Q
5
Q0
– Q
5
CLOCK
S1
S1
S1
S1
CLK
CLK
CLK
CLK
LSB
MSB
"LO"
"LO"
"LO"
C
IN
C
OUT
C
IN
C
OUT
C
IN
C
OUT
C
IN
C
OUT
CLIN
CLOUT
CLIN
CLOUT
CLIN
CLOUT
CLIN
CLOUT
D0 – D5
D0 – D5
D0 – D5
D0 – D5
Figure 5. 24-bit Programmable Divider Architecture
7
SY10E136
Micrel
SY100E136
28 LEAD PLCC (J28-1)
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
8
相关型号:
©2020 ICPDF网 联系我们和版权申明