SY87700L [MICREL]
3.3V 32-175Mbps AnyRate⑩ CLOCK AND DATA RECOVERY; 3.3V 32-175Mbps AnyRate⑩时钟和数据恢复
| 型号： | SY87700L |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 3.3V 32-175Mbps AnyRate⑩ CLOCK AND DATA RECOVERY |
| 文件： | 总12页 (文件大小：154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 32-175Mbps AnyRate™
CLOCK AND DATA RECOVERY
SY87700L
FEATURES
DESCRIPTION
■ Industrial temperature range (–40°C to +85°C)
■ 3.3V power supply
The SY87700L is a complete Clock Recovery and Data
Retiming integrated circuit for data rates from 32Mbps
up to 175Mbps NRZ. The device is ideally suited for
SONET/SDH/ATM applications and other high-speed data
transmission systems.
Clock recovery and data retiming is performed by
synchronizing the on-chip VCO directly to the incoming
data stream. The VCO center frequency is controlled by
the reference clock frequency and the selected divide
ratio. On-chip clock generation is performed through the
use of a frequency multiplier PLL with a byte rate source
as reference.
■ SONET/SDH/ATM compatible
■ Clock and data recovery from 32Mbps up to
175Mbps NRZ data stream
■ Two on-chip PLLs: one for clock generation and
another for clock recovery
■ Selectable reference frequencies
■ Differential PECL high-speed serial I/O
■ Line receiver input: no external buffering needed
■ Link Fault indication
The SY87700L also includes a link fault detection
circuit.
■ 100K ECL compatible I/O
■ Complies with Bellcore, ITU/CCITT and ANSI
specifications for applications such as OC-1 and
OC-3
APPLICATIONS
■ SONET/SDH/ATM OC-1 and OC-3
■ Fast Ethernet
■ Available in 28-pin SOIC and 32-pin EP-TQFP
packages
■ Proprietary architecture up to 175Mbps
BLOCK DIAGRAM
PLLR P/N
RDOUTP
(PECL)
RDINP
(PECL)
RDINN
PHASE
DETECTOR
RDOUTN
RCLKP
(PECL)
0
1
CHARGE
PUMP
VCO
RCLKN
PHASE/
FREQUENCY
DETECTOR
LINK
FAULT
CD
(PECL)
DETECTOR
LFIN
(TTL)
REFCLK
PHASE/
CHARGE
PUMP
FREQUENCY
VCO
(TTL)
TCLKP
(PECL)
1
0
DETECTOR
TCLKN
VCC
DIVIDER
VCCA
BY 8, 10, 16, 20
V
GND
CCO
SY87700L
DIVSEL 1/2
PLLS P/N
FREQSEL 1/2/3
(TTL)
CLKSEL
(TTL)
(TTL)
AnyRate™ is a trademark of Micrel, Inc.
Rev.: B
Amendment:/0
Issue Date: September2000
1
Micrel
SY87700L
PIN CONFIGURATION
VCCA
LFIN
1
2
3
4
5
6
7
8
9
28 VCC
27 CD
32 31
30 29 28 27 26 25
DIVSEL1
RDINP
26 DIVSEL2
25 RDOUTP
24 RDOUTN
23 VCCO
22 RCLKP
21 RCLKN
20 VCCO
19 TCLKP
18 TCLKN
17 CLKSEL
16 PLLRP
15 PLLRN
RDOUTP
RDOUTN
VCCO
NC
RDINP
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
RDINN
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
RDINN
Top View
SOIC
Z28-1
Top View
EP-TQFP
H32-1
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
NC
RCLKP
RCLKN
VCCO
N/C 10
PLLSP 11
PLLSN 12
GND 13
TCLKP
TCLKN
9
10
11 12 13 14 15 16
GND 14
PIN DESCRIPTIONS
FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs
These inputs select the output clock frequency range as
shown in the “Frequency Selection” Table.
INPUTS
RDINP, RDINN [Serial Data Input] Differential PECL
These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive
PLL recovers the embedded clock (RCLK) and data
(RDOUT) information. The incoming data rate can be within
one of five frequency ranges depending on the state of the
FREQSEL pins. See “Frequency Selection” Table.
DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs
These inputs select the ratio between the output clock
frequency (RCLK/TCLK) and the REFCLK input frequency
as shown in the “Reference Frequency Selection” Table.
CLKSEL [Clock Select] TTL Inputs
REFCLK [Reference Clock] TTL inputs
This input is used to select either the recovered clock of
the receiver PLL (CLKSEL = HIGH) or the clock of the
frequency synthesizer (CLKSEL = LOW) to the TCLK
outputs.
This input is used as the reference for the internal
frequency synthesizer and the "training" frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN inputs.
OUTPUTS
CD [Carrier Detect] PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW the
data on the inputs RDIN will be internally forced to a constant
LOW, the data outputs RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW and the clock
recovery PLL forced to look onto the clock frequency
generated from REFCLK.
LFIN [Link Fault Indicator] TTL Output
This output indicates the status of the input data stream
RDIN. Active HIGH signal is indicating when the internal
clock recovery PLL has locked onto the incoming data
stream. LFIN will go HIGH if CD is HIGH and RDIN is within
the frequency range of the Receive PLL (1000ppm). LFIN
is an asynchronous output.
2
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SY87700L
RDOUTP, RDOUTN [Receive Data Output] Differential
PECL
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
External loop filter pins for the clock synthesis PLL.
These ECL 100K outputs represent the recovered data
from the input data stream (RDIN). This recovered data is PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
specified against the rising edge of RCLK.
External loop filter pins for the receiver PLL.
RCLKP, RCLKN [Clock Output] Differential PECL
These ECL 100K outputs represent the recovered clock
used to sample the recovered data (RDOUT).
POWER & GROUND
VCC
Supply Voltage(1)
Analog Supply Voltage(1)
Output Supply Voltage(1)
Ground
VCCA
VCCO
GND
N/C
TCLKP, TCLKN [Clock Output] Differential PECL
These ECL 100K outputs represent either the recovered
clock (CLKSEL = HIGH) used to sample the recovered data
(RDOUT) or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
No Connect
NOTE:
1. VCC, VCCA, VCCO must be the same value.
FUNCTIONAL DESCRIPTION
Clock Recovery
Lock Detect
Clock Recovery, as shown in the block diagram generates
The SY87700L contains a link fault indication circuit which
a clock that is at the same frequency as the incoming data monitors the integrity of the serial data inputs. If the received
bit rate at the Serial Data input. The clock is phase aligned serial data fails the frequency test, the PLL will be forced to
by a PLL so that it samples the data in the center of the lock to the local reference clock. This will maintain the correct
data eye pattern.
frequency of the recovered clock output under loss of signal
The phase relationship between the edge transitions of or loss of lock conditions. If the recovered clock frequency
the data and those of the generated clock are compared by deviates from the local reference clock frequency by more
a phase/frequency detector. Output pulses from the detector than approximately 1000ppm, the PLL will be declared out
indicate the required direction of phase correction. These of lock. The lock detect circuit will pull the input data stream
pulses are smoothed by an integral loop filter. The output of in an attempt to reacquire lock to data. If the recovered
the loop filter controls the frequency of the Voltage Controlled clock frequency is determined to be within approximately
Oscillator (VCO), which generates the recovered clock.
1000ppm, the PLL will be declared in lock and the lock
Frequency stability without incoming data is guaranteed detect output will go active.
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30µs data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
3
Micrel
SY87700L
CHARACTERISTICS
Jitter Transfer
Performance
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on the
input OC-N/STS-N signal versus frequency. Jitter transfer
requirements are shown in Figure 2.
The SY87700L PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and
ITU-T Recommendations: G.958 document, when used with
differential inputs and outputs.
Jitter Generation
The jitter of the serial clock and serial data outputs shall
not exceed .01 U.I. rms when a serial data input with no
jitter is presented to the serial data inputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal that
causes an equivalent 1dB optical/electrical power penalty.
SONET input jitter tolerance requirement condition is the
input jitter amplitude which causes an equivalent of 1dB
power penalty.
A
Jitter Transfer (dB)
0.1
-20dB/decade
15
-20dB/decade
1.5
-20dB/decade
Acceptable
Range
-20
0.40
f0
f1
f2
f4
ft
fc
Frequency
Frequency
OC/STS-N
Level
f0
(Hz)
f1
(Hz)
f2
(Hz)
f3
(kHz)
ft
(kHz)
OC/STS-N
Level
fc
(kHz)
P
(dB)
3
10
30
300
6.5
65
3
130
0.1
Figure 1. Input Jitter Tolerance
Figure 2. Jitter Transfer
4
Micrel
SY87700L
FREQUENCY SELECTION TABLE
FREQSEL1
FREQSEL2
FREQSEL3
fVCO/fRCLK
fRCLK Data Rates (Mbps)
0
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
6
125 –175
94 – 157
63 – 104
47 – 78
8
1
12
16
24
—
—
0
1
32 – 52
0
undefined
undefined
X(2)
NOTES:
1. SY87700L operates from 32-175MHz. For higher speed applications, the SY87701L operates from 32-1250MHz.
2. X is a DON'T CARE.
(1, 2)
REFERENCE FREQUENCY SELECTION
ABSOLUTE MAXIMUM RATINGS
DIVSEL1
DIVSEL2
fRCLK/fREFCLK
Symbol
VCC
Rating
Power Supply
Value
Unit
V
0
0
1
1
0
1
0
1
8
–0.5 to +7.0
–0.5 to VCC
10
16
20
VI
Input Voltage
V
IOUT
Output Current
mA
–Continuous
50
100
–Surge
Storage Temperature
Operating Temperature
Tstore
TA
–65 to +150
–40 to +85
°C
°C
(1)
LOOP FILTER COMPONENTS
NOTES:
1. PermanentdevicedamagemayoccurifABSOLUTEMAXIMUMRATINGS
are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections
ofthisdatasheet. ExposuretoABSOLUTEMAXIMUMRATINGconditions
for extended periods may affect device reliability.
R5
C3
2. Airflow of 500LFPM recommended.
PLLSP
PLLSN
SONET
Wide Range
R5 = 80Ω
R5 = 350Ω
C3 = 1.5µF (X7R Dielectric)
C3 = 0.47µF (X7R Dielectric)
R6
C4
PLLRP
PLLRN
SONET
Wide Range
R6 = 50Ω
R6 = 680Ω
C4 = 1.0µF (X7R Dielectric)
C4 = 0.47µF (X7R Dielectric)
NOTE:
1. Suggested Values. Values may vary for different applications.
5
Micrel
SY87700L
DC ELECTRICAL CHARACTERISTICS
Symbol
VCC
Parameter
Power Supply Voltage
Power Supply Current
Min.
3.15
—
Typ.
3.3
Max.
3.45
230
Unit
V
Condition
ICC
170
mA
PECL 100K DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to + 85°C
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input LOW Current
Output HIGH Voltage
Output LOW Voltage
Min.
Typ.
—
Max.
Unit
V
Condition
VCC - 1.165
VCC - 1.810
0.5
VCC - 0.880
VCC - 1.475
—
VIL
—
V
IIL
—
µA
V
VIN = VIL(Min.)
VOH
VOL
VCC - 1.075
VCC - 1.860
—
VCC - 0.830
VCC - 1.570
50Ω to VCC –2V
50Ω to VCC –2V
—
V
TTL DC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to + 85°C
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Min.
2.0
—
Typ.
—
Max.
VCC
0.8
Unit
V
Condition
VIL
—
V
IIH
–125
—
—
—
—
+100
µA
µA
VIN = 2.7V, VCC = Max.
VIN = VCC, VCC = Max.
IIL
Input LOW Current
–300
2.0
—
—
—
—
—
—
µA
V
VIN = 0.5V, VCC = Max.
IOH = –0.4mA
VOH
VOL
IOS
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
—
0.5
V
IOL = 4mA
–15
–100
mA
VOUT = 0V (maximum 1sec)
AC ELECTRICAL CHARACTERISTICS
VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to + 85°C
Symbol
fVCO
Parameter
Min.
750
—
Typ.
Max.
1250
—
Unit
MHz
%
Condition
fREFCLK * Byte Rate
Nominal
VCO Center Frequency
—
∆fVCO
VCO Center Frequency
Tolerance
5
tACQ
tCPWH
tCPWL
tir
Acquisition Lock Time
REFCLK Pulse Width HIGH
REFCLK Pulse Width LOW
REFCLK Input Rise Time
Output Duty Cycle (RCLK/TCLK)
ECL Output Rise/Fall Time
Recovered Clock Skew
Data Valid
—
—
—
—
0.5
—
—
—
—
—
15
—
µs
ns
4
4
—
ns
—
45
2
ns
tODC
tr, tf
55
% of UI
ps
100
500
+200
—
50Ω to VCC –2V (20% to 80%)
trskew
tDV
–200
ps
1/(2*fRCLK) – 200
1/(2*fRCLK) – 200
ps
tDH
Data Hold
—
ps
6
Micrel
SY87700L
TIMING WAVEFORMS
t
t
CPWH
CPWL
REFCLK
t
t
ODC
ODC
RCLK
t
SKEW
t
tDH
DV
RDOUT
7
Micrel
SY87700L
APPLICATION EXAMPLE
VCC
(R17 - R22)
5kΩ x 6
1
2
3
4
5
6
GND
R10
Q1
2N2222A
LED
D2
VCC
Ferrite Bead
BLM21A102
DIODE D1
Stand Off
R9
VCC
0.1µF FB1 22µF 0.1µF
22µF
1N4148
VCC
VCC
R7
C9
C8
C7
C6
1
2
3
VCCA
LFIN
VCC
CD
28
27
Capacitor Pads
(1206 format)
J1
R1
R3
R2
26
25
DIVSEL1
RDINP
DIVSEL2
RDOUTP
RDOUTN
VCCO
0.1µF
0.1µF
R8
C1
4
5
C14
C15
RDIN
RDINN
24
23
22
C2
R4
6
7
8
FREQSEL1
REFCLK
FREQSEL2
FREQSEL3
N/C
0.1µF
0.1µF
See Table 1
RCLKP
RCLKN
C16
C17
GND
21
9
VCCO 20
0.1µF
0.1µF
19
10
11
TCLKP
C18
C19
R5
80Ω
18
PLLSP
TCLKN
LOOP FILTER
NETWORK
C3
12
13
14
17
PLLSN
CLKSEL
1.5µF
R6 50Ω
If VCC = +5V:
R9 through R14 = 330Ω
16
15
PLLRP
PLLRN
GND
GND
C4
1.0µF
REFCLK
(TTL)
If VCC = +3.3V:
R9 through R14 = 220Ω
GND
NC
XTAL
Oscillator
VCC
14
C13
1
7
C5
Pin 1 (VCCA)
Pin 28 (VCC)
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
8
C10
C11
C12
VCC
120Ω
R23
Pin 23 (VCCO)
Pin 20 (VCCO)
NOTES:
1. For VCC = 3.3V
For AC coupling only
C1 = C2 = 0.1µF
R1 = R2 = 680Ω
R3 = R4 = 1kΩ
For DC mode only
C1 = C2 = Shorted
R1 = R2 = 130Ω
R3 = R4 = 82Ω
R8 = 12kΩ; R = 130Ω
2. For VCC = 5.0V
R8 = 24kΩ; R9 = 200Ω
Table 1.
8
Micrel
SY87700L
Material List
For Bypass and AC coupling capacitor, high quality factor
(High Q) capacitors are recommended. This will optimize
the performance of the device in high frequency domain.
The suggested dielectric characteristics for these capacitors
are NPO and/or COG. AVX is a suggested provider of
electronic components. www.avxcorp.com
Description
Component Part No.(1, 2)
SY87700L/SY87700V/SY87701L/SY87701V
U1
80Ω
PLLS+, R5
1.5µF
PLLS–, C3
50Ω
PLLR+, R6
1.0µF
PLLR–, C4
5kΩ or 4.7kΩ
Pull Up Resistor x 6, R17 – R22
330Ω or 220Ω (see schematic)
Output Pull Down Resistor, R11 – R16
4.7KΩ
Pull Up Resistor, R7
130Ω
Pull Up Resistor, R9
12kΩ
Pull Down Resistor, R8
12kΩ
R10
120Ω
R23
0.1µF
AC Coupling Capacitors x 6, C1, C2, C14 – C19
Tantalum, 22µF, 16V
0.1µF
Decoupling Capacitor, C6, C8
Decoupling Capacitors x 7, C5, C7, C9 – C13
Murata BLM21A102F
1N4148
Ferrite Bead, FB1
Diode, D1
SMAs x 9
Johnson SMAs, ID#142-0701-201
6-pin Dip switch
SW1
DPDT Slide Switch
LED
NOTES:
1. For VCC = 3.3V
R8 = 12kΩ; R = 130Ω
2. For VCC = 5.0V
R8 = 24kΩ; R9 = 200Ω
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
SY87700LZI
Z28-1
Industrial
Industrial
SY87700LHI
H32-1*
*Contact factory for availability.
9
Micrel
SY87700L
28 LEAD SOIC .300" WIDE (Z28-1)
Rev. 02
10
Micrel
SY87700L
32 LEAD EPAD TQFP (DIE UP) (H32-1)
Rev. 01
11
Micrel
SY87700L
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
12
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