SY89809ALTZTR [MICREL]
89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, TQFP-32;
| 型号： | SY89809ALTZTR |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 89809 SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, TQFP-32 时钟驱动器 |
| 文件： | 总4页 (文件大小：81K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V 1:9 HIGH-PERFORMANCE,
LOW-VOLTAGE
BUS CLOCK DRIVER
ClockWorks™
SY89809L
FEATURES
DESCRIPTION
■ 3.3V core supply, 1.8V output supply for reduced
The SY89809L is a High-Performance Bus Clock Driver
with 9 differential HSTL (High-Speed Transceiver Logic)
output pairs. The part is designed for use in low-voltage
(3.3V/1.8V) applications which require a large number of
outputs to drive precisely aligned, ultralow skew signals to
their destination. The input is multiplexed from either HSTL
or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic)
by the CLK_SEL pin. The Output Enable (OE) is
synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
power
■ LVPECL and HSTL inputs
■ 9 differential HSTL (low-voltage swing) output pairs
■ HSTL outputs drive 50Ω to ground with no
offset voltage
■ 500MHz maximum clock frequency
■ Low part-to-part skew (200ps max.)
■ Low pin-to-pin skew (50ps max.)
■ Available in 32-pin TQFP package
The SY89809L features low pin-to-pin skew (50ps max.)
and low part-to-part skew (200ps max.)—performance
previously unachievable in a standard product having such
a high number of outputs. The SY89809L is available in a
single space saving package, enabling a lower overall cost
solution.
PIN CONFIGURATION
32 31 30 29 28 27 26 25
24
23
22
21
VCCO
Q3
VCCI
HSTL_CLK
HSTL_CLK
CLK_SEL
1
2
3
Q3
APPLICATIONS
Top View
TQFP
T32-1
Q4
4
5
6
7
8
20
19
18
17
Q4
■ High-performance PCs
■ Workstations
LVPECL_CLK
LVPECL_CLK
GND
Q5
Q5
■ Parallel processor-based systems
■ Other high-performance computing
■ Communications
OE
VCCO
9
10 11 12 13 14 15 16
PIN NAMES
LOGIC SYMBOL
Pin
Function
Differential HSTL Inputs
LVPECL_CLK, /LVPECL_CLK Differential LVPECL Inputs
CLK_SEL
HSTL_CLK, /HSTL_CLK
HSTL_CLK
0
HSTL_CLK
9
CLK_SEL
OE
Input CLK Select (LVTTL)
Output Enable (LVTTL)
Differential HSTL Outputs
Ground
Q0 – Q8
9
Q0 – Q8
LVPECL_CLK
1
Q0-Q8, /Q0-/Q8
GND
LEN
D
LVPECL_CLK
Q
VCCI
VCC Core
OE
VCCO
VCC Output
Rev.: A
Amendment: /0
Issue Date: March 2000
1
ClockWorks™
Micrel
SY89809L
TRUTH TABLE
SIGNAL GROUPS
OE(1)
CLK_SEL
Q0 – Q8
LOW
/Q0 – /Q8
HIGH
Level
HSTL
Direction
Signal
0
0
1
1
0
1
0
1
Input
Output
Input
HSTL_CLK, /HSTL_CLK
Q0 – Q8, /Q0 – /Q8
LOW
HIGH
HSTL
HSTL_CLK
LVPECL_CLK
/HSTL_CLK
/LVPECL_CLK
LVPECL
LVPECL_CLK, /LVPECL_CLK
CLK_SEL, OE
LVCMOS/LVTTL
Input
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
HSTL_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCCI, VCCO
Rating
VCC Pin Potential to Ground Pin
Value
Unit
–0.5 to +4.0
–0.5 to VCCI
–50
V
V
VIN
Input Voltage
IOUT
Tstore
DC Output Current (Output HIGH)
Storage Temperature
mA
°C
–65 to +150
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = 0°C
Typ.
3.3
TA = +25°C
Typ.
TA = +70°C
Typ.
Symbol
VCCI
Parameter
Min.
3.0
1.6
—
Max.
3.6
Min.
3.0
1.6
—
Max.
3.6
Min.
3.0
1.6
—
Max.
3.6
Unit
V
VCC Core
3.3
3.3
VCCO
ICCI
VCC Output
ICC Core
1.8
2.0
1.8
2.0
1.8
2.0
V
115
140
115
140
115
140
mA
HSTL
TA = 0°C
TA = +25°C
TA = +70°C
Symbol
VOH
VOL
VIH
Parameter
Min.
1.0
Typ.
—
Max.
1.2
Min.
1.0
0
Typ.
—
Max.
1.2
Min.
1.0
0
Typ.
—
Max.
1.2
Unit
V
Output HIGH Voltage(1)
Output LOW Voltage(1)
Input HIGH Voltage
Input LOW Voltage
0
—
0.4
—
0.4
—
0.4
V
VX +0.1
–0.3
0.68
+20
—
—
1.6
VX +0.1
—
—
—
—
—
1.6
VX +0.1
—
—
—
—
—
1.6
V
VIL
—
VX –0.1 –0.3
VX –0.1 –0.3
VX –0.1
0.9
V
VX
Input Crossover Voltage
Input HIGH Current
Input LOW Current
—
0.9
0.68
+20
—
0.9
0.68
+20
—
V
IIH
—
–350
–500
–350
–500
–350
–500
µA
µA
IIL
—
NOTE:
1. Outputs loaded with 50Ω to ground.
2
ClockWorks™
Micrel
SY89809L
DC ELECTRICAL CHARACTERISTICS
LVPECL
TA = 0°C
Min. Max.
TA = +25°C
Min. Max.
TA = +70°C
Min. Max.
Symbol
VIH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Unit
V
VCCI – 1.165 VCCI – 0.880 VCCI – 1.165 VCCI – 0.880 VCCI – 1.165 VCCI – 0.880
VCCI – 1.810 VCCI – 1.475 VCCI – 1.810 VCCI – 1.475 VCCI – 1.810 VCCI – 1.475
VIL
V
IIH
—
+150
—
+150
—
+150
µA
µA
IIL
0.5
—
0.5
—
0.5
—
LVCMOS/LVTTL
TA = 0°C
TA = +25°C
TA = +70°C
Symbol
Parameter
Min.
Typ.
—
Max.
—
Min.
2.0
—
Typ.
—
Max.
—
Min.
2.0
—
Typ.
—
Max.
—
Unit
V
VIH
VIL
IIH
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
—
—
0.8
—
0.8
—
0.8
V
+20
—
—
–250
–600
+20
—
—
–250
–600
+20
—
—
–250
–600
µA
µA
IIL
—
—
—
AC ELECTRICAL CHARACTERISTICS(1)
TA = 0°C
TA = +25°C
Typ.
TA = +70°C
Typ.
Symbol
Parameter
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
Unit
tPHL
tPLH
Propagation Delay(2)
—
1.0
—
—
1.0
—
—
1.0
—
ns
fMAX
tskew
tskpp
VPP
Maximum Operating Freq.(3)
Within-Device Skew(4)
Part-to-Part Skew(5)
Minimum Input Swing(6)
LVPECL_CLK
500
—
—
—
—
—
—
50
500
—
—
—
—
—
—
50
500
—
—
—
—
—
—
50
MHz
ps
—
200
—
—
200
—
—
200
—
ps
600
600
600
mV
VCMR
Common Mode Range(7)
LVPECL_CLK
–1.5
—
–0.4
–1.5
—
–0.4
–1.5
—
–0.4
V
tS
tH
OE Set-Up Time(8)
1.0
0.5
300
—
—
—
—
—
1.0
0.5
—
—
—
—
—
1.0
0.5
—
—
—
—
—
ns
ns
ps
OE Hold Time
tr
tf
Output Rise/Fall Time
(20% – 80%)
800
300
800
300
800
NOTES:
1. Outputs loaded with 50Ω to ground. Airflow ≥ 300 LFPM.
2. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
3. Output swing greater than 450mV.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature.
6. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
7. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the
table are referenced to VCCI. The VIL level must be such that the peak-
to-peak voltage is less than 1.0V and greater than or equal to VPP
(min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR
PRODUCT ORDERING CODE
(min) will be fixed at 3.3V – |VCMR (min)|.
8. OE set-up time is defined with respect to the rising edge of the clock.
OE HIGH-to-LOW transition ensures outputs remain disabled during
the next clock cycle. OE LOW-to-HIGH transition enables normal
operation of the next input clock.
Ordering
Code
Package
Type
Operating
Range
SY89809LTC
T32-1
Commercial
3
ClockWorks™
Micrel
SY89809L
32 LEAD TQFP (T32-1)
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
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