SY89828LHI [MICREL]
3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX; 3.3V 1GHz双精度1:10 LVDS扇出缓冲器/翻译以2： 1输入MUX
| 型号： | SY89828LHI |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | 3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX |
| 文件： | 总13页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
3.3V 1GHz DUAL 1:10 PRECISION
LVDS FANOUT BUFFER/
TRANSLATOR WITH 2:1 INPUT MUX
®
Precision Edge
SY89828L
FEATURES
■ High-performance dual 1:10, 1GHz LVDS fanout
®
Precision Edge
buffer/translator
■ Two banks of 10 differential LVDS outputs
DESCRIPTION
■ Guaranteed AC parameters over temperature and
voltage:
• > 1GHz f
• < 50ps within device skew
• < 400ps t , t time
The SY89828L is a precision fanout buffer with 20
differential LVDS (Low Voltage Differential Swing) output
pairs. The part is designed for use in low voltage 3.3V
applications that require a large number of outputs to drive
precisely aligned, ultra low-skew signals to their destination.
The input is multiplexed from either LVDS or LVPECL (Low
Voltage Positive Emitter Coupled Logic) by the CLK_SEL1
and CLK_SEL2 pins. The Output Enables (OE1 and OE2)
are synchronous so that the outputs will only be enabled/
disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when
the device is enabled/disabled as can happen with an
asynchronous control.
MAX
r
f
■ Each bank includes a 2:1 input mux
■ 2:1 mux input accepts LVDS and LVPECL
■ Low jitter performance
• < 1ps
cycle-to-cycle jitter
RMS
• < 1ps total jitter
PP
■ 3.3V supply voltage
■ Output enable function
■ LVDS input includes internal 100Ω termination
■ Available in a 64-Pin EPAD-TQFP
The SY89828L features a low pin-to-pin skew of less
than 50ps—performance previously unachievable in a
standard product having such a high number of outputs.
The SY89828L is available in a single space saving package,
enabling a lower overall cost solution.
APPLICATIONS
■ Enterprise networking
■ High-end servers
■ Communications
TYPICAL APPLICATION CIRCUIT
100Ω
100Ω
5
5
Primary Clock Source
LVDS_CLKA
Primary
Card
/LVDS_CLKA
Backup Clock Source
5
5
LVDS_CLKB
Redundant
Card
/LVDS_CLKB
SEL1
Primary/Backup Clock Select
(Switchover with 2.0ns)
System using SY89828L as a switchover circuit from a Primary Clock to a Redundant backup Clock in a fail-safe application.
LVPECL inputs not shown in this application.
Precision Edge is a registered trademark of Micrel, Inc.
M9999-012208
Rev.: D
Amendment: /0
1
Issue Date: January 2008
hbwhelp@micrel.com or (408) 955-1690
Precision Edge®
SY89828L
Micrel, Inc.
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Package Operating
Package
Marking
Lead
Finish
Part Number
SY89828LHI(2)
Type
Range
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GNDO
Q7
/Q7
Q8
/Q8
SEL2
LVDS_CLKB
/LVDS_CLKB
1
2
3
H64-1
Industrial
SY89828LHI
SY89828LHI
Sn-Pb
Sn-Pb
VCCI
LVDS_CLKA
/LVDS_CLKA
CLK_SEL1
4
5
6
7
SY89828LHITR(2)
SY89828LHY(2)
H64-1
H64-1
Industrial
Industrial
Q9
/Q9
SY89828LHY with
Pb-Free bar-line indicator Matte-Sn
Pb-Free
VCCO
VCCO
Q10
/Q10
Q11
/Q11
Q12
/Q12
GNDO
LVPECL_CLKA
/LVPECL_CLKA
GNDI
8
9
10
11
12
13
14
15
16
OE1
LVPECL_CLKB
/LVPECL_CLKB
CLK_SEL2
SY89828LHYTR(2) H64-1
Industrial
SY89828LHY with Pb-Free
Pb-Free bar-line indicator Matte-Sn
OE2
Notes:
SEL1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Pb-Free package recommended for new designs.
64-Pin TQFP (H64-1)
FUNCTIONAL BLOCK DIAGRAM
100Ω termination
internal
CLK_SEL1
SEL1
OE1
LVDS_CLKA
/LVDS_CLKA
0
0
10
10
Q0 – Q9
LVPECL_CLKA
/LVPECL_CLKA
1
/Q0 – /Q9
1
LEN
D
Q
100Ω termination
internal
LVDS_CLKB
0
0
10
10
/LVDS_CLKB
Q10 – Q19
/Q10 – /Q19
1
LVPECL_CLKB
/LVPECL_CLKB
LEN
D
Q
1
CLK_SEL2
SEL2
OE2
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
2
Precision Edge®
SY89828L
MicreL, Inc.
PIN DESCRIPTIONS
Internal
P/U
Pin Number
Pin Name
I/O
Type
Pin Function
5, 6
LVDS_CLKA
/LVDS_CLKA
Input
LVDS
3.5kΩ
Pull-up
Differential clock input selected by CLK_SEL1, SEL1 and
SEL2. Can be left floating if not selected. Floating input, if
See Fig. 2 selected produces an indeterminate output. Has internal
100Ω termination.
2, 3
LVDS_CLKB
/LVDS_CLKB
Input
LVDS
3.5kΩ
Pull-up
Differential clock input selected by CLK_SEL1, SEL1 and
SEL2. Can be left floating if not selected. Floating input, if
See Fig. 2 selected produces an indeterminate output. Has internal
100Ω termination.
8, 9
LVPECL_CLKA Input LVPECL
/LVPECL_CLKA
75kΩ
pull-down
Differential clock input selected by CLK_SEL1, SEL1
and SEL2. Can be left floating. Floating input, if selected
See Fig. 1 produces a LOW at output. Requires external termination.
12, 13
LVPECL_CLKB Input LVPECL
/LVPECL_CLKB
75kΩ
pull-down
See Fig. 1
Differential clock input selected by CLK_SEL2, SEL1
and SEL2. Requires external termination.
7
CLK_SEL1
CLK_SEL2
SEL1
Input
Input
Input
Input
Input
Input
Power
LVTTL/
CMOS
11kΩ
Pull-up
Selects LVDS_CLKA input when LOW and
LVPECL_CLKA input when HIGH.
14
16
1
LVTTL/
CMOS
11kΩ
Pull-up
Selects LVDS_CLKB input when LOW and
LVPECL_CLKB input when HIGH.
LVTTL/
CMOS
11kΩ
Pull-up
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q0 – Q9 and /Q0 – /Q9.
SEL2
LVTTL/
CMOS
11kΩ
Pull-up
Selects input source CLKA when LOW and CLKB
when HIGH for outputs Q10 – Q19 and /Q10 – /Q19.
11
15
4
OE1
LVTTL/
CMOS
11kΩ
Pull-up
Enable input synchronized internally to prevent output
glitches or runt pulses.
OE2
LVTTL/
CMOS
11kΩ
Pull-up
Enable input synchronized internally to prevent output
glitches or runt pulses.
VCCI
Core VCC connected to 3.3V supply. Not connected to
VCCO internally. Connected to VCCO on PCB.
Bypass with 0.1µF in parallel with 0.01µF low ESR
capacitors as close to VCC pins as possible.
17, 32, 40,
41, 49, 64
VCCO
Power
Output buffer VCC connected to 3.3V suppy. Not connected
to VCCI internally. Connected to VCCI on PCB.
Bypass with 0.1µF in parallel with 0.01µF low ESR
capacitors as close to VCC pins as possible.
10
GNDI
GNDO
Power
Power
Output
Core ground not connected to GNDO internally.
To be connected to GNDO on PCB.
33, 48
Output buffer ground not connected to GNDI internally.
To be connected to GNDI on PCB.
63, 61, 59, 57, 55
53, 51, 47, 45, 43
Q0 – Q9
LVDS
LVDS
Differential clock outputs from CLKA when SEL1 = LOW
and from CLKB when SEL1 = HIGH. Q outputs are static
when OE1 = LOW. Unused output pair must be terminated
with 100Ω to maintain low jitter and skew.
62, 60, 58, 56, 54
52, 50, 46, 44, 42
/Q0 – /Q9
Output
Output
Differential clock outputs (complement) from CLKA when
SEL1 = LOW and from CLKB when SEL1 = HIGH. /Q
outputs are static HIGH when OE1 = LOW. Unused output
pairs must be externally terminated with 100Ω to maintain
low jitter and skew.
39, 37, 35, 31, 29
27, 25, 23, 21, 19
Q10 – Q19
LVDS
Differential outputs from CLKA when SEL2 = LOW and
from CLKB when SEL2 = HIGH. Q outputs are static LOW
when OE2 = LOW. Unused output pairs must be externally
terminated with 100Ω to maintain low jitter and skew.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
3
Precision Edge®
SY89828L
Micrel, Inc.
Internal
P/U
Pin Number
Pin Name
I/O
Type
Pin Function
38, 36, 34, 30, 28
26, 24, 22, 20, 18
/Q10 – /Q19
Output
LVDS
Differential outputs (complement) from CLKA when SEL2
= LOW and from CLKB when SEL2 = HIGH. /Q outputs
are static HIGH when OE2 = LOW. Unused output
pairs must be externally terminated with 100Ω to maintain
low jitter and skew.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
4
Precision Edge®
SY89828L
MicreL, Inc.
TRUTH TABLE
OE1(1) OE2(1) SEL1(1) SEL2(1) CLK_SEL1(1) CLK_SEL2(1)
Q0 – Q9
/Q0 – /Q9
Q10 – Q19
/Q10 – /Q19
1
1
1
1
0
0
0
0
0
1
X
X
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKA /LVPECL_CLKA
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB
LVDS_CLKB /LVDS_CLKB
LVPECL_CLKA /LVPECL_CLKA LVPECL_CLKB /LVPECL_CLKB
/LVDS_CLKB
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB
LVDS_CLKB /LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB /LVDS_CLKB LVDS_CLKB /LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB LVPECL_CLKB /LVPECL_CLKB
/LVDS_CLKB
LVDS_CLKA
/LVDS_CLKA
LVDS_CLKA
/LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA
1
1
1
1
1
1
1
1
X
X
0
1
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
1
X
X
0
1
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LVDS_CLKA
LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB /LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB
/LVDS_CLKA
X
X
1
1
1
1
0
0
0
0
0
0
1
1
X
X
X
X
0
1
X
X
0
1
LVDS_CLKA
/LVDS_CLKA
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LVPECL_CLKA /LVPECL_CLKA
LVDS_CLKB /LVDS_CLKB
LVPECL_CLKB /LVPECL_CLKB
LOW HIGH
X
X
0
0
X
X
X
X
LOW
HIGH
NOTE:
1. Input has internal pull-up so floating input = 1.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
5
Precision Edge®
SY89828L
Micrel, Inc.
Absolute Maximum Ratings(Note 1)
Operating Ratings(Note 2)
Power Supply Voltage (V , V
) ..............–0.5 to +4.0V
Supply Voltage ............................................... +3V to +3.6V
CCI CCO
Input Voltage (V ) ........................................... –0.5 to V
Ambient Temperature (T ) ......................... –40°C to +85°C
IN
CCI
A
Output Current (I
) ...............................................±10mA Package Thermal Resistance
OUT
TQFP (θ )
Exposed pad soldered to GND
Storage Temperature (T ) ........................... –65 to +150°C
JA
S
ESD Rating, Note 3 ...................................................... 1kV
Still-Air (multi-layer PCB).................................23°C/W
–200lfpm (multi-layer PCB) .............................18°C/W
–500lfpm (multi-layer PCB) .............................15°C/W
Exposed pad NOT soldered to GND (not recommened)
Still-Air (multi-layer PCB).................................44°C/W
–200lfpm (multi-layer PCB) .............................36°C/W
–500lfpm (multi-layer PCB) .............................30°C/W
TQFP (θ ) .........................................................4.4°C/W
JC
DC ELECTRICAL CHARACTERISTICS
Power Supply: TA = –40°C to +85°C
Symbol
VCCI, VCCO
ICCI
Parameter
Condition
Min
Typ
3.3
45
Max
3.6
Units
V
VCC Core, VCC Output
ICC Core
Note 4
3.0
Max. VCC
70
mA
mA
ICCO
ICC Output
No Load, Max. VCC
160
260
LVDS Input: VCC = 3.3V ±10%, TA = –40°C to +85°C
Symbol
VIN
Parameter
Condition
Min
0
Typ
Max
Units
V
Input Voltage Range
Differential Input Swing
Input LOW Current
2.4
VID
100
–1.25
80
mV
mA
Ω
IIL
RIN
LVDS Differential Input Resistance
(LVDS_CLK to /LVDS_CLK)
100
120
Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation
is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3. Devices are ESD sensitive. Handling precautions recommended.
Note 4.
V
and V
must be connected together on the PCB such that they remain at the same potential. V
and V
are not internally
CCI
CCO
CCI
CCO
connected on the die.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
6
Precision Edge®
SY89828L
MicreL, Inc.
DC ELECTRICAL CHARACTERISTICS
LVPECL Input: VCC = 3.3V ±10%, TA = –40°C to +85°C
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage (Single-Ended)
Input LOW Voltage
VCC –1.165
VCC –1.945
300
VCC –0.880
VCC –1.625
VIL
V
VPP
VCMR
IIH
Minimum Input Swing (LVPECL_CLK)
Note 5
mV
V
Common Mode Range (LVPECL_CLK) Note 6
Input HIGH Current
GNDI +1.8
VCCI –0.4
150
µA
µA
IIL
Input LOW Current
0.5
Note 5. The V (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
PP
Note 6.
V
is defined as the range within which the V level may vary, with the device still meeting the propagation delay specification. The
CMR IH
numbers in the table are referenced to V . The V level must be such that the peak-to-peak voltage is less than 1.0V and greater than or
CCI
IL
equal to V (min.). CMR range varies 1:1 with V . V (min) is fixed at GNDI + 1.8V.
PP
CCI
CMR
CMOS/LVTTL: VCC = 3.3V ±10%, TA = –40°C to +85°C
Symbol
VIH
Parameter
Condition
Min
Typ
Max
Units
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
2.0
VIL
0.8
V
IIH
VIN = VCC
VIN = 0.5V
150
µA
µA
IIL
–600
LVDS Output: VCC = 3.3V ±10%, TA = –40°C to +85°C
Symbol
VOD
Parameter
Condition
Note 7, 8
Note 7
Min
Typ
Max
400
Units
mV
V
Differential Output Voltage
Output HIGH Voltage
250
350
VOH
1.474
VOL
Output LOW Voltage
Note 7
0.925
1.125
–50
V
VOCM
∆VOCM
Output Common Mode Voltage
Change in Commom Mode Voltage
Note 8
1.375
50
V
mV
Note 7. Measured as per Figure 3, 100Ω across Q and /Q outputs.
Note 8. Measured as per Figure 4.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
7
Precision Edge®
SY89828L
Micrel, Inc.
(NOTE 1)
AC ELECTRICAL CHARACTERISTICS
VCC = 3.3V ±10%, TA = –40°C to +85°C, unless noted.
Symbol
Parameter
Condition
Note 2
Min
Typ
Max
Units
fMAX
Maximum Toggle Frequency
1.0
GHz
tPHL
tPLH
Differential Propagation Delay
Note 3
LVPECL Input: 150mV
LVPECL Input: 800mV
0.950
0.80
1.15
1.0
1.45
1.3
ns
ns
LVDS Input: 100mV
LVDS Input: 400mV
1.10
0.950
1.35
1.20
1.60
1.450
ns
ns
tSWITCHOVER Clock Input Switchover
CLK_SEL to Valid Output
1.55
1.85
ns
ns
ns
tS(OE)
tH(OE)
tSKEW
Output Enable Set-Up Time
Output Enable Hold Time
Within Device Skew
Note 4
Note 4
Note 5
1.0
0.5
0°C to +85°C
–40°C
25
35
50
75
ps
ps
Part-to-Part Skew
Note 6
400
ps
tJITTER
tr, tf
Cycle-to-Cycle
Total Jitter
Note 7
Note 8
<1
2
psRMS
psPP
<1
Output Rise/Fall Times
(20% to 80%)
200
290
400
ps
Note 1. 100Ω termination between Q and /Q outputs. Airflow ≥300lfpm, or exposed pad soldered to ground plane.
Note 2. is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Outut swing is > 200mV.
f
MAX
Note 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
Note 4. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
Note 5. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device identical input transition,
operating at the same voltage and temperature.
Note 6. Thepart-to-partskewisdefinedastheabsoluteworstcasedifferencebetweenanytwodelaypathsonanytwodevicesoperatingatthesamevoltage
and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
Note 7. Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. T
= Tn –Tn+1
JITTER_CC
where T is the time between rising edges of the output signal.
12
Note 8. Total jitter definition: with an ideal clock input, no more than one output edge in 10 output edges will deviate by more than the specified peak-
to-peak jitter value.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
8
Precision Edge®
SY89828L
MicreL, Inc.
TYPICAL OPERATING CHARACTERISTICS
(Conditions: V = 3.3V, T = 25°C, unless otherwise stated)
CC
A
Output Amplitude
vs. Frequency
Nominal Propagation Delay
vs. Temperature
500
450
400
350
300
250
200
150
100
50
2000
1800
1600
1400
1200
1000
800
LVPECL IN = 750mV
LVDS IN = 250mV
LVDS INPUT
LVPECL INPUT
600
400
200
0
0
0
200 400 600 800 1000 1200
FREQUENCY (MHz)
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
CLK_SEL Switchover Time
vs. Temperature
Propagation Delay
vs. Input Amplitude
2000
1800
1600
1400
1200
1000
800
1800
1600
1400
1200
1000
800
600
400
200
0
LVDS INPUT
LVPECL INPUT
600
400
200
0
0
200 400 600 800 1000
INPUT AMPLITUDE (mV)
-50 -25
0
25 50 75 100
TEMPERATURE (°C)
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
9
Precision Edge®
SY89828L
Micrel, Inc.
FUNCTIONAL CHARACTERISTICS
155MHz Output
622MHz Output
TA = 25°C
VCC = 3.3V
TA = 25°C
VCC = 3.3V
TIME (500ps/div.)
TIME (200ps/div.)
1GHz Output
TA = 25°C
VCC = 3.3V
TIME (100ps/div.)
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
10
Precision Edge®
SY89828L
MicreL, Inc.
LVPECL/LVDS INPUTS
VCC
1.9k
1.9k
1.4k
1.4k
LVDS_CLK
/LVDS_CLK
100Ω
GND
Figure 2. Simplified LVDS Input Stage
Figure 1. Simplified LVPECL Input Stage
LVDS OUTPUTS
LVDS stands for Low Voltage Differential Swing. LVDS between an LVDS driver and receiver. Also, change in
specifies a small swing of 350mV typical, on a nominal common mode voltage, as a function of data input, is also
1.25V common mode above ground. The common mode kept tight, to keep EMI low.
voltage has tight limits to permit large variations in ground
50Ω, ±1%
vOD
100Ω
vOH, vOL
vOCM
,
vOH, vOL
50Ω, ±1%
∆vOCM
GND
GND
Figure 3. LVDS Differential Measurement
Figure 4. LVDS Common Mode Measurement
QOUT
QOUT
750mV
QOUT – /QOUT
350mV
(typical)
/QOUT
/QOUT
Figure 5. Output Driver Signal Levels
(Single-Ended)
Figure 6. Output Driver Signal Levels
(Differential)
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
11
Precision Edge®
SY89828L
Micrel, Inc.
DETAILED DESCRIPTION
The SY89828L is a precision dual 1:10 fanout buffer. It CLK_SEL1, CLK_SEL2 TTL Inputs
allows either LVPECL or LVDS inputs, selectable by an
The CLK_SEL1 Input is used to select either LVDS_CLKA
(CLK_SEL1 is LOW) or LVPECL_CLKA (CLK_SEL1 is
HIGH). In a similar manner, The CLK_SEL2 Input is used
to select either LVDS_CLKB (CLK_SEL2 is LOW) or
LVPECL_CLKB (CLK_SEL2 is HIGH).
input muxes, and outputs 2 sets of 10 LVDS output pairs.
The device features 2 synchronous output enables. The
SY89828L provides extremely low skew across its outputs.
LVPECL_CLKA, LVPECL_CLKB
The SY89828L allows two inputs with standard LVPECL OE1, OE2 TTL Inputs
voltage swings. These inputs may be adjusted per the data
The SY89828L’s output enable functions are designed to
sheet characteristics regarding the CMR and minimum input
swing. As the SY89828L contains no appropriate internal
termination, upstream devices need to be properly
terminated to provide the proper LVPECL input swing. If
not being used (CLK_SEL1 and CLK_SEL2 are LOW), these
input pairs may be left floating, as they are internally
terminated to ground via 75kΩ pull-down resistors.
disable the outputs only when the outputs are LOW. The
OE1 TTL Input controls the Q0-Q9 outputs and OE2 controls
the Q10-Q19 outputs. This avoids the possibility of
generating runt pulses. The OE1 and OE2 inputs are
asynchronous inputs, but operate as synchronous enables.
For synchronous operation, please adhere to the specific
setup and hold times. When disabled, the Q outputs are
LOW and the /Q outputs are HIGH.
LVDS_CLKA, LVDS_CLKB
The SY89828L allows two inputs with standard LVDS Q0-Q9, Q10-Q19 LVDS Outputs
voltage swings. The SY89828L provides an appropriate
The SY89828L’s LVDS outputs swing typically 350mV
internal 100Ω termination resistor. Hence, upstream LVDS
devices do not require external termination to drive the
SY89828L. If not being used (CLK_SEL1 and CLK_SEL2
are HIGH), these inputs pair may be left floating.
around a 1.25V common mode voltage above ground. The
common mode voltage has tight limits to permit large
variations in ground between an LVDS driver and receiver.
Also, change in common mode voltage, as a function of
data input is kept tight to keep EMI low. Each of the
SY89828L’s LVDS outputs should be terminated with a 100Ω
termination resistor including any unused output pairs. This
ensures the best jitter and skew performance of the device.
In a similar manner, The SEL2 Input is used to select either
CLKA (SEL2 is LOW)or CLKB (SEL2 is HIGH) for the Q10-
Q19 differential output pairs.
SEL1, SEL2 TTL Inputs
The SEL1 Input is used to select either CLKA (SEL1 is
LOW) or CLKB (SEL1 is HIGH) for the Q0-Q9 differential
output pairs. In a similar manner, The SEL2 Input is used to
select either CLKA (SEL2 is LOW)or CLKB (SEL2 is HIGH)
for the Q10-Q19 differential output pairs.
RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION
Part Number Function
Data Sheet Link
SY55855V
SY89825U
Dual CML/PECL/LVPECL-to-LVDS Translator
www.micrel.com/product-info/products/sy55855v.shtml
2.5/3.3V 1:22 High-Performance, Low-Voltage PECL
Bus Clock Driver & Translator w/Internal Termination
www.micrel.com/product-info/products/sy89825u.shtml
www.micrel.com/product-info/products/sy89826u.shtml
SY89826U
SY89829U
M-0317
3.3V 1GHz Precision 1:22 LVDS Fanout Buffer
with 2:1 Input Mux
2.5/3.3V High-Performance, Dual 1:10 LVPECL Clock
Driver w/Internal Termination & Redundant Switchover www.micrel.com/product-info/products/sy89829u.shtml
HBW Solutions
www.micrel.com/product-info/products/solutions.shtml
www.amkor.com/products/notes_papers/ePad.pdf
Exposed pad Amkor Exposed Pad Application Note
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
12
Precision Edge®
SY89828L
MicreL, Inc.
64-PIN EPAD-TQFP (DIE UP) (H64-1)
+0.05
–0.05
+0.002
–0.002
+0.05
–0.05
+0.012
–0.012
+0.03
+0.15
–0.03
–0.15
+0.012
–0.012
+0.006
–0.006
+0.05
–0.05
Rev. 02
+0.002
–0.002
Package
EP- Exposed Pad
Die
CompSide Island
Heat Dissipation
Heat Dissipation
VEE
Heavy Copper Plane
Heavy Copper Plane
VEE
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
Package Notes:
Note 1. Package meets Level 3 qualifications.
Note 2. All parts are 100% baked and dry-packed before shipment.
Note 3. Exposedpadmustbesolderedtoagroundforproperthermalmanagement.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2002 Micrel, Incorporated.
M9999-012208
hbwhelp@micrel.com or (408) 955-1690
13
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