TLA-7T101LF [MICREL]
Gigabit Ethernet Transceiver with RGMII Support; 千兆以太网收发器，支持RGMII
| 型号： | TLA-7T101LF |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | Gigabit Ethernet Transceiver with RGMII Support |
| 文件： | 总56页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ9021RL/RN
Gigabit Ethernet Transceiver
with RGMII Support
General Description
Features
The KSZ9021RL is a completely integrated triple speed
(10Base-T/100Base-TX/1000Base-T) Ethernet Physical
Layer Transceiver for transmission and reception of data
over standard CAT-5 unshielded twisted pair (UTP) cable.
• Single-chip 10/100/1000Mbps IEEE 802.3 compliant
Ethernet Transceiver
• RGMII interface compliant to RGMII Version 1.3
• RGMII I/Os with 3.3V/2.5V tolerant and programmable
timings to adjust and correct delays on both Tx and Rx
paths
The KSZ9021RL provides the Reduced Gigabit Media
Independent Interface (RGMII) for direct connection to
RGMII MACs in Gigabit Ethernet Processors and Switches
for data transfer at 10/100/1000Mbps speed.
• Auto-negotiation to automatically select the highest link
up speed (10/100/100Mbps) and duplex (half/full)
The KSZ9021RL reduces board cost and simplifies board
layout by using on-chip termination resistors for the four
differential pairs and by integrating a LDO controller to
drive a low cost MOSFET to supply the 1.2V core.
• On-chip termination resistors for the differential pairs
• On-chip LDO controller to support single 3.3V supply
operation – requires only external FET to generate 1.2V
for the core
The KSZ9021RL provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ9021 I/Os and board.
Micrel LinkMD® TDR-based cable diagnostics permit
identification of faulty copper cabling. Remote and local
loopback functions provide verification of analog and
digital data paths.
• Jumbo frame support up to 16KB
• 125MHz Reference Clock Output
• Programmable LED outputs for link, activity and speed
• Baseline Wander Correction
• LinkMD® TDR-based cable diagnostics for identification
of faulty copper cabling
• Parametric NAND Tree support for fault detection
The KSZ9021RL is available in a 64-pin, lead-free E-LQFP
package, and is offered as the KSZ9021RN in the smaller
48-pin QFN package (See Ordering Information).
between chip I/Os and board.
• Loopback modes for diagnostics
____________________________________________________________________________________________________________
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
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More Features
Applications
• Automatic MDI/MDI-X crossover for detection and
• Laser/Network Printer
• Network Attached Storage (NAS)
• Network Server
• Gigabit LAN on Motherboard (GLOM)
• Broadband Gateway
• Gigabit SOHO/SMB Router
• IPTV
• IP Set-top Box
• Game Console
• Triple-play (data, voice, video) Media Center
• Media Converter
correction of pair swap at all speeds of operation
• Automatic detection and correction of pair swap, pair
skew and pair polarity
• MDC/MDIO Management Interface for PHY register
configuration
• Interrupt pin option
• Power down and power saving modes
• Operating Voltages
Core:
I/O:
Transceiver:
1.2V (external FET or regulator)
3.3V or 2.5V
3.3V
• Available packages
64-pin E-LQFP (10mm x 10mm): KSZ9021RL
48-pin QFN (7mm x 7mm):
KSZ9021RN
Ordering Information
Part Number
Temp. Range
0°C to 70°C
Package
Lead Finish
Description
KSZ9021RL
64-Pin E-LQFP
64-Pin E-LQFP
48-Pin QFN
Pb-Free
Pb-Free
Pb-Free
Pb-Free
RGMII, Commercial Temperature, 64-E-LQFP
RGMII, Industrial Temperature, 64-E-LQFP
RGMII, Commercial Temperature, 48-QFN
RGMII, Industrial Temperature, 48-QFN
KSZ9021RLI (1)
KSZ9021RN
KSZ9021RNI (1)
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
48-Pin QFN
Note:
1. Contact factory for lead time.
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Revision History
Revision
1.0
Date
Summary of Changes
1/16/09
10/13/09
Data sheet created.
1.1
Updated current consumption in Electrical Characteristics section.
Corrected data sheet omission of register 1 bit 8 for 1000Base-T Extended Status information.
Added the following register bits to provide further power saving during software power down: Tri-
state all digital I/Os (reg. 258.7), LDO disable (reg. 263.15), Low frequency oscillator mode (reg.
263.8).
Added KSZ9021RN device and updated entire data sheet accordingly.
Added 48-Pin QFN package information.
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Contents
Pin Configuration – KSZ9021RL..........................................................................................................................................8
Pin Description – KSZ9021RL..............................................................................................................................................9
Strapping Options – KSZ9021RL.......................................................................................................................................14
Pin Configuration – KSZ9021RN........................................................................................................................................15
Pin Description – KSZ9021RN ...........................................................................................................................................16
Strapping Options – KSZ9021RN ......................................................................................................................................21
Functional Overview...........................................................................................................................................................22
Functional Description: 10Base-T/100Base-TX Transceiver.........................................................................................23
100Base-TX Transmit....................................................................................................................................................... 23
100Base-TX Receive........................................................................................................................................................ 23
Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 23
10Base-T Transmit ........................................................................................................................................................... 23
10Base-T Receive ............................................................................................................................................................ 23
Functional Description: 1000Base-T Transceiver ..........................................................................................................24
Analog Echo Cancellation Circuit ..................................................................................................................................... 24
Automatic Gain Control (AGC) ......................................................................................................................................... 24
Analog-to-Digital Converter (ADC) ................................................................................................................................... 24
Timing Recovery Circuit.................................................................................................................................................... 25
Adaptive Equalizer............................................................................................................................................................ 25
Trellis Encoder and Decoder............................................................................................................................................ 25
Functional Description: 10/100/1000 Transceiver Features ..........................................................................................25
Auto MDI/MDI-X................................................................................................................................................................ 25
Pair- Swap, Alignment, and Polarity Check...................................................................................................................... 26
Wave Shaping, Slew Rate Control and Partial Response................................................................................................ 26
PLL Clock Synthesizer...................................................................................................................................................... 26
Auto-Negotiation.................................................................................................................................................................26
RGMII Interface....................................................................................................................................................................28
RGMII Signal Definition .................................................................................................................................................... 29
RGMII Signal Diagram...................................................................................................................................................... 29
RGMII In-band Status....................................................................................................................................................... 30
MII Management (MIIM) Interface.......................................................................................................................................30
Interrupt (INT_N)..................................................................................................................................................................30
LED Mode.............................................................................................................................................................................31
Single LED Mode.............................................................................................................................................................. 31
Tri-color Dual LED Mode .................................................................................................................................................. 31
NAND Tree Support ............................................................................................................................................................32
Power Management ............................................................................................................................................................33
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Power Saving Mode.......................................................................................................................................................... 33
Software Power Down Mode............................................................................................................................................ 33
Chip Power Down Mode................................................................................................................................................... 33
Register Map........................................................................................................................................................................33
Register Description...........................................................................................................................................................34
IEEE Defined Registers.................................................................................................................................................... 34
Vendor Specific Registers ................................................................................................................................................ 41
Extended Registers .......................................................................................................................................................... 44
Absolute Maximum Ratings...............................................................................................................................................46
Operating Ratings...............................................................................................................................................................46
Electrical Characteristic .....................................................................................................................................................46
Timing Diagrams.................................................................................................................................................................48
RGMII Timing.................................................................................................................................................................... 48
Auto-Negotiation Timing ................................................................................................................................................... 49
MDC/MDIO Timing ........................................................................................................................................................... 50
Reset Timing..................................................................................................................................................................... 51
Reset Circuit ........................................................................................................................................................................51
Reference Circuits – LED Strap-in Pins............................................................................................................................52
Reference Clock – Connection and Selection..................................................................................................................53
Magnetics Specification .....................................................................................................................................................53
Package Information...........................................................................................................................................................54
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List of Figures
Figure 1. KSZ9021RL/RN Block Diagram............................................................................................................................22
Figure 2: KSZ9021RL/RN 1000Base-T Block Diagram – Single Channel ..........................................................................24
Figure 3: Auto-Negotiation Flow Chart.................................................................................................................................27
Figure 4: KSZ9021RL/RN RGMII Interface..........................................................................................................................29
Figure 5. RGMII v1.3 Specification (Figure 2 – Multiplexing & Timing Diagram) ................................................................48
Figure 6. Auto-Negotiation Fast Link Pulse (FLP) Timing ...................................................................................................49
Figure 7. MDC/MDIO Timing................................................................................................................................................50
Figure 8. Reset Timing.........................................................................................................................................................51
Figure 9. Recommended Reset Circuit................................................................................................................................51
Figure 10. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output .....................................................52
Figure 11. Reference Circuits for LED Strapping Pins.........................................................................................................52
Figure 12. 25MHz Crystal / Oscillator Reference Clock Connection ...................................................................................53
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List of Tables
Table 1: MDI / MDI-X Pin Mapping ......................................................................................................................................25
Table 2: Auto-Negotiation Timers ........................................................................................................................................28
Table 3. RGMII Signal Definition..........................................................................................................................................29
Table 4: RGMII In-Band Status............................................................................................................................................30
Table 5. MII Management Frame Format – for KSZ9021RL/RN.........................................................................................30
Table 6: Single LED Mode – Pin Definition..........................................................................................................................31
Table 7: Tri-color Dual LED Mode – Pin Definition..............................................................................................................31
Table 8: NAND Tree Test Pin Order – for KSZ9021RL.......................................................................................................32
Table 9: NAND Tree Test Pin Order – for KSZ9021RN ......................................................................................................32
Table 10. RGMII v1.3 Specification (Timing Specifics from Table 2) ..................................................................................48
Table 11. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters...............................................................................49
Table 12. MDC/MDIO Timing Parameters...........................................................................................................................50
Table 13. Reset Timing Parameters ....................................................................................................................................51
Table 14. Reference Crystal/Clock Selection Criteria..........................................................................................................53
Table 15. Magnetics Selection Criteria ................................................................................................................................53
Table 16. Qualified Single Port 10/100/1000 Magnetics......................................................................................................53
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Pin Configuration – KSZ9021RL
64-Pin E-LQFP
(Top View)
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Pin Description – KSZ9021RL
Pin Number
Pin Name
Type(1)
Pin Function
1
TXRXP_A
I/O
Media Dependent Interface[0], positive signal of differential pair
1000Base-T Mode:
TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_A is the positive transmit signal (TX+) for MDI configuration and
the positive receive signal (RX+) for MDI-X configuration, respectively.
2
TXRXM_A
I/O
Media Dependent Interface[0], negative signal of differential pair
1000Base-T Mode:
TXRXM_A corresponds to BI_DA- for MDI configuration and BI_DB- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_A is the negative transmit signal (TX-) for MDI configuration and
the negative receive signal (RX-) for MDI-X configuration, respectively.
3
4
5
6
7
AGNDH
AVDDL
Gnd
P
Analog ground
1.2V analog VDD
1.2V analog VDD
3.3V analog VDD
AVDDL
P
AVDDH
TXRXP_B
P
I/O
Media Dependent Interface[1], positive signal of differential pair
1000Base-T Mode:
TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_B is the positive receive signal (RX+) for MDI configuration and
the positive transmit signal (TX+) for MDI-X configuration, respectively.
8
TXRXM_B
I/O
Media Dependent Interface[1], negative signal of differential pair
1000Base-T Mode:
TXRXM_B corresponds to BI_DB- for MDI configuration and BI_DA- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_B is the negative receive signal (RX-) for MDI configuration and
the negative transmit signal (TX-) for MDI-X configuration, respectively.
9
AGNDH
Gnd
I/O
Analog ground
10
TXRXP_C
Media Dependent Interface[2], positive signal of differential pair
1000Base-T Mode:
TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_C is not used.
11
TXRXM_C
I/O
Media Dependent Interface[2], negative signal of differential pair
1000Base-T Mode:
TXRXM_C corresponds to BI_DC- for MDI configuration and BI_DD- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_C is not used.
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Pin Number
Pin Name
AVDDL
Type(1)
Pin Function
12
13
14
P
P
1.2V analog VDD
AVDDL
1.2V analog VDD
TXRXP_D
I/O
Media Dependent Interface[3], positive signal of differential pair
1000Base-T Mode:
TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_D is not used.
15
TXRXM_D
I/O
Media Dependent Interface[3], negative signal of differential pair
1000Base-T Mode:
TXRXM_D corresponds to BI_DD- for MDI configuration and BI_DC- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_D is not used.
3.3V analog VDD
16
17
18
19
AVDDH
VSS
P
Gnd
Gnd
I/O
Digital ground
VSS
Digital ground
LED2 /
PHYAD1
LED Output:
Config Mode:
Programmable LED2 Output /
The pull-up/pull-down value is latched as PHYAD[1] during
power-up / reset. See “Strapping Options” section for details.
The LED2 pin is programmed by the LED_MODE strapping option (pin 55), and is
defined as follows.
Single LED Mode
Link
Pin State LED Definition
Link off
H
L
OFF
ON
Link on (any speed)
Tri-color Dual LED Mode
Link / Activity
Pin State
LED Definition
LED2
LED1
LED2
OFF
LED1
Link off
H
L
H
OFF
1000 Link / No Activity
H
ON
OFF
1000 Link / Activity (RX, TX) Toggle
H
Blinking
OFF
OFF
100 Link / No Activity
H
L
ON
100 Link / Activity (RX, TX)
10 Link / No Activity
H
Toggle
L
OFF
Blinking
ON
L
ON
10 Link / Activity (RX, TX)
Toggle
Toggle
Blinking
Blinking
For Tri-color Dual LED Mode, LED2 works in conjunction with LED1 (pin 21) to
indicate 10 Mbps Link and Activity.
20
DVDDH
P
3.3V / 2.5V digital VDD
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Pin Number
Pin Name
LED1 /
Type(1)
Pin Function
LED Output:
Config Mode:
21
I/O
Programmable LED1 Output /
PHYAD0
The pull-up/pull-down value is latched as PHYAD[0] during
power-up / reset. See “Strapping Options” section for details.
The LED1 pin is programmed by the LED_MODE strapping option (pin 55), and is
defined as follows.
Single LED Mode
Activity
Pin State LED Definition
No Activity
H
OFF
Activity (RX, TX)
Toggle
Blinking
Tri-color Dual LED Mode
Link / Activity
Pin State
LED Definition
LED2
LED1
LED2
OFF
LED1
Link off
H
L
H
OFF
1000 Link / No Activity
H
ON
OFF
1000 Link / Activity (RX, TX) Toggle
H
Blinking
OFF
OFF
100 Link / No Activity
H
L
ON
100 Link / Activity (RX, TX)
10 Link / No Activity
H
Toggle
L
OFF
Blinking
ON
L
ON
10 Link / Activity (RX, TX)
Toggle
Toggle
Blinking
Blinking
For Tri-color Dual LED Mode, LED1 works in conjunction with LED2 (pin 19) to
indicate 10 Mbps Link and Activity.
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DVDDL
VSS
P
1.2V digital VDD
Digital ground
Gnd
TXD0
I
RGMII Mode:
RGMII Mode:
RGMII Mode:
RGMII Mode:
Digital ground
1.2V digital VDD
RGMII TD0 (Transmit Data 0) Input
RGMII TD1 (Transmit Data 1) Input
RGMII TD2 (Transmit Data 2) Input
RGMII TD3 (Transmit Data 3) Input
TXD1
I
TXD2
I
TXD3
I
VSS
Gnd
DVDDL
DVDDH
TX_ER
GTX_CLK
TX_EN
VSS
P
P
3.3V / 2.5V digital VDD
I
RGMII Mode:
RGMII Mode:
RGMII Mode:
Digital ground
1.2V digital VDD
This pin is not used and should be left as a no connect.
I
I
RGMII TXC (Transmit Reference Clock) Input
RGMII TX_CTL (Transmit Control) Input
Gnd
P
DVDDL
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Pin Number
Pin Name
RXD3 /
Type(1)
Pin Function
RGMII Mode:
Config Mode:
36
I/O
RGMII RD3 (Receive Data 3) Output /
MODE3
The pull-up/pull-down value is latched as MODE3 during
power-up / reset. See “Strapping Options” section for details.
37
38
DVDDH
RXD2 /
MODE2
P
3.3V / 2.5V digital VDD
I/O
RGMII Mode:
Config Mode:
RGMII RD2 (Receive Data 2) Output /
The pull-up/pull-down value is latched as MODE2 during
power-up / reset. See “Strapping Options” section for details.
39
40
41
VSS
Gnd
P
Digital ground
1.2V digital VDD
RGMII Mode:
Config Mode:
DVDDL
RXD1 /
MODE1
I/O
RGMII RD1 (Receive Data 1) Output /
The pull-up/pull-down value is latched as MODE1 during
power-up / reset. See “Strapping Options” section for details.
42
43
RXD0 /
I/O
I/O
RGMII Mode:
Config Mode:
RGMII RD0 (Receive Data 0) Output /
MODE0
The pull-up/pull-down value is latched as MODE0 during
power-up / reset. See “Strapping Options” section for details.
RX_DV /
RGMII Mode:
Config Mode:
RGMII RX_CTL (Receive Control) Output /
CLK125_EN
Latched as CLK125_NDO Output Enable during power-up /
reset. See “Strapping Options” section for details.
44
45
46
DVDDH
RX_ER
P
O
3.3V / 2.5V digital VDD
RGMII Mode:
RGMII Mode:
Config Mode:
This pin is not used and should be left as a no connect.
RX_CLK /
PHYAD2
I/O
RGMII RXC (Receive Reference Clock) Output /
The pull-up/pull-down value is latched as PHYAD[2] during
power-up / reset. See “Strapping Options” section for details.
47
48
CRS
MDC
O
RGMII Mode:
This pin is not used and should be left as a no connect.
Ipu
Management Data Clock Input
This pin is the input reference clock for MDIO (pin 49).
Management Data Input / Output
49
MDIO
Ipu/O
This pin is synchronous to MDC (pin 48) and requires an external pull-up resistor
to 3.3V digital VDD in a range from 1.0KΩ to 4.7KΩ.
50
51
COL
O
O
RGMII Mode:
This pin is not used and should be left as a no connect.
INT_N
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up
resistor to 3.3V digital VDD in a range from 1.0KΩ to 4.7KΩ when active low.
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt
output to active low (default) or active high.
52
53
54
55
DVDDL
VSS
P
Gnd
P
1.2V digital VDD
Digital ground
DVDDL
1.2V digital VDD
CLK125_NDO /
I/O
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the MAC. /
LED_MODE
Config Mode:
The pull-up/pull-down value is latched as LED_MODE during
power-up / reset. See “Strapping Options” section for details.
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Pin Number
Pin Name
Type(1)
Pin Function
56
RESET_N
Ipu
Chip Reset (active low)
Hardware pin configurations are strapped-in at the de-assertion (rising edge) of
RESET_N. See “Strapping Options” section for more details.
57
LDO_O
O
On-chip 1.2V LDO Controller Output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the
chip’s core voltages. If 1.2V is provided by the system and this pin is not used, it
can be left floating.
58
59
AVDDL_PLL
XO
P
1.2V analog VDD for PLL
O
25MHz Crystal feedback
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm tolerance
60
XI
I
61
62
AVDDH
ISET
P
3.3V analog VDD
I/O
Set transmit output level
Connect a 4.99KΩ 1% resistor to ground on this pin.
Analog ground
63
64
AGNDH_BG
AVDDH
Gnd
P
3.3V analog VDD
E-PAD
E-PAD
Gnd
Exposed Pad on bottom of chip
Connect E-PAD to ground.
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up.
Ipu/O = Input with internal pull-up / Output.
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Strapping Options – KSZ9021RL
Type(1)
Pin Number
Pin Name
Pin Function
46
19
21
PHYAD2
PHYAD1
PHYAD0
I/O
The PHY Address, PHYAD[2:0], is latched at power-up / reset and is configurable to
any value from 1 to 7. Each PHY address bit is configured as follows:
I/O
Pull-up = 1
I/O
Pull-down = 0
PHY Address bits [4:3] are always set to ‘00’.
36
38
41
42
MODE3
MODE2
MODE1
MODE0
I/O
I/O
I/O
I/O
The MODE[3:0] strap-in pins are latched at power-up / reset and are defined as
follows:
MODE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
Mode
Reserved – not used
Reserved – not used
Reserved – not used
Reserved – not used
NAND Tree Mode
Reserved – not used
Reserved – not used
Chip Power Down Mode
Reserved – not used
Reserved – not used
Reserved – not used
Reserved – not used
RGMII Mode – advertise 1000Base-T full-duplex only
RGMII Mode – advertise 1000Base-T full and half-duplex only
RGMII Mode – advertise all capabilities (10/100/1000 speed
half/full duplex),except 1000Base-T half-duplex
1111
RGMII Mode – advertise all capabilities (10/100/1000 speed
half/full duplex)
43
55
CLK125_EN
LED_MODE
I/O
I/O
CLK125_EN is latched at power-up / reset and is defined as follows:
Pull-up = Enable 125MHz Clock Output
Pull-down = Disable 125MHz Clock Output
Pin 55 (CLK125_NDO) provides the 125MHz reference clock output option for use by
the MAC.
LED_MODE is latched at power-up / reset and is defined as follows:
Pull-up = Single LED Mode
Pull-down = Tri-color Dual LED Mode
Note:
1. I/O = Bi-directional.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to the incorrect
configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure the
PHY is configured to the correct pin strap-in mode.
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Pin Configuration – KSZ9021RN
48-Pin QFN
(Top View)
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Pin Description – KSZ9021RN
Pin Number
Pin Name
Type(1)
Pin Function
1
2
AVDDH
P
3.3V analog VDD
TXRXP_A
I/O
Media Dependent Interface[0], positive signal of differential pair
1000Base-T Mode:
TXRXP_A corresponds to BI_DA+ for MDI configuration and BI_DB+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_A is the positive transmit signal (TX+) for MDI configuration and
the positive receive signal (RX+) for MDI-X configuration, respectively.
3
TXRXM_A
I/O
Media Dependent Interface[0], negative signal of differential pair
1000Base-T Mode:
TXRXM_A corresponds to BI_DA- for MDI configuration and BI_DB- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_A is the negative transmit signal (TX-) for MDI configuration and
the negative receive signal (RX-) for MDI-X configuration, respectively.
4
5
AVDDL
P
1.2V analog VDD
TXRXP_B
I/O
Media Dependent Interface[1], positive signal of differential pair
1000Base-T Mode:
TXRXP_B corresponds to BI_DB+ for MDI configuration and BI_DA+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_B is the positive receive signal (RX+) for MDI configuration and
the positive transmit signal (TX+) for MDI-X configuration, respectively.
6
TXRXM_B
I/O
Media Dependent Interface[1], negative signal of differential pair
1000Base-T Mode:
TXRXM_B corresponds to BI_DB- for MDI configuration and BI_DA- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_B is the negative receive signal (RX-) for MDI configuration and
the negative transmit signal (TX-) for MDI-X configuration, respectively.
7
8
TXRXP_C
TXRXM_C
AVDDL
I/O
I/O
P
Media Dependent Interface[2], positive signal of differential pair
1000Base-T Mode:
TXRXP_C corresponds to BI_DC+ for MDI configuration and BI_DD+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_C is not used.
Media Dependent Interface[2], negative signal of differential pair
1000Base-T Mode:
TXRXM_C corresponds to BI_DC- for MDI configuration and BI_DD- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_C is not used.
1.2V analog VDD
9
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Pin Number
Pin Name
Type(1)
Pin Function
10
TXRXP_D
I/O
Media Dependent Interface[3], positive signal of differential pair
1000Base-T Mode:
TXRXP_D corresponds to BI_DD+ for MDI configuration and BI_DC+ for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_D is not used.
11
TXRXM_D
I/O
Media Dependent Interface[3], negative signal of differential pair
1000Base-T Mode:
TXRXM_D corresponds to BI_DD- for MDI configuration and BI_DC- for
MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_D is not used.
3.3V analog VDD
12
13
14
15
AVDDH
VSS_PS
DVDDL
LED2 /
P
Gnd
P
Digital ground
1.2V digital VDD
I/O
LED Output:
Config Mode:
Programmable LED2 Output /
PHYAD1
The pull-up/pull-down value is latched as PHYAD[1] during
power-up / reset. See “Strapping Options” section for details.
The LED2 pin is programmed by the LED_MODE strapping option (pin 41), and is
defined as follows.
Single LED Mode
Link
Pin State LED Definition
Link off
H
L
OFF
ON
Link on (any speed)
Tri-color Dual LED Mode
Link / Activity
Pin State
LED Definition
LED2
LED1
LED2
OFF
LED1
Link off
H
L
H
OFF
1000 Link / No Activity
H
ON
OFF
1000 Link / Activity (RX, TX) Toggle
H
Blinking
OFF
OFF
100 Link / No Activity
H
L
ON
100 Link / Activity (RX, TX)
10 Link / No Activity
H
Toggle
L
OFF
Blinking
ON
L
ON
10 Link / Activity (RX, TX)
Toggle
Toggle
Blinking
Blinking
For Tri-color Dual LED Mode, LED2 works in conjunction with LED1 (pin 17) to
indicate 10 Mbps Link and Activity.
16
DVDDH
P
3.3V / 2.5V digital VDD
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Pin Number
Pin Name
LED1 /
Type(1)
Pin Function
LED Output:
Config Mode:
17
I/O
Programmable LED1 Output /
PHYAD0
The pull-up/pull-down value is latched as PHYAD[0] during
power-up / reset. See “Strapping Options” section for details.
The LED1 pin is programmed by the LED_MODE strapping option (pin 41), and is
defined as follows.
Single LED Mode
Activity
Pin State LED Definition
No Activity
H
OFF
Activity (RX, TX)
Toggle
Blinking
Tri-color Dual LED Mode
Link / Activity
Pin State
LED Definition
LED2
LED1
LED2
OFF
LED1
Link off
H
L
H
OFF
1000 Link / No Activity
H
ON
OFF
1000 Link / Activity (RX, TX) Toggle
H
Blinking
OFF
OFF
100 Link / No Activity
H
L
ON
100 Link / Activity (RX, TX)
10 Link / No Activity
H
Toggle
L
OFF
Blinking
ON
L
ON
10 Link / Activity (RX, TX)
Toggle
Toggle
Blinking
Blinking
For Tri-color Dual LED Mode, LED1 works in conjunction with LED2 (pin 15) to
indicate 10 Mbps Link and Activity.
18
19
20
21
22
23
24
25
26
27
DVDDL
TXD0
P
1.2V digital VDD
I
I
RGMII Mode:
RGMII Mode:
RGMII Mode:
RGMII Mode:
1.2V digital VDD
RGMII Mode:
RGMII Mode:
1.2V digital VDD
RGMII Mode:
Config Mode:
RGMII TD0 (Transmit Data 0) Input
RGMII TD1 (Transmit Data 1) Input
RGMII TD2 (Transmit Data 2) Input
RGMII TD3 (Transmit Data 3) Input
TXD1
TXD2
I
TXD3
I
DVDDL
GTX_CLK
TX_EN
DVDDL
RXD3 /
MODE3
P
I
RGMII TXC (Transmit Reference Clock) Input
RGMII TX_CTL (Transmit Control) Input
I
P
I/O
RGMII RD3 (Receive Data 3) Output /
The pull-up/pull-down value is latched as MODE3 during
power-up / reset. See “Strapping Options” section for details.
28
RXD2 /
I/O
RGMII Mode:
Config Mode:
RGMII RD2 (Receive Data 2) Output /
MODE2
The pull-up/pull-down value is latched as MODE2 during
power-up / reset. See “Strapping Options” section for details.
29
30
31
VSS
Gnd
P
Digital ground
1.2V digital VDD
RGMII Mode:
Config Mode:
DVDDL
RXD1 /
MODE1
I/O
RGMII RD1 (Receive Data 1) Output /
The pull-up/pull-down value is latched as MODE1 during
power-up / reset. See “Strapping Options” section for details.
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Pin Number
Pin Name
RXD0 /
Type(1)
Pin Function
RGMII Mode:
Config Mode:
32
I/O
RGMII RD0 (Receive Data 0) Output /
MODE0
The pull-up/pull-down value is latched as MODE0 during
power-up / reset. See “Strapping Options” section for details.
33
RX_DV /
I/O
RGMII Mode:
Config Mode:
RGMII RX_CTL (Receive Control) Output /
CLK125_EN
Latched as CLK125_NDO Output Enable during power-up /
reset. See “Strapping Options” section for details.
34
35
DVDDH
RX_CLK /
PHYAD2
P
3.3V / 2.5V digital VDD
I/O
RGMII Mode:
Config Mode:
RGMII RXC (Receive Reference Clock) Output /
The pull-up/pull-down value is latched as PHYAD[2] during
power-up / reset. See “Strapping Options” section for details.
36
37
MDC
Ipu
Management Data Clock Input
This pin is the input reference clock for MDIO (pin 37).
Management Data Input / Output
MDIO
Ipu/O
This pin is synchronous to MDC (pin 36) and requires an external pull-up resistor
to 3.3V digital VDD in a range from 1.0KΩ to 4.7KΩ.
38
INT_N
O
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up
resistor to 3.3V digital VDD in a range from 1.0KΩ to 4.7KΩ when active low.
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt
output to active low (default) or active high.
39
40
41
DVDDL
DVDDH
P
P
1.2V digital VDD
3.3V / 2.5V digital VDD
CLK125_NDO /
I/O
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the MAC. /
LED_MODE
RESET_N
Config Mode:
The pull-up/pull-down value is latched as LED_MODE during
power-up / reset. See “Strapping Options” section for details.
42
43
Ipu
O
Chip Reset (active low)
Hardware pin configurations are strapped-in at the de-assertion (rising edge) of
RESET_N. See “Strapping Options” section for more details.
LDO_O
On-chip 1.2V LDO Controller Output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the
chip’s core voltages. If 1.2V is provided by the system and this pin is not used, it
can be left floating.
44
45
AVDDL_PLL
XO
P
1.2V analog VDD for PLL
O
25MHz Crystal feedback
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm tolerance
46
XI
I
47
48
AVDDH
ISET
P
3.3V analog VDD
I/O
Set transmit output level
Connect a 4.99KΩ 1% resistor to ground on this pin.
Exposed Paddle on bottom of chip
Connect P_GND to ground.
PADDLE
P_GND
Gnd
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Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up.
Ipu/O = Input with internal pull-up / Output.
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Strapping Options – KSZ9021RN
Type(1)
Pin Number
Pin Name
Pin Function
35
15
17
PHYAD2
PHYAD1
PHYAD0
I/O
The PHY Address, PHYAD[2:0], is latched at power-up / reset and is configurable to
any value from 1 to 7. Each PHY address bit is configured as follows:
I/O
Pull-up = 1
I/O
Pull-down = 0
PHY Address bits [4:3] are always set to ‘00’.
27
28
31
32
MODE3
MODE2
MODE1
MODE0
I/O
I/O
I/O
I/O
The MODE[3:0] strap-in pins are latched at power-up / reset and are defined as
follows:
MODE[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
Mode
Reserved – not used
Reserved – not used
Reserved – not used
Reserved – not used
NAND Tree Mode
Reserved – not used
Reserved – not used
Chip Power Down Mode
Reserved – not used
Reserved – not used
Reserved – not used
Reserved – not used
RGMII Mode – advertise 1000Base-T full-duplex only
RGMII Mode – advertise 1000Base-T full and half-duplex only
RGMII Mode – advertise all capabilities (10/100/1000 speed
half/full duplex),except 1000Base-T half-duplex
1111
RGMII Mode – advertise all capabilities (10/100/1000 speed
half/full duplex)
33
41
CLK125_EN
LED_MODE
I/O
I/O
CLK125_EN is latched at power-up / reset and is defined as follows:
Pull-up = Enable 125MHz Clock Output
Pull-down = Disable 125MHz Clock Output
Pin 41 (CLK125_NDO) provides the 125MHz reference clock output option for use by
the MAC.
LED_MODE is latched at power-up / reset and is defined as follows:
Pull-up = Single LED Mode
Pull-down = Tri-color Dual LED Mode
Note:
1. I/O = Bi-directional.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the RGMII signals to be latched to the incorrect
configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure the
PHY is configured to the correct pin strap-in mode.
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KSZ9021RL/RN
Functional Overview
The KSZ9021RL/RN is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer
Transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable.
Its on-chip proprietary 1000Base-T transceiver and Manchester/MLT-3 signaling-based 10Base-T/100Base-TX
transceivers are all IEEE 802.3 compliant.
The KSZ9021RL/RN reduces board cost and simplifies board layout by using on-chip termination resistors for the four
differential pairs and by integrating a LDO controller to drive a low cost MOSFET to supply the 1.2V core.
On the copper media interface, the KSZ9021RL/RN can automatically detect and correct for differential pair
misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential
pairs, as specified in the IEEE 802.3 standard for 1000Base-T operation.
The KSZ9021RL/RN provides the RGMII interface for a direct and seamless connection to RGMII MACs in Gigabit
Ethernet Processors and Switches for data transfer at 10/100/1000Mbps speed.
The following figure shows a high-level block diagram of the KSZ9021RL/RN.
Figure 1. KSZ9021RL/RN Block Diagram
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Functional Description: 10Base-T/100Base-TX Transceiver
100Base-TX Transmit
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT-3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the RGMII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized data
is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is set by
an external 4.99KΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the RGMII format and provided as the input data to the MAC.
Scrambler/De-scrambler (100Base-TX only)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
10Base-T Transmit
The output 10Base-T driver is incorporated into the 100Base-TX driver to allow transmission with the same magnetic.
They are internally wave-shaped and pre-emphasized into typical outputs of 2.5V amplitude. The harmonic contents are
at least 31 dB below the fundamental when driven by an all-ones Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in order to
prevent noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL
locks onto the incoming signal and the KSZ9021RL/RN decodes a data frame. The receiver clock is maintained active
during idle periods in between receiving data frames.
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Functional Description: 1000Base-T Transceiver
The 1000Base-T transceiver is based on a mixed-signal/digital signal processing (DSP) architecture, which includes the
analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision
clock recovery scheme, and power efficient line drivers.
The following figure shows a high-level block diagram of a single channel of the 1000Base-T transceiver for one of the
four differential pairs.
OTHER
CHANNELS
XTAL
Clk
Generation
Side-Stream Scrambler
&
TX
Signal
Symbol Encoder
Transmit
Block
PCS State Machines
LED Driver
Pair Swap
&
Analog
Hybrid
NEXT Canceller
Descrambler
Echo Canceller
Align Unit
+
Decoder
Baseline
Wander
Compensation
RX-
ADC
FFE
SLICER
+
RX
Signal
Clock & Phase
Recovery
DFE
MII
MII
Registers
Auto-Negotiation
Management
Control
PMA State
Machines
Figure 2. KSZ9021RL/RN 1000Base-T Block Diagram – Single Channel
Analog Echo Cancellation Circuit
In 1000Base-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit
relieves the burden of the ADC and the adaptive equalizer.
This circuit is disabled in 10Base-T/100Base-TX mode.
Automatic Gain Control (AGC)
In 1000Base-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal level.
This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.
Analog-to-Digital Converter (ADC)
In 1000Base-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential to
the overall performance of the transceiver.
This circuit is disabled in 10Base-T/100Base-TX mode.
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Timing Recovery Circuit
In 1000Base-T mode, the mixed-signal clock recovery circuit, together with the digital phase locked loop, is used to
recover and track the incoming timing information from the received data. The digital phase locked loop has very low long-
term jitter to maximize the signal-to-noise ratio of the receive signal.
The 1000Base-T slave PHY is required to transmit the exact receive clock frequency recovered from the received data
back to the 1000Base-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission.
Additionally, this helps to facilitate echo cancellation and NEXT removal.
Adaptive Equalizer
In 1000Base-T mode, the adaptive equalizer provides the following functions:
•
•
•
Detection for partial response signaling
Removal of NEXT and ECHO noise
Channel equalization
Signal quality is degraded by residual echo that is not removed by the analog hybrid and echo due to impedance
mismatch. The KSZ9021RL/RN employs a digital echo canceller to further reduce echo components on the receive signal.
In 1000Base-T mode, the data transmission and reception occurs simultaneously on all four pairs of wires (four channels).
This results in high frequency cross-talk coming from adjacent wires. The KSZ9021RL/RN employs three NEXT
cancellers on each receive channel to minimize the cross-talk induced by the other three channels.
In 10Base-T/100Base-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover
the channel loss from the incoming data.
Trellis Encoder and Decoder
In 1000Base-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5
symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one
KSZ9021RL/RN is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed,
pair skew, pair order and polarity have to be resolved through the logic. The incoming 4D-PAM5 data is then converted
into 9-bit symbols and then de-scrambled into 8-bit data.
Functional Description: 10/100/1000 Transceiver Features
Auto MDI/MDI-X
The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable
between the KSZ9021RL/RN and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the
link partner, and then assigns the MDI/MDI-X pair mapping of the KSZ9021RL/RN accordingly.
The following table shows the KSZ9021RL/RN 10/100/1000 pin-out assignments for MDI/MDI-X pin mapping.
MDI
100Base-TX
TX+/-
MDI-X
100Base-TX
RX+/-
Pin (RJ-45 pair)
1000Base-T
A+/-
10Base-T
TX+/-
1000Base-T
B+/-
10Base-T
RX+/-
TXRXP/M_A (1,2)
TXRXP/M_B (3,6)
TXRXP/M_C (4,5)
TXRXP/M_D (7,8)
B+/-
RX+/-
RX+/-
A+/-
TX+/-
TX+/-
C+/-
Not used
Not used
Not used
Not used
D+/-
Not used
Not used
Not used
Not used
D+/-
C+/-
Table 1. MDI / MDI-X Pin Mapping
Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 28 (1Ch) bit 6. MDI and MDI-X mode is
set by register 28 (1Ch) bit 7 if auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
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Pair- Swap, Alignment, and Polarity Check
In 1000Base-T mode, the KSZ9021RL/RN
•
•
Detects incorrect channel order and automatically restore the pair order for the A, B, C, D pairs (four channels)
Supports 50±10ns difference in propagation delay between pairs of channels in accordance with the IEEE 802.3
standard, and automatically corrects the data skew so the corrected 4-pairs of data symbols are synchronized
Incorrect pair polarities of the differential signals are automatically corrected for all speeds.
Wave Shaping, Slew Rate Control and Partial Response
In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to
minimize distortion and error in the transmission channel.
•
For 1000Base-T, a special partial response signaling method is used to provide the band-limiting feature for the
transmission path.
•
•
For 100Base-TX, a simple slew rate control method is used to minimize EMI.
For 10Base-T, pre-emphasis is used to extend the signal quality through the cable.
PLL Clock Synthesizer
The KSZ9021RL/RN generates 125MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from
the external 25MHz crystal or reference clock.
Auto-Negotiation
The KSZ9021RL/RN conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their own
capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest.
•
•
•
•
•
•
Priority 1: 1000Base-T, full-duplex
Priority 2: 1000Base-T, half-duplex
Priority 3: 100Base-TX, full-duplex
Priority 4: 100Base-TX, half-duplex
Priority 5: 10Base-T, full-duplex
Priority 6: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ9021RL/RN link partner is forced to bypass auto-negotiation for 10Base-T
and 100Base-TX modes, then the KSZ9021RL/RN sets its operating mode by observing the input signal at its receiver.
This is known as parallel detection, and allows the KSZ9021RL/RN to establish a link by listening for a fixed signal
protocol in the absence of auto-negotiation advertisement protocol.
The auto-negotiation link up process is shown in the following flow chart.
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Start Auto Negotiation
Parallel
Operation
No
Force Link Setting
Yes
Attempt Auto
Negotiation
Listen for 100BaseTX
Idles
Listen for 10BaseT Link
Pulses
Bypass Auto Negotiation
and Set Link Mode
No
Join Flow
Link Mode Set ?
Yes
Link Mode Set
Figure 3. Auto-Negotiation Flow Chart
For 1000Base-T mode, auto-negotiation is required and always used to establish link. During 1000Base-T auto-
negotiation, Master and Slave configuration is first resolved between link partners, and then link is established with the
highest common capabilities between link partners.
Auto-negotiation is enabled by default at power-up or after hardware reset. Afterwards, auto-negotiation can be enabled
or disabled through register 0 bit 12. If auto-negotiation is disabled, then the speed is set by register 0 bits 6 and 13, and
the duplex is set by register 0 bit 8.
If the speed is changed on the fly, then the link goes down and either auto-negotiation or parallel detection will initiate until
a common speed between KSZ9021RL/RN and its link partner is re-established for link.
If link is already established, and there is no change of speed on the fly, then the changes will not take effect unless either
auto-negotiation is restarted through register 0 bit 9, or a link down to link up transition occurs (i.e., disconnecting and
reconnecting the cable).
After auto-negotiation is completed, the link status is updated in register 1 and the link partner capabilities are updated in
registers 5, 6, and 10.
The auto-negotiation finite state machines employ interval timers to manage the auto-negotiation process. The duration of
these timers under normal operating conditions are summarized in the following table.
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Auto-Negotiation Interval Timers
Transmit Burst interval
Time Duration
16 ms
Transmit Pulse interval
68 us
FLP detect minimum time
FLP detect maximum time
Receive minimum Burst interval
Receive maximum Burst interval
Data detect minimum interval
Data detect maximum interval
NLP test minimum interval
NLP test maximum interval
Link Loss time
17.2 us
185 us
6.8 ms
112 ms
35.4 us
95 us
4.5 ms
30 ms
52 ms
Break Link time
1480 ms
830 ms
1000 ms
Parallel Detection wait time
Link Enable wait time
Table 2. Auto-Negotiation Timers
RGMII Interface
The Reduced Gigabit Media Independent Interface (RGMII) is compliant with the RGMII Version 1.3 Specification. It
provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:
•
•
•
•
Pin count is reduced from 24 pins for the IEEE Gigabit Media Independent Interface (GMII) to 12 pins for RGMII.
All speeds (10Mbps, 100Mbps, and 1000Mbps) are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 4-bit wide, a nibble.
In RGMII operation, the RGMII pins function as follow:
•
•
•
•
The MAC sources the transmit reference clock, TXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps and 2.5MHz
for 10Mbps.
The PHY recovers and sources the receive reference clock, RXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps
and 2.5MHz for 10Mbps.
For 1000Base-T, the transmit data, TXD[3:0], is presented on both edges of TXC, and the received data,
RXD[3:0], is clocked out on both edges of the recovered 125 MHz clock, RXC.
For 10Base-T/100Base-TX, the MAC will hold TX_CTL low until both PHY and MAC operate at the same speed.
During the speed transition, the receive clock will be stretched on either positive or negative pulse to ensure that
no clock glitch is presented to the MAC at any time.
•
TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These
two RGMII control signals are valid at the falling clock edge.
After power-up or reset, the KSZ9021RL/RN is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of
the RGMII mode capability options. See Strapping Options section for available options.
The KSZ9021RL/RN has the option to output a low jitter 125MHz reference clock on the CLK125_NDO pin. This clock
provides a lower cost reference clock alternative for RGMII MACs that require a 125MHz crystal or oscillator. The 125MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
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RGMII Signal Definition
The following table describes the RGMII signals. Refer to the RGMII Version 1.3 Specification for more detailed
information.
RGMII
RGMII
Pin Type
(with respect
to PHY)
Pin Type
(with respect
to MAC)
Signal Name Signal Name
Description
(per spec)
(per KSZ9021RL/RN)
TXC
GTX_CLK
Input
Output
Transmit Reference Clock
(125MHz for 1000Mbps, 25MHz for
100Mbps, 2.5MHz for 10Mbps)
TX_CTL
TXD[3:0]
RXC
TX_EN
Input
Output
Output
Input
Transmit Control
TXD[3:0]
RX_CLK
Input
Transmit Data [3:0]
Receive Reference Clock
Output
(125MHz for 1000Mbps, 25MHz for
100Mbps, 2.5MHz for 10Mbps)
RX_CTL
RXD[3:0]
RX_DV
Output
Output
Input
Input
Receive Control
RXD[3:0]
Receive Data [3:0]
Table 3. RGMII Signal Definition
RGMII Signal Diagram
The KSZ9021RL/RN RGMII pin connections to the MAC are shown in the following figure.
RGMII
KSZ9021RL/RN
Ethernet MAC
TXC
GTX_CLK
TX_EN
TX_CTL
TXD[3:0]
TXD[3:0]
RX_CLK
RX_DV
RXC
RX_CTL
RXD[3:0]
RXD[3:0]
Figure 4. KSZ9021RL/RN RGMII Interface
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RGMII In-band Status
The KSZ9021RL/RN can provide in-band status to the MAC during the inter-frame gap when RX_DV is de-asserted.
RGMII in-band status is disabled by default. It is enabled by writing a one to extended register 256 (100h) bit 8.
The in-band status is sent to the MAC using the RXD[3:0] data pins, and is described in the following table.
RX_DV
RXD3
RXD[2:1]
RXD0
Duplex Status
0 = half-duplex
RX_CLK clock speed
00 =2.5MHz
Link Status
0 = Link down
1 = Link up
0
(valid only when RX_DV 1 = full-duplex
is low and register 256
01 =25MHz
10 =125MHz
11 = reserved
bit 8 is set to 1)
Table 4. RGMII In-Band Status
MII Management (MIIM) Interface
The KSZ9021RL/RN supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9021RL/RN.
An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Further detail
on the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
•
•
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ9021RL/RN device. Each KSZ9021RL/RN device is assigned a PHY
address between 1 and 7 by the PHYAD[2:0] strapping pins.
•
A 32 register address space to access the KSZ9021RL/RN IEEE Defined Registers, Vendor Specific Registers
and Extended Registers. See Register Map section.
The following table shows the MII Management frame format for the KSZ9021RL/RN.
Preamble
Start of
Frame
Read/Write PHY
REG
TA
Data
Idle
OP Code
Address
Address
Bits [4:0]
RRRRR
RRRRR
Bits [15:0]
Bits [4:0]
00AAA
Read 32 1’s
01
01
10
01
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Z
Z
Write 32 1’s
00AAA
Table 5. MII Management Frame Format – for KSZ9021RL/RN
Interrupt (INT_N)
The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9021RL/RN PHY register. Bits [15:8] of register 27 (1Bh) are the interrupt control bits to enable and
disable the conditions for asserting the INT_N signal. Bits [7:0] of register 27 (1Bh) are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 27 (1Bh).
Bit 14 of register 31 (1Fh) sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ9021RL/RN control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
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LED Mode
The KSZ9021RL/RN provides two programmable LED output pins, LED2 and LED1, which are configurable to support
two LED modes. The LED mode is configured by the LED_MODE strap-in pin. It is latched at power-up/reset and is
defined as follows:
•
•
Pull-up:
Single LED Mode
Pull-down: Tri-color Dual LED Mode
Single LED Mode
In Single LED Mode, the LED2 pin indicates the link status while the LED1 pin indicates the activity status, as shown in
the following table.
LED pin
LED2
Pin State
LED Definition Link / Activity
H
OFF
Link off
L
ON
Link on (any speed)
No Activity
H
OFF
LED1
Toggle
Blinking
Activity (RX, TX)
Table 6. Single LED Mode – Pin Definition
Tri-color Dual LED Mode
In Tri-color Dual LED Mode, the Link and Activity status are indicated by the LED2 pin for 1000Base-T, by the LED1 pin
for 100Base-TX, and by both LED2 and LED1 pin, working in conjunction, for 10Base-T. This is summarized in the
following table.
LED Pin
LED Pin
(State)
(Definition)
Link / Activity
LED2
LED1
LED2
OFF
LED1
H
H
OFF
Link off
L
H
ON
OFF
1000 Link / No Activity
1000 Link / Activity (RX, TX)
100 Link / No Activity
100 Link / Activity (RX, TX)
10 Link / No Activity
10 Link / Activity (RX, TX)
Toggle
H
Blinking
OFF
OFF
H
L
ON
H
Toggle
L
OFF
Blinking
ON
L
ON
Toggle
Toggle
Blinking
Blinking
Table 7. Tri-color Dual LED Mode – Pin Definition
Each LED output pin can directly drive a LED with a series resistor (typically 220Ω to 470Ω).
For activity indication, the LED output toggles at approximately 12.5Hz (80ms) to ensure visibility to the human eye.
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NAND Tree Support
The KSZ9021RL/RN provides parametric NAND tree support for fault detection between chip I/Os and board. NAND tree
mode is enabled at power-up / reset with the MODE[3:0] strap-in pins set to 0100.
The following tables list the NAND tree pin order for KSZ9021RL and KSZ9021RN.
Pin
Description
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
LED2
LED1
TXD0
TXD1
TXD2
TXD3
TX_ER
GTX_CLK
TX_EN
RX_DV
RX_ER
RX_CLK
CRS
COL
INT_N
MDC
MDIO
CLK125_NDO
Table 8. NAND Tree Test Pin Order – for KSZ9021RL
Pin
Description
Input
LED2
LED1
Input
TXD0
Input
TXD1
Input
TXD2
Input
TXD3
Input
GTX_CLK
TX_EN
RX_DV
RX_CLK
INT_N
MDC
Input
Input
Input
Input
Input
Input
MDIO
Input
CLK125_NDO
Output
Table 9. NAND Tree Test Pin Order – for KSZ9021RN
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Power Management
The KSZ9021RL/RN offers the following power management modes:
Power Saving Mode
This mode is a KSZ9021RL/RN green feature to reduce power consumption when the cable is unplugged. It is in effect
when auto-negotiation mode is enabled and the cable is disconnected (no link).
Software Power Down Mode
This mode is used to power down the KSZ9021RL/RN device when it is not in use after power-up. Power down mode is
enabled by writing a one to register 0h bit 11. In the power down state, the KSZ9021RL/RN disables all internal functions,
except for the MII management interface. The KSZ9021RL/RN exits power down mode after writing a zero to register 0h
bit 11.
Chip Power Down Mode
This mode provides the lowest power state for the KSZ9021RL/RN when it is not in use and is mounted on the board.
Chip power down mode is enabled at power-up / reset with the MODE[3:0] strap-in pins set to 0111. The KSZ9021RL/RN
exits chip power down mode when a hardware reset is applied to the RESET_N pin with the MODE[3:0] strap-in pins set
to an operating mode other than chip power down mode.
Register Map
The IEEE 802.3 Specification provides a 32 register address space for the PHY. Registers 0 thru 15 are standard PHY
registers, defined per the specification. Registers 16 thru 31 are vendor specific registers.
The KSZ9021RL/RN uses the IEEE provided register space for IEEE Defined Registers and Vendor Specific Registers,
and uses the following registers to access Extended Registers:
•
•
•
Register 11 (Bh) for Extended Register – Control
Register 12 (Ch) for Extended Register – Data Write
Register 13 (Dh) for Extended Register – Data Read
Examples:
•
Extended Register Read
// Read from Operation Mode Strap Status Register
// Set register 259 (103h) for read
// Read register value
1. Write register 11 (Bh) with 0103h
2. Read register 13 (Dh)
•
Extended Register Write
// Write to Operation Mode Strap Override Register
// Set register 258 (102h) for write
1. Write register 11 (Bh) with 8102h
2. Write register 12 (Ch) with 0010h
// Write 0010h value to register to set NAND Tree mode
Register Number (Hex)
Description
IEEE Defined Registers
0 (0h)
1 (1h)
2 (2h)
3 (3h)
4 (4h)
5 (5h)
6 (6h)
7 (7h)
Basic Control
Basic Status
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
Auto-Negotiation Next Page
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Register Number (Hex)
8 (8h)
Description
Auto-Negotiation Link Partner Next Page Ability
1000Base-T Control
9 (9h)
10 (Ah)
1000Base-T Status
11 (Bh)
Extended Register – Control
Extended Register – Data Write
Extended Register – Data Read
Reserved
12 (Ch)
13 (Dh)
14 (Eh)
15 (Fh)
Extended – MII Status
Vendor Specific Registers
16 (10h)
Reserved
17 (11h)
Remote Loopback, LED Mode
LinkMD® – Cable Diagnostic
Digital PMA/PCS Status
Reserved
18 (12h)
19 (13h)
20 (14h)
21 (15h)
RXER Counter
22 (16h) – 26 (1Ah)
27 (1Bh)
Reserved
Interrupt Control/Status
Digital Debug Control 1
Reserved
28 (1Ch)
29 (1Dh) – 30 (1Eh)
31 (1Fh)
PHY Control
Extended Registers
256 (100h)
257 (101h)
258 (102h)
259 (103h)
260 (104h)
261 (105h)
263 (107h)
Common Control
Strap Status
Operation Mode Strap Override
Operation Mode Strap Status
RGMII Clock and Control Pad Skew
RGMII RX Data Pad Skew
Analog Test Register
Register Description
IEEE Defined Registers
Mode(1)
Address
Name
Description
Default
Register 0 (0h) – Basic Control
0.15
0.14
Reset
1 = Software PHY reset
RW/SC
0
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
1 = Loop-back mode
Loop-back
RW
0
0 = Normal operation
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Mode(1)
Address
Name
Description
Default
0.13
Speed Select
(LSB)
[0.6, 0.13]
RW
Hardware Setting
[1,1] = Reserved
[1,0] = 1000Mbps
[0,1] = 100Mbps
[0,0] = 10Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
0.12
0.11
Auto-
Negotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
RW
RW
1
0
If enabled, auto-negotiation result overrides
settings in register 0.13, 0.8 and 0.6.
Power Down
Isolate
1 = Power down mode
0 = Normal operation
0.10
0.9
1 = Electrical isolation of PHY from RGMII
0 = Normal operation
RW
0
0
Restart Auto-
Negotiation
1 = Restart auto-negotiation process
0 = Normal operation.
RW/SC
This bit is self-cleared after a ‘1’ is written to it.
1 = Full-duplex
0.8
Duplex Mode
Reserved
RW
Hardware Setting
0 = Half-duplex
0.7
0.6
RW
RW
0
0
Speed Select
(MSB)
[0.6, 0.13]
[1,1] = Reserved
[1,0] = 1000Mbps
[0,1] = 100Mbps
[0,0] = 10Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
0.5:0
Reserved
RO
RO
RO
RO
RO
RO
00_0000
Register 1 (1h) – Basic Status
1.15
1.14
1.13
1.12
1.11
100Base-T4
1 = T4 capable
0
1
1
1
1
0 = Not T4 capable
100Base-TX
Full Duplex
1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex
1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex
1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex
100Base-TX
Half Duplex
10Base-T Full
Duplex
10Base-T Half 1 = Capable of 10Mbps half-duplex
Duplex
0 = Not capable of 10Mbps half-duplex
1.10:9
1.8
Reserved
RO
RO
00
1
Extended
Status
1 = Extended Status Information in Reg. 15.
0 = No Extended Status Information in Reg. 15.
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Mode(1)
RO
Address
1.7
Name
Description
Default
Reserved
No Preamble
0
1
1.6
1 = Preamble suppression
RO
0 = Normal preamble
1.5
Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
RO
0
1.4
1.3
Remote Fault
1 = Remote fault
RO/LH
RO
0
1
0 = No remote fault
Auto-
Negotiation
Ability
1 = Capable to perform auto-negotiation
0 = Not capable to perform auto-negotiation
1.2
1.1
1.0
Link Status
1 = Link is up
RO/LL
RO/LH
RO
0
0
1
0 = Link is down
Jabber Detect
1 = Jabber detected
0 = Jabber not detected (default is low)
1 = Supports extended capabilities registers
Extended
Capability
Register 2 (2h) – PHY Identifier 1
2.15:0
PHY ID
Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
RO
0022h
Register 3 (3h) – PHY Identifier 2
3.15:10
PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
0001_01
10_0001
3.9:4
3.3:0
Model Number Six bit manufacturer’s model number
RO
RO
Revision
Number
Four bit manufacturer’s revision number
Indicates silicon revision
Register 4 (4h) – Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
RW
0
0 = No next page capability.
4.14
4.13
Reserved
RO
0
0
Remote Fault
1 = Remote fault supported
0 = No remote fault
RW
4.12
Reserved
Pause
RO
0
4.11:10
[4.11, 4.10]
RW
00
[0,0] = No PAUSE
[1,0] = Asymmetric PAUSE (link partner)
[0,1] = Symmetric PAUSE
[1,1] = Symmetric & Asymmetric PAUSE
(local device)
4.9
4.8
100Base-T4
1 = T4 capable
RO
0
1
0 = No T4 capability
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RW
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Mode(1)
Address
Name
Description
Default
4.7
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
[00001] = IEEE 802.3
RW
1
4.6
10Base-T
Full-Duplex
RW
RW
RW
1
4.5
10Base-T
Half-Duplex
1
4.4:0
Selector Field
0_0001
Register 5 (5h) – Auto-Negotiation Link Partner Ability
5.15
5.14
5.13
Next Page
1 = Next page capable
RO
RO
RO
0
0
0
0 = No next page capability
1 = Link code word received from partner
0 = Link code word not yet received
1 = Remote fault detected
Acknowledge
Remote Fault
0 = No remote fault
5.12
Reserved
Pause
RO
0
5.11:10
[5.11, 5.10]
RW
00
[0,0] = No PAUSE
[1,0] = Asymmetric PAUSE (link partner)
[0,1] = Symmetric PAUSE
[1,1] = Symmetric & Asymmetric PAUSE
(local device)
5.9
100Base-T4
1 = T4 capable
RO
RO
RO
RO
RO
RO
0
0 = No T4 capability
5.8
5.7
5.6
5.5
5.4:0
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
[00001] = IEEE 802.3
0
100Base-TX
Half-Duplex
0
10Base-T
Full-Duplex
0
10Base-T
Half-Duplex
0
Selector Field
0_0000
Register 6 (6h) – Auto-Negotiation Expansion
6.15:5
6.4
Reserved
RO
0000_0000_000
0
Parallel
Detection Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection.
1 = Link partner has next page capability
RO/LH
6.3
6.2
6.1
Link Partner
Next Page
Able
RO
0
1
0
0 = Link partner does not have next page
capability
Next Page
Able
1 = Local device has next page capability
RO
0 = Local device does not have next page
capability
Page Received 1 = New page received
0 = New page not received yet
RO/LH
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Mode(1)
Address
Name
Description
Default
6.0
Link Partner
Auto-
Negotiation
Able
1 = Link partner has auto-negotiation capability
RO
0
0 = Link partner does not have auto-negotiation
capability
Register 7 (7h) – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
RW
0
7.14
7.13
Reserved
RO
0
1
Message Page 1 = Message page
0 = Unformatted page
RW
7.12
7.11
Acknowledge2
1 = Will comply with message
RW
RO
0
0
0 = Cannot comply with message
Toggle
1 = Previous value of the transmitted link code
word equaled logic one
0 = Logic zero
7.10:0
Message Field
11-bit wide field to encode 2048 messages
RW
RO
RO
RO
RO
RO
000_0000_0001
Register 8 (8h) – Auto-Negotiation Link Partner Next Page Ability
8.15
8.14
8.13
8.12
8.11
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
0
0
0
0
0
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
Message Page 1 = Message page
0 = Unformatted page
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
Toggle
1 = Previous value of transmitted link code
word equal to logic zero
0 = Previous value of transmitted link code
word equal to logic one
8.10:0
Message Field
RO
000_0000_0000
Register 9 (9h) – 1000Base-T Control
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Mode(1)
Address
Name
Description
Default
9:15:13
Test Mode Bits Transmitter test mode operations
RW
000
[9.15:13]
[000]
Mode
Normal Operation
[001]
Test mode 1 –Transmit waveform
test
[010]
[011]
[100]
[101]
[110]
[111]
Test mode 2 –Transmit jitter test
in Master mode
Test mode 3 –Transmit jitter test
in Slave mode
Test mode 4 –Transmitter
distortion test
Reserved, operations not
identified
Reserved, operations not
identified
Reserved, operations not
identified
9.12
9.11
MASTER-
SLAVE
1 = Enable MASTER-SLAVE Manual
configuration value
RW
RW
0
0
Manual Config
Enable
0 = Disable MASTER-SLAVE Manual
configuration value
MASTER-
SLAVE
1 = Configure PHY as MASTER during
MASTER-SLAVE negotiation
Manual Config
Value
0 = Configure PHY as SLAVE during MASTER-
SLAVE negotiation
This bit is ignored if MASTER-SLAVE Manual
Config is disabled (register 9.12 = 0).
9.10
Port Type
1 = Indicate the preference to operate as
RW
0
multiport device (MASTER)
0 = Indicate the preference to operate as single-
port device (SLAVE)
This bit is valid only if the MASTER-SLAVE
Manual Config Enable bit is disabled (register
9.12 = 0).
9.9
1000Base-T
Full-Duplex
1 = Advertise PHY is 1000Base-T full-duplex
capable
RW
RW
1
0 = Advertise PHY is not 1000Base-T full-
duplex capable
9.8
1000Base-T
Half-Duplex
1 = Advertise PHY is 1000Base-T half-duplex
capable
Hardware Setting
0 = Advertise PHY is not 1000Base-T half-
duplex capable
9.7:0
Reserved
Write as 0, ignore on read
RO
Register 10 (Ah) – 1000Base-T Status
10.15
MASTER-
SLAVE
1 = MASTER-SLAVE configuration fault
detected
RO/LH/SC
0
configuration
fault
0 = No MASTER-SLAVE configuration fault
detected
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Mode(1)
Address
Name
Description
Default
10.14
MASTER-
SLAVE
1 = Local PHY configuration resolved to
MASTER
RO
0
configuration
resolution
0 = Local PHY configuration resolved to
SLAVE
10.13
10.12
Local
Receiver
Status
1 = Local Receiver OK (loc_rcvr_status = 1)
0 = Local Receiver not OK (loc_rcvr_status = 0)
RO
RO
0
0
Remote
Receiver
Status
1 = Remote Receiver OK (rem_rcvr_status = 1)
0 = Remote Receiver not OK (rem_rcvr_status
= 0)
10.11
A.10
LP 1000T FD
LP 1000T HD
Reserved
1 = Link Partner is capable of 1000Base-T full-
duplex
RO
RO
0
0
0 = Link Partner is not capable of 1000Base-T
full-duplex
1 = Link Partner is capable of 1000Base-T half-
duplex
0 = Link Partner is not capable of 1000Base-T
half-duplex
10.9:8
10.7:0
RO
00
Idle Error
Count
Cumulative count of errors detected when
receiver is receiving idles and
RO/SC
0000_0000
PMA_TXMODE.indicate = SEND_N.
The counter is incremented every symbol
period that rxerror_status = ERROR.
Register 11 (Bh) – Extended Register – Control
11.15
Extended
Register –
read/write
select
1 = Write Extended Register
0 = Read Extended Register
RW
0
11.14:9
11.8
Reserved
RW
RW
000_000
0
Extended
Register –
page
Select page for Extended Register
Select Extended Register Address
11.7:0
Extended
Register –
address
RW
0000_0000
Register 12 (Ch) – Extended Register – Data Write
12.15:0
Extended
Register –
write
16-bit value to write to Extend Register Address RW
in register 11 (Bh) bits [7:0]
0000_0000_0000_0000
Register 13 (Dh) – Extended Register – Data Read
13.15:0
Extended
Register –
read
16-bit value read from Extend Register Address RO
in register 11 (Bh) bits [7:0]
0000_0000_0000_0000
Register 15 (Fh) – Extended – MII Status
15.15
1000Base-X
Full-duplex
1 = PHY able to perform 1000Base-X
full-duplex
RO
0
0 = PHY not able to perform 1000Base-X
full-duplex
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Mode(1)
Address
Name
Description
Default
15.14
1000Base-X
Half-duplex
1 = PHY able to perform 1000Base-X
half-duplex
RO
0
0 = PHY not able to perform 1000Base-X
half-duplex
15.13
15.12
1000Base-T
Full-duplex
1 = PHY able to perform 1000Base-T
full-duplex 1000BASE-X
0 = PHY not able to perform 1000Base-T
full-duplex
RO
RO
RO
1
1
-
1000Base-T
Half-duplex
1 = PHY able to perform 1000Base-T
half-duplex
0 = PHY not able to perform 1000Base-T
half-duplex
15.11:0
Reserved
Ignore when read
Note:
1. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
Vendor Specific Registers
Mode(1)
Address
Name
Description
Default
Register 17 (11h) – Remote Loopback, LED Mode
17.15:9
17.8
Reserved
RW
RW
0000_001
0
Remote
Loopback
1 = Enable Remote Loopback
0 = Disable Remote Loopback
17.7:6
17.5:4
17.3
Reserved
Reserved
RW
RW
RW
11
11
0
LED Test
Enable
1 = Enable LED test mode
0 = Disable LED test mode
17.2:1
17.0
Reserved
Reserved
RW
RO
00
0
Register 18 (12h) – LinkMD® – Cable Diagnostic
18.15
Reserved
Reserved
Reserved
RW/SC
RW
0
18.14:8
18.7:0
000_0000
0000_0000
RO
Register 19 (13h) – Digital PMA/PCS Status
19.15:3
19.2
Reserved
RO/LH
RO
0000_0000_0000_0
0
1000Base-T
Link Status
1000 Base-T Link Status
1 = Link status is OK
0 = Link status is not OK
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Micrel, Inc.
KSZ9021RL/RN
Mode(1)
Address
Name
Description
Default
19.1
100Base-TX
Link Status
100 Base-TX Link Status
1 = Link status is OK
RO
0
0 = Link status is not OK
19.0
Reserved
RO
0
Register 21 (15h) – RXER Counter
21.15:0
RXER Counter Receive error counter for Symbol Error frames
RO/RC
RW
0000_0000_0000_0000
0
Register 27 (1Bh) – Interrupt Control/Status
27.15
27.14
27.13
27.12
27.11
Jabber
Interrupt
Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
Receive Error
Interrupt
Enable
1 = Enable Receive Error Interrupt
0 = Disable Receive Error Interrupt
RW
RW
RW
RW
0
0
0
0
Page Received 1 = Enable Page Received Interrupt
Interrupt
Enable
0 = Disable Page Received Interrupt
Parallel Detect 1 = Enable Parallel Detect Fault Interrupt
Fault Interrupt
Enable
0 = Disable Parallel Detect Fault Interrupt
Link Partner
Acknowledge
Interrupt
1 = Enable Link Partner Acknowledge Interrupt
0 = Disable Link Partner Acknowledge
Interrupt
Enable
27.10
27.9
27.8
Link Down
Interrupt
Enable
1 = Enable Link Down Interrupt
0 = Disable Link Down Interrupt
RW
RW
RW
0
0
0
Remote Fault
Interrupt
Enable
1 = Enable Remote Fault Interrupt
0 = Disable Remote Fault Interrupt
Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
0 = Disable Link Up Interrupt
27.7
27.6
27.5
27.4
27.3
Jabber
Interrupt
1 = Jabber occurred
RO/RC
RO/RC
RO/RC
RO/RC
RO/RC
0
0
0
0
0
0 = Jabber did not occurred
1 = Receive Error occurred
0 = Receive Error did not occurred
1 = Page Receive occurred
0 = Page Receive did not occurred
Receive Error
Interrupt
Page Receive
Interrupt
Parallel Detect 1 = Parallel Detect Fault occurred
Fault Interrupt
0 = Parallel Detect Fault did not occurred
Link Partner
Acknowledge
Interrupt
1 = Link Partner Acknowledge occurred
0 = Link Partner Acknowledge did not occurred
27.2
27.1
Link Down
Interrupt
1 = Link Down occurred
RO/RC
RO/RC
0
0
0 = Link Down did not occurred
1 = Remote Fault occurred
0 = Remote Fault did not occurred
Remote Fault
Interrupt
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Mode(1)
Address
Name
Description
Default
27.0
Link Up
Interrupt
1 = Link Up occurred
0 = Link Up did not occurred
RO/RC
0
Register 28 (1Ch) – Digital Debug Control 1
28.15:8
28.7
Reserved
mdi_set
RW
0000_0000
0
mdi_set has no function when swapoff (reg28.6) RW
is de-asserted.
1 = When swapoff is asserted, if mdi_set is
asserted, chip will operate at MDI mode.
0 = When swapoff is asserted, if mdi_set is de-
asserted, chip will operate at MDI-X mode.
28.6
swapoff
1 = Disable auto crossover function
0 = Enable auto crossover function
RW
0
28.5:1
28.0
Reserved
RW
RW
00_000
0
PCS Loopback 1 = Enable 10Base-T and 100Base-TX
Loopback for register 0h bit 14.
0 = normal function
Register 31 (1Fh) – PHY Control
31.15
31.14
Reserved
RW
RW
0
0
Interrupt Level
1 = Interrupt pin active high
0 = Interrupt pin active low
31.13:12
31.11:10
31.9
Reserved
RW
00
Reserved
RO/LH/RC 00
Enable Jabber
1 = Enable jabber counter
0 = Disable jabber counter
RW
1
31.8:7
31.6
Reserved
RW
RO
00
0
Speed status
1000Base-T
1 = Indicate chip final speed status at
1000Base-T
31.5
31.4
31.3
Speed status
100Base-TX
1 = Indicate chip final speed status at
100Base-TX
RO
RO
RO
0
0
0
Speed status
10Base-T
1 = Indicate chip final speed status at
10Base-T
Duplex status
Indicate chip duplex status
1 = Full-duplex
0 = Half-duplex
31.2
1000Base-T
Mater/Slave
status
1 = Indicate 1000Base-T Master mode
0 = Indicate 1000Base-T Slave mode
RO
0
31.1
31.0
Software
Reset
1 = Reset chip, except all registers
0 = Disable reset
RW
RO
0
0
Link Status
Check Fail
1 = Fail
0 = Not Failing
Note:
1. RW = Read/Write.
RC = Read-cleared
RO = Read only.
SC = Self-cleared.
LH = Latch high.
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Extended Registers
Mode(1)
Address
Name
Description
Default
Register 256 (100h) – Common Control
256.15:9
256.8
Reserved
RW
RW
0000_000
0
RGMII In-band 1 = Enable
PHY Status
0 = Disable
256.7:0
Reserved
RW
Register 257 (101h) – Strap Status
257.15:6
257.5
Reserved
RO
RO
CLK125_EN
status
1 = CLK125_EN strap-in is enabled
0 = CLK125_EN strap-in is disabled
Strapped-in value for PHY Address
257.4:0
PHYAD[4:0]
status
RO
Register 258 (102h) – Operation Mode Strap Override
258.15
258.14
258.13
258.12
RGMII all
capabilities
override
1 = Override strap-in for RGMII advertise all
capabilities
RW
RW
RW
RW
RGMII no
1000BT_HD
override
1 = Override strap-in for RGMII advertise all
capabilities except 1000Base-T half-duplex
RGMII
1000BT_H/FD
only override
1 = Override strap-in for RGMII advertise
1000Base-T full and half-duplex only
RGMII
1000BT_FD
only override
1 = Override strap-in for RGMII advertise
1000Base-T full-duplex only
258.11:8
258.7
Reserved
RW
RW
Tri-state all
digital I/Os
1 = Tri-state all digital I/Os for further power
saving during software power down
0
258.6:5
258.4
Reserved
RW
RW
NAND Tree
override
1 = Override strap-in for NAND Tree mode
258.3:0
Reserved
RW
RO
Register 259 (103h) – Operation Mode Strap Status
259.15
259.14
259.13
RGMII all
capabilities
strap-in status
1 = Strap to RGMII advertise all capabilities
RGMII no
1000BT_HD
strap-in status
1 = Strap to RGMII advertise all capabilities
except 1000Base-T half-duplex
RO
RO
RGMII only
1000BT_H/FD
strap-in status
1 = Strap to RGMII advertise 1000Base-T full
and half-duplex only
259.12
RGMII only
1000BT_FD
strap-in status
1 = Strap to RGMII advertise 1000Base-T full-
duplex only
RO
RO
259.11:5
Reserved
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Mode(1)
Address
Name
Description
Default
259.4
NAND Tree
1 = Strap to NAND Tree mode
RO
strap-in status
259.3:0
Reserved
RO
Register 260 (104h) – RGMII Clock and Control Pad Skew
260.15:12
260.11:8
260.7:4
rxc_pad_skew
RGMII RXC PAD Skew Control (0.2ns/step)
RW
0111
0111
0111
0111
rxdv_pad_skew RGMII RX_CTL PAD Skew Control (0.2ns/step) RW
txc_pad_skew
RGMII TXC PAD Skew Control (0.2ns/step)
RW
RW
260.3:0
txen_pad_skew RGMII TX_CTL PAD Skew Control (0.2ns/step)
Register 261 (105h) – RGMII RX Data Pad Skew
261.15:12
261.11:8
261.7:4
rxd3_pad_skew RGMII RXD3 PAD Skew Control (0.2ns/step)
RW
RW
RW
RW
0111
0111
0111
0111
rxd2_pad_skew RGMII RXD2 PAD Skew Control (0.2ns/step)
rxd1_pad_skew RGMII RXD1 PAD Skew Control (0.2ns/step)
rxd0_pad_skew RGMII RXD0 PAD Skew Control (0.2ns/step)
261.3:0
Register 263 (107h) – Analog Test Register
263.15
LDO disable
1 = LDO controller disable
0 = LDO controller enable
RW
0
263.14:9
263.8
Reserved
RW
RW
000_000
0
Low frequency
oscillator mode
1 = Low frequency oscillator mode enable
0 = Low frequency oscillator mode disable
Use for further power saving during software
power down.
263.7:0
Reserved
RW
0000_0000
Note:
1. RW = Read/Write.
RO = Read only.
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
Supply Voltage
(DVDDL, AVDDL, AVDDL_PLL)....... -0.5V to VDD+10%
(AVDDH).......................................... -0.5V to VDD +10%
(DVDDH)................................ -0.5V to VDD (3.3V)+10%
Input Voltage (all inputs) ........................ -0.5V to VDD +10%
Output Voltage (all outputs) ................... -0.5V to VDD +10%
Lead Temperature (soldering, 10sec.)....................... 260°C
Storage Temperature (Ts) ..........................-55°C to +150°C
(DVDDL, AVDDL, AVDDL_PLL).... +1.140V to +1.260V
(AVDDH)........................................ +3.135V to +3.465V
(DVDDH @ 3.3V) ..........................+3.135V to +3.465V
(DVDDH @ 2.5V) ..........................+2.375V to +2.625V
Ambient Temperature
(TA Commercial: KSZ9021RL/RN) ..........0°C to +70°C
(TA Industrial: KSZ9021RLI/RNI)..........-40°C to +85°C
Maximum Junction Temperature (TJ Max) ................. 125°C
Thermal Resistance (θJA)....................................31.85°C/W
Thermal Resistance (θJC)......................................8.07°C/W
Electrical Characteristics(3)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Supply Current – Core / Digital I/Os
ICORE
1.2V total of:
1000Base-T Link-up (no traffic)
528
563
158
158
7
mA
mA
mA
mA
mA
mA
mA
mA
mA
DVDDL (1.2V digital core) +
AVDDL (1.2V analog core) +
AVDDL_PLL (1.2V for PLL)
1000Base-T Full-duplex @ 100% utilization
100Base-TX Link-up (no traffic)
100Base-TX Full-duplex @ 100% utilization
10Base-T Link-up (no traffic)
10Base-T Full-duplex @ 100% utilization
Power Saving Mode (cable unplugged)
Software Power Down Mode (register 0.11 =1)
7
15
1.3
1.3
Chip Power Down Mode
(strap-in pins MODE[3:0] = 0111)
IDVDDH_2.5
2.5V for digital I/Os
1000Base-T Link-up (no traffic)
13
37
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
1000Base-T Full-duplex @ 100% utilization
100Base-TX Link-up (no traffic)
(RGMII operating @ 2.5V)
100Base-TX Full-duplex @ 100% utilization
10Base-T Link-up (no traffic)
9
2
10Base-T Full-duplex @ 100% utilization
Power Saving Mode (cable unplugged)
Software Power Down Mode (register 0.11 =1)
5
7
3
Chip Power Down Mode
1
(strap-in pins MODE[3:0] = 0111)
IDVDDH_3.3
3.3V for digital I/Os
1000Base-T Link-up (no traffic)
20
58
11
15
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
1000Base-T Full-duplex @ 100% utilization
100Base-TX Link-up (no traffic)
(RGMII operating @ 3.3V)
100Base-TX Full-duplex @ 100% utilization
10Base-T Link-up (no traffic)
10Base-T Full-duplex @ 100% utilization
Power Saving Mode (cable unplugged)
Software Power Down Mode (register 0.11 =1)
11
9
7
Chip Power Down Mode
1
(strap-in pins MODE[3:0] = 0111)
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October 2009
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Micrel, Inc.
KSZ9021RL/RN
Symbol
Parameter
Condition
Min
Typ
Max
Units
Supply Current – Transceiver (equivalent to current draw through external transformer center taps for PHY transceivers with
current-mode transmit drivers)
IAVDDH
3.3V for transceiver
1000Base-T Link-up (no traffic)
75
75
29
29
35
43
36
2
mA
mA
mA
mA
mA
mA
mA
mA
mA
1000Base-T Full-duplex @ 100% utilization
100Base-TX Link-up (no traffic)
100Base-TX Full-duplex @ 100% utilization
10Base-T Link-up (no traffic)
10Base-T Full-duplex @ 100% utilization
Power Saving Mode (cable unplugged)
Software Power Down Mode (register 0.11 =1)
Chip Power Down Mode
1
(strap-in pins MODE[3:0] = 0111)
TTL Inputs
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Current
2.0
2.4
V
V
0.8
10
VIN = GND ~ VDDIO
-10
µA
TTL Outputs
VOH
VOL
|Ioz|
Output High Voltage
IOH = -4mA
IOL = 4mA
V
V
Output Low Voltage
0.4
10
Output Tri-State Leakage
µA
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
Output Voltage Imbalance
Rise/Fall Time
0.95
1.05
V
%
ns
ns
ns
%
100Ω termination across differential output
100Ω termination across differential output
VIMB
tr, tf
2
5
3
0
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
0.5
± 0.25
5
VSET
Reference Voltage of ISET
Output Jitter
R(ISET) = 4.99K
Peak-to-peak
0.535
0.7
V
1.4
ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
Peak Differential Output Voltage
Jitter Added
2.2
2.8
3.5
V
100Ω termination across differential output
Peak-to-peak
ns
dB
Harmonic Rejection
Transmit all-one signal sequence
-31
10Base-T Receive
VSQ
Squelch Threshold
5MHz square wave
300
400
mV
Notes:
1. Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is
not implied. Maximum conditions for extended periods may affect reliability.
2. The device is not guaranteed to function outside its operating rating.
3. TA = 25°C. Specification is for packaged product only.
M9999-101309-1.1
October 2009
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Micrel, Inc.
KSZ9021RL/RN
Timing Diagrams
RGMII Timing
The KSZ9021RL/RN RGMII timing conforms to the timing requirements per the RGMII Version 1.3 Specification.
Figure 5. RGMII v1.3 Specification (Figure 2 – Multiplexing and Timing Diagram)
Timing Parameter
TskewT
Description
Min
-500
1
Typ
Max
500
2.6
8.8
Unit
ps
Data to Clock output Skew (at Transmitter)
Data to Clock input Skew (at Receiver)
Clock Cycle Duration for 1000Base-T
TskewR
ns
Tcyc (1000Base-T)
7.2
36
8
ns
Tcyc (100Base-TX) Clock Cycle Duration for 100Base-TX
Tcyc (10Base-T) Clock Cycle Duration for 10Base-T
40
44
ns
360
400
440
ns
Table 10. RGMII v1.3 Specification (Timing Specifics from Table 2)
Accounting for TskewT, the TskewR specification in the above table requires the PCB board design to incorporate clock
routing for TXC and RXC with an additional trace delay of greater than 1.5ns and less than 2.1ns for 1000Base-T. For
10Base-T/100Base-TX, the maximum delay is much greater than the 2.1ns for 1000Base-T, and thus is not specified.
M9999-101309-1.1
October 2009
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Micrel, Inc.
KSZ9021RL/RN
Auto-Negotiation Timing
Auto-Negotiation
Fast Link Pulse (FLP) Tim ing
FLP
FLP
Burst
Burst
TX+/TX-
tFLPW
tBTB
Clock
Pulse
Data
Pulse
Clock
Pulse
Data
Pulse
TX+/TX-
tPW
tPW
tCTD
tCTC
Figure 6. Auto-Negotiation Fast Link Pulse (FLP) Timing
Timing Parameter
Description
Min
Typ
16
Max
Units
ms
ms
ns
tBTB
tFLPW
tPW
FLP Burst to FLP Burst
FLP Burst width
8
24
2
Clock/Data Pulse width
Clock Pulse to Data Pulse
Clock Pulse to Clock Pulse
100
64
tCTD
tCTC
55.5
111
17
69.5
139
33
µs
128
µs
Number of Clock/Data Pulse per
FLP Burst
Table 11. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
M9999-101309-1.1
October 2009
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Micrel, Inc.
KSZ9021RL/RN
MDC/MDIO Timing
tP
MDC
tMD1
tMD2
MDIO
(PHY input)
Valid
Data
Valid
Data
tMD3
MDIO
(PHY output)
Valid
Data
Figure 7. MDC/MDIO Timing
Timing Parameter
Description
Min
Typ
Max
Unit
ns
tP
MDC period
400
t1MD1
tMD2
tMD3
MDIO (PHY input) setup to rising edge of MDC
MDIO (PHY input) hold from rising edge of MDC
MDIO (PHY output) delay from rising edge of MDC
10
10
0
ns
ns
ns
Table 12. MDC/MDIO Timing Parameters
M9999-101309-1.1
October 2009
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Micrel, Inc.
KSZ9021RL/RN
Reset Timing
The recommended KSZ9021RL/RN power-up reset timing is summarized in the following figure and table.
Supply
Voltage
tsr
RESET_N
Figure 8. Reset Timing
Parameter
Description
Min
Max
Units
tsr
Stable supply voltage to reset high
10
ms
Table 13. Reset Timing Parameters
After the de-assertion of reset, it is recommended to wait a minimum of 100µs before starting programming on the MIIM
(MDC/MDIO) Interface.
Reset Circuit
The following reset circuit is recommended for powering up the KSZ9021RL/RN if reset is triggered by the power supply.
3.3V
D1: 1N4148
D1
R 10K
KSZ9021RL/RN
RESET_N
C 10uF
Figure 9. Recommended Reset Circuit
M9999-101309-1.1
October 2009
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Micrel, Inc.
KSZ9021RL/RN
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA).
At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ9021RL/RN device. The
RST_OUT_n from CPU/FPGA provides the warm reset after power up.
3.3V
R 10K
D1
KSZ9021RL/RN
CPU/FPGA
RESET_N
RST_OUT_n
D2
C 10uF
D1, D2: 1N4148
Figure 10. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Reference Circuits – LED Strap-in Pins
The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in the
following figure.
Figure 11. Reference Circuits for LED Strapping Pins
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Micrel, Inc.
KSZ9021RL/RN
Reference Clock – Connection and Selection
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9021RL/RN.
The reference clock is 25 MHz for all operating modes of the KSZ9021RL/RN.
The following figure and table shows the reference clock connection to pins XI and XO of the KSZ9021RL/RN, and the
reference clock selection criteria.
22pF
22pF
XI
XI
25MHz OSC
+/-50ppm
22pF
22pF
NC
XO
XO
NC
25MHz XTAL
+/-50ppm
Figure 12. 25MHz Crystal / Oscillator Reference Clock Connection
Characteristics
Value
25
Units
MHz
ppm
Frequency
Frequency tolerance (max)
±50
Table 14. Reference Crystal/Clock Selection Criteria
Magnetics Specification
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes
is recommended for exceeding FCC requirements.
The following tables provide recommended magnetic characteristics and a list of qualified magnetics for the
KSZ9021RL/RN.
Parameter
Value
Test Condition
Turns ratio
1 CT : 1 CT
350µH
Open-circuit inductance (min.)
Insertion loss (max.)
HIPOT (min.)
100mV, 100kHz, 8mA
0MHz – 100MHz
1.0dB
1500Vrms
Table 15. Magnetics Selection Criteria
Magnetic Manufacturer
Part Number
H5007NL
Auto MDI-X
Yes
Number of Port
Pulse
TDK
1
1
TLA-7T101LF
Yes
Table 16. Qualified Single Port 10/100/1000 Magnetics
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Micrel, Inc.
KSZ9021RL/RN
Package Information
48-Pin (7mm x 7mm) QFN
M9999-101309-1.1
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Micrel, Inc.
KSZ9021RL/RN
64-Pin (10mm x 10mm) E-LQFP (V)
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Micrel, Inc.
KSZ9021RL/RN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility
is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without
notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems
where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems
are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose
failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of
Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to
fully indemnify Micrel for any damages resulting from such use or sale.
© 2009 Micrel, Incorporated.
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