24AA164P [MICROCHIP]

16K 1.8V Cascadable I2CTM Serial EEPROM; 16K 1.8V I2C？级联串行EEPROM


型号：	24AA164P
厂家：	MICROCHIP
描述：	16K 1.8V Cascadable I2CTM Serial EEPROM 16K 1.8V I2C？级联串行EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：125K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24AA164

2 ™

16K 1.8V Cascadable I C Serial EEPROM

FEATURES

PACKAGE TYPES

PDIP

• Single supply with operation down to 1.8V

• Low power CMOS technology

VCC

- 1 mA active current typical

- 10 µA standby current typical at 5.5V

- 5 µA standby current typical at 3.0V

• Organized as 8 blocks of 256 bytes (8 x 256 x 8)

• 2-wire serial interface bus, I C compatible

SCL

SDA

• Functional address inputs for cascading up to 8

devices

VSS

• Schmitt trigger, ﬁltered inputs for noise suppres-

sion

• Output slope control to eliminate ground bounce

• 100 kHz (1.8V) and 400 kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

8-lead

SOIC

VCC

• 1,000,000 Erase/Write cycles guaranteed

• Data retention > 200 years

• 8-pin DIP, 8-lead SOIC packages

• Available for commercial temperature range

SCL

SDA

VSS

- Commercial (C):

0°C to +70°C

BLOCK DIAGRAM

DESCRIPTION

The Microchip Technology Inc. 24AA164 is a cascad-

able 16K bit Electrically Erasable PROM. The device is

organized as eight blocks of 256 x 8-bit memory with a

2-wire serial interface. Low voltage design permits

operation down to 1.8 volts (end-of-life voltage for most

popular battery technologies) with standby and active

currents of only 5 µA and 1 mA respectively. The

24AA164 also has a page-write capability for up to 16

bytes of data.The 24AA164 is available in the standard

8-pin DIP and 8-lead surface mount SOIC packages.

A0 A1 A2

HV GENERATOR

I/O

CONTROL

LOGIC

MEMORY

CONTROL

LOGIC

EEPROM ARRAY

(8 x 256 x 8)

XDEC

PAGE LATCHES

SDA

SCL

YDEC

The three select pins, A0, A1, and A2, function as chip

select inputs and allow up to eight devices to share a

common bus, for up to 128K bits total system

EEPROM.

SENSE AMP

R/W CONTROL

VCC

VSS

I²C is a trademark of Philips Corporation.

1999 Microchip Technology Inc.

DS21100F-page 1

24AA164

TABLE 1-1:

Name

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

VSS

SDA

Ground

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS.................. -0.3V to VCC +1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins..................................................≥ 4 kV

Serial Address/Data I/O

Serial Clock

SCL

Write Protect Input

1.8V to 6.0V Power Supply

Chip Address Inputs

VCC

A0, A1, A2

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-2:

DC CHARACTERISTICS

VCC = 1.8V to +6.0

Commercial (C): Tamb = 0˚C to +70˚C

Parameter

Symbol

Min

Typ

Max Units

Conditions

WP, SCL and SDA pins:

High level input voltage

VIH

VIL

.7 VCC

—

.3 VCC

—

Low level input voltage

Hysteresis of Schmitt trigger inputs

Low level output voltage

Input leakage current

VHYS

VOL

ILI

.05 VCC

—

(Note)

.40

I^OL= 3.0 mA, V^CC= 1.8V

V^IN= .1V to V^CC

-10

µA

Output leakage current

ILO

-10

V^OUT= .1V to V^CC

Pin capacitance

(all inputs/outputs

CIN,

COUT

—

pF VCC = 5.0V (Note 1)

Tamb = 25˚C, FCLK = 1 MHz

Operating current

ICC Write

—

0.5

—

mA VCC = 5.5V, SCL = 400 kHz

mA VCC = 1.8V, SCL = 100 kHz

mA VCC = 5.5V, SCL = 400 kHz

mA VCC = 1.8V, SCL = 100 kHz

ICC Read

0.05

—

Standby current

ICCS

—

100

—

µA VCC = 5.5V, SDA = SCL=V^CC

µA VCC = 3.0V, SDA = SCL=VCC

µA VCC = 1.8V, SDA = SCL=VCC

WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

THD:STA

TSU:STA

TSU:STO

SDA

START

STOP

DS21100F-page 2

1999 Microchip Technology Inc.

24AA164

TABLE 1-3:

AC CHARACTERISTICS

STANDARD

MODE

VCC = 4.5-5.5V

FAST MODE

Parameter

Symbol

Units

Remarks

Min

Max

Min

Max

Clock frequency

FCLK

THIGH

TLOW

—

4000

4700

—

100

—

600

1300

—

400

—

kHz

Clock high time

Clock low time

—

SDA and SCL rise time

SDA and SCL fall time

1000

300

—

300

—

(Note 1)

—

(Note 1)

START condition hold

time

THD:STA

4000

600

After this period the ﬁrst

clock pulse is generated

START condition setup

time

TSU:STA

4700

—

600

—

Only relevant for repeated

START condition

Data input hold time

Data input setup time

THD:DAT

TSU:DAT

TSU:STO

—

250

4000

100

600

STOP condition setup

time

Output valid from clock

Bus free time

TAA

—

3500

—

900

—

(Note 2)

TBUF

4700

1300

Time the bus must be free

before a new transmission

can start

Output fall time from V^IH

min to VIL max

TOF

TSP

—

250

20 + 0.1

250

(Note 1), CB ≤ 100 pF

Input ﬁlter spike suppres-

sion (SDA and SCL pins)

—

(Note 3)

Write cycle time

Endurance

TWR

—

Byte or Page mode

cycles 25°C, Vcc = 5.0V, Block

Mode ((Note 4)

Note 1: Not 100% tested. C^B= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T^SPand V^HYS=speciﬁcations are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T^Ispeciﬁcation for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our website.

FIGURE 1-2: BUS TIMING DATA

THIGH

TLOW

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

THD:STA

SDA

TSP

TBUF

TAA

SDA

OUT

1999 Microchip Technology Inc.

DS21100F-page 3

24AA164

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The 24AA164 supports aBi-directional two wire bus

and data transmission protocol. A device that sends

data onto the bus is deﬁned as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24AA164 works as slave. Both, master and slave can

operate as transmitter or receiver but the master device

determines which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwrite does occur it will replace data in a ﬁrst in ﬁrst

out fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

Note: The 24AA164 does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to the slave by not generating an acknowledge bit

on the last byte that has been clocked out of the slave.

In this case, the slave (24AA164) will leave the data line

HIGH to enable the master to generate the STOP con-

dition.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

DS21100F-page 4

1999 Microchip Technology Inc.

24AA164

3.6

Device Addressing

4.0

WRITE OPERATION

A control byte is the ﬁrst byte received following the

start condition from the master device. The ﬁrst bit is

always a one. The next three bits of the control byte are

the device select bits (A2, A1, A0). They are used to

select which of the eight devices are to be accessed.

The A1 bit must be the inverse of the A1 device select

pin.

4.1

Byte Write

Following the start condition from the master, the

device code (4 bits), the block address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore the next byte transmitted

by the master is the word address and will be written

into the address pointer of the 24AA164. After receiv-

ing another acknowledge signal from the 24AA164 the

master device will transmit the data word to be written

into the addressed memory location. The 24AA164

acknowledges again and the master generates a stop

condition. This initiates the internal write cycle, and

during this time the 24AA164 will not generate

acknowledge signals (Figure 4-1).

The next three bits of the control byte are the block

select bits (B2, B1, B0). They are used by the master

device to select which of the eight 256 word blocks of

memory are to be accessed. These bits are in effect

the three most signiﬁcant bits of the word address.

The last bit of the control byte deﬁnes the operation to

be performed. When set to one a read operation is

selected, when set to zero a write operation is selected.

Following the start condition, the 24AA164 looks for the

slave address for the device selected. Depending on

the state of the R/W bit, the 24AA164 will select a read

or write operation.

4.2

Page Write

The write control byte, word address and the ﬁrst data

byte are transmitted to the 24AA164 in the same way

as in a byte write. But instead of generating a stop con-

dition the master transmits up to 16 data bytes to the

24AA164 which are temporarily stored in the on-chip

page buffer and will be written into the memory after the

master has transmitted a stop condition. After the

receipt of each word, the four lower order address

pointer bits are internally incremented by one. The

higher order seven bits of the word address remains

constant. If the master should transmit more than 16

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

Operation Control Code

Block Select R/W

Read

Write

A2 A1 A0 Block Address

FIGURE 3-2: CONTROL BYTE

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W A

A1 A0

MSB

LSB

Note:

Page write operations are limited to writing

bytes within single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer multiples

of the page buffer size (or Ôpage sizeÕ) and

end at addresses that are integer multiples

of [page size - 1]. If a page write command

attempts to write across a physical page

boundary, the result is that the data wraps

around to the beginning of the current page

(overwriting data previously stored there),

instead of being written to the next page as

might be expected. It is therefore neces-

sary for the application software to prevent

page write operations that would attempt to

cross a page boundary.

1999 Microchip Technology Inc.

DS21100F-page 5

24AA164

FIGURE 4-1: BYTE WRITE

WORD

ADDRESS

CONTROL

BYTE

BUS ACTIVITY:

MASTER

DATA

SDA LINE

A2 A1 A0 B2 B1 B0

BUS ACTIVITY:

FIGURE 4-2: PAGE WRITE

WORD

ADDRESS (n)

CONTROL

BYTE

BUS ACTIVITY:

MASTER

DATA n

DATA n + 1

DATA n + 15

SDA LINE

A2 A1 A0 B2 B1 B0

BUS ACTIVITY:

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

5.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master

sending a start condition followed by the control byte for

a write command (R/W = 0). If the device is still busy

with the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for ﬂow diagram.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Operation

6.0

WRITE PROTECTION

The 24AA164 can be used as a serial ROM when the

WP pin is connected to VCC. Programming will be

inhibited and the entire memory will be write-protected.

DS21100F-page 6

1999 Microchip Technology Inc.

24AA164

before the internal address pointer is set. Then the master

issues the control byte again but with the R/W bit set to a

one. The 24AA164 will then issue an acknowledge and

transmits the 8-bit data word. The master will not acknowl-

edge the transfer but does generate a stop condition and

the 24AA164 discontinues transmission (Figure 7-2).

7.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the slave

address is set to one. There are three basic types of read

operations: current address read, random read, and

sequential read.

7.3

Sequential Read

7.1

Current Address Read

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24AA164 transmits the

ﬁrst data byte, the master issues an acknowledge as

opposed to a stop condition in a random read. This

directs the 24AA164 to transmit the next sequentially

addressed 8-bit word (Figure 7-3).

The 24AA164 contains an address counter that maintains

the address of the last word accessed, internally incre-

mented by one.Therefore, if the previous access (either a

read or write operation) was to address n, the next current

address read operation would access data from address n

+ 1. Upon receipt of the slave address with R/W bit set to

one, the 24AA164 issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge the

transfer but does generate a stop condition and the

24AA164 discontinues transmission (Figure 7-1).

To provide sequential reads the 24AA164 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows an entire device memory contents to be serially

read during one operation.

7.2

Random Read

7.4

Noise Protection

Random read operations allow the master to access any

memory location in a random manner. To perform this

type of read operation, ﬁrst the word address must be set.

This is done by sending the word address to the 24AA164

as part of a write operation. After the word address is sent,

the master generates a start condition following the

acknowledge. This terminates the write operation, but not

The 24AA164 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and ﬁlter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

BUS ACTIVITY

BYTE

CONTROL

DATA n

MASTER

1 A2 A1 A0 B2 B1 B0

SDA LINE

BUS ACTIVITY

FIGURE 7-2: RANDOM READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

DATA (n)

1 A2A1A0B2B1B0

SDA LINE

BUS ACTIVITY

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

SDA LINE

BUS ACTIVITY

DS21100F-page 7

1999 Microchip Technology Inc.

24AA164

8.3

8.0

PIN DESCRIPTIONS

This pin must be connected to either VSS or VCC.

8.1

SDA Serial Address/Data Input/Output

If tied to VSS, normal memory operation is enabled

(read/write the entire memory 000-7FF).

This is a Bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pullup

resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for

400 kHz).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read opera-

tions are not affected.

This feature allows the user to use the 24AA164 as a

serial ROM when WP is enabled (tied to VCC).

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

8.4

A0, A1, A2

These pins are used to conﬁgure the proper chip

address in multiple-chip applications (more than one

24AA164 on the same bus). The levels on these pins

are compared to the corresponding bits in the slave

address. The chip is selected if the compare is true.

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

Note: The level on A1 is compared to the inverse

of the slave address.

Up to eight 24AA164s may be connected to the same

bus. These pins must be connected to either VSS or

VCC.

DS21100F-page 8

1999 Microchip Technology Inc.

24AA164

NOTES:

1999 Microchip Technology Inc.

DS21100F-page 9

24AA164

NOTES:

1999 Microchip Technology Inc.

DS21100F-page 10

24AA164

24AA164 Product Identiﬁcation System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

24AA164

–

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body), 8-lead

Package:

Temperature

Range:

Blank = 0°C to 70°C

24AA164

24AA164T

16K I C Serial EEPROM

Device:

16K I C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notiﬁcation System

1999 Microchip Technology Inc.

DS21100F-page 11

WORLDWIDE SALES AND SERVICE

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Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950 Fax: 408-436-7955

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed

by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products

as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip

logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

 1999 Microchip Technology Inc.

24AA164P [MICROCHIP]

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