24AA256-E/SM_技术文档

24AA256/24LC256/24FC256

256K I²C^™CMOS Serial EEPROM

Device Selection Table

Description:

Part

Number

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

The Microchip Technology Inc. 24AA256/24LC256/

24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial

Electrically Erasable PROM, capable of operation

across a broad voltage range (1.8V to 5.5V). It has

been developed for advanced, low-power applications

such as personal communications or data acquisition.

This device also has a page write capability of up to 64

bytes of data. This device is capable of both random

and sequential reads up to the 256K boundary.

Functional address lines allow up to eight devices on

the same bus, for up to 2 Mbit address space. This

device is available in the standard 8-pin plastic DIP,

SOIC, TSSOP, MSOP and DFN packages.

24AA256

24LC256

24FC256

1.8-5.5V

2.5-5.5V

1.8-5.5V

400 kHz⁽¹⁾

400 kHz

1 MHz⁽²⁾

I

I, E

I

Note 1: 100 kHz for VCC < 2.5V.

2: 400 kHz for VCC < 2.5V.

Features:

• Low-power CMOS technology:

- Maximum write current 3 mA at 5.5V

- Maximum read current 400 μA at 5.5V

- Standby current 100 nA, typical at 5.5V

Block Diagram

• 2-wire serial interface bus, I²C^™compatible

• Cascadable for up to eight devices

• Self-timed erase/write cycle

A0 A1A2WP

HV Generator

I/O

Control

Logic

• 64-byte Page Write mode available

• 5 ms max. write cycle time

Memory

Control

Logic

EEPROM

Array

XDEC

• Hardware write-protect for entire array

• Output slope control to eliminate ground bounce

• Schmitt Trigger inputs for noise suppression

• 1,000,000 erase/write cycles

Page Latches

I/O

SCL

YDEC

SDA

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

VCC

VSS

• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN

packages, 14-lead TSSOP package

Sense Amp.

R/W Control

• Pb-free finishes available

• Temperature ranges:

- Industrial (I):

- Automotive (E):

-40°C to +85°C

-40°C to +125°C

Package Types

PDIP/SOIC

TSSOP/MSOP*

DFN

A0

1

8

VCC

1

2

3

4

A0

A1

8

7

6

5

VCC

WP

1

2

8

7

A0

A1

VCC

A1

A2

2

3

7

6

WP

A2

SCL

SDA

SCL

3

4

6

5

A2

SCL

SDA

VSS

4

5

SDA

VSS

Note: * Pins A0 and A1 are no connects for the MSOP package only.

*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.

DS21203N-page 1

24AA256/24LC256/24FC256

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-40°C to +125°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Electrical Characteristics:

DC CHARACTERISTICS

Industrial (I):

Automotive (E): VCC = +2.5V to 5.5V

VCC = +1.8V to 5.5V

TA = -40°C to +85°C

TA = -40°C to +125°C

Param.

Sym.

No.

Characteristic

Min.

Max.

Units

Conditions

D1

—

A0, A1, A2, SCL, SDA

and WP pins:

—

D2

D3

VIH

VIL

High-level input voltage

Low-level input voltage

0.7 VCC

—

V

0.3 VCC

0.2 VCC

V

VCC ≥ 2.5V

VCC < 2.5V

D4

VHYS

Hysteresis of Schmitt

Trigger inputs

0.05 VCC

—

V

VCC ≥ 2.5V (Note)

(SDA, SCL pins)

D5

D6

VOL

ILI

Low-level output voltage

Input leakage current

Output leakage current

—

0.40

±1

V

IOL = 3.0 ma @ VCC = 4.5V

IOL = 2.1 ma @ VCC = 2.5V

μA

VIN = VSS or VCC, WP = VSS

VIN = VSS or VCC, WP = VCC

D7

D8

ILO

—

±1

10

μA

VOUT = VSS or VCC

CIN,

Pin capacitance

pF

VCC = 5.0V (Note)

COUT

(all inputs/outputs)

TA = 25°C, FCLK = 1 MHz

D9

ICC Read Operating current

ICC Write

—

400

3

μA

mA

μA

VCC = 5.5V, SCL = 400 kHz

VCC = 5.5V

D10

ICCS

Standby current

1

TA = -40°C to +85°C

SCL = SDA = VCC = 5.5V

A0, A1, A2, WP = VSS

—

5

μA

TA = -40°C to +125°C

SCL = SDA = VCC = 5.5V

A0, A1, A2, WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

DS21203N-page 2

24AA256/24LC256/24FC256

TABLE 1-2:

AC CHARACTERISTICS

Electrical Characteristics:

AC CHARACTERISTICS

Industrial (I):

Automotive (E): VCC = +2.5V to 5.5V

VCC = +1.8V to 5.5V

TA = -40°C to +85°C

TA = -40°C to +125°C

Param.

Sym.

No.

Characteristic

Clock frequency

Min.

Max.

Units

Conditions

1

2

3

4

FCLK

—

100

400

kHz 1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

1000

THIGH

TLOW

Clock high time

Clock low time

4000

600

500

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

4700

1300

500

—

TR

TF

SDA and SCL rise time

(Note 1)

—

1000

300

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FC256

5

6

SDA and SCL fall time

(Note 1)

—

300

100

ns

All except, 24FC256

1.8V ≤ VCC ≤ 5.5V 24FC256

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

THD:STA Start condition hold time

4000

600

250

—

7

TSU:STA Start condition setup time

4700

600

250

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

8

9

THD:DAT Data input hold time

TSU:DAT Data input setup time

0

—

ns

(Note 2)

250

100

—

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FC256

10

TSU:STO Stop condition setup time

4000

600

250

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

11

12

TSU:WP WP setup time

THD:WP WP hold time

4000

600

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FC256

4700

1300

—

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC ≤ 5.5V 24FC256

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

DS21203N-page 3

24AA256/24LC256/24FC256

Electrical Characteristics:

AC CHARACTERISTICS (Continued)

Industrial (I):

Automotive (E): VCC = +2.5V to 5.5V

VCC = +1.8V to 5.5V

TA = -40°C to +85°C

TA = -40°C to +125°C

Param.

Sym.

Characteristic

Min.

Max.

Units

Conditions

No.

13

TAA

Output valid from clock

(Note 2)

—

3500

900

400

ns

1.8 V ≤ VCC < 2.5V

2.5 V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5 V ≤ VCC ≤ 5.5V 24FC256

14

15

TBUF

TOF

Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

500

—

ns

1.8V ≤ VCC < 2.5V

2.5V ≤ VCC ≤ 5.5V

1.8V ≤ VCC < 2.5V 24FC256

2.5V ≤ VCC ≤ 5.5V 24FC256

All except, 24FC256 (Note 1)

Output fall time from VIH

minimum to VIL maximum

CB ≤ 100 pF

10 + 0.1CB

250

16

17

18

TSP

TWC

—

Input filter spike suppression

(SDA and SCL pins)

—

50

5

ns

All except, 24FC256 (Notes 1

and 3)

Write cycle time (byte or

page)

ms

—

Endurance

1,000,000

—

cycles 25°C (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

FIGURE 1-1:

BUS TIMING DATA

5

4

D4

2

SCL

7

3

10

8

9

SDA

IN

6

16

14

12

13

SDA

OUT

(protected)

WP

11

(unprotected)

DS21203N-page 4

24AA256/24LC256/24FC256

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

Name

PIN FUNCTION TABLE

8-pin

PDIP

8-pin

SOIC

8-pin

TSSOP

8-pin

MSOP

8-pin

DFN

Function

A0

1

2

1

2

1

2

—

1, 2

3

1

2

User Configurable Chip Select

Not Connected

A1

(NC)

A2

—

3

—

3

—

3

—

3

User Configurable Chip Select

Ground

VSS

SDA

SCL

(NC)

WP

VCC

4

5

Serial Data

6

Serial Clock

—

7

—

7

—

7

—

7

—

7

Not Connected

Write-Protect Input

8

+1.8V to 5.5V (24AA256)

+2.5V to 5.5V (24LC256)

+1.8V to 5.5V (24FC256)

2.1

A0, A1, A2 Chip Address Inputs

2.3

Serial Clock (SCL)

The A0, A1 and A2 inputs are used by the 24XX256 for

multiple device operations. The levels on these inputs

are compared with the corresponding bits in the slave

address. The chip is selected if the compare is true.

This input is used to synchronize the data transfer to

and from the device.

2.4

Write-Protect (WP)

For the MSOP package only, pins A0 and A1 are not

connected.

This pin must be connected to either VSS or VCC. If tied

to VSS, write operations are enabled. If tied to VCC,

write operations are inhibited but read operations are

not affected.

Up to eight devices (two for the MSOP package) may

be connected to the same bus by using different Chip

Select bit combinations. These inputs must be

connected to either VCC or VSS.

3.0

FUNCTIONAL DESCRIPTION

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

The 24XX256 supports a bidirectional 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter and a device

receiving data as a receiver. The bus must be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24XX256 works as a slave. Both master and slave can

operate as a transmitter or receiver, but the master

device determines which mode is activated.

2.2

Serial Data (SDA)

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for

400 kHz and 1 MHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

DS21203N-page 5

24AA256/24LC256/24FC256

4.4

Data Valid (D)

4.0

BUS CHARACTERISTICS

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line, while the clock line is high, will be

interpreted as a Start or Stop condition.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.1

Bus Not Busy (A)

4.5

Acknowledge

Both data and clock lines remain high.

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high, determines a Start condition. All

commands must be preceded by a Start condition.

Note: The 24XX256 does not generate any

Acknowledge

programming cycle is in progress.

bits

if

an

internal

4.3

Stop Data Transfer (C)

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24XX256) will leave the data line high to enable

the master to generate the Stop condition.

A low-to-high transition of the SDA line, while the clock

(SCL) is high, determines a Stop condition. All

operations must end with a Stop condition.

DS21203N-page 6

24AA256/24LC256/24FC256

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

1

2

3

4

5

6

7

8

9

1

2

3

SCL

SDA

Data from transmitter

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line

at this point so the Transmitter can

continue sending data.

DS21203N-page 7

24AA256/24LC256/24FC256

FIGURE 5-1:

CONTROL BYTE

FORMAT

5.0

DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a 4-bit control code. For the

24XX256, this is set as ‘1010’ binary for read and write

operations. The next three bits of the control byte are

the Chip Select bits (A2, A1, A0). The Chip Select bits

allow the use of up to eight 24XX256 devices on the

same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are, in effect, the three Most Significant bits of the word

address.

Read/Write Bit

Chip Select

Bits

Control Code

S

1

0

A2 A1 A0 R/W ACK

1

Slave Address

Start Bit

Acknowledge Bit

For the MSOP package, the A0 and A1 pins are not

connected. During device addressing, the A0 and A1

Chip Select bits (Figures 5-1 and 5-2) should be set to

‘0’. Only two 24XX256 MSOP packages can be

connected to the same bus.

5.1

Contiguous Addressing Across

Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 2 Mbit

by adding up to eight 24XX256 devices on the same

bus. In this case, software can use A0 of the control

byte as address bit A15; A1 as address bit A16; and A2

as address bit A17. It is not possible to sequentially

read across device boundaries.

The last bit of the control byte defines the operation to

be performed. When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A14…A0 are used, the upper address bits are a

“don’t care.” The upper address bits are transferred

first, followed by the Less Significant bits.

For the MSOP package, up to two 24XX256 devices

can be added for up to 512 Kbit of address space. In

this case, software can use A2 of the control byte as

address bit A17. Bits A0 (A15) and A1 (A16) of the

control byte must always be set to a logic ‘0’ for the

MSOP.

Following the Start condition, the 24XX256 monitors

the SDA bus checking the device type identifier being

transmitted. Upon receiving a ‘1010’ code and appro-

priate device select bits, the slave device outputs an

Acknowledge signal on the SDA line. Depending on the

state of the R/W bit, the 24XX256 will select a read or

write operation.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte

Address High Byte

Address Low Byte

A

2

A

1

A

0

A

9

A

8

A

7

A

0

•

1

0

1

0

R/W

x

12 11 10

14 13

Control

Code

Chip

Select

Bits

x = “don’t care” bit

DS21203N-page 8

24AA256/24LC256/24FC256

Upon receipt of each word, the six lower Address

Pointer bits are internally incremented by one. If the

master should transmit more than 64 bytes prior to

generating the Stop condition, the address counter will

6.0

6.1

WRITE OPERATIONS

Byte Write

roll over and the previously received data will be over-

written. As with the byte write operation, once the Stop

condition is received, an internal write cycle will begin

(Figure 6-2). If an attempt is made to write to the array

with the WP pin held high, the device will acknowledge

the command, but no write cycle will occur, no data will

be written and the device will immediately accept a new

command.

Following the Start condition from the master, the

control code (four bits), the Chip Select (three bits) and

the R/W bit (which is a logic low) are clocked onto the

bus by the master transmitter. This indicates to the

addressed slave receiver that the address high byte will

follow after it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte

transmitted by the master is the high-order byte of the

word address and will be written into the Address

Pointer of the 24XX256. The next byte is the Least

Significant Address Byte. After receiving another

Acknowledge signal from the 24XX256, the master

device will transmit the data word to be written into the

addressed memory location. The 24XX256 acknowl-

edges again and the master generates a Stop

condition. This initiates the internal write cycle and

during this time, the 24XX256 will not generate

Acknowledge signals (Figure 6-1). If an attempt is

made to write to the array with the WP pin held high, the

device will acknowledge the command but no write

cycle will occur, no data will be written, and the device

will immediately accept a new command. After a byte

Write command, the internal address counter will point

to the address location following the one that was just

written.

6.3

Write-Protection

The WP pin allows the user to write-protect the entire

array (0000-7FFF) when the pin is tied to VCC. If tied to

VSS the write protection is disabled. The WP pin is

sampled at the Stop bit for every Write command

(Figure 1-1). Toggling the WP pin after the Stop bit will

have no effect on the execution of the write cycle.

Note: Page write operations are limited to writing

bytes within

a single physical page,

regardless of the number of bytes actually

being written. Physical page boundaries

start at addresses that are integer

multiples of the page buffer size (or ‘page

size’) and end at addresses that are

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is, therefore, necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX256 in much the same

way as in a byte write. The exception is that instead of

generating a Stop condition, the master transmits up to

63 additional bytes, which are temporarily stored in the

on-chip page buffer, and will be written into memory

once the master has transmitted a Stop condition.

FIGURE 6-1:

BYTE WRITE

S

T

A

R

T

Bus Activity

Master

S

Control

Byte

Address

High Byte

Address

Low Byte

T

O

P

Data

SDA Line

A A A

x

S 1 0 1 0

0

P

2 1 0

Bus Activity

A

C

K

A

C

K

A

C

K

A

C

K

x = “don’t care” bit

FIGURE 6-2:

PAGE WRITE

S

T

A

R

T

Bus Activity

Master

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Data Byte 0

Data Byte 63

SDA Line

A A A

x

P

S 1 0 1 0

0

2 1 0

Bus Activity

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

x = “don’t care” bit

DS21203N-page 9

24AA256/24LC256/24FC256

FIGURE 7-1:

ACKNOWLEDGE

POLLING FLOW

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (This feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition, followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, the Start bit and control byte must

be resent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next Read or Write command. See Figure 7-1 for

flow diagram.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

NO

Did Device

Acknowledge

(ACK = 0)?

YES

DS21203N-page 10

24AA256/24LC256/24FC256

8.2

Random Read

8.0

READ OPERATION

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is done by sending the word address to the

24XX256 as part of a write operation (R/W bit set to

‘0’). Once the word address is sent, the master gener-

ates a Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. The master then issues

the control byte again, but with the R/W bit set to a one.

The 24XX256 will then issue an acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer, though it does generate a

Stop condition, which causes the 24XX256 to discon-

tinue transmission (Figure 8-2). After a random Read

command, the internal address counter will point to the

address location following the one that was just read.

Read operations are initiated in much the same way as

write operations, with the exception that the R/W bit of

the control byte is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 24XX256 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘1’. Therefore, if the previous read

access was to address ‘n’ (n is any legal address), the

next current address read operation would access data

from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24XX256 issues an acknowledge and transmits the

8-bit data word. The master will not acknowledge the

transfer, but does generate a Stop condition and the

24XX256 discontinues transmission (Figure 8-1).

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX256 transmits

the first data byte, the master issues an acknowledge

as opposed to the Stop condition used in a random

read. This acknowledge directs the 24XX256 to

transmit the next sequentially addressed 8-bit word

(Figure 8-3). Following the final byte transmitted to the

master, the master will NOT generate an acknowledge,

but will generate a Stop condition. To provide sequen-

tial reads, the 24XX256 contains an internal Address

Pointer which is incremented by one at the completion

of each operation. This Address Pointer allows the

entire memory contents to be serially read during one

operation. The internal Address Pointer will

automatically roll over from address 7FFF to address

0000 if the master acknowledges the byte received

from the array address 7FFF.

FIGURE 8-1:

CURRENT ADDRESS

READ

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Data

Byte

A A A

2 1 0

SDA Line

S 1 0 1 0

1

P

A

C

K

N

O

Bus Activity

A

C

K

FIGURE 8-2:

RANDOM READ

S

T

A

R

T

S

Bus Activity

Master

T

A

R

T

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Control

Byte

Data

Byte

A A A

2 1 0

A A A

2 1 0

SDA Line

x

S 1 0 1 0

0

S 1 0 1 0

1

P

A

C

K

A

C

K

A

C

K

A

C

K

N

O

A

C

Bus Activity

x = “don’t care” bit

FIGURE 8-3:

SEQUENTIAL READ

S

Control

Byte

Bus Activity

Master

T

Data (n)

Data (n + 1)

Data (n + x)

Data (n + 2)

O

P

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

N

O

A

C

K

Bus Activity

DS21203N-page 11

24AA256/24LC256/24FC256

9.0

9.1

PACKAGING INFORMATION

Package Marking Information

8-Lead PDIP (300 mil)

Example:

24AA256

I/P 017

XXXXXXXX

T/XXXNNN

YYWW

e

3

0510

8-Lead SOIC (150 mil)

Example:

24LC256I

XXXXXXXX

T/XXYYWW

e

3

SN

0510

NNN

017

8-Lead SOIC (208 mil)

Example:

24LC256

XXXXXXXX

T/XXXXXX

YYWWNNN

e

3

I/SM

0510017

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

YY

WW

NNN

e

3

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For

device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

DS21203N-page 12

24AA256/24LC256/24FC256

Package Marking Information (Continued)

Example:

8-Lead TSSOP

XXXX

4LD

I510

TYWW

NNN

017

8-Lead MSOP

Example:

XXXXXT

4L256I

510017

YWWNNN

8-Lead DFN-S

Example:

24LC256

XXXXXXX

T/XXXXX

YYWW

e

3

I/MF

0510

017

NNN

First Line Marking Codes

TSSOP Package Codes

MSOP Package Codes

Part No.

24AA256

24LC256

24FC256

4AD

4LD

4FD

4A256T

4L256T

4F256T

DS21203N-page 13

24AA256/24LC256/24FC256

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.100

.155

.130

2.54

Top to Seating Plane

A

.140

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

3.68

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

DS21203N-page 14

24AA256/24LC256/24FC256

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

1

B

n

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.050

.061

.056

.007

.237

.154

.193

.015

.025

4

1.27

Overall Height

A

.053

.069

1.35

1.32

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

0.10

5.79

3.71

4.80

0.25

0.48

0

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS21203N-page 15

24AA256/24LC256/24FC256

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

E

E1

p

D

2

n

1

B

α

c

A2

A

φ

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.050

.075

.074

.005

.313

.208

.205

.025

4

1.27

Overall Height

A

.070

.080

1.78

1.75

1.97

1.88

0.13

7.95

5.28

5.21

0.64

4

2.03

Molded Package Thickness

Standoff

A2

A1

E

.069

.002

.300

.078

.010

.325

.212

.210

.030

8

1.98

0.25

8.26

5.38

5.33

0.76

8

§

0.05

7.62

5.11

5.13

0.51

0

Overall Width

Molded Package Width

Overall Length

E1

D

.201

.202

.020

0

Foot Length

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.014

0

.009

.017

12

.010

.020

15

0.20

0.36

0

0.23

0.43

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

Drawing No. C04-056

DS21203N-page 16

24AA256/24LC256/24FC256

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

A1

A2

φ

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.026

0.65

Overall Height

A

.043

1.10

0.95

0.15

6.50

4.50

3.10

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.033

.035

.004

.251

.173

.118

.024

4

.037

.006

.256

.177

.122

.028

8

0.85

0.05

0.90

0.10

6.38

4.40

3.00

0.60

4

§

.002

.246

.169

.114

.020

0

Overall Width

6.25

4.30

2.90

0.50

0

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

DS21203N-page 17

24AA256/24LC256/24FC256

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

E

E1

p

D

2

B

n

1

α

A2

A

c

φ

A1

(F)

L

β

Units

Dimension Limits

INCHES

NOM

MILLIMETERS*

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.026 BSC

0.65 BSC

Overall Height

A

A2

A1

E

-

.043

-

0.85

-

1.10

Molded Package Thickness

Standoff

.030

.033

.037

0.75

0.95

0.15

.000

-

.006

0.00

Overall Width

.193 TYP.

4.90 BSC

Molded Package Width

Overall Length

Foot Length

E1

D

.118 BSC

3.00 BSC

L

.016

.024

.037 REF

.031

0.40

0.60

0.95 REF

0.80

Footprint (Reference)

Foot Angle

F

φ

c

0°

.003

.009

5°

-

8°

.009

.016

15°

0°

0.08

0.22

5°

-

8°

0.23

0.40

15°

Lead Thickness

Lead Width

.006

B

α

β

.012

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

-

5°

15°

5°

15°

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed .010" (0.254mm) per side.

JEDEC Equivalent: MO-187

Drawing No. C04-111

DS21203N-page 18

24AA256/24LC256/24FC256

8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S)

E

p

B

E1

n

L

R

D1

D

D2

PIN 1

EXPOSED

METAL

PADS

ID

1

2

E2

BOTTOM VIEW

TOP VIEW

α

A2

A3

A

A1

Units

Dimension Limits

INCHES

MILLIMETERS*

MIN

NOM

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.050 BSC

1.27 BSC

0.85

Overall Height

A

A2

A1

A3

E

.033

.039

1.00

Molded Package Thickness

Standoff

.026

.0004

.031

.002

0.65

0.80

0.05

.000

.152

0.00

0.01

0.20 REF.

Base Thickness

Overall Length

.008 REF.

.194 BSC

.184 BSC

.158

4.92 BSC

4.67 BSC

Molded Package Length

Exposed Pad Length

Overall Width

E1

E2

D

.163

3.85

4.00

4.15

.236 BSC

.226 BSC

.091

5.99 BSC

5.74 BSC

Molded Package Width

Exposed Pad Width

Lead Width

D1

D2

B

.085

.014

.020

.097

.019

.030

2.16

0.35

0.50

2.31

2.46

0.47

0.75

.016

0.40

0.60

.356

Lead Length

L

.024

Tie Bar Width

R

.014

α

Mold Draft Angle Top

12

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC equivalent: pending

Drawing No. C04-113

DS21203N-page 19

24AA256/24LC256/24FC256

APPENDIX A: REVISION HISTORY

Revision L

Corrections to Section 1.0, Electrical Characteristics.

Revision M

Added 1.8V 400 kHz option for 24FC256.

Revision N

Revised Sections 2.1 and 2.4. Removed 14-Lead

TSSOP Package.

DS21203N-page 20

24AA256/24LC256/24FC256

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

DS21203N-page 21

24AA256/24LC256/24FC256

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

24AA256/24LC256/24FC256

DS21203N

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21203N-page 22

24AA256/24LC256/24FC256

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

X

a) 24AA256-I/P:

Industrial Temp.,

Temperature

Range

Package

Lead

Finish

1.8V, PDIP package.

b) 24AA256T-I/SN: Tape and Reel,

Industrial Temp., 1.8V, SOIC

package.

Device:

24AA256:

256 Kbit 1.8V I²C Serial

EEPROM

c) 24AA256-I/ST:

Industrial Temp.,

24AA256T: 256 Kbit 1.8V I²C Serial

1.8V, TSSOP package.

EEPROM Tape and Reel)

256 Kbit 2.5V I²C Serial

EEPROM

d) 24AA256-I/MS: Industrial Temp.,

1.8V, MSOP package.

24LC256:

24LC256T: 256 Kbit 2.5V I²C Serial

EEPROM Tape and Reel)

24FC256:

e) 24LC256-E/P:

Extended Temp.,

2.5V, PDIP package.

256 Kbit High Speed I²C Serial

EEPROM

f) 24LC256-I/SN: Industrial Temp.,

2.5V, SOIC package.

24FC256T: 256 Kbit High Speed I²C Serial

EEPROM Tape and Reel)

g) 24LC256T-I/SN: Tape and Reel,

Industrial Temp., 2.5V, SOIC

package.

Temperature

Range:

I

E

=

-40°C to +85°C

-40°C to +125°C

h) 24LC256-I/MS: Industrial Temp,

2.5V, MSOP package.

i) 24FC256-I/P:

Industrial Temp,

Package:

P

= Plastic DIP (300 mil body), 8-lead

1.8V, High Speed, PDIP package.

SN = Plastic SOIC (150 mil body), 8-lead

SM = Plastic SOIC (208 mil body), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

MF = Dual, Flat, No Lead (DFN)(6x5 mm

body), 8-lead

j) 24FC256-I/SN: Industrial Temp,

1.8V, High Speed, SOIC package.

k) 24FC256T-I/SN: Tape and Reel,

Industrial Temp, 1.8V, High Speed,

SOIC package

MS = Plastic Micro Small Outline (MSOP),

8-lead

l) 24LC256T-I/STG: Industrial Temp,

2.5V, TSSOP package, Tape & Reel,

Pb-free

Lead Finish:

Blank= Pb-free – Matte Tin (see Note 1)

G

= Pb-free – Matte Tin only

m) 24LC256-I/PG: Industrial Temp,

2.5V, PDIP package, Pb-free

Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products

manufactured before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb). Please

visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences

and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of

the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

DS21203N-page 23

24AA256/24LC256/24FC256

NOTES:

DS21203N-page 24

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21203N-page 25

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

India - Bangalore

Tel: 91-80-2229-0061

Fax: 91-80-2229-0062

Austria - Weis

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Atlanta

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-352-30-52

Fax: 34-91-352-11-47

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Malaysia - Penang

Tel: 604-646-8870

Fax: 604-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Philippines - Manila

Tel: 632-634-9065

Fax: 632-634-9069

China - Shenzhen

Detroit

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

08/24/05

DS21203N-page 26


型号：	24AA256-E/SM
厂家：	MICROCHIP
描述：	256K I2C CMOS Serial EEPROM 256K I2C CMOS串行EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总26页 (文件大小：465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24AA256-E/SM [MICROCHIP]

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