24AA256UIDT-I/ST_技术文档

24AA256UID

256K I²C™ Serial EEPROM with EUI-48™, EUI-64™ and

Unique 32-Bit Serial Number

Device Selection Table

VCC

Range

Max. Clock

Frequency

Temp.

Ranges

Page

Size

Unique ID

Length

Part Number

EUI-48™

EUI-64™

24AA256UID

1.7-5.5V

400 kHz⁽¹⁾

I

64-byte

Yes

32-bit

Note 1: 100 kHz for VCC < 2.5V.

Features:

Description:

• Pre-Programmed 32-Bit Serial Number:

- Unique across all UID-family EEPROMs

The Microchip Technology Inc. 24AA256UID is a 32K x

8 (256 Kbit) Serial Electrically Erasable PROM with

pre-programmed EUI-48 and EUI-64 node addresses

and a 32-bit Unique ID, capable of operation across a

broad voltage range (1.7V to 5.5V). This device also

has a page write capability of up to 64 bytes of data.

This device is available in the standard 8-pin plastic

DIP, SOIC and TSSOP packages.

- Scalable to 48-bit, 64-bit, 128-bit, 256-bit,

and other lengths

• Pre-Programmed Globally Unique, 48-bit or 64-bit

Node Address:

- Compatible with EUI-48™ and EUI-64™

• Codes Stored in Permanently Write-Protected

Upper 1/8th of EEPROM Array

Block Diagram

• Single Supply with Operation Down to 1.7V

• Low-Power CMOS Technology:

- Active current 400 uA, typical

A0 A1A2

HV Generator

- Standby current 100 nA, typical

• 2-Wire Serial Interface, I²C^™Compatible

• Cascadable up to Eight Devices

• Schmitt Trigger Inputs for Noise Suppression

• Output Slope Control to Eliminate Ground Bounce

• 100 kHz and 400 kHz Clock Compatibility

• Page Write Time 5 ms Max.

I/O

Control

Logic

Memory

Control

Logic

EEPROM

Array

XDEC

Page Latches

I/O

SCL

YDEC

SDA

• Self-Timed Erase/Write Cycle

VCC

VSS

• 64-Byte Page Write Buffer

Sense Amp.

R/W Control

• ESD Protection >4000V

• More than One Million Erase/Write Cycles

• Data Retention >200 years

Package Types

• Packages Include 8-lead PDIP, SOIC and TSSOP

• RoHS Compliant

PDIP

SOIC/TSSOP

• Temperature Ranges:

- Industrial (I):

A0

1

8

VCC

1

2

3

4

8

7

6

5

A0

A1

VCC

NC

-40C to +85C

A1

A2

2

3

7

6

NC

SCL

A2

SCL

SDA

VSS

4

5

SDA

VSS

 2013 Microchip Technology Inc.

DS20005215A-page 1

24AA256UID

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied..................................................................................................-40°C to +85°C

ESD protection on all pins  4 kV

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions above those

indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

Electrical Characteristics:

DC CHARACTERISTICS

Industrial (I):

VCC = +1.7V to 5.5V

TA = -40°C to +85°C

Param.

Sym.

No.

Characteristic

Min.

Max.

Units

Conditions

—

A0, A1, A2, SCL and

SDA pins:

—

D1

D2

VIH

VIL

High-level input voltage

Low-level input voltage

0.7 VCC

—

V

0.3 VCC

0.2 VCC

V

VCC  2.5V

VCC < 2.5V

D3

D4

VHYS

VOL

Hysteresis of Schmitt

Trigger inputs

(SDA, SCL pins)

0.05 VCC

—

V

VCC  2.5V (Note)

Low-level output voltage

0.40

V

IOL = 3.0 mA @ VCC = 4.5V

IOL = 2.1 mA @ VCC = 2.5V

D5

D6

D7

ILI

Input leakage current

Output leakage current

—

±1

10

A

pF

VIN = VSS or VCC

ILO

VOUT = VSS or VCC

CIN,

Pin capacitance

VCC = 5.0V (Note)

COUT

(all inputs/outputs)

TA = 25°C, FCLK = 1 MHz

D8

D9

ICC Read Operating current

ICC Write

—

400

3

A

mA

A

VCC = 5.5V, SCL = 400 kHz

VCC = 5.5V

ICCS

Standby current

1

TA = -40°C to +85°C

SCL = SDA = VCC = 5.5V

A0, A1, A2 = VSS

Note: This parameter is periodically sampled and not 100% tested.

DS20005215A-page 2

 2013 Microchip Technology Inc.

24AA256UID

TABLE 1-2:

AC CHARACTERISTICS

Electrical Characteristics:

AC CHARACTERISTICS

Industrial (I):

VCC = +1.7V to 5.5V

TA = -40°C to +85°C

Param.

Sym.

No.

Characteristic

Clock frequency

Min.

Max.

Units

Conditions

1

2

3

4

5

6

7

FCLK

THIGH

TLOW

TR

—

100

400

kHz 1.7V  VCC  2.5V

2.5V  VCC  5.5V

Clock high time

Clock low time

4000

600

—

ns

1.7V  VCC  2.5V

2.5V  VCC  5.5V

4700

1300

—

1.7V  VCC  2.5V

2.5V  VCC  5.5V

SDA and SCL rise time

(Note 1)

—

1000

300

1.7V  VCC  2.5V

2.5V  VCC  5.5V

TF

SDA and SCL fall time

(Note 1)

—

300

—

THD:STA Start condition hold time

TSU:STA Start condition setup time

4000

600

—

1.7V  VCC  2.5V

2.5V  VCC  5.5V

4700

600

—

1.7V  VCC  2.5V

2.5V  VCC  5.5V

8

9

THD:DAT Data input hold time

TSU:DAT Data input setup time

0

—

ns

(Note 2)

250

100

—

1.7V  VCC  2.5V

2.5V  VCC  5.5V

10

11

12

TSU:STO Stop condition setup time

4000

600

—

ns

1.7V  VCC  2.5V

2.5V  VCC  5.5V

TAA

Output valid from clock

—

3500

900

1.7 V  VCC  2.5V

2.5 V  VCC  5.5V

(Note 2)

TBUF

Bus free time: Time the bus

must be free before a new

transmission can start

4700

1300

—

1.7V  VCC  2.5V

2.5V  VCC  5.5V

13

TOF

Output fall time from VIH

minimum to VIL maximum

CB  100 pF

10 + 0.1CB

250

ns

(Note 1)

14

15

16

TSP

TWC

—

Input filter spike suppression

(SDA and SCL pins)

—

50

5

ns

(Notes 1 and 3)

Write cycle time (byte or

page)

ms

—

Endurance

1,000,000

—

cycles Page mode, 25°C, 5.5V (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved

noise spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site

at www.microchip.com.

 2013 Microchip Technology Inc.

DS20005215A-page 3

24AA256UID

FIGURE 1-1:

BUS TIMING DATA

5

4

D3

2

SCL

7

3

10

8

9

SDA

IN

6

14

12

11

SDA

OUT

2.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

8-pin

PIN FUNCTION TABLE

8-pin

SOIC

8-pin

TSSOP

Name

Function

PDIP

A0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

User Configurable Chip Select

Ground

A1

A2

VSS

SDA

SCL

NC

Serial Data

Serial Clock

Not Connected

VCC

+1.7V to 5.5V

2.1

A0, A1, A2 Chip Address Inputs

2.2

Serial Data (SDA)

The A0, A1 and A2 inputs are used by the 24AA256UID

for multiple device operations. The levels on these

inputs are compared with the corresponding bits in the

slave address. The chip is selected if the compare is

true.

This is a bidirectional pin used to transfer addresses

and data into and out of the device. It is an open drain

terminal. Therefore, the SDA bus requires a pull-up

resistor to VCC (typical 10 k for 100 kHz, 2 k for

400 kHz).

Up to eight devices may be connected to the same bus

by using different Chip Select bit combinations. These

inputs must be connected to either VCC or VSS.

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating the Start and Stop conditions.

In most applications, the chip address inputs A0, A1

and A2 are hard-wired to logic ‘0’ or logic ‘1’. For

applications in which these pins are controlled by a

microcontroller or other programmable device, the chip

address pins must be driven to logic ‘0’ or logic ‘1’

before normal device operation can proceed.

2.3

Serial Clock (SCL)

This input is used to synchronize the data transfer to

and from the device.

DS20005215A-page 4

 2013 Microchip Technology Inc.

24AA256UID

4.4

Data Valid (D)

3.0

FUNCTIONAL DESCRIPTION

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The 24AA256UID supports a bidirectional 2-wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter and a

device receiving data as a receiver. The bus must be

controlled by a master device which generates the

Serial Clock (SCL), controls the bus access, and

generates the Start and Stop conditions while the

24AA256UID works as a slave. Both master and slave

can operate as a transmitter or receiver, but the master

device determines which mode is activated.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

4.0

BUS CHARACTERISTICS

4.5

Acknowledge

The following bus protocol has been defined:

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line, while the clock line is high, will be

interpreted as a Start or Stop condition.

Note:

The 24AA256UID does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SDA line is stable-low during the high period of

the acknowledge-related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (24AA256UID) will leave the data line high to

enable the master to generate the Stop condition.

4.1

Bus Not Busy (A)

Both data and clock lines remain high.

4.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high, determines a Start condition. All

commands must be preceded by a Start condition.

4.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line, while the clock

(SCL) is high, determines a Stop condition. All

operations must end with a Stop condition.

 2013 Microchip Technology Inc.

DS20005215A-page 5

24AA256UID

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C) (A)

SCL

SDA

Start

Condition

Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

FIGURE 4-2:

ACKNOWLEDGE TIMING

Acknowledge

Bit

1

2

3

4

5

6

7

8

9

1

2

3

SCL

SDA

Data from transmitter

Transmitter must release the SDA line at this point,

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line

at this point so the Transmitter can

continue sending data.

DS20005215A-page 6

 2013 Microchip Technology Inc.

24AA256UID

FIGURE 5-1:

CONTROL BYTE

FORMAT

5.0

DEVICE ADDRESSING

A control byte is the first byte received following the

Start condition from the master device (Figure 5-1).

The control byte consists of a 4-bit control code. For the

24AA256UID, this is set as ‘1010’ binary for read and

write operations. The next three bits of the control byte

are the Chip Select bits (A2, A1, A0). The Chip Select

bits allow the use of up to eight 24AA256UID devices

on the same bus and are used to select which device is

accessed. The Chip Select bits in the control byte must

correspond to the logic levels on the corresponding A2,

A1 and A0 pins for the device to respond. These bits

are, in effect, the three Most Significant bits of the word

address.

Read/Write Bit

Chip Select

Control Code

Bits

S

1

0

A2 A1 A0 R/W ACK

1

Slave Address

Start Bit

Acknowledge Bit

The last bit of the control byte defines the operation to

be performed. When set to a one, a read operation is

selected. When set to a zero, a write operation is

selected. The next two bytes received define the

address of the first data byte (Figure 5-2). Because

only A14…A0 are used, the upper address bits are a

“don’t care.” The upper address bits are transferred

first, followed by the Less Significant bits.

5.1

Contiguous Addressing Across

Multiple Devices

The Chip Select bits A2, A1 and A0 can be used to

expand the contiguous address space for up to 2 Mbit

by adding up to eight 24AA256UID devices on the

same bus. In this case, software can use A0 of the

control byte as address bit A15; A1 as address bit

A16; and A2 as address bit A17. It is not possible to

sequentially read across device boundaries.

Following the Start condition, the 24AA256UID moni-

tors the SDA bus checking the device type identifier

being transmitted. Upon receiving a ‘1010’ code and

appropriate device select bits, the slave device outputs

an Acknowledge signal on the SDA line. Depending on

the state of the R/W bit, the 24AA256UID will select a

read or write operation.

FIGURE 5-2:

ADDRESS SEQUENCE BIT ASSIGNMENTS

Control Byte

Address High Byte

Address Low Byte

A

2

A

1

A

0

A

10

A

9

A

8

A

7

A

0

•

1

0

1

0

R/W

x

12 11

14 13

Control

Code

Chip

Select

Bits

x = “don’t care” bit

 2013 Microchip Technology Inc.

DS20005215A-page 7

24AA256UID

6.3

Write Protection

6.0

6.1

WRITE OPERATIONS

Byte Write

The upper eighth of the array (7000h-7FFFh) is perma-

nently write-protected. Write operations to this address

range are inhibited. Read operations are not affected.

Following the Start condition from the master, the

control code (four bits), the Chip Select (three bits) and

the R/W bit (which is a logic low) are clocked onto the

bus by the master transmitter. This indicates to the

addressed slave receiver that the address high byte will

follow after it has generated an Acknowledge bit during

the ninth clock cycle. Therefore, the next byte

transmitted by the master is the high-order byte of the

word address and will be written into the Address

Pointer of the 24AA256UID. The next byte is the Least

Significant Address Byte. After receiving another

Acknowledge signal from the 24AA256UID, the master

device will transmit the data word to be written into the

addressed memory location. The 24AA256UID

acknowledges again and the master generates a Stop

condition. This initiates the internal write cycle and

during this time, the 24AA256UID will not generate

Acknowledge signals (Figure 6-1).

The remainder of the array (0000h-6FFFh) can be writ-

ten to and read from normally.

Note:

Page write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page size’) and end at addresses that

are integer multiples of [page size – 1]. If

a Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is, therefore, necessary for

the application software to prevent page

write operations that would attempt to

cross a page boundary.

Note:

When doing a write of less than 64 bytes

the data in the rest of the page is

refreshed along with the data bytes being

written. This will force the entire page to

endure a write cycle, for this reason

endurance is specified per page.

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24AA256UID in much the

same way as in a byte write. The exception is that

instead of generating a Stop condition, the master

transmits up to 63 additional bytes, which are tempo-

rarily stored in the on-chip page buffer, and will be writ-

ten into memory once the master has transmitted a

Stop condition. Upon receipt of each word, the six lower

Address Pointer bits are internally incremented by one.

If the master should transmit more than 64 bytes prior

to generating the Stop condition, the address counter

will roll over and the previously received data will be

overwritten. As with the byte write operation, once the

Stop condition is received, an internal write cycle will

begin (Figure 6-2).

DS20005215A-page 8

 2013 Microchip Technology Inc.

24AA256UID

FIGURE 6-1:

BYTE WRITE

S

T

A

R

T

Bus Activity

Master

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Data

SDA Line

A A A

x

S 1 0 1 0

0

P

2 1 0

Bus Activity

A

C

K

A

C

K

A

C

K

A

C

K

x = “don’t care” bit

FIGURE 6-2:

PAGE WRITE

S

T

A

R

T

Bus Activity

Master

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Data Byte 0

Data Byte 63

SDA Line

A A A

x

P

S 1 0 1 0

0

2 1 0

Bus Activity

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

x = “don’t care” bit

 2013 Microchip Technology Inc.

DS20005215A-page 9

24AA256UID

FIGURE 7-1:

ACKNOWLEDGE

POLLING FLOW

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (This feature can be used to maximize bus

throughput). Once the Stop condition for a Write

command has been issued from the master, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master

sending a Start condition, followed by the control byte

for a Write command (R/W = 0). If the device is still

busy with the write cycle, then no ACK will be returned.

If no ACK is returned, the Start bit and control byte must

be resent. If the cycle is complete, then the device will

return the ACK and the master can then proceed with

the next Read or Write command. See Figure 7-1 for

the flow diagram.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

NO

Did Device

Acknowledge

(ACK = 0)?

YES

DS20005215A-page 10

 2013 Microchip Technology Inc.

24AA256UID

8.2

Random Read

8.0

READ OPERATION

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, the word address must first

be set. This is done by sending the word address to the

24AA256UID as part of a write operation (R/W bit set to

‘0’). Once the word address is sent, the master gener-

ates a Start condition following the acknowledge. This

terminates the write operation, but not before the

internal Address Pointer is set. The master then issues

the control byte again, but with the R/W bit set to a one.

The 24AA256UID will then issue an acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer, though it does generate a

Stop condition, which causes the 24AA256UID to dis-

continue transmission (Figure 8-2). After a random

Read command, the internal address counter will point

to the address location following the one that was just

read.

Read operations are initiated in much the same way as

write operations, with the exception that the R/W bit of

the control byte is set to ‘1’. There are three basic types

of read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 24AA256UID contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by ‘1’. Therefore, if the previous read

access was to address ‘n’ (n is any legal address), the

next current address read operation would access data

from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘1’,

the 24AA256UID issues an acknowledge and transmits

the 8-bit data word. The master will not acknowledge

the transfer, but does generate a Stop condition and the

24AA256UID discontinues transmission (Figure 8-1).

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24AA256UID trans-

mits the first data byte, the master issues an acknowl-

edge as opposed to the Stop condition used in a

random read. This acknowledge directs the

24AA256UID to transmit the next sequentially

addressed 8-bit word (Figure 8-3). Following the final

byte transmitted to the master, the master will NOT

generate an acknowledge, but will generate a Stop

condition. To provide sequential reads, the

24AA256UID contains an internal Address Pointer

which is incremented by one at the completion of each

operation. This Address Pointer allows the entire mem-

ory contents to be serially read during one operation.

The internal Address Pointer will automatically roll over

from address 7FFF to address 0000 if the master

acknowledges the byte received from the array

address 7FFF.

FIGURE 8-1:

CURRENT ADDRESS

READ

S

T

A

R

T

S

T

O

P

Bus Activity

Master

Control

Byte

Data

Byte

A A A

2 1 0

SDA Line

S 1 0 1 0

1

P

A

C

K

N

O

Bus Activity

A

C

K

FIGURE 8-2:

RANDOM READ

S

T

A

R

T

S

Bus Activity

Master

T

A

R

T

S

T

O

P

Control

Byte

Address

High Byte

Address

Low Byte

Control

Byte

Data

Byte

A A A

2 1 0

A A A

2 1 0

SDA Line

x

S 1 0 1 0

0

S 1 0 1 0

1

P

A

C

K

A

C

K

A

C

K

N

O

A

C

A

C

K

Bus Activity

x = “don’t care” bit

FIGURE 8-3:

SEQUENTIAL READ

S

Control

Byte

Bus Activity

Master

T

Data (n)

Data (n + 1)

Data (n + x)

Data (n + 2)

O

P

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

N

O

A

C

K

Bus Activity

 2013 Microchip Technology Inc.

DS20005215A-page 11

24AA256UID

9.1

32-Bit Serial Number

9.0

PRE-PROGRAMMED SERIAL

NUMBER AND NODE

ADDRESSES

The 24AA256UID features a unique 32-bit serial

number stored in array locations 0x7FFC through

0x7FFF, as shown in Figure 9-2.

The 24AA256UID is programmed at the factory with

globally unique EUI-48 and EUI-64 node addresses,

and a 32-bit serial number stored in the upper eighth of

the array and permanently write-protected. The

remaining 229,376 bits are available for application

use.

Note:

The 32-bit serial number is unique across

all Microchip UID-family serial EEPROM

devices.

9.1.1

MANUFACTURER AND DEVICE

IDENTIFIERS

FIGURE 9-1:

MEMORY ORGANIZATION

In addition to the serial number, a manufacturer code is

stored at location 0x7FFA and a device identifier is

stored at 0x7FFB. The manufacturer code is fixed as

0x29. For the 24AA256UID, the device identifier is

0x48. The ‘4’ indicates the I²C™ family and the ‘8’ indi-

cates a 256 Kbit memory density.

0000h

Standard EEPROM

9.1.2

EXTENDING THE 32-BIT SERIAL

NUMBER

(User – Writable)

For applications that require serial numbers larger than

32 bits, additional data bytes can be used to pad the

provided serial number to meet the required length.

Any data byte values can be used for padding as the

32-bit serial number ensures the extended serial

number remains unique.

6FFFh

7000h

The padding can be performed in two ways. The first

method is to pad the data in software by combining the

32-bit serial number from the 24AA256UID with fixed

data. The second method is to extend the number of

bytes read from the 24AA256UID to meet the required

length. Table 9-1 shows example address ranges and

their corresponding serial number lengths.

Unused (Read as 0xFF)

7F79h

7F7Ah

EUI-48™ Node Address

Unused (Read as 0xFF)

7F7Fh

7FB8h

7FBFh

EUI-64™ Node Address

Unused (Read as 0xFF)

TABLE 9-1:

EXTENDED READ EXAMPLES

7FFAh

7FFFh

Serial Number

End Address

32-Bit Serial Number and Identifiers

Start Address

Length

0x7FFC

0x7FFA

0x7FF8

0x7FF0

0x7FE0

0x7FFF

32 bits

48 bits

64 bits

128 bits

256 bits

Note:

Shaded region is permanently write-protected

DS20005215A-page 12

 2013 Microchip Technology Inc.

24AA256UID

FIGURE 9-2:

SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE

Manufacturer

Code

Device

Code

Description

32-bit Serial Number

29h

48h

12h

34h

56h

78h

Data

Type

Fixed

Serialized

Array

Address

7FFAh

7FFBh

7FFCh

7FFDh

7FFEh

7FFFh

9.2

EUI-48 Node Address

9.3

EUI-64 Node Address

The 6-byte EUI-48 node address value is stored in

array locations 0x7F7A through 0x7F7F, as shown in

Figure 9-3. The first three bytes are the

Organizationally Unique Identifier (OUI) assigned to

Microchip by the IEEE Registration Authority. Currently,

Microchip’s OUIs are 0x0004A3 and 0x001EC0,

though this will change as addresses are exhausted.

The remaining three bytes are the Extension Identifier,

and are generated by Microchip to ensure a globally

unique, 48-bit value.

The 8-byte EUI-64 node address value is stored in

array locations 0x7FB8 through 0x7FBF, as shown in

Figure 9-4. The first three bytes are the

Organizationally Unique Identifier (OUI) assigned to

Microchip by the IEEE Registration Authority. Currently,

Microchip’s OUIs are 0x0004A3 and 0x001EC0,

though this will change as addresses are exhausted.

The remaining five bytes are the Extension Identifier,

and are generated by Microchip to ensure a globally

unique, 64-bit value.

Note:

In conformance with IEEE guidelines,

Microchip will not use the values 0xFFFE

and 0xFFFF for the first two bytes of the

EUI-64 Extension Identifier. These two

values are specifically reserved to allow

applications to encapsulate EUI-48

addresses into EUI-64 addresses.

FIGURE 9-3:

EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE

24-bit Organizationally

Unique Identifier

24-bit Extension

Identifier

Description

00h

04h

A3h

12h

34h

56h

Data

Array

Address

7F7Ah

7F7Fh

Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56

 2013 Microchip Technology Inc.

DS20005215A-page 13

24AA256UID

FIGURE 9-4:

EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE

24-bit Organizationally

Unique Identifier

40-bit Extension

Identifier

Description

Data

00h

04h

A3h

12h

34h

56h

78h

90h

Array

Address

7FB8h

7FBFh

Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90

DS20005215A-page 14

 2013 Microchip Technology Inc.

24AA256UID

10.0 PACKAGING INFORMATION

10.1

Package Marking Information

8-Lead PDIP (300 mil)

Example:

4A256UID

I/P 017

XXXXXXXX

T/XXXNNN

YYWW

e

3

1321

8-Lead SOIC (150 mil)

Example:

XXXXXXXT

4A256UID

e

3

XXXXYYWW

SN

1321

NNN

017

Example:

8-Lead TSSOP

XXXX

YYWW

AAAP

1321

NNN

017

Legend: XX...X Part number or part number code

T

Temperature (I, E)

Y

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

YY

WW

NNN

e

3

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For

device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.

 2013 Microchip Technology Inc.

DS20005215A-page 15

24AA256UID

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N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

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ꢁꢞꢺꢨ

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ꢩꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ

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ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ

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ꢠꢀ

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ꢁꢣꢀꢥ

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ꢁꢞꢙꢨ

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ꢯꢡꢡꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢳꢕꢗꢌꢐꢅꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢴꢆꢌꢐꢉꢊꢊꢅꢼꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ

ꢜꢘꢊꢃꢉꢝ

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ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢶꢩ

DS20005215A-page 16

 2013 Microchip Technology Inc.

24AA256UID

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2013 Microchip Technology Inc.

DS20005215A-page 17

24AA256UID

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20005215A-page 18

 2013 Microchip Technology Inc.

24AA256UID

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ

ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ

ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ

 2013 Microchip Technology Inc.

DS20005215A-page 19

24AA256UID

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D

N

E

E1

NOTE 1

1

2

b

e

c

φ

A

A2

A1

L

L1

ꢯꢄꢃꢏꢇ

ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ

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ꢱ

ꢌ

ꢶ

ꢣꢁꢺꢨꢅꢩꢛꢝ

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ꢷ

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ꢷ

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ꢀꢁꢣꢨ

ꢣꢁꢀꢨ

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ꢦꢀ

ꢠ

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ꢠꢀ

ꢟ

ꢳ

ꢥꢁꢞꢣ

ꢙꢁꢸꢣ

ꢣꢁꢥꢨ

ꢥꢁꢥꢣ

ꢞꢁꢣꢣ

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ꢥꢁꢨꢣ

ꢞꢁꢀꢣ

ꢣꢁꢻꢨ

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ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ

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ꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ

ꢳꢀ

ꢀ

ꢀꢁꢣꢣꢅꢼꢠꢬ

ꢣꢾ

ꢣꢁꢣꢸ

ꢣꢁꢀꢸ

ꢷ

ꢶꢾ

ꢖ

ꢔ

ꢣꢁꢙꢣ

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DS20005215A-page 20

 2013 Microchip Technology Inc.

24AA256UID

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2013 Microchip Technology Inc.

DS20005215A-page 21

24AA256UID

APPENDIX A: REVISION HISTORY

Revision A (06/2013)

Initial Release.

DS20005215A-page 22

 2013 Microchip Technology Inc.

24AA256UID

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following informa-

tion:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers should contact their distributor, representa-

tive or Field Application Engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A listing of sales offices and locations is included in

the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registration

instructions.

 2013 Microchip Technology Inc.

DS20005215A-page 23

24AA256UID

NOTES:

DS20005215A-page 24

 2013 Microchip Technology Inc.

24AA256UID

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a) 24AA256UID-I/P: Industrial Temp.,

1.7V, PDIP package.

Temperature

Range

Package

b) 24AA256UIDT-I/SN: Tape and Reel,

Industrial Temp., 1.7V, SOIC

package.

Device:

24AA256UID = 256 Kbit 1.7V I²C Serial

EEPROM, with EUI-48 and

c) 24AA256UID-I/ST: Industrial Temp.,

1.7V, TSSOP package.

EUI-64 Node Identities and 32-bit

Serial Number

24AA256UIDT = 256 Kbit 1.7V I²C Serial

EEPROM, with EUI-48 and

EUI-64 Node Identities and 32-bit

Serial Number (Tape and Reel)

Temperature I

=

-40C to +85C

Range:

Package:

P

= Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (3.90 mm body), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

 2013 Microchip Technology Inc.

DS20005215A-page 25

24AA256UID

NOTES:

DS20005215A-page 26

 2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash

and UNI/O are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

32

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MTP, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

Analog-for-the-Digital Age, Application Maestro, BodyCom,

chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,

Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA

and Z-Scale are trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

GestIC and ULPP are registered trademarks of Microchip

Technology Germany II GmbH & Co. KG, a subsidiary of

Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 9781620772911

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TS 16949 ==

 2013 Microchip Technology Inc.

DS20005215A-page 27

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Korea - Seoul

China - Hangzhou

Tel: 86-571-2819-3187

Fax: 86-571-2819-3189

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7828

Fax: 886-7-330-9305

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

China - Xiamen

Tel: 905-673-0699

Fax: 905-673-6509

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

11/29/12

DS20005215A-page 28

 2013 Microchip Technology Inc.


型号：	24AA256UIDT-I/ST
厂家：	MICROCHIP
描述：	256K I2Câ¢ Serial EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总28页 (文件大小：575K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24AA256UIDT-I/ST [MICROCHIP]

相关型号：

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24AA32-/SM

24AA32-P

24AA32-SN

24AA32/P

24AA32/SM

24AA32/SN

24AA32A

24AA32A-/P