24C02A-IP [MICROCHIP]

1K/2K/4K 5.0V I 2 C O Serial EEPROMs; 1K / 2K / 4K 5.0V的I 2 C O串行EEPROM的


型号：	24C02A-IP
厂家：	MICROCHIP
描述：	1K/2K/4K 5.0V I 2 C O Serial EEPROMs 1K / 2K / 4K 5.0V的I 2 C O串行EEPROM的可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总12页 (文件大小：80K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24C01A/02A/04A

1K/2K/4K 5.0V I C Serial EEPROMs

FEATURES

PACKAGE TYPES

• Low power CMOS technology

• Hardware write protect

• Two wire serial interface bus, I²C compatible

DIP

VCC

WP*

• 5.0V only operation

• Self-timed write cycle (including auto-erase)

• Page-write buffer

SCL

SDA

VSS

• 1ms write cycle time for single byte

• 1,000,000 Erase/Write cycles guaranteed

• Data retention >200 years

8-lead

SOIC

• 8-pin DIP/SOIC packages

VCC

• Available for extended temperature ranges

WP*

SCL

SDA

- Commercial (C):

- Industrial (I):

- Automotive (E):

0˚C to +70˚C

-40˚C to +85˚C

-40˚C to +125˚C

DESCRIPTION

VSS

The Microchip Technology Inc. 24C01A/02A/04A is a

1K/2K/4K bit Electrically Erasable PROM. The device

is organized as shown, with a standard two wire serial

interface. Advanced CMOS technology allows a signif-

icant reduction in power over NMOS serial devices. A

special feature in the 24C02A and 24C04A provides

hardware write protection for the upper half of the block.

The 24C01A and 24C02A have a page write capability

of two bytes and the 24C04A has a page length of eight

bytes. Up to eight 24C01A or 24C02A devices and up

to four 24C04A devices may be connected to the same

two wire bus.

14-lead

SOIC

V^CC

SCL

SDA

V^SS

* “TEST” pin in 24C01A

This device offers fast (1ms) byte write and

extended (-40°C to 125°C) temperature operation. It

is recommended that all other applications use

Microchip’s 24LCXXB.

BLOCK DIAGRAM

Data

Buffer

(FIFO)

24C01A

24C02A

24C04A

Vcc

Vpp

R/W Amp

Vss

Organization

Write Protect

128 x 8

None

258 x 8

080-0FF

2 Bytes

2 x 256 x 8

100-1FF

8 Bytes

Data Reg.

A P

d o

Page Write

Buffer

2 Bytes

Memory

Array

SDA

Slave Addr.

A0 to

s e

Control

Logic

Increment

SCL

A0 A1 A2 WP

I²C is a trademark of Philips Corporation.

1996 Microchip Technology Inc.

DS11183D-page 1

This document was created with FrameMaker 4 0 4

24C01A/02A/04A

TABLE 1-1:

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

Name

1.1

Maximum Ratings*

No Function for 24C04A only, Must

be connected to VCC or VSS

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V

Storage temperature ..................................... -65˚C to +150˚C

Ambient temp. with power applied ................ -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins................................................4 kV

A0, A1, A2 Chip Address Inputs

VSS

SDA

SCL

TEST

Ground

Serial Address/Data I/O

Serial Clock

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this speciﬁcation is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

(24C01A only) VCC or VSS

Write Protect Input

+5V Power Supply

VCC

TABLE 1-2:

DC CHARACTERISTICS

VCC = +5V (±10%)

Commercial (C): Tamb = 0°C to +70°C

Industrial (I): Tamb = -40°C to +85°C

Automotive (E): Tamb = -40°C to +125°C

Parameter

Symbol

Min.

Max.

Units

Conditions

VCC detector threshold

VTH

2.8

4.5

SCL and SDA pins:

High level input voltage

Low level input voltage

Low level output voltage

VIH

VIL

VOL

VCC x 0.7 VCC + 1

-0.3

VCC x 0.3

0.4

IOL = 3.2 mA (SDA only)

A1 & A2 pins:

High level input voltage

Low level input voltage

VIH

VIL

VCC - 0.5 VCC + 0.5

-0.3

0.5

Input leakage current

Output leakage current

ILI

—

µA

VIN = 0V to VCC

ILO

—

VOUT = 0V to VCC

Pin capacitance

CIN,

—

7.0

VIN/VOUT = 0V (Note)

(all inputs/outputs)

COUT

Tamb = +25˚C, f = 1 MHz

Operating current

ICC Write

—

3.5

4.25

750

100

µA

FCLK = 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = 0˚C to +70˚C

ICC Write

FCLK = 100 kHz, program cycle time = 1 ms,

Vcc = 5V, Tamb = (I) and (E)

ICC

Read

VCC = 5V, Tamb= (C), (I) and (E)

Standby current

ICCS

µA

SDA=SCL=VCC=5V (no PROGRAM active)

Note: This parameter is periodically sampled and not 100% tested

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

SDA

THD:STA

TSU:STA

TSU:STO

START

STOP

DS11183D-page 2

1996 Microchip Technology Inc.

24C01A/02A/04A

TABLE 1-3:

AC CHARACTERISTICS

Parameter

Symbol

Min.

Typ

Max.

Units

Remarks

Clock frequency

FCLK

THIGH

TLOW

—

4000

4700

—

100

—

kHz

Clock high time

Clock low time

—

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

1000

300

—

THD:STA

4000

After this period the ﬁrst

clock pulse is generated

START condition setup time

TSU:STA

4700

—

Only relevant for repeated

START condition

Data input hold time

Data input setup time

Data output delay time

STOP condition setup time

Bus free time

THD:DAT

TSU:DAT

TAA

—

250

300

3500

—

(Note 1)

TSU:STO

TBUF

4700

—

Time the bus must be free

before a new transmission

can start

Input ﬁlter time constant

(SDA and SCL pins)

—

100

Program cycle time

TWC

.4N

—

Byte mode

Page mode, N=# of bytes

Endurance

—

cycles

25°C, Vcc = 5.0V, Block

Mode (Note 2)

Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undeﬁned region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

THIGH

TLOW

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

THD:STA

SDA

TSP

TBUF

TAA

THD:STA

SDA

OUT

1996 Microchip Technology Inc.

DS11183D-page 3

24C01A/02A/04A

3.3

Stop Data Transfer (C)

2.0

FUNCTIONAL DESCRIPTION

The 24C01A/02A/04A supports a bidirectional two wire

bus and data transmission protocol. A device that

sends data onto the bus is deﬁned as transmitter, and

a device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24C01A/02A/04A works as slave. Both master and

slave can operate as transmitter or receiver but the

master device determines which mode is activated.

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Up to eight 24C01/24c02s can be connected to the bus,

selected by the A0, A1 and A2 chip address inputs. Up

to four 24C04As can be connected to the bus, selected

by A1 and A2 chip address inputs. A0 must be tied to

VCC or VSS for the 24C04A. Other devices can be con-

nected to the bus but require different device codes

than the 24C01A/02A/04A (refer to section Slave

Address).

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited.

3.5

Acknowledge

3.0

BUS CHARACTERISTICS

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Note: The 24C01A/02A/04A does not generate

any acknowledge bits if an internal pro-

gramming cycle is in progress.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case, the slave must leave the data line HIGH to enable

the master to generate the STOP condition.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

DS11183D-page 4

1996 Microchip Technology Inc.

24C01A/02A/04A

4.0

SLAVE ADDRESS

6.0

PAGE PROGRAM MODE

The chip address inputs A0, A1 and A2 of each 24C01A/

02A/04A must be externally connected to either VCC or

ground (VSS), assigning to each 24C01A/02A/04A a

unique address. A0 is not used on the 24C04A and

must be connected to either VCC or VSS. Up to eight

24C01A or 24C02A devices and up to four 24C04A

devices may be connected to the bus. Chip selection is

then accomplished through software by setting the bits

A0, A1 and A2 of the slave address to the corresponding

hard-wired logic levels of the selected 24C01A/02A/04A.

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the 24C01A/02A/04A, followed by the

chip address bits A0, A1 and A2. In the 24C04A, the

seventh bit of that byte (A0) is used to select the upper

block (addresses 100—1FF) or the lower block

(addresses 000—0FF) of the array.

To program the 24C01A/02A/04A, the master sends

addresses and data to the 24C01A/02A/04A which is

the slave (Figure 6-1 and Figure 6-2). This is done by

supplying a START condition followed by the 4-bit

device code, the 3-bit slave address, and the R/W bit

which is deﬁned as a logic LOW for a write. This indi-

cates to the addressed slave that a word address will

follow so the slave outputs the acknowledge pulse to

the master during the ninth clock pulse. When the word

address is received by the 24C01A/02A/04A, it places

it in the lower 8 bits of the address pointer deﬁning

which memory location is to be written. (The A0 bit

transmitted with the slave address is the ninth bit of the

address pointer for the 24C04A). The 24C01A/02A/04A

will generate an acknowledge after every 8-bits

received and store them consecutively in a RAM buffer

until a STOP condition is detected. This STOP condi-

tion initiates the internal programming cycle. The RAM

buffer is 2 bytes for the 24C01A/02A and 8 bytes for the

24C04A. If more than 2 bytes are transmitted by the

master to the 24C01A/02A, the device will not acknowl-

edge the data transfer and the sequence will be

aborted. If more than 8 bytes are transmitted by the

master to the 24C04A, it will roll over and overwrite the

data beginning with the ﬁrst received byte. This does

not affect erase/write cycles of the EEPROM array and

is accomplished as a result of only allowing the address

registers bottom 3 bits to increment while the upper 5

bits remain unchanged.

The eighth bit of slave address determines if the master

device wants to read or write to the 24C01A/02A/04A

(Figure 4-1).

The 24C01A/02A/04A monitors the bus for its corre-

sponding slave address all the time. It generates an

acknowledge bit if the slave address was true and it is

not in a programming mode.

FIGURE 4-1: SLAVE ADDRESS

ALLOCATION

START

READ/WRITE

If the master generates a STOP condition after trans-

mitting the ﬁrst data word (Point ‘P’ on Figure 6-1), byte

programming mode is entered.

SLAVE ADDRESS

R/W

The internal, completely self-timed PROGRAM cycle

starts after the STOP condition has been generated by

the master and all received data bytes in the page

buffer will be written in a serial manner.

The PROGRAM cycle takes N milliseconds, whereby N

is the number of received data bytes (N max = 8 for

24C04A, 2 for 24C01A/02A).

5.0

BYTE PROGRAM MODE

In this mode, the master sends addresses and one data

byte to the 24C01A/02A/04A.

Following the START signal from the master, the device

code (4-bits), the slave address (3-bits), and the R/W

bit, which is logic LOW, are placed onto the bus by the

master. This indicates to the addressed 24C01A/02A/

04A that a byte with a word address will follow after it

has generated an acknowledge bit. Therefore the next

byte transmitted by the master is the word address and

will be written into the address pointer of the 24C01A/

02A/04A. After receiving the acknowledge of the

24C01A/02A/04A, the master device transmits the data

word to be written into the addressed memory location.

The 24C01A/02A/04A acknowledges again and the

master generates a STOP condition. This initiates the

internal programming cycle of the 24C01A/02A/04A

(Figure 6-1).

1996 Microchip Technology Inc.

DS11183D-page 5

24C01A/02A/04A

FIGURE 6-1: BYTE WRITE

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS

DATA

SDA LINE

BUS ACTIVITY

FIGURE 6-2: PAGE WRITE

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 1

DATA n + 7

SDA LINE

BUS ACTIVITY

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

7.0

ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 7-1 for ﬂow diagram.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

YES

Operation

DS11183D-page 6

1996 Microchip Technology Inc.

24C01A/02A/04A

The master now generates another START condition

and transmits the slave address again, except this time

the read/write bit is set into the read mode. After the

slave generates the acknowledge bit, it then outputs

the data from the addressed location on to the SDA pin,

increments the address pointer and, if it receives an

acknowledge from the master, will transmit the next

consecutive byte. This auto-increment sequence is

only aborted when the master sends a STOP condition

instead of an acknowledge.

8.0

WRITE PROTECTION

Programming of the upper half of the memory will not

take place if the WP pin of the 24C02A or 24C04A is

connected to VCC (+5.0V). The device will accept slave

and word addresses but if the memory accessed is

write protected by the WP pin, the 24C02A/04A will not

generate an acknowledge after the ﬁrst byte of data has

been received, and thus the program cycle will not be

started when the STOP condition is asserted. Polarity

of the WP pin has no effect on the 24C01A.

Note 1: If the master knows where the address

pointer is, it can begin the read sequence

at the current address (Figure 9-1) and

save time transmitting the slave and word

addresses.

9.0

READ MODE

This mode illustrates master device reading data from

the 24C01A/02A/04A.

As can be seen from Figure 9-2 and Figure 9-3, the

master ﬁrst sets up the slave and word addresses by

doing a write. (Note: Although this is a read mode, the

address pointer must be written to). During this period

the 24C01A/02A/04A generates the necessary

acknowledge bits as deﬁned in the appropriate section.

Note 2: In all modes, the address pointer will not

increment through a block (256 byte)

boundary, but will rotate back to the ﬁrst

location in that block.

FIGURE 9-1: CURRENT ADDRESS READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

SDA LINE

BUS ACTIVITY

FIGURE 9-2: RANDOM READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

DATA (n)

SDA LINE

BUS ACTIVITY

1996 Microchip Technology Inc.

DS11183D-page 7

24C01A/02A/04A

FIGURE 9-3: SEQUENTIAL READ

BUS ACTIVITY

MASTER

CONTROL

BYTE

DATA n

DATA n + 1

DATA n + 2

DATA n + X

SDA LINE

BUS ACTIVITY

This feature allows the user to assign the upper half of

the memory as ROM which can be protected against

accidental programming. When write is disabled, slave

address and word address will be acknowledged but

data will not be acknowledged.

10.0 PIN DESCRIPTION

10.1

A0, A1, A2 Chip Address Inputs

The levels on these inputs are compared with the cor-

responding bits in the slave address. The chip is

selected if the compare is true. For 24C04 A0 is no

function.

Note 1: A “page” is deﬁned as the maximum num-

ber of bytes that can be programmed in a

single write cycle. The 24C04A page is 8

bytes long; the 24C01A/02A page is 2

bytes long.

Up to eight 24C01A/02A's or up to four 24C04A's can

be connected to the bus.

These inputs must be connected to either VSS or VCC.

Note 2: A “block” is deﬁned as a continuous area

of memory with distinct boundaries. The

address pointer can not cross the bound-

ary from one block to another. It will how-

ever, wrap around from the end of a block

to the ﬁrst location in the same block. The

24C04A has two blocks, 256 bytes each.

The 24C01A and 24C02A each have only

one block.

10.2

SDASerialAddress/DataInput/Output

This is a bidirectional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typical 10KΩ).

For normal data transfer, SDAis allowed to change only

during SCL LOW. Changes during SCL HIGH are

reserved for indicating the START and STOP condi-

tions.

10.3

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

10.4

WP Write Protection

This pin must be connected to either VCC or VSS for

24C02A or 24C04A. It has no effect on 24C01A.

If tied to VCC, PROGRAM operations onto the upper

memory block will not be executed. Read operations

are possible.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

DS11183D-page 8

1996 Microchip Technology Inc.

24C01A/02A/04A

NOTES:

1996 Microchip Technology Inc.

DS11183D-page 9

24C01A/02A/04A

NOTES:

DS11183D-page 10

1996 Microchip Technology Inc.

24C01A/02A/04A

24C01A/02A/04A Product Identiﬁcation System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

24C01A/02A/04A

Package:

P = Plastic DIP

SN = Plastic SOIC (150 mil Body), 8-lead

SM = Plastic SOIC (207 mil Body), 8-lead

SL = Plastic SOIC (150 mil Body), 14-lead, 24C04A only

Temperature

Range:

Blank = 0°C to +70°C

I = -40°C to +85°C

E = -40°C to +125°C

Device:

24C01A

1K I C Serial EEPROM

24C01AT

24C02A

24C02AT

24C04A

24C04AT

1K I C Serial EEPROM (Tape and Reel)

2K I C Serial EEPROM

2K I C Serial EEPROM (Tape and Reel)

4K I C Serial EEPROM

4K I C Serial EEPROM (Tape and Reel)

1996 Microchip Technology Inc.

DS11183D-page 11

WORLDWIDE SALES & SERVICE

AMERICAS

Corporate Ofﬁce

ASIA/PACIFIC

China

EUROPE

United Kingdom

Microchip Technology Inc.

Microchip Technology

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Bourne End, Buckinghamshire SL8 5AJ

Tel: 44 1628 850303 Fax: 44 1628 850178

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 602 786-7200 Fax: 602 786-7277

Technical Support: 602 786-7627

Web: http://www.microchip.com

Unit 406 of Shanghai Golden Bridge Bldg.

2077 Yan’an Road West, Hongiao District

Shanghai, Peoples Republic of China

Tel: 86 21 6275 5700

Fax: 011 86 21 6275 5060

Hong Kong

Microchip Technology

RM 3801B, Tower Two

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T. Hong Kong

Tel: 852 2 401 1200 Fax: 852 2 401 3431

India

Microchip Technology

No. 6, Legacy, Convent Road

Bangalore 560 025 India

Tel: 91 80 526 3148 Fax: 91 80 559 9840

France

Atlanta

Arizona Microchip Technology SARL

Zone Industrielle de la Bonde

2 Rue du Buisson aux Fraises

91300 Massy - France

Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Muenchen, Germany

Tel: 49 89 627 144 0 Fax: 49 89 627 144 44

Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770 640-0034 Fax: 770 640-0307

Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 508 480-9990 Fax: 508 480-8575

Chicago

Italy

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 708 285-0071 Fax: 708 285-0075

Dallas

Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 972 991-7177 Fax: 972 991-8588

Dayton

Microchip Technology Inc.

Suite 150

Arizona Microchip Technology SRL

Centro Direzionale Colleone Pas Taurus 1

Viale Colleoni 1

20041 Agrate Brianza

Milan Italy

Korea

Microchip Technology

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku,

Seoul, Korea

Tel: 82 2 554 7200 Fax: 82 2 558 5934

Singapore

Microchip Technology

200 Middle Road

#10-03 Prime Centre

Singapore 188980

Tel: 65 334 8870 Fax: 65 334 8850

Taiwan, R.O.C

Microchip Technology

10F-1C 207

Tung Hua North Road

Taipei, Taiwan, ROC

Tel: 886 2 717 7175 Fax: 886 2 545 0139

Tel: 39 39 6899939 Fax: 39 39 689 9883

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Two Prestige Place

Miamisburg, OH 45342

Tel: 513 291-1654 Fax: 513 291-9175

Tel: 81 45 471 6166 Fax: 81 45 471 6122

9/3/96

Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 714 263-1888 Fax: 714 263-1338

NewYork

Microchip Technmgy Inc.

150 Motor Parkway, Suite 416

Hauppauge, NY 11788

Tel: 516 273-5305 Fax: 516 273-5335

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 436-7950 Fax: 408 436-7955

Toronto

Microchip Technology Inc.

5925 Airport Road, Suite 200

Mississauga, Ontario L4V 1W1, Canada

Tel: 905 405-6279 Fax: 905 405-6253

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-

sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement

of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-

rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and

DS11183D-page 12

1996 Microchip Technology Inc.

24C02A-IP [MICROCHIP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E