24C02BT-E/P_技术文档

Obsolete Device

Please use 24LC01B or 24LC02B.

24C01B/02B

1K/2K 5.0V I²C^™Serial EEPROM

FEATURES

PACKAGE TYPES

PDIP

• Single supply with 5.0V operation

• Low power CMOS technology

NC

1

2

3

8

7

6

Vcc

WP

- 1 mA active current typical

- 10 µA standby current typical at 5.0V

- 5 µA standby current typical at 5.0V

• Organized as a single block of 128 bytes (128 x 8)

or 256 bytes (256 x 8)

• 2-wire serial interface bus, I²C compatible

• 100 kHz compatibility

SCL

SDA

Vss

4

5

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• ESD protection > 3,000V

• 1,000,000 ERASE/WRITE cycles guaranteed

Data retention > 200 years

• 8 pin DIP or SOIC package

SOIC

1

2

8

NC

Vcc

7

6

5

WP

• Available for extended temperature ranges

3

4

SCL

SDA

- Automotive (E):

-40°C to +125°C

Vss

DESCRIPTION

The Microchip Technology Inc. 24C01B and 24C02B

are 1K bit and 2K bit Electrically Erasable PROMs. The

devices are organized as a single block of 128 x 8 bit

or 256 x 8 bit memory with a 2-wire serial interface.

The 24C01B and 24C02B also have page-write capa-

bility for up to 8 bytes of data. The 24C01B and 24C02B

are available in the standard 8-pin DIP and an 8-pin

surface mount SOIC package.

BLOCK DIAGRAM

WP

HV GENERATOR

I/O

CONTROL

LOGIC

MEMORY

CONTROL

LOGIC

These devices are for extended temperature

applications only. It is recommended that all other

applications use Microchip’s 24LC01B/02B.

EEPROM

ARRAY

XDEC

PAGE LATCHES

SDA SCL

YDEC

VCC

VSS

SENSE AMP

R/W CONTROL

I²C is a trademark of Philips Corporation.

 2004 Microchip Technology Inc.

Preliminary

DS21233B-page 1

24C01B/02B

TABLE 1-1:

Name

PIN FUNCTION TABLE

Function

1.0

ELECTRICAL CHARACTERISTICS

1.1

Maximum Ratings*

VSS

SDA

SCL

WP

VCC

NC

Ground

Serial Address/Data I/O

Serial Clock

Write Protect Input

+5.0V Power Supply

No Internal Connection

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD protection on all pins............................................ Š 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

TABLE 1-1:

DC CHARACTERISTICS

All parameters apply across the speci-

VCC = +4.5V to 5.5V

fied operating ranges unless otherwise Automotive (E): Tamb = -40°C to 125°C

noted.

Parameter

Symbol

Min.

Max.

Units

Conditions

WP, SCL and SDA pins:

High level input voltage

VIH

.7 VCC

V

Low level input voltage

Hysteresis of Schmidt trigger inputs

Low level output voltage

VIL

VHYS

VOL

ILI

.3 VCC

—

V

.05 VCC

(Note)

.40

10

V

IOL = 3.0 mA, VCC = 2.5V

VIN = .1V to 5.5V

Input leakage current

-10

—

µA

µmA

pF

Output leakage current

ILO

10

VOUT = .1V to 5.5V

Pin capacitance (all inputs/outputs)

CIN,

10

VCC = 5.0V (Note)

COUT

Tamb = 25°C, FCLK = 1 MHz

Operating current

Standby current

ICC Write

ICC Read

ICCS

—

3

1

mA

µA

VCC = 5.5V, SCL = 100 kHz

30

100

VCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC

µA

Note:

This parameter is periodically sampled and not 100% tested.

FIGURE 1-1: BUS TIMING START/STOP

VHYS

SCL

THD:STA

TSU:STA

TSU:STO

SDA

START

STOP

DS21233B-page 2

Preliminary

 2004 Microchip Technology Inc.

24C01B/02B

TABLE 1-2:

AC CHARACTERISTICS

All Parameters apply across the

specified operating ranges unless

otherwise noted

Vcc = 4.5V to 5.5V

Automotive (E):

Tamb = -40°C to +125°C,

Parameter

Symbol

Min.

Max.

Units

Remarks

Clock frequency

FCLK

THIGH

TLOW

TR

—

4000

4700

—

100

—

kHz

ns

Clock high time

Clock low time

—

ns

SDA and SCL rise time

SDA and SCL fall time

START condition hold time

1000

300

—

ns

(Note 1)

TF

—

ns

THD:STA

4000

ns

After this period the first clock pulse is

generated

START condition setup time

TSU:STA

4700

—

ns

Only relevant for repeated

START condition

Data input hold time

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time

THD:DAT

TSU:DAT

TSU:STO

TAA

0

—

ns

(Note 2)

250

4000

—

3500

—

TBUF

4700

Time the bus must be free before a new

transmission can start

Output fall time from VIH

minimum to VIL maximum

TOF

TSP

—

250

50

ns

(Note 1), CB ð 100 pF

Input filter spike suppression

(SDA and SCL pins)

(Note 3)

Write cycle time

Endurance

TWR

—

10

—

ms

Byte or Page mode

1M

cycles 25°C, Vcc = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-2: BUS TIMING DATA

TR

TF

THIGH

TLOW

SCL

TSU:STA

THD:DAT

TSU:DAT

TSU:STO

THD:STA

SDA

IN

TSP

TAA

THD:STA

TAA

TBUF

SDA

OUT

 2004 Microchip Technology Inc.

Preliminary

DS21233B-page 3

24C01B/02B

3.3

Stop Data Transfer (C)

2.0

FUNCTIONAL DESCRIPTION

The 24C01B/02B supports a bi-directional two wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24C01B/02B works as slave. Both master and slave

can operate as transmitter or receiver but the master

device determines which mode is activated.

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

3.0

BUS CHARACTERISTICS

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last six-

teen will be stored when doing a write operation. When

an overwrite does occur it will replace data in a first in

first out fashion.

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

3.1

Bus Not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

Note: The 24C01B/02B does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

DS21233B-page 4

Preliminary

 2004 Microchip Technology Inc.

24C01B/02B

3.6

Device Address

4.0

WRITE OPERATION

After generating a START condition, the bus master

transmits the slave address consisting of a 4-bit device

code (1010) for the 24C01B/02B, followed by three

don't care bits.

4.1

Byte Write

Following the start signal from the master, the device

code (4 bits), the don't care bits (3 bits), and the R/W bit

which is a logic low is placed onto the bus by the master

transmitter. This indicates to the addressed slave

receiver that a byte with a word address will follow after

it has generated an acknowledge bit during the ninth

clock cycle. Therefore the next byte transmitted by the

master is the word address and will be written into the

address pointer of the 24C01B/02B. After receiving

another acknowledge signal from the 24C01B/02B the

master device will transmit the data word to be written

into the addressed memory location. The 24C01B/02B

acknowledges again and the master generates a stop

condition. This initiates the internal write cycle, and

during this time the 24C01B/02B will not generate

acknowledge signals (Figure 4-1).

The eighth bit of slave address determines if the master

device wants to read or write to the 24C01B/02B

(Figure 3-2).

The 24C01B/02B monitors the bus for its correspond-

ing slave address all the time. It generates an acknowl-

edge bit if the slave address was true and it is not in a

programming mode.

Control

Code

Chip

Select

Operation

R/W

Read

Write

1010

XXX

1

0

FIGURE 3-2: CONTROL BYTE

ALLOCATION

4.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24C01B/02B in the same

way as in a byte write. But instead of generating a stop

condition the master transmits up to eight data bytes to

the 24C01B/02B which are temporarily stored in the

on-chip page buffer and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the three lower order address

pointer bits are internally incremented by one. The

higher order five bits of the word address remains con-

stant. If the master should transmit more than eight

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 4-2).

START

READ/WRITE

R/W

X

A

SLAVE ADDRESS

1

0

1

0

X

X = Don’t care

FIGURE 4-1: BYTE WRITE

S

BUS ACTIVITY

MASTER

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS

DATA

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

FIGURE 4-2: PAGE WRITE

S

BUS ACTIVITY

MASTER

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS (n)

A

R

T

DATA n

DATAn + 1

DATAn + 7

SDA LINE

S

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

 2004 Microchip Technology Inc.

Preliminary

DS21233B-page 5

24C01B/02B

5.0

ACKNOWLEDGE POLLING

7.0

READ OPERATION

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. ACK polling can

be initiated immediately. This involves the master send-

ing a start condition followed by the control byte for a

write command (R/W = 0). If the device is still busy with

the write cycle, then no ACK will be returned. If the

cycle is complete, then the device will return the ACK

and the master can then proceed with the next read or

write command. See Figure 5-1 for flow diagram.

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read,

and sequential read.

7.1

Current Address Read

The 24C01B/02B contains an address counter that

maintains the address of the last word accessed, inter-

nally incremented by one. Therefore, if the previous

access (either a read or write operation) was to

address n, the next current address read operation

would access data from address n + 1. Upon receipt of

the slave address with R/W bit set to one, the 24C01B/

02B issues an acknowledge and transmits the eight bit

data word. The master will not acknowledge the trans-

fer but does generate a stop condition and the 24C01B/

02B discontinues transmission (Figure 7-1).

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

7.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24C01B/02B as part of a write operation. After the word

address is sent, the master generates a start condition

following the acknowledge. This terminates the write

operation, but not before the internal address pointer is

set. Then the master issues the control byte again but

with the R/W bit set to a one. The 24C01B/02B will then

issue an acknowledge and transmits the eight bit data

word. The master will not acknowledge the transfer but

does generate a stop condition and the 24C01B/02B

discontinues transmission (Figure 7-2).

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

7.3

Sequential Read

Did Device

NO

Acknowledge

Sequential reads are initiated in the same way as a ran-

dom read except that after the 24C01B/02B transmits

the first data byte, the master issues an acknowledge

as opposed to a stop condition in a random read. This

directs the 24C01B/02B to transmit the next sequen-

tially addressed 8-bit word (Figure 7-3).

(ACK = 0)?

YES

To provide sequential reads the 24C01B/02B contains

an internal address pointer which is incremented by

one at the completion of each operation. This address

pointer allows the entire memory contents to be serially

read during one operation.

6.0

WRITE PROTECTION

The 24C01B/02B can be used as a serial ROM when

the WP pin is connected to VCC. Programming will be

inhibited and the entire memory will be write-protected.

7.4

Noise Protection

The 24C01B/02B employs a VCC threshold detector

circuit which disables the internal erase/write logic if the

VCC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter

circuits which suppress noise spikes to assure proper

device operation even on a noisy bus.

DS21233B-page 6

Preliminary

 2004 Microchip Technology Inc.

24C01B/02B

FIGURE 7-1: CURRENT ADDRESS READ

S

T

BUS ACTIVITY

CONTROL

S

T

O

P

A

R

T

MASTER

BYTE

DATA n

SDA LINE

S

P

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 7-2: RANDOM READ

S

T

A

R

T

S

T

A

R

T

S

T

CONTROL

BYTE

WORD

ADDRESS (n)

CONTROL

BYTE

BUS ACTIVITY

MASTER

DATA n

O

P

S

SDA LINE

A

C

K

A

C

K

A

C

K

N

O

BUS ACTIVITY

A

C

K

FIGURE 7-3: SEQUENTIAL READ

S

A

C

K

A

C

K

A

C

K

T

CONTROL

BYTE

BUS ACTIVITY

MASTER

O

P

SDA LINE

P

A

C

K

N

O

BUS ACTIVITY

DATA n

DATA n + 1

DATA n + 2

DATA n + X

A

C

K

8.3

WP

8.0

PIN DESCRIPTIONS

This pin must be connected to either VSS or VCC.

8.1

Serial Data

If tied to VSS, normal memory operation is enabled

(read/write the entire memory).

This is a bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain terminal, therefore the SDA bus requires a pull-up

resistor to VCC (typically 10 K¾ for 100 kHz).

If tied to VCC, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations

are not affected.

For normal data transfer SDA is allowed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

This feature allows the user to use the 24C01B/02B as

a serial ROM when WP is enabled (tied to VCC).

8.2

SCL Serial Clock

This input is used to synchronize the data transfer from

and to the device.

 2004 Microchip Technology Inc.

Preliminary

DS21233B-page 7

24C01B/02B

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

24C01B/02B

—

/P

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body)

Package:

Temperature

Range:

E = -40°C to +125°C

24C01B

1K I²C Serial EEPROM

24C01BT

24C02B

1K I²C Serial EEPROM (Tape and Reel)

2K I²C Serial EEPROM

Device:

24C02BT

2K I²C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

DS21233B-page 8

Preliminary

 2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized except

with express written approval by Microchip. No licenses are

conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,

SmartSensor and The Embedded Control Solutions Company

are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Migratable Memory, MPASM,

MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,

PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,

PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,

SmartTel and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc.

Preliminary

DS21233B-page 9

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Addison, TX 75001

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Tel: 86-21-6275-5700

Fax: 86-21-6275-5060

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250

China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86-755-82901380

Fax: 86-755-8295-1393

China - Shunde

Fax: 248-538-2260

Kokomo

2767 S. Albright Road

Kokomo, IN 46902

Tel: 765-864-8360

Fax: 765-864-8387

Room 401, Hongjian Building, No. 2

Fengxiangnan Road, Ronggui Town, Shunde

District, Foshan City, Guangdong 528303, China

Tel: 86-757-28395507 Fax: 86-757-28395571

Los Angeles

25950 Acero St., Suite 200

Mission Viejo, CA 92691

Tel: 949-462-9523

Germany

China - Qingdao

Rm. B505A, Fullhope Plaza,

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Tel: 86-532-5027355 Fax: 86-532-5027205

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Fax: 949-462-9608

San Jose

1300 Terra Bella Avenue

Mountain View, CA 94043

Tel: 650-215-1444

Italy

India

Via Salvatore Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-22290061 Fax: 91-80-22290062

Japan

Fax: 650-961-0286

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

Waegenburghtplein 4

NL-5152 JR, Drunen, Netherlands

Tel: 31-416-690399

Toronto

6285 Northam Drive, Suite 108

Mississauga, Ontario L4V 1X5, Canada

Tel: 905-673-0699

Yusen Shin Yokohama Building 10F

3-17-2, Shin Yokohama, Kohoku-ku,

Yokohama, Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Fax: 905-673-6509

Fax: 31-416-690340

ASIA/PACIFIC

Australia

Microchip Technology Australia Pty Ltd

Unit 32 41 Rawson Street

Epping 2121, NSW

Sydney, Australia

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

United Kingdom

505 Eskdale Road

Winnersh Triangle

Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

Wokingham

Berkshire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or

82-2-558-5934

07/12/04

Preliminary

 2004 Microchip Technology Inc.


型号：	24C02BT-E/P
厂家：	MICROCHIP
描述：	1K/2K 5.0V I2C⑩ Serial EEPROM 1K / 2K 5.0V I2C⑩串行EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总10页 (文件大小：111K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

24C02BT-E/P [MICROCHIP]

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