24LC04B/STRVC [MICROCHIP]
512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 4.40 MM, PLASTIC, TSSOP-8;型号: | 24LC04B/STRVC |
厂家: | MICROCHIP |
描述: | 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 4.40 MM, PLASTIC, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
文件: | 总20页 (文件大小:355K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
24LC04B/08B
M
4K/8K 2.5 I2C™ Serial EEPROMs
FEATURES
PACKAGE TYPES
• Single supply with operation down to 2.5V
• Low power CMOS technology
PDIP, SOIC
A0
A1
A2
1
2
3
8
7
6
VCC
WP
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as two or four blocks of 256 bytes
(2 x 256 x 8) and (4 x 256 x 8)
SCL
SDA
Vss
4
5
• 2-wire serial interface bus, I2C™ compatible
• Schmitt trigger, filtered inputs for noise
suppression
TSSOP
MSOP
1
2
3
4
8
7
6
5
A0
A1
VCC
• Output slope control to eliminate ground bounce
WP
• 100 kHz (E-temp) and 400 kHz (C/I-temp.)
compatibility
A2
SCL
SDA
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• Factory programming (QTP) available
• ESD protection > 4,000V
VSS
1
2
3
4
8
A0
A1
A2
VCC
7
6
5
WP
SCL
SDA
VSS
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
Note: A0, A1 and A2 are not used
• 8-pin DIP, 8-lead SOIC, 8-pin TSSOP packages
• Available temperature ranges:
- Commercial (C):
- Industrial (I):
- Automotive (E):
0°C to
-40°C to
-40°C to +125°C
+70°C
+85°C
BLOCK DIAGRAM
WP
DESCRIPTION
HV GENERATOR
The Microchip Technology Inc. 24LC04B/08B is a 4
Kbit or 8 Kbit Electrically Erasable PROM (EEPROM).
The device is organized as two or four blocks of 256 x
8-bit memory with a 2-wire serial interface. Low voltage
design permits operation down to 2.5 volts with typical
standby and active currents of only 5 µA and 1 mA
respectively. The 24LC04B/08B also has a page-write
capability for up to 16 bytes of data. The 24LC04B/08B
is available in the standard 8-pin DIP, 8-lead surface
mount SOIC, MSOP and TSSOP packages.
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
EEPROM ARRAY
(2 x 256 x 8) or
(4 x 256 x 8)
XDEC
PAGE LATCHES
SDA
SCL
YDEC
VCC
VSS
SENSE AMP
R/W CONTROL
2001 Microchip Technology Inc.
DS21051H-page 1
24LC04B/08B
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
VSS
SDA
Ground
1.1
Maximum Ratings*
Serial Address/Data I/O
Serial Clock
VCC........................................................................7.0V
All inputs and outputs w.r.t. VSS ....-0.3V to VCC + 1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
Soldering temperature of leads (10 seconds) ..+300°C
ESD protection on all pins .....................................≥ 4 KV
SCL
WP
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
VCC
A0, A1, A2
*Notice: Stresses above those listed under “Maximum
ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the opera-
tional listings of this specification is not implied.
Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C):
TAMB = 0°C to +70°C
TAMB = -40°C to +85°C
TAMB = -40°C to +125°C
VCC = +2.5V to +5.5V
Industrial (I):
Automotive (E):
Parameter
Symbol
Min.
Max.
Units
Conditions
WP, SCL and SDA pins:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger
Inputs
VIH
VIL
VHYS
.7 VCC
—
.05 VCC
—
.3 VCC
—
V
V
V
—
—
(Note)
Low level output voltage
VOL
ILI
—
-10
-10
—
.40
10
10
10
V
IOL = 3.0mA, VCC = 2.5V
VIN = 0.1V to VCC
Input leakage current
Output leakage current
µA
µA
pF
ILO
VOUT = 0.1V to VCC
Pin capacitance
CIN, COUT
VCC = 5.0V (Note)
(all inputs/outputs)
TAMB = 25°C, FCLK = 1 MHz
Operating current
ICC Write
ICC Read
—
—
3
1
mA
mA
VCC = 5.5V, SCL = 400 kHz
—
Standby current
ICCS
—
—
30
100
µA
µA
VCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note:
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
VHYS
SCL
THD:STA
TSU:STA
TSU:STO
SDA
START
STOP
DS21051H-page 2
2001 Microchip Technology Inc.
24LC04B/08B
TABLE 1-3:
AC CHARACTERISTICS
Commercial (C):
TAMB = 0°C to +70°C
TAMB = -40°C to +85°C
TAMB = -40°C to +125°C
Industrial (I):
VCC = +2.5V to 5.5V
Automotive (E):
Parameter
Clock frequency
Symbol
Min
Max
Units
Conditions
FCLK
—
—
400
100
kHz
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
Clock high time
Clock low time
THIGH
TLOW
TR
600
—
—
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
4000
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
1300
4700
—
—
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
SDA and SCL rise time
(Note 1)
—
—
300
1000
4.5V ≤ VCC ≤ 5.5V (Note 1)
2.5V ≤ VCC ≤ 5.5V (E-temp. range) (Note 1)
SDA and SCL fall time
TF
—
300
ns
ns
(Note 1)
START condition hold time
THD:STA
600
4000
—
—
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
START condition setup time
TSU:STA
600
4700
—
—
ns
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
Data input hold time
Data input setup time
THD:DAT
TSU:DAT
0
—
ns
ns
(Note 2)
100
250
—
—
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
STOP condition setup time
TSU:STO
TAA
600
—
—
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
4000
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
Output valid from clock
(Note 2)
—
—
900
3500
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
Bus free time: Time the bus must be
free before a new transmission can
start
TBUF
1300
4700
—
—
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (E-temp. range)
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
20+0.1CB
250
250
ns
ns
4.5V ≤ VCC ≤ 5.5V (Note 1)
—
2.5V ≤ VCC ≤ 5.5V (E-temp. range) (Note 1)
Input filter spike suppression
(SDA and SCL pins)
—
50
(Notes 1 and 3)
Write cycle time (byte or page)
Endurance
TWC
—
5
ms
—
1M
—
cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined Tsp and Vhys specifications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s website: www.microchip.com.
2001 Microchip Technology Inc.
DS21051H-page 3
24LC04B/08B
FIGURE 1-2:
BUS TIMING DATA
TF
TR
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TBUF
TAA
TAA
THD:STA
SDA
OUT
3.4
Data Valid (D)
2.0
FUNCTIONAL DESCRIPTION
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The 24LC04B/08B supports a bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter and if receiv-
ing data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC04B/08B works as
slave. Both master and slave can operate as transmit-
ter or receiver, but the master device determines which
mode is activated.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy
3.5
Acknowledge
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
Note: The 24LC04B/08B does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
3.1
Bus not Busy (A)
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
DS21051H-page 4
2001 Microchip Technology Inc.
24LC04B/08B
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
2001 Microchip Technology Inc.
DS21051H-page 5
24LC04B/08B
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
3.6
Device Addressing
A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC04B/08B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). B2 is a ‘don't care’ for both the
24LC04B and 24LC08B; B1 is a ‘don't care’ for the
24LC04B. They are used by the master device to select
which of the two or four 256 word blocks of memory are
to be accessed. These bits are in effect the most signif-
icant bits of the word address.
START
READ/WRITE
R/W
A
SLAVE ADDRESS
1
0
1
0
X
B1
B0
X = ’Don’t care’. B1 is ‘don’t care’ for 24LC04B.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected and when set to ‘0’, a write operation is
selected. Following the start condition, the 24LC04B/
08B monitors the SDA bus checking the device type
identifier being transmitted. Upon a 1010 code, the
slave device outputs an acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24LC04B/08B will select a read or write operation.
Control
Code
Operation
Block Select
R/W
Read
Write
1010
1010
Block Address
Block Address
1
0
DS21051H-page 6
2001 Microchip Technology Inc.
24LC04B/08B
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 4-2).
4.0
4.1
WRITE OPERATION
Byte Write
Following the start condition from the master, the
device code (4 bits), the block address (3 bits) and the
R/W bit, which is a logic LOW is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will fol-
low after it has generated an acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmit-
ted by the master is the word address and will be writ-
ten into the address pointer of the 24LC04B/08B. After
receiving another acknowledge signal from the
24LC04B/08B, the master device will transmit the data
word to be written into the addressed memory location.
The 24LC04B/08B acknowledges again and the mas-
ter generates a stop condition. This initiates the internal
write cycle. During this time, the 24LC04B/08B will not
generate acknowledge signals (Figure 4-1).
Note: Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a page write com-
mand attempts to write across a physi-
cal page boundary, the result is that the
data wraps around to the beginning of
the current page (overwriting data pre-
viously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for
the application software to prevent
page write operations that would
attempt to cross a page boundary.
4.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC04B/08B in the same
way as in a byte write. But instead of generating a stop
condition, the master transmits up to 16 data bytes to
the 24LC04B/08B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
FIGURE 4-1:
BYTE WRITE
S
T
A
R
T
S
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
FIGURE 4-2:
PAGE WRITE
S
T
A
R
T
BUS ACTIVITY
MASTER
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
DATA (n)
DATA (n + 1)
DATA (n + 15)
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
2001 Microchip Technology Inc.
DS21051H-page 7
24LC04B/08B
5.0
ACKNOWLEDGE POLLING
7.0
READ OPERATION
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the master, the device ini-
tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send-
ing a start condition followed by the control byte for a
write command (R/W = 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to a ’1’. There are three basic types
of read operations: current address read, random read
and sequential read.
7.1
Current Address Read
The 24LC04B/08B contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to ’1’, the 24LC04B/
08B issues an acknowledge and transmits the 8-bit
data word. The master will not acknowledge the trans-
fer but does generate a stop condition and the
24LC04B/08B discontinues transmission (Figure 7-1).
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
7.2
Random Read
Write Command
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC04B/08B as part of a write operation. After the
word address is sent, the master generates a start con-
dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W bit set to a ’1’. The 24LC04B/
08B will then issue an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC04B/08B discontinues transmission (Figure 7-2).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
7.3
Sequential Read
Did Device
Acknowledge
(ACK = 0)?
No
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC04B/08B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC04B/08B to transmit the next sequen-
tially addressed 8-bit word (Figure 7-3).
Yes
Next
Operation
To provide sequential reads the 24LC04B/08B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
6.0
WRITE PROTECTION
The 24LC04B/08B can be used as a serial ROM when
the WP pin is connected to VCC. Programming will be
inhibited and the entire memory will be write-protected.
7.4
Noise Protection
The 24LC04B/08B employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.
DS21051H-page 8
2001 Microchip Technology Inc.
24LC04B/08B
FIGURE 7-1:
CURRENT ADDRESS READ
S
T
S
T
A
R
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
O
DATA (n)
P
SDA LINE
S
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-2:
RANDOM READ
S
T
O
P
S
T
A
R
T
S
T
A
R
T
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
DATA (n)
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 7-3:
SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY CONTROL
DATA (n)
DATA (n + 1)
DATA (n + 2)
DATA (n + X)
MASTER
BYTE
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
8.3
WP
8.0
8.1
PIN DESCRIPTIONS
This pin must be connected to either VSS or VCC.
SDA Serial Address/Data Input/
Output
If tied to VSS, normal memory operation is enabled
(read/write the entire memory).
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for
400 kHz).
If tied to VCC, WRITE operations are inhibited. The
entire memory will be write-protected. Read operations
are not affected.
This feature allows the user to use the 24LC04B/08B
as a serial ROM when WP is enabled (tied to VCC).
For normal data transfer, SDA is allowed to change
only during SCL LOW. Changes during SCL HIGH are
reserved for indicating the START and STOP condi-
tions.
8.4
A0, A1, A2
These pins are not used by the 24LC04B/08B. They
may be left floating or tied to either VSS or VCC.
8.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2001 Microchip Technology Inc.
DS21051H-page 9
24LC04B/08B
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil)
Example
24LC04B
XXXXXXXX
XXXXXNNN
XXXXXNNN
YYWW
0025
8-Lead SOIC (150 mil)
Example
24LC04B
XXXX0025
XXXXXXXX
XXXXYYWW
NNN
NNN
Example
8-Lead TSSOP
XXXX
XYWW
NNN
4L04
IYWW
NNN
Example
8-Lead MSOP
XXXXX
YWWNNN
4L4BI
YWWNNN
Legend: XX...X Customer specific information*
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS21051H-page 10
2001 Microchip Technology Inc.
24LC04B/08B
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
A
.140
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2001 Microchip Technology Inc.
DS21051H-page 11
24LC04B/08B
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45×
c
A2
A
f
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
h
Chamfer Distance
Foot Length
L
f
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21051H-page 12
2001 Microchip Technology Inc.
24LC04B/08B
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
E
E1
p
D
2
1
n
B
α
A
c
A1
A2
f
β
L
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.026
0.65
Overall Height
A
.043
1.10
Molded Package Thickness
Standoff
A2
A1
E
.033
.035
.004
.251
.173
.118
.024
4
.037
.006
.256
.177
.122
.028
8
0.85
0.90
0.10
6.38
4.40
3.00
0.60
4
0.95
0.15
6.50
4.50
3.10
0.70
8
§
.002
.246
.169
.114
.020
0
0.05
6.25
4.30
2.90
0.50
0
Overall Width
Molded Package Width
Molded Package Length
Foot Length
E1
D
L
f
Foot Angle
c
Lead Thickness
.004
.007
0
.006
.010
5
.008
.012
10
0.09
0.19
0
0.15
0.25
5
0.20
0.30
10
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
2001 Microchip Technology Inc.
DS21051H-page 13
24LC04B/08B
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
NOM
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
8
8
.026
0.65
Overall Height
A
A2
A1
E
.044
1.18
Molded Package Thickness
Standoff
.030
.034
.038
.006
.200
.122
.122
.028
.039
0.76
0.05
0.86
0.97
0.15
.5.08
3.10
3.10
0.70
1.00
§
.002
.184
.114
.114
.016
.035
Overall Width
.193
.118
.118
.022
.037
4.90
3.00
3.00
0.55
0.95
4.67
2.90
2.90
0.40
0.90
Molded Package Width
Overall Length
E1
D
Foot Length
L
Footprint (Reference)
Foot Angle
F
φ
0
6
0
6
c
Lead Thickness
Lead Width
.004
.010
.006
.012
.008
.016
0.10
0.25
0.15
0.30
0.20
0.40
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
7
7
β
7
7
*Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
Drawing No. C04-111
DS21051H-page 14
2001 Microchip Technology Inc.
24LC04B/08B
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
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Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
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and a web browser, such as Netscape® or Microsoft®
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
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• Links to other useful web sites related to
Microchip Products
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technical information and more
• Listing of seminars and events
2001 Microchip Technology Inc.
DS21051H-page 15
24LC04B/08B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Literature Number:
DS21051H
Device:
24LC04B/08B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
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8. How would you improve our software, systems, and silicon products?
DS21051H-page 16
2001 Microchip Technology Inc.
24LC04B/08B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package Pattern
Range
a) 24LC04B–I/P Industrial Temp,
PDIP package, normal VDD limits.
b) 24LC08B/SN Commercial Temp.,
SOIC package, normal VDD limits.
Device:
24LC04B: VDD range 1.8V to 5.5V
24LC04BT: (Tape and Reel)
24LC08B: VDD range 2.5V to 5.5V
24LC08BT: (Tape and Reel)
Temperature
Range:
-
I
E
=
=
=
0°C to+70°C
-40°C to+85°C
-40°C to+125°C
Package:
P
SN
=
=
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body),
8-lead
ST
=
=
Plastic TSSOP (4.4mm body),
8-lead
MSOP, 8-lead
MS
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences
and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of
the following:
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3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2001 Microchip Technology Inc.
DS21051H-page 17
24LC04B/08B
NOTES:
DS21051H-page 18
2001 Microchip Technology Inc.
24LC04B/08B
“All rights reserved. Copyright © 2001, Microchip
Technology Incorporated, USA. Information contained
in this publication regarding device applications and the
like is intended through suggestion only and may be
superseded by updates. No representation or warranty
is given and no liability is assumed by Microchip
Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or
other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized
except with express written approval by Microchip. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip
Technology Inc. in the U.S.A. and other countries. All
rights reserved. All other trademarks mentioned herein
are the property of their respective companies. No
licenses are conveyed, implicitly or otherwise, under
any intellectual property rights.”
Trademarks
The Microchip name, logo, PIC, PICmicro,
PICMASTER, PICSTART, PRO MATE, KEELOQ,
SEEVAL, MPLAB and The Embedded Control
Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and
other countries.
Total Endurance, ICSP, In-Circuit Serial Programming,
FilterLab, MXDEV, microID, FlexROM, fuzzyLAB,
MPASM, MPLINK, MPLIB, PICDEM, ICEPIC,
Migratable Memory, FanSense, ECONOMONITOR,
Select Mode and microPort are trademarks of
Microchip Technology Incorporated in the U.S.A.
Serialized Quick Term Programming (SQTP) is a
service mark of Microchip Technology Incorporated in
the U.S.A.
All other trademarks mentioned herein are property of
their respective companies.
© 2001, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2001 Microchip Technology Inc.
DS21051H-page 19
M
WORLDWIDE SALES AND SERVICE
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AMERICAS
Corporate Office
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Technical Support: 480-792-7627
Web Address: http://www.microchip.com
ASIA/PACIFIC (continued)
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01/30/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 4/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21051H-page 20
2001 Microchip Technology Inc.
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