25AA160/ST [MICROCHIP]

2K X 8 SPI BUS SERIAL EEPROM, PDSO8, TSSOP-8;


型号：	25AA160/ST
厂家：	MICROCHIP
描述：	2K X 8 SPI BUS SERIAL EEPROM, PDSO8, TSSOP-8 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总16页 (文件大小：124K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M _{25AA160/25LC160/25C160}

™

16K SPI Bus Serial EEPROM

DEVICE SELECTION TABLE

PACKAGE TYPES

PDIP/SOIC

Part

Number

VCC

Range

Max Clock

Frequency

Temp

Ranges

VCC

HOLD

SCK

25C160

25LC160

25AA160

4.5-5.5V

2.5-5.5V

1.8-5.5V

3 MHz

2 MHz

1 MHz

C,I,E

C,I

VSS

FEATURES

• Low power CMOS technology

- Write current: 3 mA maximum

- Read current: 500 µA typical

- Standby current: 500 nA typical

• 2048 x 8 bit organization

• 16 byte page

BLOCK DIAGRAM

Status

HV Generator

• Write cycle time: 5ms max.

• Self-timed ERASE and WRITE cycles

• Block write protection

- Protect none, 1/4, 1/2, or all of array

• Built-in write protection

EEPROM

Array

Memory

Control

Logic

I/O Control

Logic

- Power on/off data protection circuitry

- Write enable latch

Dec

- Write protect pin

• Sequential read

• High reliability

Page Latches

Y Decoder

- Endurance: 1M cycles (guaranteed)

- Data retention: > 200 years

- ESD protection: > 4000 V

• 8-pin PDIP and SOIC packages

• Temperature ranges supported:

- Commercial (C):

- Industrial (I):

- Automotive (E) (25C160):

SCK

Sense Amp.

R/W Control

HOLD

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

Vcc

Vss

DESCRIPTION

The Microchip Technology Inc. 25AA160/25LC160/

25C160 (25xx160 ) are 16K bit serial Electrically Eras-

able PROMs. The memory is accessed via a simple

Serial Peripheral Interface (SPI) compatible serial bus.

The bus signals required are a clock input (SCK) plus

separate data in (SI) and data out (SO) lines. Access to

the device is controlled through a chip select (CS)

input.

Communication to the device can be paused via the

hold pin (HOLD). While the device is paused, transi-

tions on its inputs will be ignored, with the exception of

chip select, allowing the host to service higher priority

interrupts.

*25xx160 is used in this document as a generic part number for the 25AA160/25LC160/25C160 devices.

SPI is a trademark of Motorola.

1998 Microchip Technology Inc.

DS21231B-page 1

25AA160/25LC160/25C160

FIGURE 1-1: AC TEST CIRCUIT

1.0

ELECTRICAL

CHARACTERISTICS

VCC

1.1

Maximum Ratings*

2.25 K

Vcc ...................................................................................7.0V

All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V

Storage temperature ....................................... -65˚C to 150˚C

Ambient temperature under bias..................... -65˚C to 125˚C

Soldering temperature of leads (10 seconds) ............. +300˚C

ESD protection on all pins.................................................4kV

1.8 K

100 pF

*Notice: Stresses above those listed under ‘Maximum ratings’ may

cause permanent damage to the device.This is a stress rating only and

functional operation of the device at those or any other conditions

above those indicated in the operational listings of this speciﬁcation is

not implied. Exposure to maximum rating conditions for an extended

period of time may affect device reliability

1.2

AC Test Conditions

AC Waveform:

VLO = 0.2V

TABLE 1-1:

Name

PIN FUNCTION TABLE

Function

VHI = VCC - 0.2V

(Note 1)

(Note 2)

VHI = 4.0V

Chip Select Input

Serial Data Output

Serial Data Input

Serial Clock Input

Write Protect Pin

Ground

Timing Measurement Reference Level

Input

0.5 VCC

Output

SCK

Note 1: For VCC ≤ 4.0V

2: For VCC > 4.0V

VSS

VCC

HOLD

Supply Voltage

Hold Input

TABLE 1-2:

DC CHARACTERISTICS

All parameters apply over the Commercial (C): TAMB = 0°C to +70°C

VCC = 1.8V to 5.5V

speciﬁed operating ranges

unless otherwise noted.

Industrial (I):

Automotive (E): TAMB = -40°C to +125°C

TAMB = -40°C to +85°C

VCC = 1.8V to 5.5V

VCC = 4.5V to 5.5V (25C160 only)

Parameter

Symbol

Min

Max

Units

Test Conditions

VCC ≥ 2.7V (Note)

VIH1

VIH2

VIL1

VIL2

VOL

VOH

ILI

2.0

0.7 VCC

-0.3

VCC+1

0.8

High level input voltage

VCC< 2.7V (Note)

VCC ≥ 2.7V (Note)

Low level input voltage

Low level output voltage

-0.3

0.3 VCC

0.4

VCC < 2.7V (Note)

—

IOL = 2.1 mA

—

0.2

IOL = 1.0 mA, VCC < 2.5V

IOH =-400 µA

High level output voltage

Input leakage current

Output leakage current

VCC -0.5

-10

—

µA

CS = VCC, VIN = VSS TO VCC

CS = VCC, VOUT = VSS TO VCC

ILO

-10

Internal Capacitance

(all inputs and outputs)

CINT

—

TAMB = 25˚C, CLK = 1.0 MHz,

VCC = 5.0V (Note)

ICC Read

ICC Write

ICCS

—

500

µA

VCC = 5.5V; FCLK=3.0 MHz; SO = Open

VCC = 2.5V; FCLK=2.0 MHz; SO = Open

Operating Current

Standby Current

—

VCC= 5.5V

VCC = 2.5V

—

µA

CS = Vcc = 5.5V, Inputs tied to VCC or VSS

CS = Vcc = 2.5V, Inputs tied to VCC or VSS

Note: This parameter is periodically sampled and not 100% tested.

DS21231B-page 2

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

TABLE 1-3:

AC CHARACTERISTICS

All parameters apply over the

speciﬁed operating ranges

unless otherwise noted.

Commercial (C): Tamb = 0°C to +70°C

VCC = 1.8V to 5.5V

Industrial (I):

Tamb = -40°C to +85°C

Automotive (E):

Tamb = -40°C to +125°C VCC = 4.5V to 5.5V (25C160 only)

Parameter

Symbol

Min

Max

Units

Test Conditions

Clock Frequency

FCLK

—

MHz

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

CS Setup Time

CS Hold Time

TCSS

TCSH

100

250

500

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

150

250

475

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

CS Disable Time

Data Setup Time

TCSD

TSU

500

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

Data Hold Time

THD

100

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

CLK Rise Time

CLK Fall Time

Clock High Time

—

µs

(Note 1)

THI

150

250

475

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

Clock Low Time

TLO

150

250

475

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

Clock Delay Time

Clock Enable Time

TCLD

TCLE

—

Output Valid from

Clock Low

—

150

250

475

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

Output Hold Time

THO

TDIS

—

(Note 1)

Output Disable Time

—

200

250

500

VCC = 4.5V to 5.5V (Note 1)

VCC = 2.5V to 4.5V (Note 1)

VCC = 1.8V to 2.5V (Note 1)

HOLD Setup Time

THS

THH

THZ

THV

100

200

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

HOLD Hold Time

100

200

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

HOLD Low to Output High-Z

HOLD High to Output Valid

100

150

200

—

VCC = 4.5V to 5.5V (Note 1)

VCC = 2.5V to 4.5V (Note 1)

VCC = 1.8V to 2.5V (Note 1)

100

150

200

—

VCC = 4.5V to 5.5V

VCC = 2.5V to 4.5V

VCC = 1.8V to 2.5V

Internal Write Cycle Time

Endurance

TWC

—

E/W Cycles (Note 2)

Note 1: This parameter is periodically sampled and not 100% tested.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a speciﬁc application, please

consult the Total Endurance Model which can be obtained on ourwebsite.

1998 Microchip Technology Inc.

DS21231B-page 3

25AA160/25LC160/25C160

FIGURE 1-2: HOLD TIMING

THH

THS

THH

SCK

THZ

THV

high impedance

don’t care

n+2

n+1

n-1

TSU

n+1

n-1

HOLD

FIGURE 1-3: SERIAL INPUT TIMING

TCSD

TCLE

TCLD

TCSS

TCSH

Mode 1,1

Mode 0,0

Tsu

SCK

THD

MSB in

LSB in

high impedance

FIGURE 1-4: SERIAL OUTPUT TIMING

TCSH

TDIS

THI

TLO

Mode 1,1

Mode 0,0

SCK

MSB out

ISB out

don’t care

DS21231B-page 4

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

2.5

Write Protect (WP)

2.0

PIN DESCRIPTIONS

This pin is used in conjunction with the WPEN bit in

the status register to prohibit writes to the non-volatile

bits in the status register. When WP is low and WPEN

is high, writing to the non-volatile bits in the status reg-

ister is disabled. All other operations function normally.

When WP is high, all functions, including writes to the

non-volatile bits in the status register operate normally.

If the WPEN bit is set, WP low during a status register

write sequence will disable writing to the status regis-

ter. If an internal write cycle has already begun, WP

going low will have no effect on the write.

2.1

Chip Select (CS)

A low level on this pin selects the device. A high level

deselects the device and forces it into standby mode.

However, a programming cycle which is already initi-

ated or in progress will be completed, regardless of

the CS input signal. If CS is brought high during a pro-

gram cycle, the device will go in standby mode as

soon as the programming cycle is complete. As soon

as the device is deselected, SO goes to the high

impedance state, allowing multiple parts to share the

same SPI bus. A low to high transition on CS after a

valid write sequence initiates an internal write cycle.

After power-up, a low level on CS is required prior to

any sequence being initiated.

The WP pin function is blocked when the WPEN bit in

the status register is low. This allows the user to install

the 25xx160 in a system with WP pin grounded and

still be able to write to the status register. The WP pin

functions will be enabled when the WPEN bit is set

high.

2.2

Serial Input (SI)

The SI pin is used to transfer data into the device. It

receives instructions, addresses, and data. Data is

latched on the rising edge of the serial clock.

2.6

Hold (HOLD)

The HOLD pin is used to suspend transmission to the

25xx160 while in the middle of a serial sequence with-

out having to re-transmit the entire sequence over at a

later time. It must be held high any time this function is

not being used. Once the device is selected and a

serial sequence is underway, the HOLD pin may be

pulled low to pause further serial communication with-

out resetting the serial sequence. The HOLD pin must

be brought low while SCK is low, otherwise the HOLD

function will not be invoked until the next SCK high to

low transition. The 25xx160 must remain selected dur-

ing this sequence. The SI, SCK, and SO pins are in a

high impedance state during the time the part is

paused and transitions on these pins will be ignored.

To resume serial communication, HOLD must be

brought high while the SCK pin is low, otherwise serial

communication will not resume. Lowering the HOLD

line at any time will tri-state the SO line.

2.3

Serial Output (SO)

The SO pin is used to transfer data out of the 25xx160.

During a read cycle, data is shifted out on this pin after

the falling edge of the serial clock.

2.4

Serial Clock (SCK)

The SCK is used to synchronize the communication

between a master and the 25xx160. Instructions,

addresses, or data present on the SI pin are latched

on the rising edge of the clock input, while data on the

SO pin is updated after the falling edge of the clock

input.

1998 Microchip Technology Inc.

DS21231B-page 5

25AA160/25LC160/25C160

3.3

Write Sequence

3.0

FUNCTIONAL DESCRIPTION

Prior to any attempt to write data to the 25xx160, the

write enable latch must be set by issuing the WREN

instruction (Figure 3-4). This is done by setting CS low

and then clocking out the proper instruction into the

25xx160. After all eight bits of the instruction are trans-

mitted, the CS must be brought high to set the write

enable latch. If the write operation is initiated immedi-

ately after the WREN instruction without CS being

brought high, the data will not be written to the array

because the write enable latch will not have been

properly set.

3.1

PRINCIPLES OF OPERATION

The 25xx160 are 2048 byte Serial EEPROMs

designed to interface directly with the Serial Peripheral

Interface (SPI) port of many of today’s popular micro-

controller families, including Microchip’s PIC16C6X/7X

microcontrollers. It may also interface with

microcontrollers that do not have a built-in SPI port by

using discrete

the software.

I/O lines programmed properly with

The 25xx160 contains an 8-bit instruction register. The

part is accessed via the SI pin, with data being clocked

in on the rising edge of SCK. The CS pin must be low

and the HOLD pin must be high for the entire opera-

tion. The WP pin must be held high to allow writing to

the memory array.

Once the write enable latch is set, the user may pro-

ceed by setting the CS low, issuing a write instruction,

followed by the 16-bit address, with the ﬁve MSBs of

the address being don’t care bits, and then the data to

be written. Up to 16 bytes of data can be sent to the

25xx160 before a write cycle is necessary. The only

restriction is that all of the bytes must reside in the

same page. A page address begins with XXXX XXXX

XXXX 0000 and ends with XXXX XXXX XXXX 1111. If

the internal address counter reaches XXXX XXXX

XXXX 1111 and the clock continues, the counter will

roll back to the ﬁrst address of the page and overwrite

any data in the page that may have been written.

Table 3-1 contains a list of the possible instruction

bytes and format for device operation. All instructions,

addresses, and data are transferred MSB ﬁrst, LSB

last.

Data is sampled on the ﬁrst rising edge of SCK after

CS goes low. If the clock line is shared with other

peripheral devices on the SPI bus, the user can assert

the HOLD input and place the 25xx160 in ‘HOLD’

mode. After releasing the HOLD pin, operation will

resume from the point when the HOLD was asserted.

For the data to be actually written to the array, the CS

must be brought high after the least signiﬁcant bit (D0)

of the n data byte has been clocked in. If CS is

brought high at any other time, the write operation will

not be completed. Refer to Figure 3-2 and Figure 3-3

for more detailed illustrations on the byte write

sequence and the page write sequence respectively.

While the write is in progress, the status register may

be read to check the status of the WPEN, WIP, WEL,

BP1, and BP0 bits (Figure 3-6). A read attempt of a

memory array location will not be possible during a

write cycle. When the write cycle is completed, the

write enable latch is reset.

3.2

Read Sequence

The part is selected by pulling CS low. The 8-bit read

instruction is transmitted to the 25xx160 followed by the

16-bit address, with the ﬁve MSBs of the address being

don’t care bits. After the correct read instruction and

address are sent, the data stored in the memory at the

selected address is shifted out on the SO pin.The data

stored in the memory at the next address can be read

sequentially by continuing to provide clock pulses. The

internal address pointer is automatically incremented

to the next higher address after each byte of data is

shifted out. When the highest address is reached

(07FFh), the address counter rolls over to address

0000h allowing the read cycle to be continued indeﬁ-

nitely. The read operation is terminated by raising the

CS pin (Figure 3-1).

TABLE 3-1:

INSTRUCTION SET

Instruction Name

Instruction Format

Description

READ

WRITE

WRDI

0000 0011

0000 0010

0000 0100

0000 0110

0000 0101

0000 0001

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Reset the write enable latch (disable write operations)

Set the write enable latch (enable write operations)

Read status register

WREN

RDSR

WRSR

Write status register

DS21231B-page 6

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

FIGURE 3-1: READ SEQUENCE

10 11

21 22 23 24 25 26 27 28 29 30 31

SCK

instruction

16 bit address

15 14 13 12

data out

high impedance

FIGURE 3-2: BYTE WRITE SEQUENCE

10 11

21 22 23 24 25 26 27 28 29 30 31

data byte

SCK

instruction

16 bit address

15 14 13 12

high impedance

FIGURE 3-3: PAGE WRITE SEQUENCE

10 11

21 22 23 24 25 26 27 28 29 30 31

data byte 1

SCK

instruction

16 bit address

15 14 13 12

32 33 34 35 36 37 38 39

data byte 2

41 42 43 44 45 46 47

data byte 3

SCK

data byte n (16 max)

1998 Microchip Technology Inc.

DS21231B-page 7

25AA160/25LC160/25C160

The following is a list of conditions under which the

write enable latch will be reset:

3.4

Write Enable (WREN) and Write

Disable (WRDI)

• Power-up

The 25xx160 contains a write enable latch.

See

• WRDI instruction successfully executed

• WRSR instruction successfully executed

• WRITE instruction successfully executed

Table 3-3 for the Write Protect Functionality Matrix.

This latch must be set before any write operation will

be completed internally. The WREN instruction will set

the latch, and the WRDI will reset the latch.

FIGURE 3-4: WRITE ENABLE SEQUENCE

SCK

high impedance

FIGURE 3-5: WRITE DISABLE SEQUENCE

SCK

high impedance

DS21231B-page 8

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

prohibits writes to the array. The state of this bit can

always be updated via the WREN or WRDI commands

regardless of the state of write protection on the status

3.5

Read Status Register (RDSR)

The RDSR instruction provides access to the status

even during a write cycle. The status register is format-

ted as follows:

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write protected. These bits

are set by the user issuing the WRSR instruction.

These bits are non-volatile.

WPEN

BP1

BP0

WEL

WIP

See Figure 3-6 for the RDSR timing sequence.

The Write-In-Process (WIP) bit indicates whether the

25xx160 is busy with a write operation. When set to a

‘1’ a write is in progress, when set to a ‘0’ no write is in

progress. This bit is read only.

The Write Enable Latch (WEL) bit indicates the sta-

tus of the write enable latch. When set to a ‘1’ the latch

allows writes to the array, when set to a ‘0’ the latch

FIGURE 3-6: READ STATUS REGISTER SEQUENCE

SCK

instruction

data from status register

high impedance

1998 Microchip Technology Inc.

DS21231B-page 9

25AA160/25LC160/25C160

writes to non-volatile bits in the status register are dis-

abled. See Table 3-3 for a matrix of functionality on the

WPEN bit.

3.6

Write Status Register(WRSR)

The WRSR instruction allows the user to select one of

four levels of protection for the array by writing to the

appropriate bits in the status register. The array is

divided up into four segments. The user has the ability

to write protect none, one, two, or all four of the seg-

ments of the array. The partitioning is controlled as

illustrated in Table 3-2.

See Figure 3-7 for the WRSR timing sequence.

TABLE 3-2:

BP1

ARRAY PROTECTION

Array Addresses

BP0

Write Protected

none

The Write Protect Enable (WPEN) bit is a non-volatile

bit that is available as an enable bit for the WP pin. The

Write Protect (WP) pin and the Write Protect Enable

(WPEN) bit in the status register control the program-

mable hardware write protect feature. Hardware write

protection is enabled when WP pin is low and the

WPEN bit is high. Hardware write protection is dis-

abled when either the WP pin is high or the WPEN bit

is low. When the chip is hardware write protected, only

upper 1/4

(0600h - 07FFh)

upper 1/2

(0400h - 07FFh)

all

(0000h - 07FFh)

FIGURE 3-7: WRITE STATUS REGISTER SEQUENCE

SCK

instruction

data to status register

high impedance

DS21231B-page 10

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

3.7

Data Protection

3.8

Power On State

The following protection has been implemented to pre-

vent inadvertent writes to the array:

The 25xx160 powers on in the following state:

• The device is in low power standby mode

(CS= 1).

• The write enable latch is reset.

• SO is in high impedance state.

• A low level on CS is required to enter active state.

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set

the write enable latch.

• After a byte write, page write, or status register

write, the write enable latch is reset.

• CS must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle

is ignored and programming is continued.

TABLE 3-3:

WPEN

WRITE PROTECT FUNCTIONALITY MATRIX

WEL

Protected Blocks

Unprotected Blocks

Status Register

Protected

Writable

Protected

Writable

Protected

Writable

Low

High

1998 Microchip Technology Inc.

DS21231B-page 11

25AA160/25LC160/25C160

NOTES:

DS21231B-page 12

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

NOTES:

1998 Microchip Technology Inc.

DS21231B-page 13

25AA160/25LC160/25C160

NOTES:

DS21231B-page 14

1998 Microchip Technology Inc.

25AA160/25LC160/25C160

25AA160/25LC160/25C160 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce..

25AA160/25LC160/25C160

—

P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body)

ST = TSSOP, 8-lead

Package:

OT = SOT-23, 5 lead

Blank = 0˚C to +70˚C

I = –40˚C to +85˚C

E = –40˚C to +125˚C

Temperature

Range:

24AA00

128 bit 1.8V I C Serial EEPROM

24AA00T

24LC00

24LC00T

24C00

128 bit 1.8V K I C Serial EEPROM (Tape and Reel)

128 bit 2.5V I C Serial EEPROM

Device:

128 bit 2.5V K I C Serial EEPROM (Tape and Reel)

128 bit 5.0V I C Serial EEPROM

24C00T

128 bit 5.0V K I C Serial EEPROM (Tape and Reel)

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales ofﬁce

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

1998 Microchip Technology Inc.

DS21231B-page 15

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Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

Tel: 770-640-0034 Fax: 770-640-0307

Boston

EUROPE

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 508-480-9990 Fax: 508-480-8575

Beijing

United Kingdom

Microchip Technology, Beijing

Unit 915, 6 Chaoyangmen Bei Dajie

Dong Erhuan Road, Dongcheng District

New China Hong Kong Manhattan Building

Beijing 100027 PRC

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44 118 921 5858 Fax: 44-118 921-5835

Denmark

Microchip Technology Denmark ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 86-10-85282100 Fax: 86-10-85282104

India

Tel: 630-285-0071 Fax: 630-285-0075

Dallas

Microchip Technology Inc.

4570 Westgrove Drive, Suite 160

Addison, TX 75248

Microchip Technology Inc.

India Liaison Office

No. 6, Legacy, Convent Road

Bangalore 560 025, India

Tel: 91-80-229-0061 Fax: 91-80-229-0062

Tel: 972-818-7423 Fax: 972-818-2924

Dayton

Microchip Technology Inc.

Two Prestige Place, Suite 150

Miamisburg, OH 45342

Tel: 937-291-1654 Fax: 937-291-9175

Detroit

Microchip Technology Inc.

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Japan

France

Microchip Technology Intl. Inc.

Benex S-1 6F

Arizona Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa 222-0033 Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 München, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Korea

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip Technology

RM 406 Shanghai Golden Bridge Bldg.

2077 Yan’an Road West, Hong Qiao District

Shanghai, PRC 200335

Italy

Los Angeles

Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949-263-1888 Fax: 949-263-1338

New York

Microchip Technology Inc.

150 Motor Parkway, Suite 202

Hauppauge, NY 11788

Tel: 631-273-5305 Fax: 631-273-5335

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

Tel: 86-21-6275-5700 Fax: 86 21-6275-5060

11/15/99

San Jose

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950 Fax: 408-436-7955

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed

by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products

as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip

logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

 1999 Microchip Technology Inc.

25AA160/ST [MICROCHIP]

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