27C17AF-25IP [MICROCHIP]
16K (2K x 8) CMOS EEPROM; 16K （ 2K ×8 ）的CMOS EEPROM
| 型号： | 27C17AF-25IP |
| 厂家： | 
MICROCHIP |
| 描述： | 16K (2K x 8) CMOS EEPROM |
| 文件： | 总8页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28C17A
16K (2K x 8) CMOS EEPROM
PACKAGE TYPES
FEATURES
RDY/BSY
NC
• 1
2
28 Vcc
27 WE
26 NC
25 A8
• Fast Read Access Time—150 ns
• CMOS Technology for Low Power Dissipation
- 30 mA Active
A7
3
A6
4
A6
A5
A4
A3
A2
A1 10
A0 11
NC 12
I/O0 13
5
6
7
8
9
29 A8
28 A9
A5
5
24 A9
- 100 µA Standby
A4
6
23 NC
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
27 NC
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
• Fast Byte Write Time—200 µs or 1 ms
• Data Retention >200 years
A3
7
A2
8
A1
9
4
• High Endurance - Minimum 10 Erase/Write Cycles
A0
10
11
12
13
I/O0
I/O1
I/O2
• Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
• Data Polling; Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
- Pulse Filter
VSS 14
• Pin 1 indicator on PLCC on top of package
OE
NC
A9
1
2
3
4
5
6
7
28 A10
27 CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
A8
NC
WE
Vcc
- Write Inhibit
• Electronic Signature for Device Identification
• 5-Volt-Only Operation
• Organized 2Kx8 JEDEC Standard Pinout
- 28 Pin Dual-In-Line Package
- 32-Pin PLCC Package
- 28-Pin Thin Small Outline Package (TSOP)
8x20mm
- 28-Pin Very Small Outline Package (VSOP)
8x13.4mm
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
RDY/BSY
NC
8
9
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
A7 10
A6 11
A5 12
A4 13
A3 14
OE
NC
A9
A8
NC
WE
22
23
24
25
26
27
A10
CE
21
20
19
18
17
16
15
14
13
12
11
10
9
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
28
1
VCC
RDY/BSY
2
3
4
5
6
7
NC
A7
A6
A5
A4
A3
A1
A2
8
DESCRIPTION
BLOCK DIAGRAM
The Microchip Technology Inc. 28C17A is a CMOS 16K non-
volatile electrically Erasable PROM. The 28C17A is
accessed like a static RAM for the read or write cycles without
the need of external components. During a “byte write”, the
address and data are latched internally, freeing the micropro-
cessor address and data bus for other operations. Following
the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an
internal control timer. To determine when the write cycle is
complete, the user has a choice of monitoring the Ready/
Busy output or using Data polling. The Ready/Busy pin is an
open drain output, which allows easy configuration in wired-
or systems. Alternatively, Data polling allows the user to read
the location last written to when the write operation is com-
plete. CMOS design and processing enables this part to be
used in systems where reduced power consumption and reli-
ability are required. A complete family of packages is offered
to provide the utmost flexibility in applications.
I/O0
I/O7
VSS
Data Protection
VCC
Circuitry
Chip Enable/
Output Enable
Control Logic
CE
OE
WE
Input/Output
Buffers
Auto Erase/Write
Timing
Data
Poll
Rdy/
Busy
Program Voltage
Generation
A0
Y
Y Gating
Decoder
L
a
t
c
h
e
s
16K bit
X
Decoder
Cell Matrix
A10
1996 Microchip Technology Inc.
DS11127G-page 1
28C17A
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
MAXIMUM RATINGS*
VCC and input voltages w.r.t. VSS.......-0.6V to + 6.25V
Voltage on OE w.r.t. VSS .....................-0.6V to +13.5V
Voltage on A9 w.r.t. VSS ......................-0.6V to +13.5V
Output Voltage w.r.t. VSS................ -0.6V to VCC+0.6V
Storage temperature .......................... -65˚C to +125˚C
Ambient temp. with power applied ....... -50˚C to +95˚C
A0 - A10
CE
Address Inputs
Chip Enable
OE
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy
WE
I/O0 - I/O7
RDY/Busy
VCC
*Notice: Stresses above those listed under “Maximum Ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operation listings of
this specification is not implied. Exposure to maximum rating con-
ditions for extended periods may affect device reliability.
+5V Power Supply
Ground
VSS
NC
No Connect; No Internal Connec-
tion
NU
Not Used; No External Connection
is Allowed
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
VCC = +5V ±10%
Commercial (C): Tamb = 0˚C to +70˚C
Industrial
(I): Tamb = -40˚C to +85˚C
Parameter
Status
Symbol
Min
Max
Units
Conditions
Input Voltages
Logic ‘1’
Logic ‘0’
VIH
VIL
2.0
-0.1
Vcc+1
0.8
V
V
Input Leakage
—
—
ILI
-10
—
10
10
µA
VIN = -0.1V to Vcc +1
Input Capacitance
CIN
pF
VIN = 0V; Tamb = 25˚C;
f = 1 MHz
Output Voltages
Logic ‘1’
Logic ‘0’
VOH
VOL
2.4
-10
—
V
V
IOH = -400 µA
IOL = 2.1 mA
0.45
10
Output Leakage
—
ILO
COUT
ICC
µA
VOUT = -0.1V to VCC
+0.1V
Output Capacitance
—
12
30
pF
VIN = 0V; Tamb = 25˚C;
f = 1 MHz
Power Supply Current, Active
Power Supply Current, Standby
TTL input
—
mA
f = 5 MHz (Note 1)
VCC = 5.5V;
TTL input
TTL input
CMOS input ICC(S)CMOS
ICC(S)TTL
ICC(S)TTL
—
2
3
100
mA
mA
µA
CE = VIH (0˚C to +70˚C)
CE = VIH (-40˚C to +85˚C)
CE = VCC-0.3 to Vcc +1
Note 1: AC power supply current above 5MHz: 1mA/MHz.
DS11127G-page 2
1996 Microchip Technology Inc.
28C17A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise and Fall Times:
Ambient Temperature:
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 ns
Commercial (C):
Tamb
Tamb
=
=
0˚C to +70˚C
-40˚C to +85˚C
Industrial
(I):
28C17A-15
Symbol
28C17A-20
28C17A-25
Parameter
Units
Conditions
Min
Max
Min
Max
Min
Max
Address to Output Delay
CE to Output Delay
OE to Output Delay
tACC
tCE
—
—
—
0
150
150
70
—
—
—
0
200
200
80
—
—
—
0
250
250
100
70
ns
ns
ns
ns
OE = CE = VIL
OE = VIL
tOE
CE = VIL
CE or OE High to Output
Float
tOFF
50
55
Output Hold from Address,
CE or OE, whichever occurs
first.
tOH
—
0
—
—
0
—
—
0
—
—
ns
Endurance
1M
1M
1M
cycles 25°C, Vcc =
5.0V, Block
Mode (Note)
Note: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: READ WAVEFORMS
VIH
Address
CE
Address Valid
VIL
VIH
VIL
tCE(2)
VIH
VIL
OE
tOFF(1,3)
tOH
tOE(2)
VOH
VOL
High Z
High Z
Data
Valid Output
tACC
VIH
WE
VOL
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested
1996 Microchip Technology Inc.
DS11127G-page 3
28C17A
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
Input Rise/Fall Times:
Ambient Temperature:
VIH = 2.4V; VIL = 0.45V; VOH = 2.0V; VOL = 0.8V
1 TTL Load + 100 pF
20 ns
Commercial (C):
Tamb
Tamb
=
=
0˚C to +70˚C
-40˚C to +85˚C
Industrial
(I):
Parameter
Symbol
Min
Max
Units
Remarks
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
tAS
tAH
10
50
50
10
100
50
10
10
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
tDS
—
tDH
—
Write Pulse Width
Write Pulse High Time
OE Hold Time
tWPL
tWPH
tOEH
tOES
tDV
—
Note 1
Note 2
—
—
OE Set-Up Time
—
Data Valid Time
1000
50
1
Time to Device Busy
Write Cycle Time (28C17A)
Write Cycle Time (28C17AF)
tDB
2
tWC
tWC
—
0.5 ms typical
—
200
100 µs typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the pos-
itive edge of CE or WE, whichever occurs first
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH after
the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2: PROGRAMMING WAVEFORMS
VIH
Address
VIL
tAS
tAH
VIH
VIL
tWPL
tDS
CE, WE
Data In
tDH
tDV
VIH
VIL
tOES
VIH
VIL
OE
tOEH
tDB
VOH
VOL
Rdy/Busy
Busy
Ready
tWC
DS11127G-page 4
1996 Microchip Technology Inc.
28C17A
FIGURE 1-3: DATA POLLING WAVEFORMS
VIH
Last Written
Address Valid
Address Valid
Address
CE
VIL
t ACC
VIH
VIL
tCE
t WPH
VIH
VIL
tWPL
WE
tOE
VIH
VIL
OE
tDV
VIH
VIL
Data In
Valid
True Data Out
Data
I/O7 Out
tWC
FIGURE 1-4: CHIP CLEAR WAVEFORMS
VIH
CE
VIL
VH
OE
VIH
tS
tH
tW
VIH
WE
tW
= 10ms
VIL
tS = = 1µs
tH
= 12.0V ±0.5V
VH
TABLE 1-5:
SUPPLEMENTARY CONTROL
Mode
CE
OE
WE
A9
Vcc
I/OI
Chip Clear
VIL
VIL
*
VH
VIL
VIH
VIL
VIH
*
X
VCC
Extra Row Read
Extra Row Write
Note 1: VH = 12.0V ±0.5V
A9 = VH
A9 = VH
VCC
VCC
Data Out
Data In
* Pulsed per programming waveforms.
1996 Microchip Technology Inc.
DS11127G-page 5
28C17A
2.4
Write Mode
2.0
DEVICE OPERATION
The Microchip Technology Inc. 28C17A has four basic
modes of operation—read, standby, write inhibit, and
byte write—as outlined in the following table.
The 28C17A has a write cycle similar to that of a Static
RAM. The write cycle is completely self-timed and ini-
tiated by a low going pulse on the WE pin. On the fall-
ing edge of WE, the address information is latched. On
rising edge, the data and the control pins (CE and OE)
are latched. The Ready/Busy pin goes to a logic low
level indicating that the 28C17A is in a write cycle which
signals the microprocessor host that the system bus is
free for other activity. When Ready/Busy goes back to
a high, the 28C17A has completed writing and is ready
to accept another cycle.
Operation
Mode
Rdy/Busy
(1)
CE OE WE
I/O
Read
L
H
H
X
X
L
L
X
X
L
H
X
X
X
H
L
DOUT
High Z
High Z
High Z
High Z
DIN
H
H
H
H
H
L
Standby
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
2.5
Data Polling
X
H
The 28C17A features Data polling to signal the comple-
tion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 are indetermin-
able). After completion of the write cycle, true data is
available. Data polling allows a simple read/compare
operation to determine the status of the chip eliminat-
ing the need for external hardware.
Automatic Before Each “Write”
Note 1: Open drain output.
2: X = Any TTL level.
2.1
Read Mode
The 28C17A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to
the output pins independent of device selection.
Assuming that addresses are stable, address access
time (tACC) equal to the delay from CE to output (tCE).
Data is available at the output tOE after the falling edge
of OE, assuming that CE has been low and addresses
have been stable for at least tACC-tOE.
2.6
Electronic Signature for Device
Identification
An extra row of 32 bytes of EEPROM memory is avail-
able to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 7EO to 7FF,
the additional bytes can be written to or read from in the
same manner as the regular memory array.
2.7
Chip Clear
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE low.
This procedure clears all data, except for the extra row.
2.2
Standby Mode
The 28C17A is placed in the standby mode by applying
a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
2.3
Data Protection
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the following
enhanced data protection circuits are incorporated:
First, an internal VCC detect (3.3 volts typical) will inhibit
the initiation of non-volatile programming operation
when VCC is less than the VCC detect circuit trip.
Second, there is a WE filtering circuit that prevents WE
pulses of less than 10 ns duration from initiating a write
cycle.
Third, holding WE or CE high or OE low, inhibits a write
cycle during power-on and power-off (VCC).
DS11127G-page 6
1996 Microchip Technology Inc.
28C17A
28C17A Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
28C17A
F
T
–
15
I
/P
Package:
L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP (600 mil)
TS = Thin Small Outline Package (TSOP) 8x20mm
VS = Very Small Outline Package (VSOP) 8x13.4mm
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
Access Time:
15 150 ns
20 200 ns
25 250 ns
Shipping:
Option:
Device:
Blank Tube
T
Tape and Reel “L” and “SO”
Blank = twc = 1ms
F
= twc = 200 µs
28C17A
2K x 8 CMOS EEPROM
1996 Microchip Technology Inc.
DS11127G-page 7
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
ASIA/PACIFIC
China
EUROPE
United Kingdom
Microchip Technology Inc.
Microchip Technology
Arizona Microchip Technology Ltd.
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Meadow Bank, Furlong Road
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Tel: 44 1628 850303 Fax: 44 1628 850178
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Technical Support: 602 786-7627
Web: http://www.microchip.com
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Fax: 011 86 21 6275 5060
Hong Kong
Microchip Technology
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Microchip Technology
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JAPAN
Microchip Technology Intl. Inc.
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Kanagawa 222 Japan
Two Prestige Place
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Tel: 513 291-1654 Fax: 513 291-9175
Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technmgy Inc.
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Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
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San Jose, CA 95131
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Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS11127G-page 8
1996 Microchip Technology Inc.
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