28LV64A--30/P [MICROCHIP]

64K (8K x 8) Low Voltage CMOS EEPROM; 64K （ 8K ×8 ）低电压CMOS EEPROM


型号：	28LV64A--30/P
厂家：	MICROCHIP
描述：	64K (8K x 8) Low Voltage CMOS EEPROM 64K （ 8K ×8 ）低电压CMOS EEPROM 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总10页 (文件大小：132K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Obsolete Device

28LV64A

64K (8K x 8) Low Voltage CMOS EEPROM

FEATURES

PACKAGE TYPES

• 2.7V to 3.6V Supply

RDY/BSY

A12

• 1

28 Vcc

27 WE

26 NC

25 A8

• Read Access Time—300 ns

• CMOS Technology for Low Power Dissipation

- 8 mA Active

- 50 µA CMOS Standby Current

• Byte Write Time—3 ms

• Data Retention >200 years

• High Endurance - Minimum 100,000 Erase/Write

Cycles

• Automatic Write Operation

- Internal Control Timer

A1 10

A0 11

NC 12

I/O0 13

29 A8

28 A9

24 A9

23 A11

22 OE

21 A10

20 CE

19 I/O7

18 I/O6

17 I/O5

16 I/O4

15 I/O3

27 A11

26 NC

25 OE

24 A10

23 CE

22 I/O7

21 I/O6

I/O0

I/O1

I/O2

V_SS14

Auto-Clear Before Write Operation

• Pin 1 indicator on PLCC on top of package

- On-Chip Address and Data Latches

• Data Polling

• Ready/Busy

• Chip Clear Operation

BLOCK DIAGRAM

I/O0...................I/O7

• Enhanced Data Protection

- VCC Detector

- Pulse Filter

VSS

VCC

Data Protection

Circuitry

Chip Enable/

Output Enable

Control Logic

- Write Inhibit

• Electronic Signature for Device Identification

• Organized 8Kx8 JEDEC Standard Pinout

- 28-pin Dual-In-Line Package

- 32-pin Chip Carrier (Leadless or Plastic)

• Available for Extended Temperature Ranges:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

Auto Erase/Write

Timing

Data

Poll

Input/Output

Buffers

Rdy/

Busy

Program Voltage

Generation

Y Gating

Decoder

64K bit

Cell Matrix

DESCRIPTION

Decoder

The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-

atile electrically Erasable PROM organized as 8K words by 8 bits.

The 28LV64A is accessed like a static RAM for the read or write

cycles without the need of external components. During a “byte

write”, the address and data are latched internally, freeing the

microprocessor address and data bus for other operations. Fol-

lowing the initiation of write cycle, the device will go to a busy state

and automatically clear and write the latched data using an inter-

nal control timer. To determine when the write cycle is complete,

the user has a choice of monitoring the Ready/Busy output or

using Data polling. The Ready/Busy pin is an open drain output,

which allows easy configuration in ‘wired-or’ systems. Alterna-

tively, Data polling allows the user to read the location last written

to when the write operation is complete. CMOS design and pro-

cessing enables this part to be used in systems where reduced

power consumption and reliability are required. A complete family

of packages is offered to provide the utmost flexibility in applica-

tions.

A12

2004 Microchip Technology Inc.

Preliminary

DS21113E-page 1

28LV64A

TABLE 1-1:

PIN FUCTION TABLE

1.0

ELECTRICAL

CHARACTERISTICS

Name

A0 - A12

Function

Address Inputs

Chip Enable

MAXIMUM RATINGS*

VCC and input voltages w.r.t. VSS ...... -0.6V to + 6.25V

Voltage on OE w.r.t. VSS......................-0.6V to +13.5V

Voltage on A9 w.r.t. VSS ......................-0.6V to +13.5V

Output Voltage w.r.t. VSS ............... -0.6V to VCC+0.6V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied .....-55°C to +125°C

Output Enable

Write Enable

I/O0 - I/O7 Data Inputs/Outputs

RDY/Busy Ready/Busy

VCC

VSS

+ Power Supply

*Notice: Stresses above those listed under “Maximum Ratings” may

cause permanent damage to the device. This is a stress rating only

and functional operation of the device at those or any other conditions

above those indicated in the operation listings of this specification is

not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Ground

No Connect; No Internal Connection

Not Used; No External Connection is

Allowed

TABLE 1-2:

READ/WRITE OPERATION DC CHARACTERISTICS

VCC = 2.7 to 3.6V

Commercial (C): Tamb = 0°C to 70°C

Industrial

(I): Tamb = -40°C to 85°C

Parameter

Status

Symbol

Min

Max Units

Conditions

Input Voltages

Logic “1”

Logic “2”

VIH

VIL

2.0

0.6

Input Leakage

—

ILI

—

µA VIN = 0V to VCC+1

Input Capacitance

CIN

pF Vin = 0V; Tamb = 25°C;

f = 1 MHz (Note 1)

Output Voltages

Logic “1”

Logic “0”

VOH

VOL

2.0

IOH = -100µA

IOL = 1.0 mA

0.3

I0L = 2.0 mA for RDY/Busy

Output Leakage

—

ILO

—

µA VOUT = 0V to VCC+0.1V

Output Capacitance

COUT

pF VOUT = 0V; Tamb = 25°C;

f = 1 MHz (Note 1)

Power Supply Current, Activity

Power Supply Current, Standby

TTL input

ICC

—

mA f = 5 MHz (Note 2)

IO = OmA

VCC = 3.3

CE = VIL

TTL input

CMOS input ICC(S)CMOS

ICC(S)TTL

—

100

mA CE = VIH (0°C to 70°C°)

mA CE = VIH (-40°C to 85°C°)

µA CE = VCC -3.0 to VCC+1

OE = WE = VCC

All other inputs equal VCC or

VSS

Note 1: Not 100% tested.

2: AC power supply current above 5 MHz: 2 mA/Mhz.

DS21113E-page 2

Preliminary

2004 Microchip Technology Inc.

28LV64A

TABLE 1-3:

READ OPERATION AC CHARACTERISTICS

AC Testing Waveform:

Output Load:

VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2

1 TTL Load + 100 pF

Input Rise and Fall

Times:

20 ns

Commercial (C): Tamb = 0°C to +70°C

Ambient Temperature:

Industrial

(I) : Tamb = -40°C to +85°C

28LV64-30

Parameter

Sym

Units

Conditions

Min

—

Max

300

150

Address to Output Delay

CE to Output Delay

tACC

tCE

OE = CE = VIL

OE = VIL

CE = VIL

OE to Output Delay

tOE

CE or OE High to Output Float

tOFF

tOH

(Note 1)

Output Hold from Address, CE or

OE, whichever occurs first.

—

(Note 1)

Endurance

—

10M

—

cycles

25°C, Vcc = 5.0V,

Block Mode (Note 2)

Note 1: Not 100% tested.

2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

FIGURE 1-1: READ WAVEFORMS

VIH

Address

Address Valid

VIL

VIH

VIL

tCE(2)

VIH

VIL

tOFF(1,3)

tOH

tOE(2)

VOH

VOL

High Z

Data

Valid Output

tACC

VIH

VIL

Notes: (1) tOFF is specified for OE or CE, whichever occurs first

(2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE

(3) This parameter is sampled and is not 100% tested

2004 Microchip Technology Inc.

Preliminary

DS21113E-page 3

28LV64A

TABLE 1-4:

BYTE WRITE AC CHARACTERISTICS

AC Testing Waveform:

Output Load:

VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2

1 TTL Load + 100 pF

Input Rise/Fall Times:

Ambient Temperature:

20 ns

Commercial (C): Tamb = 0°C to +70°C

Industrial

(I) : Tamb = -40°C to +85°C

Parameter

Sym

tAS

Min

Max

Units

Remarks

Address Set-Up Time

Address Hold Time

Data Set-Up Time

Data Hold Time

tAH

100

120

tDS

tDH

Write Pulse Width

OE Hold Time

tWPL

tOEH

tOES

tDV

150

(Note 1)

OE Set-Up Time

Data Valid Time

1000

(Note 2)

Time to Device Busy

Write Cycle Time (28LV64A)

tDB

tWC

1.5 ms typical

Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the

positive edge of CE or WE, whichever occurs first.

2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH

after the positive edge of WE or CE, whichever occurs first.

FIGURE 1-2: PROGRAMMING WAVEFORMS

VIH

Address

VIL

tAS

tAH

tWPL

VIH

VIL

CE, WE

Data In

tDH

tDV

tDS

VIH

VIL

tOES

VIH

VIL

tOEH

tDB

VOH

VOL

Busy

Ready

Rdy/Busy

twc

DS21113E-page 4

Preliminary

2004 Microchip Technology Inc.

28LV64A

FIGURE 1-3: DATA POLLING WAVEFORMS

VIH

Last Written

Address Valid

Address

V^IL

t _ACC

VIH

V^IL

t_CE

t ^WPH

VIH

V^IL

t_WPL

t_OE

VIH

V^IL

t_DV

VIH

V^IL

Data In

Valid

True Data Out

Data

I/O7 Out

t^WC

FIGURE 1-4: CHIP CLEAR WAVEFORMS

VIH

= 10ms

= = 1µs

= 12.0V ±0.5V

TABLE 1-5:

SUPPLEMENTARY CONTROL

Mode

VCC

I/OI

Chip Clear

VIL

VIH

VCC

Extra Row Read

Extra Row Write

Note: VH = 12.0V ± 0.5V

VIH

A9 = VH

Data Out

Data In

2004 Microchip Technology Inc.

Preliminary

DS21113E-page 5

28LV64A

2.4

Write Mode

2.0

DEVICE OPERATION

The Microchip Technology Inc. 28LV64A has four

basic modes of operation—read, standby, write inhibit,

and byte write—as outlined in the following table.

The 28LV64A has a write cycle similar to that of a

static RAM. The write cycle is completely self-timed

and initiated by a low going pulse on the WE pin. On

the falling edge of WE, the address information is

latched. On rising edge, the data and the control pins

(CE and OE) are latched. The Ready/Busy pin goes

to a logic low level indicating that the 28LV64A is in a

write cycle which signals the microprocessor host that

the system bus is free for other activity. When

Ready/Busy goes back to a high, the 28LV64A has

completed writing and is ready to accept another

cycle.

Operation Mode CE OE WE I/O

Rdy/Busy (1)

Read

Standby

OUT

High Z

Write Inhibit

Byte Write

Byte Clear

DIN

2.5

Data Polling

Automatic Before Each "Write"

Note: (1) Open drain output.

The 28LV64A features Data polling to signal the com-

pletion of a byte write cycle. During a write cycle, an

attempted read of the last byte written results in the

data complement of I/O7 (I/O0 to I/O6 can not be

determined). After completion of the write cycle, true

data is available. Data polling allows a simple

read/compare operation to determine the status of the

chip eliminating the need for external hardware.

2.1

Read Mode

The 28LV64A has two control functions, both of which

must be logically satisfied in order to obtain data at the

outputs. Chip enable (CE) is the power control and

should be used for device selection. Output Enable

(OE) is the output control and is used to gate data to

the output pins independent of device selection.

Assuming that addresses are stable, address access

time (tACC) is equal to the delay from CE to output

(tCE). Data is available at the output tOE after the fall-

ing edge of OE, assuming that CE has been low and

addresses have been stable for at least tACC-tOE.

2.6

Electronic Signature for Device

Identification

An extra row of 32 bytes of EEPROM memory is avail-

able to the user for device identification. By raising A9

to 12V ±0.5V and using address locations 1FEO to

1FFF, the additional bytes can be written to or read

from in the same manner as the regular memory array.

2.2

Standby Mode

2.7

Chip Clear

The 28LV64A is placed in the standby mode by apply-

ing a high signal to the CE input. When in the standby

mode, the outputs are in a high impedance state, inde-

pendent of the OE input.

All data may be cleared to 1's in a chip clear cycle by

raising OE to 12 volts and bringing the WE and CE

low. This procedure clears all data, except for the

extra row.

2.3

Data Protection

In order to ensure data integrity, especially during criti-

cal power-up and power-down transitions, the follow-

ing enhanced data protection circuits are incorporated:

First, an internal VCC detect (2.0 volts typical) will

inhibit the initiation of non-volatile programming opera-

tion when VCC is less than the VCC detect circuit trip.

Second, holding WE or CE high or OE low, inhibits a

write cycle during power-on and power-off (VCC).

DS21113E-page 6

Preliminary

2004 Microchip Technology Inc.

28LV64A

28LV64A Product Identification System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales offices.

28LV64A –

T – 20

Package:

L = Plastic Leaded Chip Carrier (PLCC)

P = Plastic DIP

SO = Plastic Small Outline IC

Temperature

Range:

Blank = 0°C to +70°C

I = -40°C to +85°C

Access Time:

Shipping:

20 = 200 ns

30 - 300 ns

Blank = Tube

T = Tape and Reel “L” and “SO”

Option:

Device:

Blank = twc = 1ms

F = twc = 200µs

24LV64A 8K x 8 CMOS EEPROM

2004 Microchip Technology Inc.

DS21113E-page 7

28LV64A

NOTES:

DS21113E-page 8

Preliminary

2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical

components in life support systems is not authorized except

with express written approval by Microchip. No licenses are

conveyed, implicitly or otherwise, under any intellectual

property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,

SmartSensor and The Embedded Control Solutions Company

are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Migratable Memory, MPASM,

MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,

PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,

PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,

SmartTel and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc.

Preliminary

DS21113E-page 9

WORLDWIDE SALES AND SERVICE

China - Beijing

Singapore

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: www.microchip.com

Unit 706B

200 Middle Road

Wan Tai Bei Hai Bldg.

No. 6 Chaoyangmen Bei Str.

Beijing, 100027, China

Tel: 86-10-85282100

Fax: 86-10-85282104

#07-02 Prime Centre

Singapore, 188980

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

30F - 1 No. 8

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Kaohsiung 806, Taiwan

Tel: 886-7-536-4816

Fax: 886-7-536-4817

China - Chengdu

Rm. 2401-2402, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Chengdu 610016, China

Tel: 86-28-86766200

Atlanta

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Tel: 770-640-0034

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Taiwan

Taiwan Branch

Fax: 86-28-86766599

Boston

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Dallas

EUROPE

Austria

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A-4600 Wels

Austria

Tel: 43-7242-2244-399

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Denmark

Regus Business Centre

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Tel: 86-755-82901380

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District, Foshan City, Guangdong 528303, China

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Los Angeles

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Germany

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Italy

India

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Milan, Italy

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Tel: 91-80-22290061 Fax: 91-80-22290062

Japan

Fax: 650-961-0286

Tel: 39-0331-742611

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Netherlands

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Tel: 31-416-690399

Toronto

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ASIA/PACIFIC

Australia

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Sydney, Australia

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United Kingdom

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Winnersh Triangle

Korea

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Berkshire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or

82-2-558-5934

07/12/04

Preliminary

 2004 Microchip Technology Inc.

28LV64A--30/P [MICROCHIP]

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