28LV64A-30I/L [MICROCHIP]
64K (8K x 8) Low Voltage CMOS EEPROM; 64K （ 8K ×8 ）低电压CMOS EEPROM
| 型号： | 28LV64A-30I/L |
| 厂家： | 
MICROCHIP |
| 描述： | 64K (8K x 8) Low Voltage CMOS EEPROM |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
28LV64A
64K (8K x 8) Low Voltage CMOS EEPROM
FEATURES
PACKAGE TYPES
• 2.7V to 3.6V Supply
RDY/BSY
A12
A7
• 1
2
28 Vcc
27 WE
26 NC
25 A8
• Read Access Time—300 ns
• CMOS Technology for Low Power Dissipation
- 8 mA Active
- 50 µA CMOS Standby Current
• Byte Write Time—3 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000 Erase/Write
Cycles
• Automatic Write Operation
- Internal Control Timer
3
A6
4
A6
A5
A4
A3
A2
A1 10
A0 11
NC 12
I/O0 13
5
6
7
8
9
29 A8
28 A9
A5
5
24 A9
A4
6
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
27 A11
26 NC
25 OE
24 A10
23 CE
22 I/O7
21 I/O6
A3
7
A2
8
A1
9
A0
10
11
12
13
I/O0
I/O1
I/O2
VSS 14
-
Auto-Clear Before Write Operation
• Pin 1 indicator on PLCC on top of package
- On-Chip Address and Data Latches
• Data Polling
• Ready/Busy
• Chip Clear Operation
• Enhanced Data Protection
- VCC Detector
OE
A11
A9
1
2
3
4
5
6
7
28 A10
27 CE
26 I/07
25 I/06
24 I/05
23 I/04
22 I/03
A8
NC
WE
Vcc
RDY/BSY
A12
8
9
21 Vss
20 I/02
19 I/01
18 I/00
17 A0
16 A1
15 A2
- Pulse Filter
- Write Inhibit
A7 10
A6 11
A5 12
A4 13
A3 14
• Electronic Signature for Device Identification
• Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin Chip Carrier (Leadless or Plastic)
- 28-pin Thin Small Outline Package (TSOP)
8x20mm
OE
A11
A9
22
23
24
25
26
27
A10
CE
21
20
19
18
17
16
15
14
13
12
11
10
9
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A8
NC
WE
VCC
28
1
RDY/BSY
-
28-pin Very Small Outline Package (VSOP)
8x13.4mm
2
3
4
5
6
7
A12
A7
A6
A5
A4
A3
• Available for Extended Temperature Ranges:
- Commercial: 0˚C to +70˚C
A1
A2
8
- Industrial: -40˚C to +85˚C
BLOCK DIAGRAM
DESCRIPTION
I/O0...................I/O7
The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-
atile electrically Erasable PROM organized as 8K words by 8 bits.
The 28LV64A is accessed like a static RAM for the read or write
cycles without the need of external components. During a “byte
write”, the address and data are latched internally, freeing the
microprocessor address and data bus for other operations. Fol-
lowing the initiation of write cycle, the device will go to a busy state
and automatically clear and write the latched data using an inter-
nal control timer. To determine when the write cycle is complete,
the user has a choice of monitoring the Ready/Busy output or
using Data polling. The Ready/Busy pin is an open drain output,
which allows easy configuration in ‘wired-or’ systems. Alterna-
tively, Data polling allows the user to read the location last written
to when the write operation is complete. CMOS design and pro-
cessing enables this part to be used in systems where reduced
power consumption and reliability are required. A complete family
of packages is offered to provide the utmost flexibility in applica-
tions.
VSS
Data Protection
VCC
Circuitry
Chip Enable/
Output Enable
Control Logic
CE
OE
Auto Erase/Write
Timing
Data
Poll
WE
Input/Output
Buffers
Rdy/
Busy
Program Voltage
Generation
A0
Y
I
I
I
I
I
I
I
I
Y Gating
Decoder
L
a
t
c
h
e
s
64K bit
Cell Matrix
X
Decoder
I
I
I
A12
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 1
28LV64A
TABLE 1-1:
PIN FUCTION TABLE
1.0
ELECTRICAL
CHARACTERISTICS
Name
A0 - A12
CE
Function
Address Inputs
Chip Enable
MAXIMUM RATINGS*
VCC and input voltages w.r.t. VSS ......-0.6V to + 6.25V
Voltage on OE w.r.t. VSS......................-0.6V to +13.5V
Voltage on A9 w.r.t. VSS.......................-0.6V to +13.5V
Output Voltage w.r.t. VSS............... -0.6V to VCC+0.6V
Storage temperature .......................... -65˚C to +150˚C
Ambient temp. with power applied .....-55°C to +125°C
OE
Output Enable
Write Enable
WE
I/O0 - I/O7 Data Inputs/Outputs
RDY/Busy Ready/Busy
VCC
VSS
NC
+ Power Supply
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Ground
No Connect; No Internal Connection
NU
Not Used; No External Connection is
Allowed
TABLE 1-2:
READ/WRITE OPERATION DC CHARACTERISTICS
VCC = 2.7 to 3.6V
Commercial (C): Tamb =
0°C to 70°C
Industrial
(I): Tamb = -40°C to 85°C
Parameter
Status
Symbol
Min
Max Units
Conditions
Input Voltages
Logic “1”
Logic “2”
VIH
VIL
2.0
V
V
0.6
5
Input Leakage
—
—
ILI
—
—
µA VIN = 0V to VCC+1
Input Capacitance
CIN
6
pF Vin = 0V; Tamb = 25°C;
f = 1 MHz (Note 1)
Output Voltages
Logic “1”
Logic “0”
VOH
VOL
2.0
V
V
IOH = -100µA
IOL = 1.0 mA
0.3
I0L = 2.0 mA for RDY/Busy
Output Leakage
—
—
ILO
—
—
5
µA VOUT = 0V to VCC+0.1V
Output Capacitance
COUT
12
pF VOUT = 0V; Tamb = 25°C;
f = 1 MHz (Note 1)
Power Supply Current, Activity
TTL input
ICC
—
8
mA f = 5 MHz (Note 2)
IO = OmA
VCC = 3.3
CE = VIL
Power Supply Current, Standby
Note 1: Not 100% tested.
TTL input
TTL input
CMOS input ICC(S)CMOS
ICC(S)TTL
ICC(S)TTL
—
2
3
100
mA CE = VIH (0°C to 70°C°)
mA CE = VIH (-40°C to 85°C°)
µA CE = VCC -3.0 to VCC+1
2: AC power supply current above 5 MHz: 2 mA/Mhz.
DS21113B-page 2
Preliminary
1996 Microchip Technology Inc.
28LV64A
TABLE 1-3:
READ OPERATION AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2
1 TTL Load + 100 pF
Input Rise and Fall Times: 20 ns
Ambient Temperature: Commercial (C): Tamb = 0°C to +70°C
Industrial
(I) : Tamb = -40°C to +85°C
28LV64-30
Parameter
Sym
Units
Conditions
Min
—
—
—
0
Max
300
300
150
60
Address to Output Delay
CE to Output Delay
tACC
tCE
ns
ns
ns
ns
ns
OE = CE = VIL
OE = VIL
CE = VIL
OE to Output Delay
tOE
CE or OE High to Output Float
tOFF
tOH
(Note 1)
Output Hold from Address, CE or
OE, whichever occurs first.
0
—
(Note 1)
Endurance
—
10M
—
cycles
25°C, Vcc = 5.0V,
Block Mode (Note 2)
Note 1: Not 100% tested.
2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-1: READ WAVEFORMS
VIH
Address
CE
Address Valid
VIL
VIH
VIL
tCE(2)
VIH
VIL
OE
tOFF(1,3)
tOH
tOE(2)
VOH
VOL
High Z
High Z
Data
Valid Output
tACC
VIH
VIL
WE
Notes: (1) tOFF is specified for OE or CE, whichever occurs first
(2) OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE
(3) This parameter is sampled and is not 100% tested
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 3
28LV64A
TABLE 1-4:
BYTE WRITE AC CHARACTERISTICS
AC Testing Waveform:
Output Load:
VIH = 2.0V; VIL = 0.6V; VOH = VOL = VCC/2
1 TTL Load + 100 pF
Input Rise/Fall Times:
Ambient Temperature:
20 ns
Commercial (C): Tamb = 0°C to +70°C
Industrial
(I) : Tamb = -40°C to +85°C
Parameter
Sym
tAS
Min
10
Max
Units
ns
Remarks
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
tAH
100
120
10
ns
tDS
ns
tDH
ns
Write Pulse Width
OE Hold Time
tWPL
tOEH
tOES
tDV
150
10
ns
(Note 1)
ns
OE Set-Up Time
10
ns
Data Valid Time
1000
50
ns
(Note 2)
Time to Device Busy
Write Cycle Time (28LV64A)
tDB
ns
tWC
3
ms
1.5 ms typical
Note 1: A write cycle can be initiated be CE or WE going low, whichever occurs last. The data is latched on the
positive edge of CE or WE, whichever occurs first.
2: Data must be valid within 1000ns max. after a write cycle is initiated and must be stable at least until tDH
after the positive edge of WE or CE, whichever occurs first.
FIGURE 1-2: PROGRAMMING WAVEFORMS
VIH
Address
VIL
tAS
tAH
tWPL
VIH
VIL
CE, WE
Data In
tDH
tDV
tDS
VIH
VIL
tOES
VIH
VIL
OE
tOEH
tDB
VOH
VOL
Busy
Ready
Rdy/Busy
twc
DS21113B-page 4
Preliminary
1996 Microchip Technology Inc.
28LV64A
FIGURE 1-3: DATA POLLING WAVEFORMS
VIH
Last Written
Address Valid
Address Valid
Address
CE
VIL
t ACC
VIH
VIL
tCE
t WPH
VIH
VIL
tWPL
WE
tOE
VIH
VIL
OE
tDV
VIH
VIL
Data In
Valid
True Data Out
Data
I/O7 Out
tWC
FIGURE 1-4: CHIP CLEAR WAVEFORMS
VIH
CE
VIL
VH
OE
VIH
tS
tH
tW
VIH
WE
tW
= 10ms
VIL
tS = = 1µs
tH
= 12.0V ±0.5V
VH
TABLE 1-5:
SUPPLEMENTARY CONTROL
Mode
CE
OE
WE
AI
VCC
I/OI
Chip Clear
VIL
VIL
VH
VIL
VIH
X
VCC
VCC
VCC
Extra Row Read
VIH
A9 = VH
A9 = VH
Data Out
Data In
Extra Row Write
Note: VH = 12.0V ± 0.5V
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 5
28LV64A
2.4
Write Mode
2.0
DEVICE OPERATION
The Microchip Technology Inc. 28LV64A has four
basic modes of operation—read, standby, write inhibit,
and byte write—as outlined in the following table.
The 28LV64A has a write cycle similar to that of a
static RAM. The write cycle is completely self-timed
and initiated by a low going pulse on the WE pin. On
the falling edge of WE, the address information is
latched. On rising edge, the data and the control pins
(CE and OE) are latched. The Ready/Busy pin goes
to a logic low level indicating that the 28LV64A is in a
write cycle which signals the microprocessor host that
the system bus is free for other activity. When
Ready/Busy goes back to a high, the 28LV64A has
completed writing and is ready to accept another
cycle.
Operation Mode CE OE WE I/O
Rdy/Busy(1)
Read
Standby
L
L
X
X
L
X
H
H
X
X
X
H
L
D
OUT
H
H
H
H
H
L
H
H
X
X
L
High Z
High Z
High Z
High Z
Write Inhibit
Write Inhibit
Write Inhibit
Byte Write
Byte Clear
DIN
2.5
Data Polling
Automatic Before Each "Write"
Note: (1) Open drain output.
The 28LV64A features Data polling to signal the com-
pletion of a byte write cycle. During a write cycle, an
attempted read of the last byte written results in the
data complement of I/O7 (I/O0 to I/O6 can not be
determined). After completion of the write cycle, true
data is available. Data polling allows a simple
read/compare operation to determine the status of the
chip eliminating the need for external hardware.
2.1
Read Mode
The 28LV64A has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and is used to gate data to
the output pins independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output
(tCE). Data is available at the output tOE after the fall-
ing edge of OE, assuming that CE has been low and
addresses have been stable for at least tACC-tOE.
2.6
Electronic Signature for Device
Identification
An extra row of 32 bytes of EEPROM memory is avail-
able to the user for device identification. By raising A9
to 12V ±0.5V and using address locations 1FEO to
1FFF, the additional bytes can be written to or read
from in the same manner as the regular memory array.
2.2
Standby Mode
2.7
Chip Clear
The 28LV64A is placed in the standby mode by apply-
ing a high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state, inde-
pendent of the OE input.
All data may be cleared to 1's in a chip clear cycle by
raising OE to 12 volts and bringing the WE and CE
low. This procedure clears all data, except for the
extra row.
2.3
Data Protection
In order to ensure data integrity, especially during criti-
cal power-up and power-down transitions, the follow-
ing enhanced data protection circuits are incorporated:
First, an internal VCC detect (2.0 volts typical) will
inhibit the initiation of non-volatile programming opera-
tion when VCC is less than the VCC detect circuit trip.
Second, holding WE or CE high or OE low, inhibits a
write cycle during power-on and power-off (VCC).
DS21113B-page 6
Preliminary
1996 Microchip Technology Inc.
28LV64A
28LV64A Product Identification System
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
28LV64A –
F
T – 20
I
/P
Package:
L = Plastic Leaded Chip Carrier (PLCC)
P = Plastic DIP
SO = Plastic Small Outline IC
TS = Thin Small Outline Package (TSOP) 8 x 20 mm
VS = Very Small Outline Package (VSOP) 8 x 13.4 mm
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
Access Time:
Shipping:
20 = 200 ns
30 - 300 ns
Blank = Tube
T = Tape and Reel “L” and “SO”
Option:
Device:
Blank = twc = 1ms
F = twc = 200µs
24LV64A 8K x 8 CMOS EEPROM
1996 Microchip Technology Inc.
Preliminary
DS21113B-page 7
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
ASIA/PACIFIC
China
EUROPE
United Kingdom
Microchip Technology Inc.
Microchip Technology
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
Unit 406 of Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 5700
Fax: 011 86 21 6275 5060
Hong Kong
Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
India
Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 559 9840
France
Atlanta
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
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Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990 Fax: 508 480-8575
Chicago
Italy
Microchip Technology Inc.
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Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
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Microchip Technology Inc.
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Dallas, TX 75240-8809
Tel: 972 991-7177 Fax: 972 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Arizona Microchip Technology SRL
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Korea
Microchip Technology
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Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan, R.O.C
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
Tel: 81 45 471 6166 Fax: 81 45 471 6122
9/3/96
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technmgy Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279 Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA. 9/96
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21113B-page 8
Preliminary
1996 Microchip Technology Inc.
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