93LC56B/SMRVA [MICROCHIP]
EEPROM, 128X16, Serial, CMOS, PDSO8;
| 型号： | 93LC56B/SMRVA |
| 厂家： | 
MICROCHIP |
| 描述： | EEPROM, 128X16, Serial, CMOS, PDSO8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
93LC56A/B
2K 2.5V Microwire® Serial EEPROM
FEATURES
BLOCK DIAGRAM
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
ADDRESS
DECODER
MEMORY
ARRAY
- 1 µA standby current (maximum)
• 256 x 8 bit organization (93LC56A)
• 128 x 16 bit organization (93LC56B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
ADDRESS
COUNTER
DATA
OUTPUT
BUFFER
DO
REGISTER
• Automatic ERAL before WRAL
DI
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
MODE
DECODE
LOGIC
CS
Vcc
Vss
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
CLOCK
CLK
GENERATOR
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
DESCRIPTION
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
The Microchip Technology Inc. 93LC56A/B are 2K-bit,
low-voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC56A) or
x16 bits (93LC56B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC56A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC56AX/BX are only offered in a
150-mil SOIC package.
PACKAGE TYPE
DIP
SOIC
SOIC
TSSOP
1
2
3
4
8
CS
CS
CLK
DI
DO
1
2
8
7
Vcc
NC
Vcc
NC
NC
Vss
1
8
7
1
2
8
7
NC
Vcc
CS
NC
Vss
DO
DI
7
6
5
VCC
NC
CS
CLK
DI
2
CLK
3
4
6
5
NC
3
6
5
3
4
6
5
DI
NC
Vss
DO
4
CLK
DO
Vss
Microwire is a registered trademark of National Semiconductor.
1998 Microchip Technology Inc.
DS21208C-page 1
93LC56A/B
TABLE 1-1
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL
CHARACTERISTICS
CS
CLK
DI
Chip Select
1.1
Maximum Ratings*
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
VCC...................................................................................7.0V
All inputs and outputs w.r.t. Vss ...............-0.6V to Vcc +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins................................................4 kV
DO
VSS
NC
No Connect
VCC
Power Supply
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-2
DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified Commercial (C): VCC = +2.5V to +6.0V
Tamb = 0°C to +70°C
operating ranges unless otherwise
noted
Industrial (I):
VCC = +2.5V to +6.0V
Tamb = -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
2.7V ≤ VCC ≤ 6.0V (Note 2)
VCC < 2.7V
VIH1
VIH2
VIL1
VIL2
VOL1
VOL2
VOH1
VOH2
ILI
2.0
0.7 Vcc
-0.3
-0.3
—
Vcc +1
Vcc +1
0.8
V
V
High level input voltage
V
VCC > 2.7V (Note 2)
VCC < 2.7V
Low level input voltage
Low level output voltage
High level output voltage
0.2 Vcc
0.4
V
V
IOL = 2.1 mA; Vcc = 4.5V
IOL =100 µA; Vcc = Vcc Min.
IOH = -400 µA; Vcc = 4.5V
IOH = -100 µA; Vcc = Vcc Min.
VIN = VSS
—
0.2
V
2.4
—
V
Vcc-0.2
-10
—
V
Input leakage current
Output leakage current
10
µA
µA
ILO
-10
10
VOUT = VSS
Pin capacitance
(all inputs/outputs)
VIN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, Fclk = 1 MHz
CIN, COUT
ICC read
—
—
7
pF
1
500
mA
µA
FCLK = 2 MHz; VCC = 6.0V
FCLK = 1 MHz; VCC = 3.0V
Operating current
ICC write
ICCS
—
—
1.5
1
mA
µA
Standby current
Clock frequency
CS = VSS; DI = VSS
2
1
MHz
MHz
VCC > 4.5V
VCC < 4.5V
FCLK
—
Clock high time
TCKH
TCKL
TCSS
TCSH
TCSL
TDIS
TDIH
TPD
TCZ
250
250
50
—
—
ns
ns
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time
Status valid time
—
ns
Relative to CLK
Relative to CLK
0
—
ns
250
100
100
—
—
ns
—
ns
Relative to CLK
—
ns
Relative to CLK
400
100
500
6
ns
Cl = 100 pF
—
ns
Cl = 100 pF (Note 2)
Cl = 100 pF
TSV
—
ns
TWC
TEC
—
ms
ms
ms
cycles
ERASE/WRITE mode
ERAL mode
Program cycle time
—
6
TWL
—
—
15
—
WRAL mode
Endurance
1M
25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total
Endurance Model which may be obtained on our website.
DS21208C-page 2
1998 Microchip Technology Inc.
93LC56A/B
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
2.0
PIN DESCRIPTION
2.1
Chip Select (CS)
After detection of a START condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
2.3
Data In (DI)
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.2
Serial Clock (CLK)
2.4
Data Out (DO)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC56A/B.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (TPD after the positive
edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
TABLE 2-1
INSTRUCTION SET FOR 93LC56A
Instruction SB Opcode
Address
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
X
1
0
1
X
X
0
A7 A6 A5 A4 A3 A2 A1 A0
—
—
—
—
—
(RDY/BSY)
(RDY/BSY)
HIGH-Z
12
12
12
12
20
20
20
ERASE
ERAL
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EWDS
EWEN
READ
WRITE
WRAL
HIGH-Z
A7 A6 A5 A4 A3 A2 A1 A0
D7 - D0
A7 A6 A5 A4 A3 A2 A1 A0 D7 - D0
(RDY/BSY)
(RDY/BSY)
1
X
X
X
X
X
X
X
D7 - D0
TABLE 2-2
INSTRUCTION SET FOR 93LC56B
Address
Instruction SB Opcode
Data In
Data Out
Req. CLK Cycles
1
1
1
1
1
1
1
11
00
00
00
10
01
00
X
1
0
1
X
X
0
A6 A5 A4 A3 A2 A1 A0
—
—
—
—
—
(RDY/BSY)
(RDY/BSY)
HIGH-Z
11
11
11
11
27
27
27
ERASE
ERAL
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EWDS
EWEN
READ
WRITE
WRAL
HIGH-Z
A6 A5 A4 A3 A2 A1 A0
D15 - D0
A6 A5 A4 A3 A2 A1 A0 D15 - D0
D15 - D0
(RDY/BSY)
(RDY/BSY)
1
X
X
X
X
X
X
1998 Microchip Technology Inc.
DS21208C-page 3
93LC56A/B
3.2
DATA IN (DI) AND DATA OUT (DO)
3.0
FUNCTIONAL DESCRIPTION
Instructions, addresses and write data are clocked into
the DI pin on the rising edge of the clock (CLK). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY status during a programming operation.
The READY/BUSY status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will enter
the HIGH-Z state on the falling edge of the CS.
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a “bus conflict”
to occur during the “dummy zero” that precedes the
READ operation. Under such a condition, the voltage
level seen at DO is undefined and will depend upon the
relative impedances of DO and the signal source driv-
ing A0. The higher the current sourcing capability of A0,
the higher the voltage at the DO pin.
3.3
Data Protection
3.1
START Condition
During power-up, all programming modes of operation
are inhibited until Vcc has reached a level greater than
2.2V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 2.2V at nominal conditions.
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
The EWDS and EWEN commands give additional pro-
tection against accidentally programming during
normal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don’t care bits until a new START condition is
detected.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
VIH
CS
TCSS
TCKH
TCKL
VIL
TCSH
VIH
CLK
DI
VIL
TDIS
TDIH
VIH
VIL
TCZ
TPD
TPD
VOH
DO
(READ)
TCZ
VOL
VOH
TSV
DO
(PROGRAM)
STATUS VALID
VOL
Note: AC Test Conditions: VIL = 0.4V, VIH - 2.4V.
DS21208C-page 4
1998 Microchip Technology Inc.
93LC56A/B
3.4
ERASE
3.5
Erase All (ERAL)
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The ERAL instruction will erase the entire memory
array to the logical “1” state. The ERAL cycle is identi-
cal to the ERASE cycle except for the different opcode.
The ERAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the ERAL cycle.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2: ERASE TIMING
TCSL
CS
CHECK STATUS
CLK
1
1
AN
AN-1 AN-2
•••
A0
DI
1
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
TWC
FIGURE 3-3: ERAL TIMING
TCSL
CS
CHECK STATUS
CLK
1
0
0
1
0
X
X
DI
•••
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
TEC
Guaranteed at Vcc = 4.5V to +6.0V.
1998 Microchip Technology Inc.
DS21208C-page 5
93LC56A/B
3.6
ERASE/WRITE Disable and Enable
(EWDS/EWEN)
3.7
READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (93LC56A) or 16-bit
(93LC56B) output string. The output data bits will tog-
gle on the rising edge of the CLK and are stable after
the specified time delay (TPD). Sequential read is pos-
sible when CS is held high. The memory data will auto-
matically cycle to the next register and output
sequentially.
The 93LC56A/B powers up in the ERASE/WRITE
Disable (EWDS) state. All programming modes must
be preceded by an ERASE/WRITE Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruc-
tion is executed or VCC is removed from the device. To
protect against accidental data disturbance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming opera-
tions. Execution of a READ instruction is independent
of both the EWDS and EWEN instructions.
FIGURE 3-4: EWDS TIMING
TCSL
CS
CLK
•••
1
0
0
0
0
X
X
DI
FIGURE 3-5: EWEN TIMING
TCSL
CS
CLK
•••
1
0
0
1
1
X
X
DI
FIGURE 3-6: READ TIMING
CS
CLK
DI
An
•••
A0
0
1
1
0
HIGH-Z
DO
Dx
D0
Dx
D0
Dx
D0
•••
•••
•••
DS21208C-page 6
1998 Microchip Technology Inc.
93LC56A/B
3.8
WRITE
3.9
Write All (WRAL)
The WRITE instruction is followed by 8 bits (93LC56A)
or 16 bits (93LC56B) of data which are written into the
specified address. After the last data bit is put on the DI
pin, the falling edge of CS initiates the self-timed auto-
erase and programming cycle.
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and com-
mences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
FIGURE 3-7: WRITE TIMING
TCSL
CS
CLK
0
1
1
An
A0
Dx
D0
•••
•••
DI
TSV
TCZ
HIGH-Z
BUSY
READY
DO
HIGH-Z
Twc
FIGURE 3-8: WRAL TIMING
TCSL
CS
CLK
0
0
1
X
1
0
•••
Dx
•••
DI
X
D0
TSV
TCZ
HIGH-Z
BUSY
READY
HIGH-Z
DO
TWL
Guaranteed at Vcc = 4.5V to +6.0V.
1998 Microchip Technology Inc.
DS21208C-page 7
93LC56A/B
NOTES:
DS21208C-page 8
1998 Microchip Technology Inc.
93LC56A/B
NOTES:
1998 Microchip Technology Inc.
DS21208C-page 9
93LC56A/B
NOTES:
DS21208C-page 10
1998 Microchip Technology Inc.
93LC56A/B
93LC56A/B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
93LC56A/B
—
/P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (208 mil Body), 8-lead
ST = TSSOP, 8-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
93LC56A
2K Microwire Serial EEPROM (x8)
93LC56AT
93LC56AX
2K Microwire Serial EEPROM (x8) Tape and Reel
2K Microwire Serial EEPROM (x8) in alternate
pinout (SN only)
93LC56AXT
2K Microwire Serial EEPROM (x8) in alternate
pinout, Tape and Reel (SN only)
Device:
93LC56B
93LC56BT
93LC56BX
2K Microwire Serial EEPROM (x16)
2K Microwire Serial EEPROM (x16) Tape and Reel
2K Microwire Serial EEPROM (x16) in alternate
pinout (SN only)
93LC56BXT
2K Microwire Serial EEPROM (x16) in alternate
pinout, Tape and Reel (SN only)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1998 Microchip Technology Inc.
DS21208C-page 11
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Tel: 949-263-1888 Fax: 949-263-1338
Tel: 82-2-554-7200 Fax: 82-2-558-5934
New York
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
10/01/00
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 12/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellec-
tual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21208C-page 12
Preliminary
2000 Microchip Technology Inc.
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